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October 11, 2025 13:37
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| /dts-v1/; | |
| // magic: 0xd00dfeed | |
| // totalsize: 0x5d22 (23842) | |
| // off_dt_struct: 0x38 | |
| // off_dt_strings: 0x4dc4 | |
| // off_mem_rsvmap: 0x28 | |
| // version: 17 | |
| // last_comp_version: 16 | |
| // boot_cpuid_phys: 0x0 | |
| // size_dt_strings: 0xf5e | |
| // size_dt_struct: 0x4d8c | |
| / { | |
| model = "Novatek NA51055"; | |
| compatible = "novatek,na51055", "nvt,ca9"; | |
| interrupt-parent = <0x00000001>; | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000001>; | |
| cpus { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| cpu@0 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a9"; | |
| reg = <0x00000000>; | |
| next-level-cache = <0x00000002>; | |
| clock-frequency = <0x47868c00>; | |
| apb-frequency = <0x07270e00>; | |
| linux,phandle = <0x00000004>; | |
| phandle = <0x00000004>; | |
| }; | |
| cpu@1 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a9"; | |
| reg = <0x00000001>; | |
| cpu-release-addr = <0xf07f8000>; | |
| next-level-cache = <0x00000002>; | |
| clock-frequency = <0x47868c00>; | |
| apb-frequency = <0x07270e00>; | |
| linux,phandle = <0x00000005>; | |
| phandle = <0x00000005>; | |
| }; | |
| }; | |
| cg@f0020000 { | |
| compatible = "nvt,core_clk"; | |
| reg = <0xf0020000 0x00001000>; | |
| }; | |
| periph_clk { | |
| compatible = "nvt,periph_clk"; | |
| #clock-cells = <0x00000000>; | |
| clock-output-names = "periph_clk"; | |
| linux,phandle = <0x00000003>; | |
| phandle = <0x00000003>; | |
| }; | |
| global_timer@ffd00200 { | |
| compatible = "arm,cortex-a9-global-timer"; | |
| reg = <0xffd00200 0x00000020>; | |
| interrupts = <0x00000001 0x0000000b 0x00000f01>; | |
| clocks = <0x00000003>; | |
| }; | |
| private_timer@ffd00600 { | |
| compatible = "arm,cortex-a9-twd-timer"; | |
| reg = <0xffd00600 0x00000020>; | |
| interrupts = <0x00000001 0x0000000d 0x00000f01>; | |
| clocks = <0x00000003>; | |
| }; | |
| pmu { | |
| compatible = "arm,cortex-a9-pmu"; | |
| interrupts = <0x00000000 0x00000070 0x00000004 0x00000000 0x00000071 0x00000004>; | |
| interrupt-affinity = <0x00000004 0x00000005>; | |
| }; | |
| cache-controller@ffe00000 { | |
| compatible = "arm,pl310-cache"; | |
| reg = <0xffe00000 0x00001000>; | |
| interrupts = <0x00000000 0x00000060 0x00000004>; | |
| cache-unified; | |
| arm,shared-override; | |
| cache-level = <0x00000002>; | |
| arm,data-latency = <0x00000002 0x00000002 0x00000002>; | |
| arm,tag-latency = <0x00000002 0x00000002 0x00000002>; | |
| linux,phandle = <0x00000002>; | |
| phandle = <0x00000002>; | |
| }; | |
| interrupt-controller@0xffd00000 { | |
| compatible = "arm,cortex-a9-gic"; | |
| #interrupt-cells = <0x00000003>; | |
| interrupt-controller; | |
| reg = <0xffd01000 0x00001000 0xffd00100 0x00001000>; | |
| linux,phandle = <0x00000001>; | |
| phandle = <0x00000001>; | |
| }; | |
| snoop-control-unit@0xffd00000 { | |
| compatible = "arm,cortex-a9-scu"; | |
| reg = <0xffd00000 0x00000100>; | |
| }; | |
| chosen { | |
| bootargs = " "; | |
| }; | |
| aliases { | |
| mmc0 = "/mmc@f0420000"; | |
| mmc1 = "/mmc@f0500000"; | |
| }; | |
| uart@f0290000 { | |
| compatible = "ns16550a"; | |
| reg = <0xf0290000 0x00001000>; | |
| interrupts = <0x00000000 0x0000002b 0x00000004>; | |
| baud = <0x0001c200>; | |
| reg-shift = <0x00000002>; | |
| reg-io-width = <0x00000004>; | |
| no-loopback-test = <0x00000001>; | |
| clock-frequency = <0x016e3600>; | |
| fifo-size = <0x00000040>; | |
| uart_id = <0x00000000>; | |
| }; | |
| uart@f0300000 { | |
| compatible = "ns16550a"; | |
| reg = <0xf0300000 0x00001000>; | |
| interrupts = <0x00000000 0x0000002c 0x00000004>; | |
| baud = <0x0001c200>; | |
| reg-shift = <0x00000002>; | |
| reg-io-width = <0x00000004>; | |
| no-loopback-test = <0x00000001>; | |
| clock-frequency = <0x02dc6c00>; | |
| fifo-size = <0x00000040>; | |
| hw_flowctrl = <0x00000000>; | |
| rx_trig_level = <0x00000003>; | |
| uart_id = <0x00000001>; | |
| }; | |
| uart@f0310000 { | |
| compatible = "ns16550a"; | |
| reg = <0xf0310000 0x00001000>; | |
| interrupts = <0x00000000 0x0000002d 0x00000004>; | |
| baud = <0x0001c200>; | |
| reg-shift = <0x00000002>; | |
| reg-io-width = <0x00000004>; | |
| no-loopback-test = <0x00000001>; | |
| clock-frequency = <0x02dc6c00>; | |
| fifo-size = <0x00000040>; | |
| hw_flowctrl = <0x00000000>; | |
| rx_trig_level = <0x00000003>; | |
| uart_id = <0x00000002>; | |
| }; | |
| uart@f0380000 { | |
| compatible = "ns16550a"; | |
| reg = <0xf0380000 0x00001000>; | |
| interrupts = <0x00000000 0x0000003f 0x00000004>; | |
| baud = <0x0001c200>; | |
| reg-shift = <0x00000002>; | |
| reg-io-width = <0x00000004>; | |
| no-loopback-test = <0x00000001>; | |
| clock-frequency = <0x02dc6c00>; | |
| fifo-size = <0x00000040>; | |
| hw_flowctrl = <0x00000000>; | |
| rx_trig_level = <0x00000003>; | |
| uart_id = <0x00000003>; | |
| }; | |
| uart@f03e0000 { | |
| compatible = "ns16550a"; | |
| reg = <0xf03e0000 0x00001000>; | |
| interrupts = <0x00000000 0x00000040 0x00000004>; | |
| baud = <0x0001c200>; | |
| reg-shift = <0x00000002>; | |
| reg-io-width = <0x00000004>; | |
| no-loopback-test = <0x00000001>; | |
| clock-frequency = <0x02dc6c00>; | |
| fifo-size = <0x00000040>; | |
| hw_flowctrl = <0x00000000>; | |
| rx_trig_level = <0x00000003>; | |
| uart_id = <0x00000004>; | |
| }; | |
| uart@f03f0000 { | |
| compatible = "ns16550a"; | |
| reg = <0xf03f0000 0x00001000>; | |
| interrupts = <0x00000000 0x00000041 0x00000004>; | |
| baud = <0x0001c200>; | |
| reg-shift = <0x00000002>; | |
| reg-io-width = <0x00000004>; | |
| no-loopback-test = <0x00000001>; | |
| clock-frequency = <0x02dc6c00>; | |
| fifo-size = <0x00000040>; | |
| hw_flowctrl = <0x00000000>; | |
| rx_trig_level = <0x00000003>; | |
| uart_id = <0x00000005>; | |
| }; | |
| cc@f0090000 { | |
| compatible = "kdrv_rpc"; | |
| reg = <0xf0090000 0x00000300>; | |
| interrupts = <0x00000000 0x0000003b 0x00000004>; | |
| }; | |
| mmc@f0420000 { | |
| compatible = "nvt,nvt_mmc"; | |
| reg = <0xf0420000 0x00001000>; | |
| interrupts = <0x00000000 0x0000001e 0x00000004>; | |
| max-frequency = <0x05b8d800>; | |
| voltage-switch = <0x00000001>; | |
| max-voltage = <0x00000ce4>; | |
| bus-width = <0x00000004>; | |
| neg-sample-edge = <0x00000000>; | |
| driving = <0x00000014 0x00000014 0x00000014 0x00000019 0x00000019 0x00000019 0x0000001e 0x0000001e 0x0000001e 0x0000001e 0x0000001e 0x0000001e>; | |
| no-sdio; | |
| no-mmc; | |
| cd_gpio = <0x00000080 0x00000000 0x00000001>; | |
| card_power_gpio = <0x00000076 0x00000001>; | |
| force_power_cycle = <0x00000001 0x00000064>; | |
| power_down_delay_ms = <0x00000032>; | |
| power_up_delay_ms = <0x00000032>; | |
| indly_sel = <0x00000019>; | |
| }; | |
| mmc@f0500000 { | |
| compatible = "nvt,nvt_mmc2"; | |
| reg = <0xf0500000 0x00001000>; | |
| interrupts = <0x00000000 0x0000001f 0x00000004>; | |
| max-frequency = <0x02dc6c00>; | |
| voltage-switch = <0x00000000>; | |
| max-voltage = <0x00000ce4>; | |
| bus-width = <0x00000004>; | |
| neg-sample-edge = <0x00000000>; | |
| driving = <0x00000014 0x00000006 0x00000006 0x00000014 0x00000006 0x00000006 0x00000014 0x00000006 0x00000006 0x00000014 0x00000006 0x00000006>; | |
| no-mmc; | |
| cd_gpio = <0x00000000 0x00000000 0x00000001>; | |
| }; | |
| nand@f0400000 { | |
| #address-cells = <0x00000002>; | |
| #size-cells = <0x00000002>; | |
| compatible = "nvt,nvt_spinand"; | |
| reg = <0xf0400000 0x00001000>; | |
| interrupts = <0x00000000 0x0000001d 0x00000004>; | |
| clock-frequency = <0x04c4b400>; | |
| nvt-devname = "spi_nand.0"; | |
| partition_loader { | |
| label = "loader"; | |
| reg = <0x00000000 0x00000000 0x00000000 0x00040000>; | |
| }; | |
| partition_fdt { | |
| label = "fdt"; | |
| reg = <0x00000000 0x00040000 0x00000000 0x00040000>; | |
| }; | |
| partition_fdt.restore { | |
| label = "fdt.restore"; | |
| reg = <0x00000000 0x00080000 0x00000000 0x00040000>; | |
| }; | |
| partition_uboot { | |
| label = "uboot"; | |
| reg = <0x00000000 0x000c0000 0x00000000 0x00200000>; | |
| }; | |
| partition_uenv { | |
| label = "uenv"; | |
| reg = <0x00000000 0x002c0000 0x00000000 0x00040000>; | |
| }; | |
| partition_kernel { | |
| label = "kernel"; | |
| reg = <0x00000000 0x00300000 0x00000000 0x00460000>; | |
| }; | |
| partition_rootfs { | |
| label = "rootfs"; | |
| reg = <0x00000000 0x00760000 0x00000000 0x054c0000>; | |
| }; | |
| partition_pstore { | |
| label = "pstore"; | |
| reg = <0x00000000 0x05c20000 0x00000000 0x00200000>; | |
| }; | |
| partition_app { | |
| label = "app"; | |
| reg = <0x00000000 0x05e20000 0x00000000 0x021a0000>; | |
| }; | |
| partition_all { | |
| label = "all"; | |
| reg = <0x00000000 0x00000000 0x00000000 0x08000000>; | |
| }; | |
| nvtpack { | |
| ver = "NVTPACK_FW_INI_16072017"; | |
| method = <0x00000001>; | |
| index { | |
| id0 { | |
| partition_name = "loader"; | |
| source_file = [00]; | |
| }; | |
| id1 { | |
| partition_name = "fdt"; | |
| source_file = "nvt-na51055-evb.bin"; | |
| }; | |
| id2 { | |
| partition_name = "fdt.restore"; | |
| source_file = [00]; | |
| }; | |
| id3 { | |
| partition_name = "uboot"; | |
| source_file = "u-boot.bin"; | |
| }; | |
| id4 { | |
| partition_name = "uenv"; | |
| source_file = [00]; | |
| }; | |
| id5 { | |
| partition_name = "kernel"; | |
| source_file = "uImage.bin"; | |
| }; | |
| id6 { | |
| partition_name = "rootfs"; | |
| source_file = "rootfs.ubifs.bin"; | |
| }; | |
| id7 { | |
| partition_name = "pstore"; | |
| source_file = [00]; | |
| }; | |
| id8 { | |
| partition_name = "app"; | |
| source_file = "appfs.cardv.ubifs.nand.bin"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| nor@f0400000 { | |
| #address-cells = <0x00000002>; | |
| #size-cells = <0x00000002>; | |
| compatible = "nvt,nvt_spinor"; | |
| reg = <0xf0400000 0x00001000>; | |
| interrupts = <0x00000000 0x0000001d 0x00000004>; | |
| clock-frequency = <0x02dc6c00>; | |
| nvt-devname = "spi_nor.0"; | |
| trace-stdtable = <0x00000001>; | |
| }; | |
| gpio@f0070000 { | |
| compatible = "nvt,nvt_gpio"; | |
| reg = <0xf0070000 0x00010000>; | |
| interrupts = <0x00000000 0x00000018 0x00000004>; | |
| #gpio-cells = <0x00000002>; | |
| }; | |
| eth@f02b0000 { | |
| compatible = "nvt,synopsys_eth"; | |
| reg = <0xf02b0000 0x00000200 0xf02b0208 0x000035f8>; | |
| interrupts = <0x00000000 0x00000022 0x00000004>; | |
| sp-clk = <0x00000000>; | |
| ref-clk-out = <0x00000000>; | |
| }; | |
| mdio@f02b0200 { | |
| compatible = "nvt,eth_mdio"; | |
| reg = <0xf02b0200 0x00000008>; | |
| }; | |
| phy@f02b3800 { | |
| compatible = "nvt,eth_phy"; | |
| reg = <0xf02b3800 0x00000400>; | |
| }; | |
| wdt@f0050000 { | |
| compatible = "nvt,nvt_wdt"; | |
| reg = <0xf0050000 0x00010000>; | |
| interrupts = <0x00000000 0x00000039 0x00000004>; | |
| }; | |
| pwm@f0210000 { | |
| compatible = "nvt,nvt_kdrv_pwm"; | |
| reg = <0xf0210000 0x00002000>; | |
| interrupts = <0x00000000 0x0000001a 0x00000004>; | |
| }; | |
| adc@f0260000 { | |
| compatible = "nvt,nvt_adc"; | |
| reg = <0xf0260000 0x00001000>; | |
| interrupts = <0x00000000 0x0000002f 0x00000004>; | |
| #io-channel-cells = <0x00000001>; | |
| }; | |
| rtc@f0060000 { | |
| compatible = "nvt,nvt_rtc"; | |
| reg = <0xf0060000 0x00000100>; | |
| interrupts = <0x00000000 0x00000038 0x00000004>; | |
| }; | |
| drtc@f00b0000 { | |
| compatible = "nvt,nvt_drtc"; | |
| reg = <0xf00b0000 0x00000100>; | |
| }; | |
| crypto@f0620000 { | |
| compatible = "nvt,nvt_crypto"; | |
| reg = <0xf0620000 0x00000100>; | |
| interrupts = <0x00000000 0x00000026 0x00000004>; | |
| mclk = <0x00000001>; | |
| }; | |
| hash@f0700000 { | |
| compatible = "nvt,nvt_hash"; | |
| reg = <0xf0700000 0x00000100>; | |
| interrupts = <0x00000000 0x0000001c 0x00000004>; | |
| mclk = <0x00000001>; | |
| }; | |
| rsa@f06a0000 { | |
| compatible = "nvt,nvt_rsa"; | |
| reg = <0xf06a0000 0x00000100>; | |
| interrupts = <0x00000000 0x00000014 0x00000004>; | |
| mclk = <0x00000001>; | |
| }; | |
| top@f0010000 { | |
| compatible = "nvt,nvt_top"; | |
| reg = <0xf0010000 0x00002000 0xf0030000 0x00002000 0xf0070000 0x00010000>; | |
| sdio { | |
| pinmux = <0x00000001>; | |
| }; | |
| sdio2 { | |
| pinmux = <0x00000001>; | |
| }; | |
| sdio3 { | |
| pinmux = <0x00000000>; | |
| }; | |
| nand { | |
| pinmux = <0x00000005>; | |
| }; | |
| sensor { | |
| pinmux = <0x00000000>; | |
| }; | |
| sensor2 { | |
| pinmux = <0x00000000>; | |
| }; | |
| mipi_lvds { | |
| pinmux = <0x00000000>; | |
| }; | |
| i2c { | |
| pinmux = <0x00000051>; | |
| }; | |
| sif { | |
| pinmux = <0x00000000>; | |
| }; | |
| uart { | |
| pinmux = <0x00000065>; | |
| }; | |
| spi { | |
| pinmux = <0x00000000>; | |
| }; | |
| sdp { | |
| pinmux = <0x00000000>; | |
| }; | |
| remote { | |
| pinmux = <0x00000000>; | |
| }; | |
| pwm { | |
| pinmux = <0x00000000>; | |
| }; | |
| pwm2 { | |
| pinmux = <0x00000000>; | |
| }; | |
| ccnt { | |
| pinmux = <0x00000000>; | |
| }; | |
| audio { | |
| pinmux = <0x00000000>; | |
| }; | |
| lcd { | |
| pinmux = <0x10000000>; | |
| }; | |
| tv { | |
| pinmux = <0x00000000>; | |
| }; | |
| eth { | |
| pinmux = <0x00000022>; | |
| }; | |
| misc { | |
| pinmux = <0x00000000>; | |
| }; | |
| lgpio9 { | |
| gpio_config = <0x00000069 0x00000001>; | |
| }; | |
| pgpio16 { | |
| pad_config = <0x000000a0 0x00000001 0x000000a0 0x00000001>; | |
| }; | |
| }; | |
| sie@f0c00000 { | |
| compatible = "nvt,drv_sie"; | |
| reg = <0xf0c00000 0x00000900 0xf0d20000 0x00000900 0xf0d30000 0x00000900 0xf0d40000 0x00000900 0xf0d80000 0x00000900>; | |
| interrupts = <0x00000000 0x00000001 0x00000004 0x00000000 0x00000002 0x00000004 0x00000000 0x00000003 0x00000004 0x00000000 0x0000003b 0x00000004 0x00000000 0x0000003d 0x00000004>; | |
| power_saving = <0x00000000>; | |
| }; | |
| tge@f0cc0000 { | |
| compatible = "nvt,kdrv_tge"; | |
| reg = <0xf0cc0000 0x00000150>; | |
| interrupts = <0x00000000 0x00000016 0x00000004>; | |
| }; | |
| rhe@f0ce0000 { | |
| compatible = "nvt,kdrv_rhe"; | |
| reg = <0xf0ce0000 0x00000900>; | |
| interrupts = <0x00000000 0x0000000d 0x00000004>; | |
| }; | |
| ime@f0c40000 { | |
| compatible = "nvt,kdrv_ime"; | |
| reg = <0xf0c40000 0x00001000>; | |
| interrupts = <0x00000000 0x00000006 0x00000004>; | |
| }; | |
| ife2@f0d00000 { | |
| compatible = "nvt,kdrv_ife2"; | |
| reg = <0xf0d00000 0x00000100>; | |
| interrupts = <0x00000000 0x00000009 0x00000004>; | |
| }; | |
| ise@f0c90000 { | |
| compatible = "nvt,kdrv_ise"; | |
| reg = <0xf0c90000 0x00000100>; | |
| interrupts = <0x00000000 0x00000015 0x00000004 0x00000000 0x00000055 0x00000004>; | |
| }; | |
| ipe@f0c30000 { | |
| compatible = "nvt,kdrv_ipe"; | |
| reg = <0xf0c30000 0x00000900>; | |
| interrupts = <0x00000000 0x00000005 0x00000004>; | |
| }; | |
| ife@f0c70000 { | |
| compatible = "nvt,kdrv_ife"; | |
| reg = <0xf0c70000 0x00000800>; | |
| interrupts = <0x00000000 0x00000008 0x00000004>; | |
| }; | |
| vpe@f0cd0000 { | |
| compatible = "nvt,kdrv_vpe"; | |
| reg = <0xf0cd0000 0x00001040>; | |
| interrupts = <0x00000000 0x0000003e 0x00000004>; | |
| }; | |
| ai@f0c60000 { | |
| compatible = "nvt,kdrv_ai"; | |
| reg = <0xf0c60000 0x000001cc 0xf0d50000 0x00000094 0xf0d60000 0x00000200 0xf0cb0000 0x00000200>; | |
| interrupts = <0x00000000 0x0000000e 0x00000004 0x00000000 0x0000000d 0x00000004 0x00000000 0x00000031 0x00000004 0x00000000 0x0000000b 0x00000004>; | |
| }; | |
| md@f0c10000 { | |
| compatible = "nvt,kdrv_md"; | |
| reg = <0xf0c10000 0x00000150>; | |
| interrupts = <0x00000000 0x0000002e 0x00000004>; | |
| }; | |
| dis@f0c50000 { | |
| compatible = "nvt,kdrv_dis"; | |
| reg = <0xf0c50000 0x00000114>; | |
| interrupts = <0x00000000 0x0000000a 0x00000004>; | |
| }; | |
| coe@f0a11000 { | |
| compatible = "nvt,nvt_coe"; | |
| reg = <0xf0a11000 0x000002c0>; | |
| }; | |
| dce@f0c20000 { | |
| compatible = "nvt,kdrv_dce"; | |
| reg = <0xf0c20000 0x00000650>; | |
| interrupts = <0x00000000 0x00000007 0x00000004>; | |
| }; | |
| ive@f0d70000 { | |
| compatible = "nvt,kdrv_ive"; | |
| reg = <0xf0d70000 0x0000006c>; | |
| interrupts = <0x00000000 0x00000035 0x00000004>; | |
| }; | |
| sde@f0d90000 { | |
| compatible = "nvt,kdrv_sde"; | |
| reg = <0xf0d90000 0x00000090>; | |
| interrupts = <0x00000000 0x0000004a 0x00000004>; | |
| }; | |
| ide@f0800000 { | |
| compatible = "nvt,nvt_ide"; | |
| reg = <0xf0800000 0x00001000>; | |
| interrupts = <0x00000000 0x00000030 0x00000004>; | |
| }; | |
| dsi@f0840000 { | |
| compatible = "nvt,nvt_dsi"; | |
| reg = <0xf0840000 0x00001000>; | |
| interrupts = <0x00000000 0x00000032 0x00000004>; | |
| }; | |
| csi@f0280000 { | |
| compatible = "nvt,nvt_csi"; | |
| reg = <0xf0280000 0x00000100 0xf0330000 0x00000100>; | |
| interrupts = <0x00000000 0x00000036 0x00000004 0x00000000 0x00000037 0x00000004>; | |
| }; | |
| lvds@f0270000 { | |
| compatible = "nvt,nvt_lvds"; | |
| reg = <0xf0270000 0x00000200 0xf0370000 0x00000200>; | |
| interrupts = <0x00000000 0x00000036 0x00000004 0x00000000 0x00000037 0x00000004>; | |
| }; | |
| senphy@f06b0000 { | |
| compatible = "nvt,nvt_senphy"; | |
| reg = <0xf06b0000 0x00000100>; | |
| }; | |
| ssenif@f0xx0000 { | |
| compatible = "nvt,nvt_ssenif"; | |
| reg = <0xf02c0000 0x00002000>; | |
| interrupts = <0x00000000 0x0000003d 0x00000004>; | |
| }; | |
| sif@f0240000 { | |
| compatible = "nvt,nvt_sif"; | |
| reg = <0xf0240000 0x00000200>; | |
| interrupts = <0x00000000 0x00000028 0x00000004>; | |
| clock-frequency = <0x000f4240>; | |
| }; | |
| graphic@f0c80000 { | |
| compatible = "nvt,nvt_graphic"; | |
| reg = <0xf0c80000 0x00000300 0xf0d10000 0x00000100>; | |
| interrupts = <0x00000000 0x00000012 0x00000004 0x00000000 0x00000013 0x00000004>; | |
| }; | |
| affine@f0ca0000 { | |
| compatible = "nvt,nvt_affine"; | |
| reg = <0xf0ca0000 0x00000100>; | |
| interrupts = <0x00000000 0x00000034 0x00000004>; | |
| }; | |
| h26x@f0a10000 { | |
| compatible = "nvt,nvt_h26x"; | |
| reg = <0xf0a10000 0x00000a00>; | |
| interrupts = <0x00000000 0x00000010 0x00000004>; | |
| power_saving = <0x00000001>; | |
| }; | |
| clocksource@f0040000 { | |
| compatible = "nvt,nvt_clk_src"; | |
| reg = <0xf0040000 0x00000300>; | |
| interrupts = <0x00000000 0x00000000 0x00000004>; | |
| clock-frequency1 = <0x002dc6c0>; | |
| clock-frequency2 = <0x002dc6c0>; | |
| clksrc = <0x00000001>; | |
| bits = <0x00000020>; | |
| clock-names = "f0040000.timer"; | |
| }; | |
| ptp-dte@f0040000 { | |
| compatible = "nvt,ptp-dte"; | |
| reg = <0xf0040000 0x00000300>; | |
| clock-frequency = <0x002dc6c0>; | |
| interrupts = <0x00000000 0x00000000 0x00000004>; | |
| }; | |
| timer@f0040000 { | |
| compatible = "nvt,nvt_timer"; | |
| reg = <0xf0040000 0x00000300>; | |
| interrupts = <0x00000000 0x00000000 0x00000004>; | |
| }; | |
| eac@f0640000 { | |
| compatible = "nvt,nvt_eac"; | |
| reg = <0xf0640000 0x00000200>; | |
| }; | |
| jpg@f0a00000 { | |
| compatible = "nvt,nvt_jpg"; | |
| reg = <0xf0a00000 0x00000100>; | |
| interrupts = <0x00000000 0x00000011 0x00000004>; | |
| }; | |
| nvt_usb2host@f0600000 { | |
| compatible = "nvt,ehci-nvtivot"; | |
| reg = <0xf0600000 0x00010000>; | |
| interrupts = <0x00000000 0x0000001b 0x00000004>; | |
| }; | |
| nvt_usb2dev@f0600000 { | |
| compatible = "nvt,fotg200_udc"; | |
| reg = <0xf0600000 0x00010000>; | |
| interrupts = <0x00000000 0x0000001b 0x00000004>; | |
| }; | |
| nvt_usb_chrg@f0600000 { | |
| compatible = "nvt,nvt_usb_chrgdet"; | |
| reg = <0xf0600000 0x00010000>; | |
| }; | |
| dai@f0630000 { | |
| compatible = "nvt,nvt_dai"; | |
| reg = <0xf0630000 0x000000bc>; | |
| interrupts = <0x00000000 0x0000000f 0x00000004>; | |
| }; | |
| rotate@f0cf0000 { | |
| compatible = "nvt,nvt_rotation"; | |
| reg = <0xf0cf0000 0x00000100>; | |
| interrupts = <0x00000000 0x00000051 0x00000004>; | |
| }; | |
| drvdump@0 { | |
| compatible = "nvt,nvt_drvdump"; | |
| }; | |
| dsp@f1430000 { | |
| compatible = "nvt,nvt_dsp"; | |
| reg = <0xf1430000 0x00000200 0xf2000000 0x01000000 0xf1440000 0x00000200 0xf3000000 0x01000000>; | |
| interrupts = <0x00000000 0x0000004c 0x00000004 0x00000000 0x0000004d 0x00000004>; | |
| }; | |
| spi@f0230000 { | |
| compatible = "nvt,nvt_spi"; | |
| reg = <0xf0230000 0x00010000>; | |
| interrupts = <0x00000000 0x00000023 0x00000004>; | |
| dma-support = <0x00000000>; | |
| nvt-devname = <0x00000000>; | |
| status = "okay"; | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| }; | |
| spi@f0320000 { | |
| compatible = "nvt,nvt_spi"; | |
| reg = <0xf0320000 0x00010000>; | |
| interrupts = <0x00000000 0x00000024 0x00000004>; | |
| dma-support = <0x00000000>; | |
| nvt-devname = <0x00000001>; | |
| status = "okay"; | |
| }; | |
| spi@f0340000 { | |
| compatible = "nvt,nvt_spi"; | |
| reg = <0xf0340000 0x00010000>; | |
| interrupts = <0x00000000 0x00000025 0x00000004>; | |
| dma-support = <0x00000000>; | |
| nvt-devname = <0x00000002>; | |
| status = "okay"; | |
| }; | |
| spi@f0360000 { | |
| compatible = "nvt,nvt_spi"; | |
| reg = <0xf0360000 0x00010000>; | |
| interrupts = <0x00000000 0x00000042 0x00000004>; | |
| dma-support = <0x00000000>; | |
| nvt-devname = <0x00000003>; | |
| }; | |
| spi@f03d0000 { | |
| compatible = "nvt,nvt_spi"; | |
| reg = <0xf03d0000 0x00010000>; | |
| interrupts = <0x00000000 0x00000043 0x00000004>; | |
| dma-support = <0x00000000>; | |
| nvt-devname = <0x00000004>; | |
| }; | |
| sdp@f0390000 { | |
| compatible = "nvt,nvt_sdp"; | |
| reg = <0xf0390000 0x00000028>; | |
| interrupts = <0x00000000 0x0000000c 0x00000004>; | |
| }; | |
| tse@f0650000 { | |
| compatible = "nvt,nvt_tse"; | |
| reg = <0xf0650000 0x00000090>; | |
| interrupts = <0x00000000 0x00000017 0x00000004>; | |
| }; | |
| remote@f0250000 { | |
| compatible = "nvt,nvt_remote"; | |
| reg = <0xf0250000 0x00000028>; | |
| interrupts = <0x00000000 0x00000019 0x00000004>; | |
| }; | |
| rng@f0680000 { | |
| compatible = "nvt,nvt_rng"; | |
| reg = <0xf0680000 0x00000100>; | |
| }; | |
| nvt_arb@f0000000 { | |
| compatible = "nvt,nvt_arb"; | |
| reg = <0xf0000000 0x0000a000 0xf0100000 0x0000a000 0xf0fe0000 0x00000300 0xf0fd0000 0x00000300>; | |
| interrupts = <0x00000000 0x00000021 0x00000004 0x00000000 0x00000033 0x00000004>; | |
| }; | |
| nvt_otp@f0660000 { | |
| compatible = "nvt,nvt_otp"; | |
| reg = <0xf0660000 0x00000070>; | |
| }; | |
| pll_preset@0 { | |
| pll3 { | |
| pll_config = <0x00000003 0x00000000 0x00000000>; | |
| }; | |
| pll4 { | |
| pll_config = <0x00000004 0x00000000 0x00000000>; | |
| }; | |
| pll5 { | |
| pll_config = <0x00000005 0x00000000 0x00000001>; | |
| }; | |
| pll6 { | |
| pll_config = <0x00000006 0x00000000 0x00000000>; | |
| }; | |
| pll7 { | |
| pll_config = <0x00000007 0x00000000 0x00000000>; | |
| }; | |
| pll8 { | |
| pll_config = <0x00000008 0x00000000 0x00000000>; | |
| }; | |
| pll9 { | |
| pll_config = <0x00000009 0x00000000 0x00000000>; | |
| }; | |
| pll10 { | |
| pll_config = <0x0000000a 0x00000000 0x00000001>; | |
| }; | |
| pll11 { | |
| pll_config = <0x0000000b 0x00000000 0x00000000>; | |
| }; | |
| pll12 { | |
| pll_config = <0x0000000c 0x00000000 0x00000001>; | |
| }; | |
| pll13 { | |
| pll_config = <0x0000000d 0x17d78400 0x00000001>; | |
| }; | |
| pll14 { | |
| pll_config = <0x0000000e 0x00000000 0x00000000>; | |
| }; | |
| pll15 { | |
| pll_config = <0x0000000f 0x17d78400 0x00000001>; | |
| }; | |
| pll16 { | |
| pll_config = <0x00000010 0x00000000 0x00000000>; | |
| }; | |
| pll17 { | |
| pll_config = <0x00000011 0x1dcd6500 0x00000001>; | |
| }; | |
| pll18 { | |
| pll_config = <0x00000012 0x00000000 0x00000001>; | |
| }; | |
| pllf320 { | |
| pll_config = <0x00000018 0x1312d000 0x00000001>; | |
| }; | |
| }; | |
| i2c@f0220000 { | |
| compatible = "nvt,nvt_i2c"; | |
| reg = <0xf0220000 0x00000100>; | |
| interrupts = <0x00000000 0x00000029 0x00000004>; | |
| clock-frequency = <0x00061a80>; | |
| id = <0x00000000>; | |
| auto_busclear = <0x00000001>; | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| sen_imx678@0 { | |
| compatible = "nvt,sen_imx678"; | |
| reg = <0x0000007f>; | |
| path = <0x00000000>; | |
| PRESET { | |
| expt_time = <0x00002710>; | |
| gain_ratio = <0x000003e8>; | |
| }; | |
| DIRECTION { | |
| mirror = <0x00000001>; | |
| flip = <0x00000001>; | |
| }; | |
| POWER { | |
| mclk = <0x00000000>; | |
| pwdn_pin = <0xffffffff>; | |
| rst_pin = <0x00000046>; | |
| rst_time = <0x00000032>; | |
| stable_time = <0x0000000a>; | |
| }; | |
| I2C { | |
| i2c_id = <0x00000000>; | |
| i2c_addr = <0x0000001a>; | |
| }; | |
| }; | |
| }; | |
| i2c2@f0350000 { | |
| compatible = "nvt,nvt_i2c"; | |
| reg = <0xf0350000 0x00000100>; | |
| interrupts = <0x00000000 0x0000002a 0x00000004>; | |
| clock-frequency = <0x00061a80>; | |
| id = <0x00000001>; | |
| auto_busclear = <0x00000001>; | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| }; | |
| i2c3@f03a0000 { | |
| compatible = "nvt,nvt_i2c"; | |
| reg = <0xf03a0000 0x00000100>; | |
| interrupts = <0x00000000 0x0000003c 0x00000004>; | |
| clock-frequency = <0x00061a80>; | |
| id = <0x00000002>; | |
| auto_busclear = <0x00000001>; | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000000>; | |
| ad_tp9950@0 { | |
| compatible = "nvt,ad_tp9950.0"; | |
| reg = <0x00000044>; | |
| power_cfg { | |
| mclk_sel = "MCLK3"; | |
| io_ctl0 = <0x0000fffe 0x00000000 0x00000000>; | |
| io_ctl1 = <0x0000006d 0x00000001 0x00002710>; | |
| io_ctl2 = <0x00000068 0x00000001 0x00002710>; | |
| io_ctl3 = <0x0000002b 0x00000000 0x000186a0>; | |
| io_ctl4 = <0x0000002b 0x00000001 0x000186a0>; | |
| io_ctl5 = <0x0000fffd 0x00000000 0x00000000>; | |
| io_ctl6 = <0x0000fffd 0x00000000 0x0000000a>; | |
| io_ctl7 = <0x0000fffd 0x00000000 0x0000000a>; | |
| io_ctl8 = <0x0000fffd 0x00000000 0x0000000a>; | |
| }; | |
| outport@0 { | |
| inport = <0x00000000>; | |
| signal = <0x00000000>; | |
| }; | |
| }; | |
| }; | |
| i2c4@f03b0000 { | |
| compatible = "nvt,nvt_i2c"; | |
| reg = <0xf03b0000 0x00000100>; | |
| interrupts = <0x00000000 0x00000044 0x00000004>; | |
| clock-frequency = <0x00061a80>; | |
| id = <0x00000003>; | |
| auto_busclear = <0x00000001>; | |
| }; | |
| i2c5@f03c0000 { | |
| compatible = "nvt,nvt_i2c"; | |
| reg = <0xf03c0000 0x00000100>; | |
| interrupts = <0x00000000 0x00000045 0x00000004>; | |
| clock-frequency = <0x00061a80>; | |
| id = <0x00000004>; | |
| auto_busclear = <0x00000001>; | |
| }; | |
| audio@1 { | |
| type = "none"; | |
| i2s_ctrl = <0x00000000>; | |
| sif_channel = <0x00000000>; | |
| gpio_cold_reset = <0x00000000>; | |
| gpio_data = <0x00000000>; | |
| gpio_clk = <0x00000000>; | |
| gpio_cs = <0x00000000>; | |
| adc_zero = <0x00000000>; | |
| }; | |
| audio@2 { | |
| type = "embedded"; | |
| i2s_ctrl = <0x00000004>; | |
| sif_channel = <0x00000000>; | |
| gpio_cold_reset = <0x00000000>; | |
| gpio_data = <0x00000000>; | |
| gpio_clk = <0x00000000>; | |
| gpio_cs = <0x00000000>; | |
| adc_zero = <0x00000000>; | |
| }; | |
| display { | |
| type = "lcd"; | |
| lcd_ctrl = <0x00000000>; | |
| sif_channel = <0x00000002>; | |
| gpio_cs = <0x00000076>; | |
| gpio_clk = <0x00000077>; | |
| gpio_data = <0x00000078>; | |
| }; | |
| logo { | |
| enable = <0x00000000>; | |
| lcd_type = <0x00000012>; | |
| lcd_rotate = <0x00000000>; | |
| lcd_reset = <0x00000075>; | |
| lcd_bl_gpio = <0x00000065 0x00000001>; | |
| lcd_power = <0x0000006a 0x00000000>; | |
| }; | |
| nvtmpp { | |
| compatible = "nvt,nvtmpp"; | |
| }; | |
| isf_stream { | |
| compatible = "nvt,isf_stream"; | |
| }; | |
| isf_flow { | |
| compatible = "nvt,isf_flow"; | |
| }; | |
| isf_vdocap { | |
| compatible = "nvt,isf_vdocap"; | |
| }; | |
| isf_vdoprc { | |
| compatible = "nvt,isf_vdoprc"; | |
| }; | |
| isf_dummy { | |
| compatible = "nvt,isf_dummy"; | |
| }; | |
| isf_vdoenc { | |
| compatible = "nvt,isf_vdoenc"; | |
| }; | |
| isf_vdodec { | |
| compatible = "nvt,isf_vdodec"; | |
| }; | |
| isf_vdoout { | |
| compatible = "nvt,isf_vdoout"; | |
| }; | |
| dispobj { | |
| compatible = "nvt,nvt_dispobj"; | |
| }; | |
| dispdev { | |
| compatible = "nvt,nvt_dispdev"; | |
| }; | |
| audio { | |
| compatible = "nvt,nvt_audio"; | |
| }; | |
| msdcnvt { | |
| compatible = "nvt,msdcnvt"; | |
| }; | |
| msdcnvt_adj { | |
| compatible = "nvt,msdcnvt_adj"; | |
| }; | |
| msdcnvt_custom_si { | |
| compatible = "nvt,msdcnvt_custom_si"; | |
| }; | |
| wavstudio { | |
| compatible = "nvt,wavstudio"; | |
| }; | |
| isf_audenc { | |
| compatible = "nvt,isf_audenc"; | |
| }; | |
| isf_auddec { | |
| compatible = "nvt,isf_auddec"; | |
| }; | |
| isf_audcap { | |
| compatible = "nvt,isf_audcap"; | |
| }; | |
| isf_audout { | |
| compatible = "nvt,isf_audout"; | |
| }; | |
| nvt_ipc { | |
| compatible = "nvt,nvt_ipc"; | |
| }; | |
| ad_fake { | |
| chg_mode_flag = <0x00000001>; | |
| }; | |
| nvt_disflow { | |
| compatible = "nvt,nvt_disflow"; | |
| }; | |
| nvt_memory_cfg { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000001>; | |
| dram { | |
| reg = <0x00000000 0x20000000>; | |
| }; | |
| core2entry1 { | |
| reg = <0x00000000 0x00100000>; | |
| }; | |
| fdt { | |
| reg = <0x00100000 0x00100000>; | |
| }; | |
| shmem { | |
| reg = <0x00200000 0x00100000>; | |
| }; | |
| loader { | |
| reg = <0x01000000 0x00100000>; | |
| }; | |
| linuxtmp { | |
| reg = <0x01100000 0x1cf00000>; | |
| }; | |
| uboot { | |
| reg = <0x1e000000 0x01e00000>; | |
| }; | |
| logo-fb { | |
| reg = <0x1fe00000 0x001c0000>; | |
| }; | |
| core2entry2 { | |
| reg = <0x1ffc0000 0x00040000>; | |
| }; | |
| }; | |
| memory { | |
| device_type = "memory"; | |
| reg = <0x00000000 0x0c000000>; | |
| }; | |
| reserved-memory { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000001>; | |
| ranges; | |
| cma0@0x03000000 { | |
| compatible = "shared-dma-pool"; | |
| reusable; | |
| reg = <0x03000000 0x03000000>; | |
| alignment = <0x00400000>; | |
| status = "okay"; | |
| linux,phandle = <0x00000006>; | |
| phandle = <0x00000006>; | |
| }; | |
| }; | |
| nvt_cma { | |
| compatible = "nvt,nvt_cma"; | |
| memory-region = <0x00000006>; | |
| id = <0x00000000>; | |
| }; | |
| hdal-memory { | |
| #address-cells = <0x00000001>; | |
| #size-cells = <0x00000001>; | |
| media { | |
| reg = <0x0c000000 0x14000000 0x40000000 0x20000000>; | |
| }; | |
| }; | |
| hdal-maxpath-cfg { | |
| vdocap_active_list = <0x00000001 0x00000001 0x00000001 0x00000001 0x00000000 0x00000000 0x00000000 0x00000000>; | |
| vdoprc_maxdevice = <0x00000004>; | |
| vdoenc_maxpath = <0x0000000c>; | |
| vdodec_maxpath = <0x00000003>; | |
| vdoout_maxdevice = <0x00000001>; | |
| adocap_maxdevice = <0x00000001>; | |
| adoout_maxdevice = <0x00000002>; | |
| adoenc_maxpath = <0x00000001>; | |
| adodec_maxpath = <0x00000001>; | |
| gfx_maxjob = <0x00000002>; | |
| stamp_maximg = <0x00000010>; | |
| vdoprc_maxstamp = <0x00000004 0x00000004>; | |
| vdoprc_maxmask = <0x00000004 0x00000004>; | |
| vdoenc_maxstamp = <0x00000010 0x00000010>; | |
| vdoenc_maxmask = <0x00000000 0x00000040>; | |
| vdoout_maxstamp = <0x00000000 0x00000010>; | |
| vdoout_maxmask = <0x00000000 0x00000040>; | |
| }; | |
| nvt_info { | |
| BIN_NAME = "FWA229P"; | |
| BIN_NAME_T = "FW98529T"; | |
| RTOS_APP_MAIN = "cardv"; | |
| EMBMEM_BLK_SIZE = "0x20000"; | |
| EMBMEM = "EMBMEM_SPI_NAND"; | |
| FW_TYPE = "FW_TYPE_NORMAL"; | |
| LCD1 = "disp_ifdsi_lcd1_st7701s_t23p44"; | |
| SENSOR1 = "sen_imx678"; | |
| SENSOR2 = "sen_ad_tp9950"; | |
| SENSOR3 = "sen_off"; | |
| SENSOR4 = "sen_off"; | |
| UI_STYLE = "CARDV"; | |
| TSE = "disable"; | |
| NVT_CFG_APP_EXTERNAL = "hostapd wireless_tool iperf-3 wpa_supplicant dhd_priv libiconv dosfstools rtwpriv exfat-utils"; | |
| NVT_CFG_APP = "hfs lviewd nvtrtspd msdcnvt arm_neon_perf mem mem_hotplug cardv memcpy drystone-2.0 ISP_test bluez_client"; | |
| NVT_ROOTFS_ETC = "CARDV_B80"; | |
| NVT_BINARY_FILE_STRIP = "yes"; | |
| NVT_CFG_KERNEL_CFG = "na51055_evb_cardv_defconfig_release"; | |
| NVT_MAKE_POST = "make_post.sh"; | |
| NVT_SAMPLES_INSTALL = "DISABLE"; | |
| NVT_LINUX_SMP = "NVT_LINUX_SMP_ON"; | |
| NVT_CHIP_ID = "CHIP_NA51084"; | |
| NVT_LINUX_COMPRESS = "NVT_LINUX_COMPRESS_AUTO"; | |
| NVT_DEFAULT_NETWORK_BOOT_PROTOCOL = "NVT_DEFAULT_NETWORK_BOOT_PROTOCOL_DHCP_SERVER"; | |
| NVT_ROOTFS_TYPE = "NVT_ROOTFS_TYPE_NAND_UBI"; | |
| NVT_ROOTFS_RW_PART_EN = "NVT_ROOTFS_RW_PART_EN_OFF"; | |
| NVT_ETHERNET = "NVT_ETHERNET_EQOS"; | |
| NVT_SDIO_WIFI = "NVT_SDIO_WIFI_RTK"; | |
| NVT_USB_WIFI = "NVT_USB_WIFI_NONE"; | |
| NVT_USB_4G = "NVT_USB_4G_NONE"; | |
| WIFI_RTK_MDL = "WIFI_RTK_MDL_8821CS"; | |
| WIFI_BRCM_MDL = "WIFI_BRCM_MDL_43456c0_ampk6256c0"; | |
| WIFI_NVT_MDL = "WIFI_NVT_MDL_18211"; | |
| NVT_CURL_SSL = "NVT_CURL_SSL_OPENSSL"; | |
| NVT_UBOOT_ENV_IN_STORG_SUPPORT = "NVT_UBOOT_ENV_IN_STORG_SUPPORT_OFF"; | |
| NVT_ETHREARCAM = "NVT_ETHREARCAM_RX"; | |
| NVT_ETHREARCAM_CAPS_COUNT = "NVT_ETHREARCAM_CAPS_COUNT_1"; | |
| BT_MDL = "BT_MDL_RTK_8821CS"; | |
| BT_HCI_IF = "BT_HCI_IF_UART"; | |
| BT_STACK = "BT_STACK_BLUEZ"; | |
| GSENSOR_IC = "gsensor_da380"; | |
| YQ_DX_MODEL = "CARDV_W49"; | |
| YQCONFIG_PLATFORM_NAME = "YQCONFIG_PLATFORM_NAME_W49"; | |
| YQCONFIG_FIX_BUG_CHANGE_SUPPORT = "yes"; | |
| YQCONFIG_FIX_FUNCTION_SYSRESET_SUPPORT = "yes"; | |
| YQCONFIG_USER_GETPOWER_ONSOURCE_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_COMB_POWER_SW3_DETECTION_BY_VBUS = "yes"; | |
| YQCONFIG_COMB_POWER_SW2_DETECTION_BY_ACC = "yes"; | |
| YQCONFIG_SHUTDOWN_THE_STARTUP_SUPPORT = "yes"; | |
| YQCONFIG_STARTUP_DELETE_BINFILE_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_STARTUP_STATUS_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_DELET_0KB_FILE_SUPPORT = "yes"; | |
| YQCONFIG_POWER_TYPE_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_GSENSOR_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_PARKING_MONITOR_MODE_SUPPORT = "yes"; | |
| YQCONFIG_POWER_SUPERCAPACITOR_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_AUDIO_AMPLIFIER_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_T_TEST_SUPPORT = "yes"; | |
| YQCONFIG_POWER_KEY_LONG_PRESS_SUPPORT = "yes"; | |
| YQCONFIG_CRASH_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_IR_LIGHT_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_KEY_LONG_SUPPORT = "yes"; | |
| YQCONFIG_TIMELAPSE_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_BT_FUNC_SUPPORT = "yes"; | |
| YQCONFIG_CAR_NUMBER_PLATE_STAMP_SUPPORT = "yes"; | |
| YQCONFIG_MOVIE_STAMP_STRING_SUPPORT = "yes"; | |
| YQCONFIG_BROAD_MODEL_STAMP_SUPPORT = "yes"; | |
| YQCONFIG_MOTION_DET_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_VOICE_SOUND_PLAY_SUPPORT = "yes"; | |
| YQCONFIG_CHANGE_TO_MOVIEWND_RECORD_SUPPORT = "yes"; | |
| YQCONFIG_FORMAT_REMINDER_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_EMR_TRIG_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_SOUND_AUDIO_SR_16000_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_SENSOR_CHANGE_START_RECORDING_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_HOUR_FORMAT_12H_24H_SUPPORT = "yes"; | |
| YQCONFIG_DST_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_TEMPERATURE_DET_SUPPORT = "yes"; | |
| YQCONFIG_ETH_FLOW_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_SLOW_CARD_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_AD_PTZ_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_KEEP_MENU_UPGRADE_SUPPORT = "yes"; | |
| YQCONFIG_PIP_VIEW_VPE_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_GPS_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_GPS_TEST_FUNC = "yes"; | |
| YQCONFIG_TIME_ZONEDST_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_WIFI_CONNECT_STATE_SUPPORT = "yes"; | |
| YQCONFIG_WIFI_OPEN_FLOW_SUPPORT = "yes"; | |
| YQCONFIG_WIFI_AUTO_OFF_SUPPORT = "yes"; | |
| YQCONFIG_ALGORITHM_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_WDTCHDOG_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_AI_SPEECH_FUNCTION_SUPPORT = "yes"; | |
| YQCONFIG_W49_NEW_UI_SUPPORT = "yes"; | |
| }; | |
| }; |
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