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HarkonenBade/pins.rs Secret

Created January 2, 2019 17:52
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pins.rs
#[cfg(any(
feature = "STM32F030C8Tx",
feature = "STM32F030R8Tx",
feature = "STM32F051C4Tx",
feature = "STM32F051C4Ux",
feature = "STM32F051C6Tx",
feature = "STM32F051C6Ux",
feature = "STM32F051C8Tx",
feature = "STM32F051C8Ux",
feature = "STM32F051K4Tx",
feature = "STM32F051K4Ux",
feature = "STM32F051K6Tx",
feature = "STM32F051K6Ux",
feature = "STM32F051K8Tx",
feature = "STM32F051K8Ux",
feature = "STM32F051R4Tx",
feature = "STM32F051R6Tx",
feature = "STM32F051R8Hx",
feature = "STM32F051R8Tx",
feature = "STM32F051T8Yx",
feature = "STM32F058C8Ux",
feature = "STM32F058R8Hx",
feature = "STM32F058R8Tx",
feature = "STM32F058T8Yx",
))]
pins! {
PA2 => {AF1: TxPin<USART2>},
PA3 => {AF1: RxPin<USART2>},
PA5 => {AF0: SckPin<SPI1>},
PA6 => {AF0: MisoPin<SPI1>},
PA7 => {AF0: MosiPin<SPI1>},
PA9 => {AF1: TxPin<USART1>},
PA10 => {AF1: RxPin<USART1>},
PA14 => {AF1: TxPin<USART2>},
PA15 => {AF1: RxPin<USART2>},
PB3 => {AF0: SckPin<SPI1>},
PB4 => {AF0: MisoPin<SPI1>},
PB5 => {AF0: MosiPin<SPI1>},
PB6 => {
AF0: TxPin<USART1>,
AF1: SclPin<I2C1>,
},
PB7 => {
AF0: RxPin<USART1>,
AF1: SdaPin<I2C1>,
},
PB8 => {AF1: SclPin<I2C1>},
PB9 => {AF1: SdaPin<I2C1>},
PB10 => {AF1: SclPin<I2C2>},
PB11 => {AF1: SdaPin<I2C2>},
PB13 => {AF0: SckPin<SPI2>},
PB14 => {AF0: MisoPin<SPI2>},
PB15 => {AF0: MosiPin<SPI2>},
}
#[cfg(any(
feature = "STM32F070CBTx",
feature = "STM32F070RBTx",
feature = "STM32F071C(8-B)Tx",
feature = "STM32F071C(8-B)Tx",
feature = "STM32F071C(8-B)Ux",
feature = "STM32F071C(8-B)Ux",
feature = "STM32F071CBYx",
feature = "STM32F071RBTx",
feature = "STM32F071V(8-B)Hx",
feature = "STM32F071V(8-B)Hx",
feature = "STM32F071V(8-B)Tx",
feature = "STM32F071V(8-B)Tx",
feature = "STM32F072C(8-B)Tx",
feature = "STM32F072C(8-B)Tx",
feature = "STM32F072C(8-B)Ux",
feature = "STM32F072C(8-B)Ux",
feature = "STM32F072CBYx",
feature = "STM32F072R(8-B)Tx",
feature = "STM32F072R(8-B)Tx",
feature = "STM32F072RBHx",
feature = "STM32F072RBIx",
feature = "STM32F072V(8-B)Hx",
feature = "STM32F072V(8-B)Hx",
feature = "STM32F072V(8-B)Tx",
feature = "STM32F072V(8-B)Tx",
feature = "STM32F078CBTx",
feature = "STM32F078CBUx",
feature = "STM32F078CBYx",
feature = "STM32F078RBHx",
feature = "STM32F078RBTx",
feature = "STM32F078VBHx",
feature = "STM32F078VBTx",
))]
pins! {
PA0 => {AF4: TxPin<USART4>},
PA1 => {AF4: RxPin<USART4>},
PA2 => {AF1: TxPin<USART2>},
PA3 => {AF1: RxPin<USART2>},
PA5 => {AF0: SckPin<SPI1>},
PA6 => {AF0: MisoPin<SPI1>},
PA7 => {AF0: MosiPin<SPI1>},
PA9 => {AF1: TxPin<USART1>},
PA10 => {AF1: RxPin<USART1>},
PA14 => {AF1: TxPin<USART2>},
PA15 => {AF1: RxPin<USART2>},
PB3 => {AF0: SckPin<SPI1>},
PB4 => {AF0: MisoPin<SPI1>},
PB5 => {AF0: MosiPin<SPI1>},
PB6 => {
AF0: TxPin<USART1>,
AF1: SclPin<I2C1>,
},
PB7 => {
AF0: RxPin<USART1>,
AF1: SdaPin<I2C1>,
},
PB8 => {AF1: SclPin<I2C1>},
PB9 => {AF1: SdaPin<I2C1>},
PB10 => {
AF1: SclPin<I2C2>,
AF4: TxPin<USART3>,
AF5: SckPin<SPI2>,
},
PB11 => {
AF1: SdaPin<I2C2>,
AF4: RxPin<USART3>,
},
PB13 => {
AF0: SckPin<SPI2>,
AF5: SclPin<I2C2>,
},
PB14 => {
AF0: MisoPin<SPI2>,
AF5: SdaPin<I2C2>,
},
PB15 => {AF0: MosiPin<SPI2>},
PC2 => {AF1: MisoPin<SPI2>},
PC3 => {AF1: MosiPin<SPI2>},
PC4 => {AF1: TxPin<USART3>},
PC5 => {AF1: RxPin<USART3>},
PC10 => {
AF0: TxPin<USART4>,
AF1: TxPin<USART3>,
},
PC11 => {
AF0: RxPin<USART4>,
AF1: RxPin<USART3>,
},
PD1 => {AF1: SckPin<SPI2>},
PD3 => {AF1: MisoPin<SPI2>},
PD4 => {AF1: MosiPin<SPI2>},
PD5 => {AF0: TxPin<USART2>},
PD6 => {AF0: RxPin<USART2>},
PD8 => {AF0: TxPin<USART3>},
PD9 => {AF0: RxPin<USART3>},
PE13 => {AF1: SckPin<SPI1>},
PE14 => {AF1: MisoPin<SPI1>},
PE15 => {AF1: MosiPin<SPI1>},
}
#[cfg(any(
feature = "STM32F030C6Tx",
feature = "STM32F030F4Px",
feature = "STM32F030K6Tx",
feature = "STM32F031C(4-6)Tx",
feature = "STM32F031C(4-6)Tx",
feature = "STM32F031E6Yx",
feature = "STM32F031F(4-6)Px",
feature = "STM32F031F(4-6)Px",
feature = "STM32F031G(4-6)Ux",
feature = "STM32F031G(4-6)Ux",
feature = "STM32F031K(4-6)Ux",
feature = "STM32F031K(4-6)Ux",
feature = "STM32F031K6Tx",
feature = "STM32F038C6Tx",
feature = "STM32F038E6Yx",
feature = "STM32F038F6Px",
feature = "STM32F038G6Ux",
feature = "STM32F038K6Ux",
))]
pins! {
PA2 => {
AF1: TxPin<USART1>,
AF1: TxPin<USART2>,
},
PA3 => {
AF1: RxPin<USART1>,
AF1: RxPin<USART2>,
},
PA5 => {AF0: SckPin<SPI1>},
PA6 => {AF0: MisoPin<SPI1>},
PA7 => {AF0: MosiPin<SPI1>},
PA9 => {
AF1: TxPin<USART1>,
AF4: SclPin<I2C1>,
},
PA10 => {
AF1: RxPin<USART1>,
AF4: SdaPin<I2C1>,
},
PA14 => {
AF1: TxPin<USART1>,
AF1: TxPin<USART2>,
},
PA15 => {
AF1: RxPin<USART1>,
AF1: RxPin<USART2>,
},
PB3 => {AF0: SckPin<SPI1>},
PB4 => {AF0: MisoPin<SPI1>},
PB5 => {AF0: MosiPin<SPI1>},
PB6 => {
AF0: TxPin<USART1>,
AF1: SclPin<I2C1>,
},
PB7 => {
AF0: RxPin<USART1>,
AF1: SdaPin<I2C1>,
},
PB8 => {AF1: SclPin<I2C1>},
PB9 => {AF1: SdaPin<I2C1>},
PB10 => {
AF1: SclPin<I2C1>,
AF1: SclPin<I2C2>,
},
PB11 => {
AF1: SdaPin<I2C1>,
AF1: SdaPin<I2C2>,
},
PB13 => {
AF0: SckPin<SPI1>,
AF0: SckPin<SPI2>,
},
PB14 => {
AF0: MisoPin<SPI1>,
AF0: MisoPin<SPI2>,
},
PB15 => {
AF0: MosiPin<SPI1>,
AF0: MosiPin<SPI2>,
},
}
#[cfg(any(
feature = "STM32F070C6Tx",
feature = "STM32F070F6Px",
feature = "STM32F042C(4-6)Tx",
feature = "STM32F042C(4-6)Tx",
feature = "STM32F042C(4-6)Ux",
feature = "STM32F042C(4-6)Ux",
feature = "STM32F042F4Px",
feature = "STM32F042F6Px",
feature = "STM32F042G(4-6)Ux",
feature = "STM32F042G(4-6)Ux",
feature = "STM32F042K(4-6)Tx",
feature = "STM32F042K(4-6)Tx",
feature = "STM32F042K(4-6)Ux",
feature = "STM32F042K(4-6)Ux",
feature = "STM32F042T6Yx",
feature = "STM32F048C6Ux",
feature = "STM32F048G6Ux",
feature = "STM32F048T6Yx",
))]
pins! {
PA2 => {AF1: TxPin<USART2>},
PA3 => {AF1: RxPin<USART2>},
PA5 => {AF0: SckPin<SPI1>},
PA6 => {AF0: MisoPin<SPI1>},
PA7 => {AF0: MosiPin<SPI1>},
PA9 => {
AF1: TxPin<USART1>,
AF4: SclPin<I2C1>,
},
PA10 => {
AF1: RxPin<USART1>,
AF4: SdaPin<I2C1>,
},
PA11 => {AF5: SclPin<I2C1>},
PA12 => {AF5: SdaPin<I2C1>},
PA14 => {AF1: TxPin<USART2>},
PA15 => {AF1: RxPin<USART2>},
PB3 => {AF0: SckPin<SPI1>},
PB4 => {AF0: MisoPin<SPI1>},
PB5 => {AF0: MosiPin<SPI1>},
PB6 => {
AF0: TxPin<USART1>,
AF1: SclPin<I2C1>,
},
PB7 => {
AF0: RxPin<USART1>,
AF1: SdaPin<I2C1>,
},
PB8 => {AF1: SclPin<I2C1>},
PB9 => {AF1: SdaPin<I2C1>},
PB10 => {
AF1: SclPin<I2C1>,
AF5: SckPin<SPI2>,
},
PB11 => {AF1: SdaPin<I2C1>},
PB13 => {
AF0: SckPin<SPI2>,
AF5: SclPin<I2C2>,
},
PB14 => {
AF0: MisoPin<SPI2>,
AF5: SdaPin<I2C2>,
},
PB15 => {AF0: MosiPin<SPI2>},
PF0 => {AF1: SdaPin<I2C1>},
PF1 => {AF1: SclPin<I2C1>},
}
#[cfg(any(
feature = "STM32F030CCTx",
feature = "STM32F030RCTx",
feature = "STM32F091C(B-C)Tx",
feature = "STM32F091C(B-C)Tx",
feature = "STM32F091C(B-C)Ux",
feature = "STM32F091C(B-C)Ux",
feature = "STM32F091R(B-C)Tx",
feature = "STM32F091R(B-C)Tx",
feature = "STM32F091RCHx",
feature = "STM32F091RCYx",
feature = "STM32F091V(B-C)Tx",
feature = "STM32F091V(B-C)Tx",
feature = "STM32F091VCHx",
feature = "STM32F098CCTx",
feature = "STM32F098CCUx",
feature = "STM32F098RCHx",
feature = "STM32F098RCTx",
feature = "STM32F098RCYx",
feature = "STM32F098VCHx",
feature = "STM32F098VCTx",
))]
pins! {
PA0 => {AF4: TxPin<USART4>},
PA1 => {AF4: RxPin<USART4>},
PA2 => {AF1: TxPin<USART2>},
PA3 => {AF1: RxPin<USART2>},
PA4 => {AF5: TxPin<USART6>},
PA5 => {
AF0: SckPin<SPI1>,
AF5: RxPin<USART6>,
},
PA6 => {AF0: MisoPin<SPI1>},
PA7 => {AF0: MosiPin<SPI1>},
PA9 => {
AF1: TxPin<USART1>,
AF4: SclPin<I2C1>,
},
PA10 => {
AF1: RxPin<USART1>,
AF4: SdaPin<I2C1>,
},
PA11 => {AF5: SclPin<I2C2>},
PA12 => {AF5: SdaPin<I2C2>},
PA14 => {AF1: TxPin<USART2>},
PA15 => {AF1: RxPin<USART2>},
PB3 => {
AF0: SckPin<SPI1>,
AF4: TxPin<USART5>,
},
PB4 => {
AF0: MisoPin<SPI1>,
AF4: RxPin<USART5>,
},
PB5 => {AF0: MosiPin<SPI1>},
PB6 => {
AF0: TxPin<USART1>,
AF1: SclPin<I2C1>,
},
PB7 => {
AF0: RxPin<USART1>,
AF1: SdaPin<I2C1>,
},
PB8 => {AF1: SclPin<I2C1>},
PB9 => {AF1: SdaPin<I2C1>},
PB10 => {
AF1: SclPin<I2C2>,
AF4: TxPin<USART3>,
AF5: SckPin<SPI2>,
},
PB11 => {
AF1: SdaPin<I2C2>,
AF4: RxPin<USART3>,
},
PB13 => {
AF0: SckPin<SPI2>,
AF5: SclPin<I2C2>,
},
PB14 => {
AF0: MisoPin<SPI2>,
AF5: SdaPin<I2C2>,
},
PB15 => {AF0: MosiPin<SPI2>},
PC0 => {
AF1: TxPin<USART7>,
AF2: TxPin<USART6>,
},
PC1 => {
AF1: RxPin<USART7>,
AF2: RxPin<USART6>,
},
PC2 => {
AF1: MisoPin<SPI2>,
AF2: TxPin<USART8>,
},
PC3 => {
AF1: MosiPin<SPI2>,
AF2: RxPin<USART8>,
},
PC4 => {AF1: TxPin<USART3>},
PC5 => {AF1: RxPin<USART3>},
PC6 => {AF1: TxPin<USART7>},
PC7 => {AF1: RxPin<USART7>},
PC8 => {AF1: TxPin<USART8>},
PC9 => {AF1: RxPin<USART8>},
PC10 => {
AF0: TxPin<USART4>,
AF1: TxPin<USART3>,
},
PC11 => {
AF0: RxPin<USART4>,
AF1: RxPin<USART3>,
},
PC12 => {AF2: TxPin<USART5>},
PD1 => {AF1: SckPin<SPI2>},
PD2 => {AF2: RxPin<USART5>},
PD3 => {AF1: MisoPin<SPI2>},
PD4 => {AF1: MosiPin<SPI2>},
PD5 => {AF0: TxPin<USART2>},
PD6 => {AF0: RxPin<USART2>},
PD8 => {AF0: TxPin<USART3>},
PD9 => {AF0: RxPin<USART3>},
PD13 => {AF0: TxPin<USART8>},
PD14 => {AF0: RxPin<USART8>},
PE8 => {AF1: TxPin<USART4>},
PE9 => {AF1: RxPin<USART4>},
PE10 => {AF1: TxPin<USART5>},
PE11 => {AF1: RxPin<USART5>},
PE13 => {AF1: SckPin<SPI1>},
PE14 => {AF1: MisoPin<SPI1>},
PE15 => {AF1: MosiPin<SPI1>},
PF0 => {AF1: SdaPin<I2C1>},
PF1 => {AF1: SclPin<I2C1>},
PF2 => {AF1: TxPin<USART7>},
PF3 => {AF1: RxPin<USART7>},
PF9 => {AF1: TxPin<USART6>},
PF10 => {AF1: RxPin<USART6>},
}
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