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Hikari9/FinalLabMemory.jsim

Created December 1, 2015 04:01
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CS 152 final lab using JSIM memory
Raw
FinalLabMemory.jsim
.include "8clocks.jsim"
.include "nominal.jsim"
.include "stdcell.jsim"
// for alufn connect
.subckt knex a b
.connect a b
.ends
// Xlab opcode[5:0] z pcsel[1:0] ra2sel bsel wdsel[1:0] alufn[5:0] wr werf FINALLAB
Xconn clk[7:1] opcode[5:0] z knex
Xmem vdd 0 0
+ opcode[5:0] z
+ pcsel[1:0] ra2sel bsel wdsel[1:0] alufn[5:0] wr werf //This is the corresponding below
+ $memory width=14 nlocations=128
+ contents=( // Similar to the RC RA RB thing for BSIM, so first thing we put is opCode
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 // 2 zeroes for each opCode First 2 is opCode0 next 2 is opCode1 ... until opCode7
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 // We have now filled up our memory with necessary instructions
///////////////////////////////////////////////////////////////////
// TRUTH TABLE (betaop)
// +-----+------------------------------------------------------+
// | | 000 001 010 011 100 101 110 111 |
// +-----+------------------------------------------------------+
// | 000 | ??? ??? ??? ??? ??? ??? ??? ??? |
// | 001 | ??? ??? ??? ??? ??? ??? ??? ??? |
// | 010 | ??? ??? ??? ??? ??? ??? ??? ??? |
// | 011 | LD ST ??? JMP ??? BEQ BNE LDR*|
// | 100 | ADD SUB MUL* DIV* CMPEQ CMPLT CMPLE ??? |
// | 101 | AND OR XOR ??? SHL SHR SRA ??? |
// | 110 | ADDC SUBC MULC* DIVC* CMPEQC CMPLTC CMPLEC ??? |
// | 111 | ANDC ORC XORC ??? SHLC SHRC SRAC ??? |
// +-----+------------------------------------------------------+
// OPCODE to ALUFN TRUTH TABLE (bin codes from lab 9)
// +-----+------------------------------------------------------+
// | | 000 001 010 011 100 101 110 111 |
// +-----+------------------------------------------------------+
// | 000 | ??? ??? ??? ??? ??? ??? ??? ??? |
// | 001 | ??? ??? ??? ??? ??? ??? ??? ??? |
// | 010 | ??? ??? ??? ??? ??? ??? ??? ??? |
// | 011 | 000000 000000 ??? *** ??? *** *** *** |
// | 100 | 000000 000001 *** *** 110011 110101 110111 ??? |
// | 101 | 011000 011110 010110 ??? 100000 100001 100011 ??? |
// | 110 | 000000 000001 *** *** 110011 110101 110111 ??? |
// | 111 | 011000 011110 010110 ??? 100000 100001 100011 ??? |
// +-----+------------------------------------------------------+
// INSTRUCTION TABLE
// +-------------+--------+--------+--------+--------+--------+--------+--------+
// | Instruction | LD | ST | JMP | BEQ | BNE | ALU | ALUC |
// +-------------+--------+--------+--------+--------+--------+--------+--------+
// | PCSEL [2] | 00 | 00 | 10 | 0z | 0!z | 00 | 00 |
// | RA2SEL | - | 1 | - | - | - | 0 | - |
// | BSEL | 1 | 1 | - | - | - | 0 | 1 |
// | WDSEL [2] | 10 | -- | 00 | 00 | 00 | 01 | 01 |
// | ALUFN | ADD | ADD | --- | --- | --- | ALU | ALU |
// | ALUFN code | 000000 | 000000 | ------ | ------ | ------ | ALUFN | ALUFN |
// | WR | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
// | WERF | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
// +-------------+--------+--------+--------+--------+--------+--------+--------+
+ 0b00011000000001 0b00011000000001 // LD
+ 0b00110000000010 0b00110000000010 // ST
+ 0 0 // ---
+ 0b10000000000001 0b10000000000001 // JMP
+ 0 0 // ---
+ 0b00000000000001 0b01000000000001 // BEQ
+ 0b01000000000001 0b00000000000001 // BNE
+ 0 0 // --- (LDR)
// OPCODE TO ALUFN TABLE
// +--------+--------+
// | OPCODE | ALUFN |
// +--------+--------+
// | ADD | 000000 |
// | SUB | 000001 |
// | CMPEQ | 110011 |
// | CMPLT | 110101 |
// | CMPLE | 110111 |
// | AND | 011000 |
// | OR | 011110 |
// | XOR | 010110 |
// | SHL | 100000 |
// | SHR | 100001 |
// | SRA | 100011 |
// +--------+--------+
// for ALU: 0b000001______01
// for ALUC: 0b000101______01
/// ROW 100
+ 0b00000100000001 0b00000100000001 // ADD
+ 0b00000100000101 0b00000100000101 // SUB
+ 0 0 // --- (MUL)
+ 0 0 // --- (DIV)
+ 0b00000111001101 0b00000111001101 // CMPEQ
+ 0b00000111010101 0b00000111010101 // CMPLT
+ 0b00000111011101 0b00000111011101 // CMPLE
+ 0 0 // ???
/// ROW 101
+ 0b00000101100001 0b00000101100001 // AND
+ 0b00000101111001 0b00000101111001 // OR
+ 0b00000101011001 0b00000101011001 // XOR
+ 0 0 // ???
+ 0b00000110000001 0b00000110000001 // SHL
+ 0b00000110000101 0b00000110000101 // SHR
+ 0b00000110001101 0b00000110001101 // SRA
+ 0 0 // ???
/// ROW 110
+ 0b00010100000001 0b00010100000001 // ADD
+ 0b00010100000101 0b00010100000101 // SUB
+ 0 0 // --- (MUL)
+ 0 0 // --- (DIV)
+ 0b00010111001101 0b00010111001101 // CMPEQ
+ 0b00010111010101 0b00010111010101 // CMPLT
+ 0b00010111011101 0b00010111011101 // CMPLE
+ 0 0 // ???
/// ROW 111
+ 0b00010101100001 0b00010101100001 // AND
+ 0b00010101111001 0b00010101111001 // OR
+ 0b00010101011001 0b00010101011001 // XOR
+ 0 0 // ???
+ 0b00010110000001 0b00010110000001 // SHL
+ 0b00010110000101 0b00010110000101 // SHR
+ 0b00010110001101 0b00010110001101 // SRA
+ 0 0 // ???
+ )
// for checking purposes
.plotdef alufnop
+ ADD SUB ??? ??? ??? ??? ??? ??? // 000
+ ??? ??? ??? ??? ??? ??? ??? ??? // 001
+ ??? ??? ??? ??? ??? ??? XOR ??? // 010
+ AND ??? ??? ??? ??? ??? OR ??? // 011
+ SHL SHR ??? SRA ??? ??? ??? ??? // 100
+ ??? ??? ??? ??? ??? ??? ??? ??? // 101
+ ??? ??? ??? CMPEQ ??? CMPLT ??? CMPLE // 110
+ ??? ??? ??? ??? ??? ??? ??? ??? // 111
//000 001 010 011 100 101 110 111
.tran 640ns
.plot betaop(clk[7:2]) // LOOK AT NOMINAL LOL It shows the operation's name due to this thingy
*.plot alufnop(alufn[5:0])
.plot z
.plot pcsel[1:0]
.plot ra2sel
.plot bsel
.plot wdsel[1:0]
.plot wr
.plot werf
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