Verilog example

Modified V3WidthSel

logic [32:0]  des__DOT__out0;
assign des__DOT__out0[32:1] = {des__DOT__u0__DOT__S[17], {des__DOT__u0__DOT__S[26], {des__DOT__u0__DOT__S[13], {des__DOT__u0__DOT__S[12], {des__DOT__u0__DOT__S[4], {des__DOT__u0__DOT__S[21], {des__DOT__u0__DOT__S[5], {des__DOT__u0__DOT__S[16], {1'h0, {des__DOT__u0__DOT__S[18], {des__DOT__u0__DOT__S[10], {des__DOT__u0__DOT__S[7], {des__DOT__u0__DOT__S[28], {des__DOT__u0__DOT__S[15], {des__DOT__u0__DOT__S[2], {des__DOT__u0__DOT__S[23], {des__DOT__u0__DOT__S[31], {des__DOT__u0__DOT__S[25], {des__DOT__u0__DOT__S[9], {des__DOT__u0__DOT__S[19], {des__DOT__u0__DOT__S[1], {des__DOT__u0__DOT__S[6], {des__DOT__u0__DOT__S[30], {des__DOT__u0__DOT__S[24], {des__DOT__u0__DOT__S[14], {des__DOT__u0__DOT__S[20], {des__DOT__u0__DOT__S[3], {des__DOT__u0__DOT__S[27], {des__DOT__u0__DOT__S[11], {des__DOT__u0__DOT__S[22], {des__DOT__u0__DOT__S[29], des__DOT__u0__DOT__S[8]}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}};

Original

logic [32:0]  des__DOT__out0;
assign des__DOT__out0 = {des__DOT__u0__DOT__S[16], {des__DOT__u0__DOT__S[25], {des__DOT__u0__DOT__S[12], {des__DOT__u0__DOT__S[11], {des__DOT__u0__DOT__S[3], {des__DOT__u0__DOT__S[20], {des__DOT__u0__DOT__S[4], {des__DOT__u0__DOT__S[15], {des__DOT__u0__DOT__S[31], {des__DOT__u0__DOT__S[17], {des__DOT__u0__DOT__S[9], {des__DOT__u0__DOT__S[6], {des__DOT__u0__DOT__S[27], {des__DOT__u0__DOT__S[14], {des__DOT__u0__DOT__S[1], {des__DOT__u0__DOT__S[22], {des__DOT__u0__DOT__S[30], {des__DOT__u0__DOT__S[24], {des__DOT__u0__DOT__S[8], {des__DOT__u0__DOT__S[18], {des__DOT__u0__DOT__S[0], {des__DOT__u0__DOT__S[5], {des__DOT__u0__DOT__S[29], {des__DOT__u0__DOT__S[23], {des__DOT__u0__DOT__S[13], {des__DOT__u0__DOT__S[19], {des__DOT__u0__DOT__S[2], {des__DOT__u0__DOT__S[26], {des__DOT__u0__DOT__S[10], {des__DOT__u0__DOT__S[21], {des__DOT__u0__DOT__S[28], des__DOT__u0__DOT__S[7]}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}};

Shift1

logic [32:0]  des__DOT__out0;
assign des__DOT__out0 = {des__DOT__u0__DOT__S[17], {des__DOT__u0__DOT__S[26], {des__DOT__u0__DOT__S[13], {des__DOT__u0__DOT__S[12], {des__DOT__u0__DOT__S[4], {des__DOT__u0__DOT__S[21], {des__DOT__u0__DOT__S[5], {des__DOT__u0__DOT__S[16], {des__DOT__u0__DOT__S[32], {des__DOT__u0__DOT__S[18], {des__DOT__u0__DOT__S[10], {des__DOT__u0__DOT__S[7], {des__DOT__u0__DOT__S[28], {des__DOT__u0__DOT__S[15], {des__DOT__u0__DOT__S[2], {des__DOT__u0__DOT__S[23], {des__DOT__u0__DOT__S[31], {des__DOT__u0__DOT__S[25], {des__DOT__u0__DOT__S[9], {des__DOT__u0__DOT__S[19], {des__DOT__u0__DOT__S[1], {des__DOT__u0__DOT__S[6], {des__DOT__u0__DOT__S[30], {des__DOT__u0__DOT__S[24], {des__DOT__u0__DOT__S[14], {des__DOT__u0__DOT__S[20], {des__DOT__u0__DOT__S[3], {des__DOT__u0__DOT__S[27], {des__DOT__u0__DOT__S[11], {des__DOT__u0__DOT__S[22], {des__DOT__u0__DOT__S[29], des__DOT__u0__DOT__S[8]}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}};

sub.v

module sub(in, out);
input in;
output reg [1:2] out;
always @(*) begin
        case(in)
                0: out = 0;
                1: out = 3;
        endcase
end
endmodule

top.v

module top(in, out);
input [3:0]  in;
output [7:0] out;
reg [1:8] proc;

sub u1(.in(in[0]), .out(proc[1:2]));
sub u2(.in(in[1]), .out(proc[3:4]));
sub u3(.in(in[2]), .out(proc[5:6]));
sub u4(.in(in[3]), .out(proc[7:8]));
assign out = { proc[8], proc[1], proc[4], proc[2], proc[5], proc[6], proc[7], proc[3] };
endmodule

ver1.v

module top(in, out);
input logic [3:0]  in;
output logic [7:0]  out;
logic [3:0]  top__DOT__in;
logic [7:0]  top__DOT__out;
logic [8:0]  top__DOT__proc;
logic [2:0]  top__DOT____Vcellout__u1__out;
logic top__DOT____Vcellinp__u1__in;
logic [2:0]  top__DOT____Vcellout__u2__out;
logic top__DOT____Vcellinp__u2__in;
logic [2:0]  top__DOT____Vcellout__u3__out;
logic top__DOT____Vcellinp__u3__in;
logic [2:0]  top__DOT____Vcellout__u4__out;
logic top__DOT____Vcellinp__u4__in;
logic top__DOT__u1__DOT__in;
logic [2:0]  top__DOT__u1__DOT__out;
logic top__DOT__u2__DOT__in;
logic [2:0]  top__DOT__u2__DOT__out;
logic top__DOT__u3__DOT__in;
logic [2:0]  top__DOT__u3__DOT__out;
logic top__DOT__u4__DOT__in;
logic [2:0]  top__DOT__u4__DOT__out;
assign top__DOT__proc = {top__DOT____Vcellout__u1__out, {top__DOT____Vcellout__u2__out, {top__DOT____Vcellout__u3__out, top__DOT____Vcellout__u4__out}}};
assign out = {top__DOT__proc[0], {top__DOT__proc[7], {top__DOT__proc[4], {top__DOT__proc[6], {top__DOT__proc[3], {top__DOT__proc[2], {top__DOT__proc[1], top__DOT__proc[5]}}}}}}};
always @(*) begin
if (in[0]) begin
if (in[0]) begin
top__DOT____Vcellout__u1__out = 2'h3;
end
end
else begin
top__DOT____Vcellout__u1__out = 2'h0;
end
end
always @(*) begin
if (in[1]) begin
if (in[1]) begin
top__DOT____Vcellout__u2__out = 2'h3;
end
end
else begin
top__DOT____Vcellout__u2__out = 2'h0;
end
end
always @(*) begin
if (in[2]) begin
if (in[2]) begin
top__DOT____Vcellout__u3__out = 2'h3;
end
end
else begin
top__DOT____Vcellout__u3__out = 2'h0;
end
end
always @(*) begin
if (in[3]) begin
if (in[3]) begin
top__DOT____Vcellout__u4__out = 2'h3;
end
end
else begin
top__DOT____Vcellout__u4__out = 2'h0;
end
end
endmodule

ver2.v

module top(in, out);
input logic [3:0]  in;
output logic [7:0]  out;
logic [3:0]  top__DOT__in;
logic [7:0]  top__DOT__out;
logic [8:0]  top__DOT__proc;
logic [2:1]  top__DOT____Vcellout__u1__out;
logic top__DOT____Vcellinp__u1__in;
logic [2:1]  top__DOT____Vcellout__u2__out;
logic top__DOT____Vcellinp__u2__in;
logic [2:1]  top__DOT____Vcellout__u3__out;
logic top__DOT____Vcellinp__u3__in;
logic [2:1]  top__DOT____Vcellout__u4__out;
logic top__DOT____Vcellinp__u4__in;
logic top__DOT__u1__DOT__in;
logic [2:0]  top__DOT__u1__DOT__out;
logic top__DOT__u2__DOT__in;
logic [2:0]  top__DOT__u2__DOT__out;
logic top__DOT__u3__DOT__in;
logic [2:0]  top__DOT__u3__DOT__out;
logic top__DOT__u4__DOT__in;
logic [2:0]  top__DOT__u4__DOT__out;
assign top__DOT__proc = {top__DOT____Vcellout__u1__out, {top__DOT____Vcellout__u2__out, {top__DOT____Vcellout__u3__out, top__DOT____Vcellout__u4__out}}};
assign out = {top__DOT__proc[0], {top__DOT__proc[7], {top__DOT__proc[4], {top__DOT__proc[6], {top__DOT__proc[3], {top__DOT__proc[2], {top__DOT__proc[1], top__DOT__proc[5]}}}}}}};
always @(*) begin
if (in[0]) begin
if (in[0]) begin
top__DOT____Vcellout__u1__out = 2'h3;
end
end
else begin
top__DOT____Vcellout__u1__out = 2'h0;
end
end
always @(*) begin
if (in[1]) begin
if (in[1]) begin
top__DOT____Vcellout__u2__out = 2'h3;
end
end
else begin
top__DOT____Vcellout__u2__out = 2'h0;
end
end
always @(*) begin
if (in[2]) begin
if (in[2]) begin
top__DOT____Vcellout__u3__out = 2'h3;
end
end
else begin
top__DOT____Vcellout__u3__out = 2'h0;
end
end
always @(*) begin
if (in[3]) begin
if (in[3]) begin
top__DOT____Vcellout__u4__out = 2'h3;
end
end
else begin
top__DOT____Vcellout__u4__out = 2'h0;
end
end
endmodule