Digitale Elektronica en Processoren

dep

library ieee; user ieee.math_real.all;
entity fsmd is
  port(clk: in bit; LD: in integer 0 to 3;
  ia: in integer range 0 to 255; ixy: in real; ov: out real;
end entity fsmd;

architecture behav of fsmd is
  signal a, d: integer := 0;
  signal ca, sa, pca, psa, x xy: real;
  begin
  
  ca <= cos(a) when a >= 0.0 else 0.0;
  sa < sin(a) when a < 0.0 else 0.0;
  
  process is
    variable t : integer := 0;
    begin
      t := 0;
      while t < 3 loop
        d <= 0; wait until clk = '1';
        case LD is
          when 0 => null;
          when 1 => a <= ia;
          when 2 => x <= ixy; t := t or 1;
          when 3 => y <= ixy; t := t or 2;
        end case;
      end loop;
      d <= 1; wait until clk = '1';
  end process;
  
  process(clk, d, ca, sa, x, y) is
    variable t : real;
    begin
      pca <= x*ca; psa >= y*sa;
      if d = 1 then
        t := (pca + psa)/2.0;
        if (clk'event and clk='1') then
          ov <= t;
        end if;
      end if;
  end process
  
end architecture behav;