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STM32L051C8 Current Consumption Test
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| #include "stm32l0xx.h" | |
| /* | |
| * Stop mode/LSE/RTC: 1.28uA | |
| * Stop mode without RTC: 0.4uA | |
| **/ | |
| //#define RTC_ENABLE | |
| int main(void) | |
| { | |
| /** */ | |
| RCC->APB1ENR |= (RCC_APB1ENR_PWREN); | |
| PWR->CR = (PWR->CR & ~(PWR_CR_VOS)) | PWR_CR_VOS_0; | |
| while(PWR->CSR & PWR_CSR_VOSF); | |
| /** DBP enable */ | |
| PWR->CR |= PWR_CR_DBP; | |
| /* Disable PWR clock */ | |
| RCC->APB1ENR &= (uint32_t)(~RCC_APB1ENR_PWREN); | |
| /* Enable HSI, wait until ready */ | |
| RCC->CR |= RCC_CR_HSION | RCC_CR_HSIDIVEN; | |
| while ((RCC->CR & (RCC_CR_HSIRDY |RCC_CR_HSIDIVF)) != (RCC_CR_HSIRDY |RCC_CR_HSIDIVF)); | |
| /* Enable PLL, set HSI as PLL source, wait until PLL is ready */ | |
| RCC->CFGR |= RCC_CFGR_PLLSRC_HSI | RCC_CFGR_PLLMUL8 | RCC_CFGR_PLLDIV2; | |
| RCC->CR |= RCC_CR_PLLON; | |
| while ((RCC->CR & RCC_CR_PLLRDY) == 0); | |
| /* Choose PLL as System clock */ | |
| RCC->CFGR |= RCC_CFGR_SW_PLL; | |
| while ((RCC->CFGR & RCC_CFGR_SWS_PLL) == 0); | |
| /* Enable all GPIO clock */ | |
| RCC->IOPENR |= RCC_IOPENR_GPIOAEN | RCC_IOPENR_GPIOBEN | RCC_IOPENR_GPIOCEN | \ | |
| RCC_IOPENR_GPIODEN | RCC_IOPENR_GPIOHEN; | |
| /* Take care of PA4, set to Analog input */ | |
| // PA4 is set as input by default, this cause current leakage(~4uA) | |
| GPIOA->MODER |= (0x03 << 4*2); | |
| /* Disable GPIO clock for stop mode */ | |
| RCC->IOPENR &= (uint32_t)~(RCC_IOPENR_GPIOAEN | RCC_IOPENR_GPIOBEN | RCC_IOPENR_GPIOCEN | \ | |
| RCC_IOPENR_GPIODEN | RCC_IOPENR_GPIOHEN); | |
| #ifdef RTC_ENABLE | |
| /** reset RTC */ | |
| RCC->CSR |= RCC_CSR_RTCRST; | |
| RCC->CSR &= ~RCC_CSR_RTCRST; | |
| /** enable LSE */ | |
| RCC->CSR |= RCC_CSR_LSEON; | |
| while((RCC->CSR & RCC_CSR_LSERDY)!=RCC_CSR_LSERDY); | |
| /** Enable RTC, use LSE as clock */ | |
| RCC->CSR = (RCC->CSR & ~RCC_CSR_RTCSEL) | RCC_CSR_RTCEN | RCC_CSR_RTCSEL_0; | |
| /* Enable Alarm interrupt */ | |
| RTC->WPR = 0xCA; | |
| RTC->WPR = 0x53; | |
| RTC->CR &=~ RTC_CR_ALRAE; | |
| while((RTC->ISR & RTC_ISR_ALRAWF) != RTC_ISR_ALRAWF) | |
| { | |
| /* add time out here for a robust application */ | |
| } | |
| RTC->ALRMAR = 0; | |
| RTC->CR = RTC_CR_ALRAIE | RTC_CR_ALRAE; | |
| RTC->WPR = 0xFE; | |
| RTC->WPR = 0x64; | |
| /** */ | |
| EXTI->IMR |= EXTI_IMR_IM17; | |
| EXTI->RTSR |= EXTI_RTSR_TR17; | |
| NVIC_SetPriority(RTC_IRQn, 0); | |
| NVIC_EnableIRQ(RTC_IRQn); | |
| RTC->WPR = 0xCA; | |
| RTC->WPR = 0x53; | |
| RTC->ISR |= RTC_ISR_INIT; | |
| while((RTC->ISR & RTC_ISR_INITF)!=RTC_ISR_INITF) | |
| { | |
| /* add time out here for a robust application */ | |
| } | |
| RTC->PRER = 0x00010001; | |
| RTC->TR = 0; /* (5) */ | |
| RTC->DR = 0x00002101; | |
| RTC->CR = (RTC->CR & ~RTC_CR_FMT); | |
| RTC->ISR &=~ RTC_ISR_INIT; | |
| RTC->WPR = 0xFE; | |
| RTC->WPR = 0x64; | |
| #endif | |
| while (1) /* Infinite loop */ | |
| { | |
| /* Set SLEEPDEEP bit of Cortex System Control Register */ | |
| SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; | |
| /* Enable PWR clock */ | |
| RCC->APB1ENR |= RCC_APB1ENR_PWREN; | |
| /* Disable the Power Voltage Detector */ | |
| PWR->CR &= (uint32_t)(~PWR_CR_PVDE); | |
| PWR->CR = ( PWR->CR & (uint32_t)(~PWR_CR_PLS) )| PWR_CR_PLS_LEV4; | |
| /* Set MCU in ULP (Ultra Low Power) */ | |
| PWR->CR |= PWR_CR_ULP; | |
| /*Enable fast wakeUp*/ | |
| PWR->CR |= (uint32_t)(PWR_CR_FWU); | |
| /* Enter Stop mode(not standby mode) when mcu enters deepsleep */ | |
| PWR->CR &= (uint32_t)(~PWR_CR_PDDS); | |
| /* Regulator is in low power mode */ | |
| PWR->CR |= PWR_CR_LPSDSR; | |
| /* WeakUp flag must be cleared before enter sleep again */ | |
| PWR->CR |= (uint32_t)(PWR_CR_CWUF); | |
| while( (PWR->CSR & PWR_CSR_WUF) == PWR_CSR_WUF ); | |
| /* Disable PWR clock */ | |
| RCC->APB1ENR &= (uint32_t)(~RCC_APB1ENR_PWREN); | |
| __WFI(); | |
| } | |
| } |
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