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| #include <stdio.h> | |
| #include <signal.h> | |
| #include <setjmp.h> | |
| #include <unistd.h> | |
| #include <stdlib.h> | |
| #include <string.h> | |
| #include <stdint.h> | |
| #include <pthread.h> | |
| #include <errno.h> | |
| #include <sys/mman.h> |
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| <!DOCTYPE html><html lang="en"><head><meta name="viewport" content="width=device-width"><meta charset="utf-8"> | |
| <meta name="pluto-insertion-spot-meta"> | |
| <meta name="theme-color" media="(prefers-color-scheme: light)" content="white"><meta name="theme-color" media="(prefers-color-scheme: dark)" content="#2a2928"><meta name="color-scheme" content="light dark"><link rel="icon" type="image/png" sizes="16x16" href="https://cdn.jsdelivr.net/gh/fonsp/[email protected]/frontend-dist/favicon-16x16.347d2855.png" integrity="sha384-3qsGeVLdddzV9oIkj3PhXXQX2CZCjOD/CiyrPQOX6InOWw3HAHClrsQhPfX9uRAj" crossorigin="anonymous"><link rel="icon" type="image/png" sizes="32x32" href="https://cdn.jsdelivr.net/gh/fonsp/[email protected]/frontend-dist/favicon-32x32.8789add4.png" integrity="sha384-cOe5vSoBIgKNgkUL27p9RpsGVY0uBg9PejLccDy+fR8ZD1Iv5dF1MGHjIZAIZwm6" crossorigin="anonymous"><link rel="icon" type="image/png" sizes="96x96" href="https://cdn.jsdelivr.net/gh/fonsp/[email protected]/frontend-dist/favicon-96x96.48689391.png" integrity="sh |
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| commit ec046ffc2b8b9ed6916e402ee580e18da6673709 | |
| Author: Keno Fischer <[email protected]> | |
| Date: Sun Jul 3 01:53:53 2022 +0000 | |
| WIP: AMD CPUID override | |
| Since e9ea1e7, we've had the ability to turn a userspace `cpuid` | |
| instruction into a SIGSEGV using the ARCH_(GET|SET)_CPUID arch_prctl. | |
| However, this capability is limited to supported hardware, which | |
| currently means Intel CPUs. AMD CPUs do not have a documented facility |
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| /* -*- Mode: C; tab-width: 8; c-basic-offset: 2; indent-tabs-mode: nil; -*- */ | |
| #include "util.h" | |
| pid_t main_thread_tid = 0; | |
| int fds[2]; | |
| char zeros[8192]; | |
| void sigproc_and_hang(void) | |
| { |
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| ------------------------------------------ | |
| 7) rr:juli-21726 => rr-21725 | |
| ------------------------------------------ | |
| 7) | switch_mm_irqs_off() { | |
| 7) 1.624 us | load_new_mm_cr3(); | |
| 7) 8.897 us | } | |
| ------------------------------------------ | |
| 7) rr-21725 => rr:juli-21726 | |
| ------------------------------------------ |
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| define internal {} addrspace(10)* @japi1_vect_42283({} addrspace(10)** %0, i32 %1) #0 { | |
| top: | |
| %2 = sext i32 %1 to i64 | |
| %3 = load atomic {} addrspace(10)* ({} addrspace(10)*, i64)*, {} addrspace(10)* ({} addrspace(10)*, i64)** bitcast (void ()** @jlplt_ijl_alloc_array_1d_10294_got to {} addrspace(10)* ({} addrspace(10)*, i64)**) unordered, align 8 | |
| %4 = call {} addrspace(10)* %3({} addrspace(10)* null, i64 0) | |
| %5 = bitcast {} addrspace(10)** %0 to { {} addrspace(10)*, i64 } addrspace(10)** | |
| %6 = load { {} addrspace(10)*, i64 } addrspace(10)*, { {} addrspace(10)*, i64 } addrspace(10)** %5, align 8, !tbaa !0 | |
| %7 = bitcast {} addrspace(10)* %4 to { {} addrspace(10)*, i64 } addrspace(13)* addrspace(10)* | |
| %8 = addrspacecast { {} addrspace(10)*, i64 } addrspace(13)* addrspace(10)* %7 to { {} addrspace(10)*, i64 } addrspace(13)* addrspace(11)* | |
| %9 = load { {} addrspace(10)*, i64 } addrspace(13)*, { {} addrspace(10)*, i64 } addrspace(13)* addrspace(11)* %8, align 8, !tbaa !5 |
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| target triple = "x86_64-unknown-linux-gnu" | |
| @SUM.CoreDOT.Tuple5334 = external dso_local global {}* | |
| @jlplt_ijl_alloc_array_1d_10294_got = external dso_local global void ()* | |
| @jl_sysimg_gvars = constant [15411 x i64*] [i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* undef, i64* |
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| module TortureTest | |
| # Scalability parameters - set here to roughly match the real world usecase | |
| # though that use case does more work. | |
| const NFIELDS = 888 | |
| const NSET = 387 | |
| const NREPS = 40 | |
| using Random | |
| using Base.Meta |
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| --- nv-pci.c 2022-01-08 23:12:19.137095516 +0000 | |
| +++ /usr/src/nvidia-495.46/nvidia/nv-pci.c 2022-01-09 00:05:21.323360921 +0000 | |
| @@ -217,7 +217,78 @@ | |
| +#define NV_GPU_BAR1 1 | |
| +static int nv_resize_pcie_bars(struct pci_dev *pci_dev) { | |
| + struct pci_host_bridge *host; | |
| + u16 cmd; |