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April 30, 2016 05:16
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| import x86instructions | |
| import re | |
| x86Registers = { | |
| # 8 bit | |
| "AL":(8), "CL":(8), "DL":(8), "BL":(8), | |
| "AH":(8), "CH":(8), "DH":(8), "BH":(8), | |
| # 16 bit | |
| "AX":(16),"CX":(16),"DX":(16),"BX":(16), | |
| "SP":(16),"BP":(16),"SI":(16),"DI":(16), | |
| # Segment | |
| "CS":(16), "DS":(16), "ES":(16), "FS":(16), "GS":(16), "SS":(16), | |
| # 32 bit | |
| "EAX":(32),"ECX":(32),"EDX":(32),"EBX":(32), | |
| "ESP":(32),"EBP":(32),"ESI":(32),"EDI":(32), | |
| # 64 bit | |
| "RAX":(64),"RCX":(64),"RDX":(64),"RBX":(64), | |
| "RSP":(64),"RBP":(64),"RSI":(64),"RDI":(64), | |
| "R8" :(64),"R9" :(64),"R10":(64),"R11":(64), | |
| "R12":(64),"R13":(64),"R14":(64),"R15":(64), | |
| } | |
| def tryint(str, h=10): | |
| if str == "": | |
| return 0; | |
| return int(str, h); | |
| pass | |
| class x86Operand: | |
| def __init__(self, str, index): | |
| self.str = str; | |
| self.index = index; | |
| self.sizes = []; | |
| self.rtype = ""; | |
| self.type = ""; | |
| self.fregs = []; | |
| self.IsValid = False; | |
| if str == "": return; | |
| if not self.GetFixedRegister(): | |
| self.GetSizes(); | |
| self.GetType(); | |
| pass | |
| def GetFixedRegister(self): | |
| op = str.upper(self.str); | |
| if x86Registers.has_key(op): | |
| self.type = "Register"; | |
| if self.str[0:] == "e": | |
| self.fregs.append("Register." + self.str[1:]); | |
| self.fregs.append("Register.E" + self.str[1:]); | |
| elif self.str[0:] == "r": | |
| self.fregs.append("Register." + self.str[1:]); | |
| self.fregs.append("Register.E" + self.str[1:]); | |
| self.fregs.append("Register.R" + self.str[1:]); | |
| else: | |
| self.fregs.append("Register." + op); | |
| return True; | |
| return False; | |
| pass | |
| def GetSizes(self): | |
| for sz in re.findall("(\d+)", self.str): | |
| self.sizes.append(sz); | |
| pass | |
| def GetType(self): | |
| if self.str.startswith("r/m"): | |
| self.type = "EffectiveAddress"; | |
| elif self.str.startswith("moff"): | |
| self.type = "MemoryOffset"; | |
| elif self.str.startswith("imm"): | |
| self.type = "Immedicate"; | |
| elif self.str.startswith("r"): | |
| self.type = "Register"; | |
| elif self.str.startswith("m"): | |
| self.type = "Memory"; | |
| pass | |
| def GetRegisterType(self): | |
| if self.type == "Register": | |
| if self.str in ["CRn", "CR0"]: | |
| self.rtype = "Control"; | |
| elif self.str == "DRn": | |
| self.rtype = "Debug"; | |
| pass | |
| pass | |
| class x86Instr: | |
| def __init__(self, mnem, operands, pref, pref0f, opcode, enc, mode, lock, desc): | |
| self.mnem = mnem; | |
| self.operands = self.parseOperands(operands); | |
| self.prefix = pref; | |
| self.prefix0F = pref0f; | |
| self.opcode = opcode; | |
| self.isX64 = self.parseIs64(mode); | |
| self.lock = lock; | |
| self.desc = desc; | |
| self.encoding, self.opcField = self.parseEncoding(enc); | |
| pass | |
| def parseOperands(self, op): | |
| oplist = [] | |
| for x in range(0, len(op)): | |
| operand = x86Operand(op[x], x); | |
| if operand.IsValid: | |
| oplist.append(operand) | |
| return oplist | |
| pass | |
| def parseEncoding(self, enc): | |
| enc = enc.strip().lower(); | |
| if enc == "a": | |
| return "AddToOpcode", None; | |
| if enc == "r": | |
| return "Reg", None; | |
| if enc in ['0','1','2','3','4','5','6','7']: | |
| return "ModRM", int(enc, 10); | |
| return None, None; | |
| pass | |
| def parseIs64(self, str): | |
| return str.strip().upper() == "E"; | |
| pass | |
| pass | |
| class InstrDb: | |
| def __init__(self, db): | |
| self.map = { } | |
| for instr in db: | |
| mnem = instr["name"] | |
| if not self.map.has_key(mnem): | |
| self.map[mnem] = []; | |
| self.map[mnem].append(x86Instr( | |
| mnem, | |
| instr["operands"], | |
| instr["pref"], | |
| instr["pref0F"], | |
| instr["opcode"], | |
| instr["enc"], | |
| instr["mode"], | |
| instr["lock"], | |
| instr["desc"] | |
| )) | |
| pass | |
| #def generate(self, path): | |
| # for name in sorted(self.map): | |
| # | |
| #pass | |
| pass | |
| db = InstrDb(x86instructions.instruction_list) |
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