kunyi@kunyi-TP-P53:/tmp/pico-examples$ mkdir build
kunyi@kunyi-TP-P53:/tmp/pico-examples$ cd build/
kunyi@kunyi-TP-P53:/tmp/pico-examples/build$ cmake .. -DPICO_PLATFORM=rp2350 -DPICO_BOARD=pico2 -DPICO_SDK_PATH=/tmp/pico-sdk -DPICO_EXAMPLES_PATH=/tmp/pico-examples
PICO_SDK_PATH is /tmp/pico-sdk
Target board (PICO_BOARD) is 'pico2'.
Using board configuration from /tmp/pico-sdk/src/boards/include/boards/pico2.h
Pico Platform (PICO_PLATFORM) is 'rp2350-arm-s'.
Defaulting compiler (PICO_COMPILER) to 'pico_arm_cortex_m33_gcc' since not specified.
Configuring toolchain based on PICO_COMPILER 'pico_arm_cortex_m33_gcc'
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kunyi@kunyi-TP-P53:/tmp/blink$ idf.py -p /dev/ttyUSB0 flash monitor | |
Executing action: flash | |
Running ninja in directory /tmp/blink/build | |
Executing "ninja flash"... | |
[1/5] cd /tmp/blink/build/esp-idf/esptool_py && /home/kunyi/.espressif/python_env/idf5.3_py3.10_env/bin/python /home/... --offset 0x8000 partition --type app /tmp/blink/build/partition_table/partition-table.bin /tmp/blink/build/blink.bin | |
blink.bin binary size 0x2b230 bytes. Smallest app partition is 0x100000 bytes. 0xd4dd0 bytes (83%) free. | |
[1/1] cd /tmp/blink/build/bootloader/esp-idf/esptool_py && /home/kunyi/.espressif/python_env/idf5.3_py3.10_env/bin/py...omponents/partition_table/check_sizes.py --offset 0x8000 bootloader 0x1000 /tmp/blink/build/bootloader/bootloader.bin | |
Bootloader binary size 0x6880 bytes. 0x780 bytes (7%) free. | |
[4/5] cd /home/kunyi/esp-idf/components/esptool_py && /usr/bin/cmake -D IDF_PATH=/home/kunyi/esp-idf -D "SERIAL_TOOL=...@flash_args" -D WORKING_DIRECTORY=/tmp/blink/build -P /home/kunyi/esp-idf/components/esptool_py/run |
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AMLI(? for help)-> g | |
g | |
If(Arg0=0x5) | |
ffffbd07d39b7e8e: | { | |
ffffbd07d39b7e8e: | | \_SB_.TPM_.TPTS(Arg0=0x5) | |
ffffbd07d3b28142: | | { | |
ffffbd07d3b28142: | | | Name(_T_0,Zero) | |
ffffbd07d3b28148: | | | While(One) | |
ffffbd07d3b2814c: | | | { | |
ffffbd07d3b2814c: | | | | Store(ToInteger(Arg0=0x5,)=0x5,_T_0)=0x5 |
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[NOTE ] coreboot-24.05-707-gc64bf8155bc3-dirty Tue Aug 06 14:33:11 UTC 2024 x86_32 bootblock starting (log level: 8)... | |
[DEBUG] CPU: Intel(R) N100 | |
[DEBUG] CPU: ID b06e0, Alderlake-N Platform, ucode: 00000017 | |
[DEBUG] CPU: AES supported, TXT NOT supported, VT supported | |
[INFO ] Cache: Level 3: Associativity = 12 Partitions = 1 Line Size = 64 Sets = 8192 | |
[INFO ] Cache size = 6 MiB | |
[DEBUG] MCH: device id 461c (rev 00) is Alderlake-N | |
[DEBUG] PCH: device id 5481 (rev 00) is Alderlake-N SKU |
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CPU: ID 0xb06e0, Processor Type 0x0, Family 0x6, Model 0xbe, Stepping 0x0 | |
Northbridge: 8086:461c (12th generation (Alder Lake N family) Intel Processor) | |
Southbridge: 8086:5481 (Alder Lake-N) | |
IGD: 8086:46d1 (Intel(R) UHD Graphics) | |
SBREG_BAR = 0xfd000000 (MEM) | |
============= GPIOS ============= | |
------- GPIO Community 0 ------- |
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superiotool r24.05-707-gc64bf8155bc | |
Found ITE IT8613E (id=0x8613, rev=0xc) at 0x2e | |
Register dump: | |
idx def val | |
0x20: 0x86 0x86 | |
0x21: 0x13 0x13 | |
0x22: 0x05 [0x0c] | |
0x23: 0x40 0x40 | |
0x24: 0x00 0x00 | |
0x2b: 0x48 [0x08] |
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27 10 13 0E 16 22 B9 08 00 40 00 00 02 01 00 00 | |
48 00 0A FF 92 55 05 00 AA 00 90 A8 90 C0 08 60 | |
04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | |
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | |
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | |
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | |
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | |
00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 | |
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | |
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |
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/* SPDX-License-Identifier: GPL-2.0-only */ | |
#include <baseboard/gpio.h> | |
#include <baseboard/variants.h> | |
#include <commonlib/helpers.h> | |
/* Pad configuration in ramstage*/ | |
static const struct pad_config gpio_table[] = { | |
/* ESPI_IO0_EC_R / ESPI_IO0_HDR */ | |
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), |
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/* SPDX-License-Identifier: GPL-2.0-only */ | |
#include <baseboard/variants.h> | |
#include <console/console.h> | |
#include <soc/romstage.h> | |
static const struct mb_cfg mu_lp5_mem_config = { | |
.type = MEM_TYPE_LP5X, | |
/* DQ byte map */ |
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[NOTE ] coreboot-96a61745ea29-dirty Mon Jul 29 10:28:36 UTC 2024 x86_32 bootblock starting (log level: 7)... | |
[DEBUG] CPU: Intel(R) N100 | |
[DEBUG] CPU: ID b06e0, Alderlake-N Platform, ucode: 00000015 | |
[DEBUG] CPU: AES supported, TXT NOT supported, VT supported | |
[INFO ] Cache: Level 3: Associativity = 12 Partitions = 1 Line Size = 64 Sets = 8192 | |
[INFO ] Cache size = 6 MiB | |
[DEBUG] MCH: device id 461c (rev 00) is Alderlake-N | |
[DEBUG] PCH: device id 5481 (rev 00) is Alderlake-N SKU | |
[DEBUG] IGD: device id 46d1 (rev 00) is Alderlake N GT2 | |
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x610000. |
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