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@KunYi
KunYi / mu_res_dbg.log
Created August 12, 2024 11:01
LattePanda_MU_DebugResource.log
[NOTE ] coreboot-24.05-707-gc64bf8155bc3-dirty Tue Aug 06 14:33:11 UTC 2024 x86_32 bootblock starting (log level: 8)...
[DEBUG] CPU: Intel(R) N100
[DEBUG] CPU: ID b06e0, Alderlake-N Platform, ucode: 00000017
[DEBUG] CPU: AES supported, TXT NOT supported, VT supported
[INFO ] Cache: Level 3: Associativity = 12 Partitions = 1 Line Size = 64 Sets = 8192
[INFO ] Cache size = 6 MiB
[DEBUG] MCH: device id 461c (rev 00) is Alderlake-N
[DEBUG] PCH: device id 5481 (rev 00) is Alderlake-N SKU
@KunYi
KunYi / inteltool.log
Created August 7, 2024 09:46
inteltool/coreboot dump for intelp2m convert GPIOs setting
CPU: ID 0xb06e0, Processor Type 0x0, Family 0x6, Model 0xbe, Stepping 0x0
Northbridge: 8086:461c (12th generation (Alder Lake N family) Intel Processor)
Southbridge: 8086:5481 (Alder Lake-N)
IGD: 8086:46d1 (Intel(R) UHD Graphics)
SBREG_BAR = 0xfd000000 (MEM)
============= GPIOS =============
------- GPIO Community 0 -------
@KunYi
KunYi / lattepanda_mu_sio_dump.log
Created August 7, 2024 09:26
LattePanda-MU SuperIO registers dump
superiotool r24.05-707-gc64bf8155bc
Found ITE IT8613E (id=0x8613, rev=0xc) at 0x2e
Register dump:
idx def val
0x20: 0x86 0x86
0x21: 0x13 0x13
0x22: 0x05 [0x0c]
0x23: 0x40 0x40
0x24: 0x00 0x00
0x2b: 0x48 [0x08]
@KunYi
KunYi / mu_lp5_8gb.spd.hex
Last active July 31, 2024 10:29
SPD for LattePanda MU LP5 8GB
27 10 13 0E 16 22 B9 08 00 40 00 00 02 01 00 00
48 00 0A FF 92 55 05 00 AA 00 90 A8 90 C0 08 60
04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
@KunYi
KunYi / gpio.c
Created July 31, 2024 08:55
LattePanda Mu GPIO Inititionlization Code for EMMC/HDMI(DDIB)
/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
/* Pad configuration in ramstage*/
static const struct pad_config gpio_table[] = {
/* ESPI_IO0_EC_R / ESPI_IO0_HDR */
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
@KunYi
KunYi / lattepanda_mu_memory_parameters.c
Created July 29, 2024 13:45
memory initial parameters for LattePanda MU
/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/variants.h>
#include <console/console.h>
#include <soc/romstage.h>
static const struct mb_cfg mu_lp5_mem_config = {
.type = MEM_TYPE_LP5X,
/* DQ byte map */
@KunYi
KunYi / lattepanda_mu_booting.log
Created July 29, 2024 13:43
coreboot on LattePanda Mu booting log
[NOTE ] coreboot-96a61745ea29-dirty Mon Jul 29 10:28:36 UTC 2024 x86_32 bootblock starting (log level: 7)...
[DEBUG] CPU: Intel(R) N100
[DEBUG] CPU: ID b06e0, Alderlake-N Platform, ucode: 00000015
[DEBUG] CPU: AES supported, TXT NOT supported, VT supported
[INFO ] Cache: Level 3: Associativity = 12 Partitions = 1 Line Size = 64 Sets = 8192
[INFO ] Cache size = 6 MiB
[DEBUG] MCH: device id 461c (rev 00) is Alderlake-N
[DEBUG] PCH: device id 5481 (rev 00) is Alderlake-N SKU
[DEBUG] IGD: device id 46d1 (rev 00) is Alderlake N GT2
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x610000.
@KunYi
KunYi / coreboot_fspmemoryinit.log
Created July 28, 2024 10:21
Debugging LatteMu FspMemoryInit()
[NOTE ] coreboot-d7e9b73722fb Sat Jul 27 12:49:33 UTC 2024 x86_32 bootblock starting (log level: 8)...
[DEBUG] CPU: Intel(R) N100
[DEBUG] CPU: ID b06e0, Alderlake-N Platform, ucode: 00000015
[DEBUG] CPU: AES supported, TXT NOT supported, VT supported
[INFO ] Cache: Level 3: Associativity = 12 Partitions = 1 Line Size = 64 Sets = 8192
[INFO ] Cache size = 6 MiB
[DEBUG] MCH: device id 461c (rev 00) is Alderlake-N
[DEBUG] PCH: device id 5481 (rev 00) is Alderlake-N SKU
[DEBUG] IGD: device id 46d1 (rev 00) is Alderlake N GT2
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x610000.
@KunYi
KunYi / LP-BS-S70NC1R200-SR-A.xml
Created July 19, 2024 11:06
LattePanda Mu BIOS CSME Decompress
<?xml version="1.0" ?>
<FitData version="" layout_name="Intel(R) AlderLake N Chipset - Consumer - SPI">
<BuildSettings label="Build Settings">
<BuildResults label="Build Results">
<MeuToolPath value="" label="Intel(R) Manifest Extension Utility Path" help_text="" key="ManifestSigningUtilPlugin:SigningContainer:MeuToolPath"/>
<OpenSSLToolPath value="" label="Open SSL Signing Tool Path" help_text="" key="ManifestSigningUtilPlugin:SigningContainer:OpenSSLToolPath"/>
<SigningEnabled value="Disabled" value_list="['Disabled', 'Enabled']" label="Signing Enabled" help_text="" key="ManifestSigningUtilPlugin:SigningContainer:SigningEnabled"/>
<DescSigningKey value="" label="Descriptor Debug Signing Key" help_text="This is the path to the private debug key used to sign the Descriptor, while public key hash of it is included in the OEM hash manifest. This setting is operative only when Flash Descriptor Verification is enabled (See DescConfiguration/FdvEnabled)." key="Descript
@KunYi
KunYi / 01_SPD_0x00D9977D.txt
Created July 19, 2024 03:32
SPDs informations from LP-BS-S70NC1R200-SR-A.bin of LattePanda MU
23 10 13 0E 15 1A F9 08 00 40 00 00 0A 01 00 00
48 00 0A FF 92 55 05 00 AA 00 90 A8 90 90 06 C0
03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00