Verilog Syntax Cheat Sheet

cheatsheet.v

module module_name(signal_a, signal_b);
  input [7:0] signal_a;
  output signal_b;
endmodule

parameter n = 32;

integer k;
for (k = 0; k < n; k + 1)
begin
  S[k] = ...
end

always @(X, Y, C)
end

begin
  Z = ...
  if (Z < 10)
    {Cout, S} = Z;
  else
    {Cout, S} = Z + 6;
end

begin/end

genvar i;
generate
  for (i = 0; i < n; i = i + 1)
  begin:addbit
    fulladd stage(C[i]...)
  end
endgenerate
(? - stage? syntax or user defined?)

wire [n:0] C;
wire C;

reg i;
integer i;


input [n-1:0] X, Y;
output [n-1:0] S;

S = X + Y; < N-bit adder

& AND
| OR
~ NOT

concatenation
reg [n:0]S;
reg [n-1]X;
S = {1’b0, X};

// Module instance parameter definitions
addern U1 (1’b0, A, B, S[15:0], S[16], o1);
defparam U1.n = 16;

addern #(16) U1 (1’b0, A, B, S[15:0], S[16], o1);

// Named port ordering
addern #(.n(16)) U1 (
  .carryin (1’b0), .X (A),
  .Y (B),
  .S (S[15:0]), .carryout (S[16]), .overflow (o1)
);

// Number representation
<size_in_bits>’<radix_identifier><significant_digits>

12’b100010101001 // binary
2’b1000_1010_1001
12’o4251 // octal
12’h8A9 // hexidecimal
12’d2217 // decimal (can be unspecified)

’h116 // unsized

// Conditional expression
conditional_expression ? true_expression : false_expression
A=(B<C)?(D+5): (D+2);

if (conditional_expression) statement; 
else statement;

case (S)
0: f = W[0];
1: f = W[1];
2: f = W[2];
3: f = W[3];
endcase

// Concatenate
D = {A, B}; (D = a2a1a0b2b1b0)
E = {3’b111, A, 2’b00}; (E = 111a2a1a000)

// Replication
{3{A}}  => {A, A, A}
{4{2’b10}} => 10101010

// Task
// Defined after calling `always` block
task mux4to1;
  input [0:3] X;
  input [1:0] S4;
  output reg g;
  g = X | S...
endtask

// Function
// Defined before calling `always` block
function mux4to1;
  input X;
  input S;
  mux4to1 = X | S;
endfunction

// Blocking Assignment
Q = D

// Non-Blocking Assignment
Q <= D

// FSM Declaring States
parameter [2:1] A = 2’b00, B = 2’b01, C = 2’b10;

repeat(256) @(posedge clk);

// Research
- DUT
- always