Skip to content

Instantly share code, notes, and snippets.

@LoadLow

LoadLow/ethernet_controller.vhd

Last active April 30, 2019 07:38
Show Gist options
  • Save LoadLow/65a68d0f1e123db58a401037aa025285 to your computer and use it in GitHub Desktop.
Save LoadLow/65a68d0f1e123db58a401037aa025285 to your computer and use it in GitHub Desktop.
Download ZIP
Raw
ethernet_controller.vhd
----------------------------------------------------------------------------------
-- Create Date: 09:43:04 03/16/2018
-- Design Name:
-- Module Name: ethernet_controller - Behavioral
-- Project Name: Controller
-- Description: 100mbps ethernet controller
--
-- Dependencies: lfsr25, ethernet_spec
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ethernet_spec.all;
entity ethernet_controller is
port (
CLK10I : in std_logic; -- synchronization clock
RESET : in std_logic; -- low: resets the controller
MAC_ADDR : in macaddr_type; -- mac address of the controller
-- reception ports
R_BYTEP : out std_logic; -- high: byte received and is available in R_DATAO
R_CLEANP : out std_logic; -- high: frame discarded before the end of the reception
R_CVNGP : out std_logic; -- high: receiving (after SFD)
R_SMATIP : out std_logic; -- high: match individual address (i.e when dst mac addr = MAC_ADDR)
R_STARTP : out std_logic; -- high: SFD received
R_DONEP : out std_logic; -- high: frame successfully received
R_ENABP : in std_logic; -- high: enable the reception process
R_DATAI : in etherbyte_type; -- byte received from the network
R_DATAO : out etherbyte_type; -- byte sent to the host
-- transmission ports
T_DONEP : out std_logic; -- high: frame successfully transmitted
T_READDP : out std_logic; -- high: byte on T_DATAI is going to be read
T_RNSMTP : out std_logic; -- high: the transmitter is handling a frame
T_STARTP : out std_logic; -- high: the transmitter started to process the frame sent by the host
T_SOCOLP : out std_logic; -- high: a collision has been detected
T_SECOLP : out std_logic := '0'; -- high: abort after 16 retransmission retries
T_ABORTP : in std_logic; -- high: resets the transmission process
T_AVAILP : in std_logic; -- high: the host has a frame to send
T_LASTP : in std_logic; -- high: the first bit of the last byte of the frame is sent by the host
T_DATAI : in etherbyte_type; -- byte received from the host
T_DATAO : out etherbyte_type -- byte sent to the network
);
end ethernet_controller;
architecture ethernet_core of ethernet_controller is
-- Left Feedback Shift Register of 25 bits
component lfsr25 port (
CLK10I : in std_logic;
ENABLE : in std_logic;
LOAD_SEED : in std_logic;
SEED_DATA : in std_logic_vector(24 downto 0);
PRND_SEQ : out std_logic_vector(24 downto 0));
end component;
signal lfsr25_enable : std_logic := '0';
signal lfsr25_load_seed : std_logic := '0';
signal lfsr25_seed_data : std_logic_vector(24 downto 0);
signal lfsr25_prnd_seq : std_logic_vector(24 downto 0);
-- Sychronize on byte, read bit per bit
procedure syncbyte (signal byte_offset : inout etherbyte_offset_type;
variable byte_ready : out boolean) is
begin
if byte_offset >= 7 then
byte_offset <= 0;
byte_ready := TRUE;
else
byte_offset <= byte_offset + 1;
byte_ready := FALSE;
end if;
end procedure;
--Internal ports (wired to each appropriate port)
signal int_r_cvngp : std_logic := '0';
signal int_t_rnsmtp : std_logic := '0';
signal int_t_socolp : std_logic := '0';
--Reception context
type r_state_type is (
IDLE_R, ADDR_R, DATA_R
);
signal r_frame_offset : frame_offset_type := 0; -- offset used to count where we are on the current frame
signal r_byte_offset : etherbyte_offset_type := 0; -- offset used to count bit per bit
signal r_curr_state : r_state_type := IDLE_R; -- current state
--Transmission context
type t_state_type is (
IDLE_T, DST_ADDR_T, SRC_ADDR_T, DATA_T, LASTP_T, EFD_T, ABORT_T, COLABORT_T, RWAIT_T
);
signal t_frame_offset : frame_offset_type := 0; -- offset used to count where we are on the current frame
signal t_byte_offset : etherbyte_offset_type := 0; -- offset used to count bit per bit
signal t_curr_state : t_state_type := IDLE_T; -- current state
--Collision retries
signal c_retries_cnt : natural range 0 to 15 := 0; -- number of retries
signal c_retries_wait_curr : natural range 0 to (2 ** 16 - 1) := 0; --current waited slots count
signal c_retries_wait_time : natural range 0 to (2 ** 16 - 1) := 0; --slots count to wait
begin
--Link lfsr25
link_lfsr25 : lfsr25 port map(
CLK10I, lfsr25_enable, lfsr25_load_seed, lfsr25_seed_data, lfsr25_prnd_seq
);
--Reception process
reception : process
variable data_ready : boolean := FALSE; --internally used for byte synchronization (immediate value)
begin
if R_ENABP = '0' then
R_DATAO <= NULL_FRAME;
r_curr_state <= IDLE_R;
r_frame_offset <= 0;
r_byte_offset <= 0;
end if;
wait until R_ENABP = '1' and rising_edge(CLK10I);
--reset asked
if RESET = '0' then
R_DATAO <= NULL_FRAME;
R_BYTEP <= '0';
R_CLEANP <= '0';
int_r_cvngp <= '0';
R_DONEP <= '0';
R_SMATIP <= '0';
R_STARTP <= '0';
r_curr_state <= IDLE_R;
r_frame_offset <= 0;
r_byte_offset <= 0;
--collision occurred
elsif int_t_socolp = '1' and r_curr_state /= IDLE_R then
R_DATAO <= NULL_FRAME;
R_CLEANP <= '1';
int_r_cvngp <= '0';
r_curr_state <= IDLE_R;
r_frame_offset <= 0;
r_byte_offset <= 0;
else
R_STARTP <= '0';
R_CLEANP <= '0';
R_BYTEP <= '0';
R_DONEP <= '0';
case r_curr_state is
when IDLE_R =>
if R_DATAI = START_FRAME then
syncbyte(r_byte_offset, data_ready);
if data_ready then
r_frame_offset <= 0;
r_curr_state <= ADDR_R;
R_STARTP <= '1';
R_BYTEP <= '1';
end if;
end if;
when ADDR_R =>
int_r_cvngp <= '1';
syncbyte(r_byte_offset, data_ready);
if data_ready then
R_BYTEP <= '1';
--checked bounds, [5*8:8*8+7] <=> [40:47]
--offsets 0 to 5 : 6 bytes of mac addr
if r_frame_offset <= 5 then
-- frame_offset * 8 is synthesized : frame_offset << 3
if R_DATAI /= MAC_ADDR((r_frame_offset * 8) to (r_frame_offset * 8 + 7)) then
R_CLEANP <= '1';
int_r_cvngp <= '0';
r_curr_state <= IDLE_R;
elsif r_frame_offset = 5 then
r_curr_state <= DATA_R;
r_byte_offset <= 0;
r_frame_offset <= 0;
else
r_frame_offset <= r_frame_offset + 1;
end if;
else
R_CLEANP <= '1';
int_r_cvngp <= '0';
r_curr_state <= IDLE_R;
end if;
end if;
when DATA_R =>
R_SMATIP <= '1';
syncbyte(r_byte_offset, data_ready);
if data_ready then
R_DATAO <= R_DATAI;
--minimum 6 bytes because we also receive the source mac addr
if r_frame_offset >= 8192 or (r_frame_offset >= 5 and R_DATAI = END_FRAME) then
R_DATAO <= NULL_FRAME;
R_DONEP <= '1';
int_r_cvngp <= '0';
R_SMATIP <= '0';
r_curr_state <= IDLE_R;
else
r_frame_offset <= r_frame_offset + 1;
end if;
R_BYTEP <= '1';
end if;
end case;
end if;
end process reception;
--Transmission process
transmission : process
variable data_ready : boolean := FALSE; --internally used for byte synchronization (immediate value)
begin
wait until rising_edge(CLK10I);
T_STARTP <= '0';
T_DONEP <= '0';
T_READDP <= '0';
--reset is asked
if RESET = '0' then
T_DATAO <= NULL_FRAME;
t_curr_state <= IDLE_T;
t_frame_offset <= 0;
t_byte_offset <= 0;
int_t_rnsmtp <= '0';
--abort signal received
elsif T_ABORTP = '1' and t_curr_state /= ABORT_T then
t_curr_state <= ABORT_T;
T_DATAO <= JAM_PATTERN;
t_byte_offset <= 0;
t_frame_offset <= 0;
int_t_rnsmtp <= '0';
--collision occurred
elsif int_t_socolp = '1' and t_curr_state /= COLABORT_T and t_curr_state /= RWAIT_T then
--maximum: 16 retransmission attempts
if c_retries_cnt >= 15 then
c_retries_cnt <= 0;
t_curr_state <= ABORT_T;
T_SECOLP <= '1';
else
t_curr_state <= COLABORT_T;
end if;
T_DATAO <= JAM_PATTERN;
t_byte_offset <= 0;
t_frame_offset <= 0;
int_t_rnsmtp <= '0';
else
lfsr25_enable <= '1';
lfsr25_load_seed <= '0';
case t_curr_state is
when IDLE_T =>
if T_AVAILP = '1' then
--lfsr is randomized when each transmission attempt starts
lfsr25_load_seed <= '1'; --Enable and init LFSR
lfsr25_seed_data <= MAC_ADDR(23 to 47); --load 25 LSB of source mac address
T_STARTP <= '1';
int_t_rnsmtp <= '1';
T_DATAO <= START_FRAME;
t_curr_state <= DST_ADDR_T;
t_frame_offset <= 0;
t_byte_offset <= 0;
end if;
when DST_ADDR_T =>
syncbyte(t_byte_offset, data_ready);
if data_ready then
T_DATAO <= T_DATAI;
T_READDP <= '1';
--offsets 0 to 5 : 6 bytes of dst mac addr
if t_frame_offset >= 5 then
t_curr_state <= SRC_ADDR_T;
t_frame_offset <= 0;
else
t_frame_offset <= t_frame_offset + 1;
end if;
end if;
when SRC_ADDR_T =>
syncbyte(t_byte_offset, data_ready);
if data_ready then
--offsets 0 to 5 : 6 bytes of src mac addr
--checked bounds, [5*8:5*8+7] <=> [40:47]
if t_frame_offset <= 5 then
T_DATAO <= MAC_ADDR((t_frame_offset * 8) to ((t_frame_offset * 8) + 7));
T_READDP <= '1';
if t_frame_offset = 5 then
t_curr_state <= DATA_T;
t_frame_offset <= 0;
else
t_frame_offset <= t_frame_offset + 1;
end if;
else --should never happend
t_curr_state <= IDLE_T;
end if;
end if;
when DATA_T =>
syncbyte(t_byte_offset, data_ready);
if data_ready then
T_DATAO <= T_DATAI;
T_READDP <= '1';
--it's the first bit of the last byte of the PDU
if t_frame_offset >= 8191 or T_LASTP = '1' then
t_curr_state <= LASTP_T;
end if;
t_frame_offset <= t_frame_offset + 1;
end if;
when LASTP_T =>
syncbyte(t_byte_offset, data_ready);
if data_ready then
T_DONEP <= '1'; --Done, we just send 8 bits of EFD now
T_DATAO <= END_FRAME;
t_curr_state <= EFD_T;
end if;
when EFD_T =>
syncbyte(t_byte_offset, data_ready);
if data_ready then --efd sent, everything is done
int_t_rnsmtp <= '0';
t_curr_state <= IDLE_T;
--retransmission succeeded
T_SECOLP <= '0';
c_retries_cnt <= 0;
end if;
-- We send the JAM pattern(4 bytes of JAM) and return back to the IDLE state
when ABORT_T =>
syncbyte(t_byte_offset, data_ready);
if data_ready then
if t_frame_offset >= 3 then
T_DONEP <= '1';
T_DATAO <= NULL_FRAME;
T_SECOLP <= '0';
t_curr_state <= IDLE_T;
t_frame_offset <= 0;
else
T_DATAO <= JAM_PATTERN;
t_frame_offset <= t_frame_offset + 1;
end if;
end if;
-- We send the JAM pattern(4 bytes of JAM) and wait M slots
when COLABORT_T =>
syncbyte(t_byte_offset, data_ready);
if data_ready then
if t_frame_offset >= 3 then
T_DONEP <= '1';
T_DATAO <= NULL_FRAME;
--setup transmission backoff algorithm
t_frame_offset <= 0;
c_retries_wait_curr <= 0;
t_curr_state <= RWAIT_T;
--compute next waiting time
--rnd_num % 2^k <=> rnd_num & ((1<<k) - 1) <=> lfsr25_prnd_seq((k-1) downto 0)
--we multiply each slot per 64(add 6 bits of info.) because we will use the byte synchronization
--to wait in 51.2us slots
if (c_retries_cnt >= 9) then
c_retries_wait_time <= to_integer(unsigned(lfsr25_prnd_seq(9 + 6 downto 0)));
else
c_retries_wait_time <= to_integer(unsigned(lfsr25_prnd_seq(c_retries_cnt + 6 downto 0)));
end if;
else
T_DATAO <= JAM_PATTERN;
t_frame_offset <= t_frame_offset + 1;
end if;
end if;
when RWAIT_T =>
syncbyte(t_byte_offset, data_ready);
if data_ready then
-- wait c_retries_wait_time slots, sync on 512 bits for 1 slot = 51.2 us
-- we sync on byte here(which is 0,8us), we multiplied c_retries_wait_time by 64
if c_retries_wait_curr >= c_retries_wait_time then
c_retries_wait_curr <= 0;
c_retries_cnt <= c_retries_cnt + 1;
t_curr_state <= IDLE_T; --start next retransmission iteration
else
c_retries_wait_curr <= c_retries_wait_curr + 1;
end if;
end if;
end case;
end if;
end process transmission;
--Collision detection process
collision : process
begin
wait until rising_edge(CLK10I);
--collision detected when we are receiving and transmitting in the same time
if (int_t_rnsmtp = '1' and int_r_cvngp = '1') then
int_t_socolp <= '1';
else
int_t_socolp <= '0';
end if;
end process collision;
--Wire internal ports to global ports
R_CVNGP <= int_r_cvngp;
T_RNSMTP <= int_t_rnsmtp;
T_SOCOLP <= int_t_socolp;
end ethernet_core;
Raw
ethernet_controller_collision_tb.vhd
--------------------------------------------------------------------------------
-- Create Date: 08:32:00 03/29/2019
-- Module Name: ethernet_controller_collision_tb.vhd
-- Project Name: Controller
-- VHDL Test Bench Created by ISE for module: ethernet_controller
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.ethernet_spec.all;
entity ethernet_controller_collision_tb is
end ethernet_controller_collision_tb;
architecture behavior of ethernet_controller_collision_tb is
-- Component Declaration for the Unit Under Test (UUT)
component ethernet_controller
port (
CLK10I : in std_logic;
RESET : in std_logic;
MAC_ADDR : in std_logic_vector(0 to 47);
R_BYTEP : out std_logic;
R_CLEANP : out std_logic;
R_CVNGP : out std_logic;
R_SMATIP : out std_logic;
R_STARTP : out std_logic;
R_DONEP : out std_logic;
R_ENABP : in std_logic;
R_DATAI : in std_logic_vector(0 to 7);
R_DATAO : out std_logic_vector(0 to 7);
T_DONEP : out std_logic;
T_READDP : out std_logic;
T_RNSMTP : out std_logic;
T_STARTP : out std_logic;
T_SOCOLP : out std_logic;
T_SECOLP : out std_logic;
T_ABORTP : in std_logic;
T_AVAILP : in std_logic;
T_LASTP : in std_logic;
T_DATAI : in std_logic_vector(0 to 7);
T_DATAO : out std_logic_vector(0 to 7)
);
end component;
--Inputs
signal CLK10I : std_logic := '0';
signal RESET : std_logic := '0';
signal MAC_ADDR : std_logic_vector(0 to 47) := (others => '0');
signal R_ENABP : std_logic := '0';
signal R_DATAI : std_logic_vector(0 to 7) := (others => '0');
signal T_ABORTP : std_logic := '0';
signal T_AVAILP : std_logic := '0';
signal T_LASTP : std_logic := '0';
signal T_DATAI : std_logic_vector(0 to 7) := (others => '0');
--BiDirs
signal R_CVNGP : std_logic;
signal T_RNSMTP : std_logic;
--Outputs
signal R_BYTEP : std_logic;
signal R_CLEANP : std_logic;
signal R_SMATIP : std_logic;
signal R_STARTP : std_logic;
signal R_DONEP : std_logic;
signal R_DATAO : std_logic_vector(0 to 7);
signal T_DONEP : std_logic;
signal T_READDP : std_logic;
signal T_STARTP : std_logic;
signal T_SOCOLP : std_logic;
signal T_SECOLP : std_logic;
signal T_DATAO : std_logic_vector(0 to 7);
-- Clock period definitions
constant CLK10I_period : time := 10 ns;
-- Time for 1 byte (bit per bit)
constant BTIME : time := CLK10I_period * 8;
begin
-- Instantiate the Unit Under Test (UUT)
uut : ethernet_controller port map(
CLK10I => CLK10I,
RESET => RESET,
MAC_ADDR => MAC_ADDR,
R_BYTEP => R_BYTEP,
R_CLEANP => R_CLEANP,
R_CVNGP => R_CVNGP,
R_SMATIP => R_SMATIP,
R_STARTP => R_STARTP,
R_DONEP => R_DONEP,
R_ENABP => R_ENABP,
R_DATAI => R_DATAI,
R_DATAO => R_DATAO,
T_DONEP => T_DONEP,
T_READDP => T_READDP,
T_RNSMTP => T_RNSMTP,
T_STARTP => T_STARTP,
T_SOCOLP => T_SOCOLP,
T_SECOLP => T_SECOLP,
T_ABORTP => T_ABORTP,
T_AVAILP => T_AVAILP,
T_LASTP => T_LASTP,
T_DATAI => T_DATAI,
T_DATAO => T_DATAO
);
-- Clock process definitions
CLK10I_process : process
begin
CLK10I <= '0';
wait for CLK10I_period/2;
CLK10I <= '1';
wait for CLK10I_period/2;
end process;
-- Stimulus process
stim_proc : process
begin
--'after' is used here instead of 'wait for'
--Because we are testing 3 processes in the same time (collision, receiver, transmitter)
MAC_ADDR <= X"12345678abcd";
T_AVAILP <= '1' after CLK10I_period * 10 * 5;
RESET <= '1',
'0' after CLK10I_period * 10 * 1,
'1' after CLK10I_period * 10 * 2;
T_DATAI <= X"00",
X"ff" after CLK10I_period * 1000 + CLK10I_period * 10;
R_ENABP <= '0',
'1' after CLK10I_period * 10 * 2,
'0' after 35000ns;
R_DATAI <= START_FRAME after 700ns, --SFD
X"12" after 700ns + BTIME * 1, --first byte of dst mac addr
X"34" after 700ns + BTIME * 2,
X"56" after 700ns + BTIME * 3,
X"78" after 700ns + BTIME * 4,
X"ab" after 700ns + BTIME * 5,
X"cd" after 700ns + BTIME * 6, --last byte of dst mac addr
X"de" after 700ns + BTIME * 7, --6 bytes of src mac addr + junk bytes
END_FRAME after 700ns + BTIME * (7 + 7), --EFD
NULL_FRAME after 700ns + BTIME * (7 + 7 + 4), --null data
--another eth frame after 10*BTIME ns
START_FRAME after 700ns + BTIME * (15 + 10 + 1), -- SFD
X"12" after 700ns + BTIME * (15 + 11) + BTIME * 1, --first byte of dst mac addr
X"34" after 700ns + BTIME * (15 + 11) + BTIME * 2,
X"56" after 700ns + BTIME * (15 + 11) + BTIME * 3,
X"78" after 700ns + BTIME * (15 + 11) + BTIME * 4,
X"ab" after 700ns + BTIME * (15 + 11) + BTIME * 5,
X"cd" after 700ns + BTIME * (15 + 11) + BTIME * 6, --last byte of dst mac addr
X"12" after 700ns + BTIME * (15 + 11 + 6) + BTIME * 1, --first byte of src mac addr
X"34" after 700ns + BTIME * (15 + 11 + 6) + BTIME * 2,
X"56" after 700ns + BTIME * (15 + 11 + 6) + BTIME * 3,
X"78" after 700ns + BTIME * (15 + 11 + 6) + BTIME * 4,
X"de" after 700ns + BTIME * (15 + 11 + 6) + BTIME * 5,
X"cd" after 700ns + BTIME * (15 + 11 + 6) + BTIME * 6, --last byte of src mac addr
X"de" after 700ns + BTIME * (15 + 11 + 6) + BTIME * 7, --junk bytes
END_FRAME after 700ns + BTIME * (15 + 11 + 6) + BTIME * (7 + 10), --EFD
X"00" after 700ns + BTIME * (15 + 11 + 6) + BTIME * (7 + 10 + 1); --null data
T_LASTP <= '1' after 12000ns;
wait;
end process;
end;
Raw
ethernet_controller_receiver_tb.vhd
--------------------------------------------------------------------------------
-- Create Date: 19:02:38 04/22/2019
-- Design Name:
-- Module Name: ethernet_controller_receiver_tb.vhd
-- Project Name: Controller
-- VHDL Test Bench Created by ISE for module: ethernet_controller
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
use work.ethernet_spec.all;
entity ethernet_controller_receiver_tb is
end ethernet_controller_receiver_tb;
architecture behavior of ethernet_controller_receiver_tb is
-- Component Declaration for the Unit Under Test (UUT),
component ethernet_controller
port (
CLK10I : in std_logic;
RESET : in std_logic;
MAC_ADDR : in std_logic_vector(0 to 47);
R_BYTEP : out std_logic;
R_CLEANP : out std_logic;
R_CVNGP : out std_logic;
R_SMATIP : out std_logic;
R_STARTP : out std_logic;
R_DONEP : out std_logic;
R_ENABP : in std_logic;
R_DATAI : in std_logic_vector(0 to 7);
R_DATAO : out std_logic_vector(0 to 7);
T_DONEP : out std_logic;
T_READDP : out std_logic;
T_RNSMTP : out std_logic;
T_STARTP : out std_logic;
T_SECOLP : out std_logic;
T_SOCOLP : out std_logic;
T_ABORTP : in std_logic;
T_AVAILP : in std_logic;
T_LASTP : in std_logic;
T_DATAI : in std_logic_vector(0 to 7);
T_DATAO : out std_logic_vector(0 to 7)
);
end component;
--Inputs
signal CLK10I : std_logic := '0';
signal RESET : std_logic := '0';
signal MAC_ADDR : std_logic_vector(0 to 47) := (others => '0');
signal R_ENABP : std_logic := '0';
signal R_DATAI : std_logic_vector(0 to 7) := (others => '0');
signal T_ABORTP : std_logic := '0';
signal T_AVAILP : std_logic := '0';
signal T_LASTP : std_logic := '0';
signal T_DATAI : std_logic_vector(0 to 7) := (others => '0');
--Outputs
signal R_BYTEP : std_logic;
signal R_CLEANP : std_logic;
signal R_CVNGP : std_logic;
signal R_SMATIP : std_logic;
signal R_STARTP : std_logic;
signal R_DONEP : std_logic;
signal R_DATAO : std_logic_vector(0 to 7);
signal T_DONEP : std_logic;
signal T_READDP : std_logic;
signal T_RNSMTP : std_logic;
signal T_STARTP : std_logic;
signal T_SECOLP : std_logic;
signal T_SOCOLP : std_logic;
signal T_DATAO : std_logic_vector(0 to 7);
-- Clock period definitions
constant CLK10I_period : time := 10 ns;
--Sends a mac address to the dst port, byte per byte, waits 8*clock
procedure send_macaddr (signal target : out etherbyte_type;
value : in macaddr_type) is
begin
for offset in 0 to 5 loop
target <= value(offset * 8 to offset * 8 + 7);
wait for CLK10I_period * 8;
end loop;
end procedure;
--Sends a byte to the dst port, waits 8*clock
procedure send_byte (signal target : out etherbyte_type;
value : in etherbyte_type) is
begin
target <= value;
wait for CLK10I_period * 8;
end procedure;
begin
-- Instantiate the Unit Under Test (UUT)
uut : ethernet_controller port map(
CLK10I => CLK10I,
RESET => RESET,
MAC_ADDR => MAC_ADDR,
R_BYTEP => R_BYTEP,
R_CLEANP => R_CLEANP,
R_CVNGP => R_CVNGP,
R_SMATIP => R_SMATIP,
R_STARTP => R_STARTP,
R_DONEP => R_DONEP,
R_ENABP => R_ENABP,
R_DATAI => R_DATAI,
R_DATAO => R_DATAO,
T_DONEP => T_DONEP,
T_READDP => T_READDP,
T_RNSMTP => T_RNSMTP,
T_STARTP => T_STARTP,
T_SECOLP => T_SECOLP,
T_SOCOLP => T_SOCOLP,
T_ABORTP => T_ABORTP,
T_AVAILP => T_AVAILP,
T_LASTP => T_LASTP,
T_DATAI => T_DATAI,
T_DATAO => T_DATAO
);
-- Clock process definitions
CLK10I_process : process
begin
CLK10I <= '0';
wait for CLK10I_period/2;
CLK10I <= '1';
wait for CLK10I_period/2;
end process;
-- Stimulus process
stim_proc : process
begin
-- Set eth controller mac addr
MAC_ADDR <= X"eeeeeeeeeeee";
-- hold reset state for 100 ns..
R_ENABP <= '1';
wait for CLK10I_period * 8;
RESET <= '0';
wait for CLK10I_period * 10;
RESET <= '1';
-- first frame : dst is our ethernet controller
send_byte(R_DATAI, START_FRAME); --sfd
send_macaddr(R_DATAI, MAC_ADDR); --dst mac addr
send_macaddr(R_DATAI, X"0123456789ba"); --src mac addr
for i in 0 to 15 loop --junk data
send_byte(R_DATAI, X"aa");
end loop;
send_byte(R_DATAI, END_FRAME); --efd
RESET <= '0';
wait for CLK10I_period * 10;
RESET <= '1';
wait for CLK10I_period * 10;
-- second frame : dst is wrong
send_byte(R_DATAI, START_FRAME); --sfd
send_macaddr(R_DATAI, X"eeeeeefeeeee"); --dst mac addr
send_macaddr(R_DATAI, X"0123456789ba"); --src mac addr
for i in 0 to 15 loop --junk data
send_byte(R_DATAI, X"bb");
end loop;
send_byte(R_DATAI, END_FRAME); --efd
wait for CLK10I_period * 10;
RESET <= '0';
wait;
end process;
end;
Raw
ethernet_controller_transmitter_tb.vhd
--------------------------------------------------------------------------------
-- Create Date: 08:16:15 04/24/2019
-- Design Name:
-- Module Name: ethernet_controller_transmitter_tb.vhd
-- Project Name: Controller
-- VHDL Test Bench Created by ISE for module: ethernet_controller
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ethernet_spec.all;
entity ethernet_controller_transmitter_tb is
end ethernet_controller_transmitter_tb;
architecture behavior of ethernet_controller_transmitter_tb is
-- Component Declaration for the Unit Under Test (UUT)
component ethernet_controller
port (
CLK10I : in std_logic;
RESET : in std_logic;
MAC_ADDR : in std_logic_vector(0 to 47);
R_BYTEP : out std_logic;
R_CLEANP : out std_logic;
R_CVNGP : out std_logic;
R_SMATIP : out std_logic;
R_STARTP : out std_logic;
R_DONEP : out std_logic;
R_ENABP : in std_logic;
R_DATAI : in std_logic_vector(0 to 7);
R_DATAO : out std_logic_vector(0 to 7);
T_DONEP : out std_logic;
T_READDP : out std_logic;
T_RNSMTP : out std_logic;
T_STARTP : out std_logic;
T_SOCOLP : out std_logic;
T_SECOLP : out std_logic;
T_ABORTP : in std_logic;
T_AVAILP : in std_logic;
T_LASTP : in std_logic;
T_DATAI : in std_logic_vector(0 to 7);
T_DATAO : out std_logic_vector(0 to 7)
);
end component;
--Inputs
signal CLK10I : std_logic := '0';
signal RESET : std_logic := '0';
signal MAC_ADDR : std_logic_vector(0 to 47) := (others => '0');
signal R_ENABP : std_logic := '0';
signal R_DATAI : std_logic_vector(0 to 7) := (others => '0');
signal T_ABORTP : std_logic := '0';
signal T_AVAILP : std_logic := '0';
signal T_LASTP : std_logic := '0';
signal T_DATAI : std_logic_vector(0 to 7) := (others => '0');
--Outputs
signal R_BYTEP : std_logic;
signal R_CLEANP : std_logic;
signal R_CVNGP : std_logic;
signal R_SMATIP : std_logic;
signal R_STARTP : std_logic;
signal R_DONEP : std_logic;
signal R_DATAO : std_logic_vector(0 to 7);
signal T_DONEP : std_logic;
signal T_READDP : std_logic;
signal T_RNSMTP : std_logic;
signal T_STARTP : std_logic;
signal T_SOCOLP : std_logic;
signal T_SECOLP : std_logic;
signal T_DATAO : std_logic_vector(0 to 7);
-- Clock period definitions
constant CLK10I_period : time := 10 ns;
--Sends a mac address to the dst port, byte per byte, waits 8*clock
procedure send_macaddr (signal target : out etherbyte_type;
value : in macaddr_type) is
begin
for offset in 0 to 5 loop
target <= value(offset * 8 to offset * 8 + 7);
wait for CLK10I_period * 8;
end loop;
end procedure;
--Sends a byte to the dst port, waits 8*clock
procedure send_byte (signal target : out etherbyte_type;
value : in etherbyte_type) is
begin
target <= value;
wait for CLK10I_period * 8;
end procedure;
begin
-- Instantiate the Unit Under Test (UUT)
uut : ethernet_controller port map(
CLK10I => CLK10I,
RESET => RESET,
MAC_ADDR => MAC_ADDR,
R_BYTEP => R_BYTEP,
R_CLEANP => R_CLEANP,
R_CVNGP => R_CVNGP,
R_SMATIP => R_SMATIP,
R_STARTP => R_STARTP,
R_DONEP => R_DONEP,
R_ENABP => R_ENABP,
R_DATAI => R_DATAI,
R_DATAO => R_DATAO,
T_DONEP => T_DONEP,
T_READDP => T_READDP,
T_RNSMTP => T_RNSMTP,
T_STARTP => T_STARTP,
T_SOCOLP => T_SOCOLP,
T_SECOLP => T_SECOLP,
T_ABORTP => T_ABORTP,
T_AVAILP => T_AVAILP,
T_LASTP => T_LASTP,
T_DATAI => T_DATAI,
T_DATAO => T_DATAO
);
-- Clock process definitions
CLK10I_process : process
begin
CLK10I <= '0';
wait for CLK10I_period/2;
CLK10I <= '1';
wait for CLK10I_period/2;
end process;
-- Stimulus process
stim_proc : process
begin
MAC_ADDR <= X"aabbccddeeff";
-- hold reset state for 100 ns.
RESET <= '0';
wait for CLK10I_period * 10;
RESET <= '1';
T_AVAILP <= '1';
-- basic frame
wait until falling_edge(T_STARTP); --sync with eth ctrl
send_macaddr(T_DATAI, X"aaddccbbffee"); --dst mac addr
wait for CLK10I_period * 8 * 6; --src mac addr
for i in 0 to 3 loop --junk data
send_macaddr(T_DATAI, X"abad1deafada");
end loop;
T_LASTP <= '1'; --last byte
T_DATAI <= X"66";
wait for CLK10I_period;
T_LASTP <= '0';
wait for CLK10I_period * 8 * 2;
-- test frame with abort port put to high
RESET <= '0';
wait for CLK10I_period * 10;
RESET <= '1';
wait until falling_edge(T_STARTP); --sync with eth ctrl
send_macaddr(T_DATAI, X"aaddccbbffee"); --dst mac addr
wait for CLK10I_period * 8 * 6; --src mac addr
for i in 0 to 3 loop --junk data
send_macaddr(T_DATAI, X"abad1deafada");
end loop;
T_ABORTP <= '1'; --transmission abort
for i in 0 to 3 loop --junk data
send_macaddr(T_DATAI, X"abad1deafada");
end loop;
wait for CLK10I_period * 10;
RESET <= '0';
wait;
end process;
end;
Raw
ethernet_spec.vhd
--
-- Package: Ethernet specification constants
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package ethernet_spec is
subtype etherbyte_type is std_logic_vector(0 to 7);
subtype etherbyte_offset_type is natural range 0 to 7;
subtype macaddr_type is std_logic_vector(0 to 47);
subtype frame_offset_type is natural range 0 to 8192;
constant NULL_FRAME : etherbyte_type := X"00";
constant START_FRAME : etherbyte_type := "10101011";
constant END_FRAME : etherbyte_type := "10101111";
constant JAM_PATTERN : etherbyte_type := "10101010";
end ethernet_spec;
Raw
lfsr25.vhd
----------------------------------------------------------------------------------
-- Create Date: 11:46:01 03/20/2018
-- Module Name: lfsr25 - Behavioral
-- Project Name: Controller
-- Description: Left Feedback Shift Register of 25 bits (as a PRNG)
-- AND with a XNOR gate between the 26th and the 23rd bit
-- as stated in "Efficient Shift Registers, LFSR Counters, and Long PseudoRandom Sequence Generators"
-- at : https://www.xilinx.com/support/documentation/application_notes/xapp052.pdf
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lfsr25 is
port (
CLK10I : in std_logic; --synchronization clock
ENABLE : in std_logic; --high/low = enable/disable this component
LOAD_SEED : in std_logic; --high = load seed instead of doing the left feedback shift
SEED_DATA : in std_logic_vector(24 downto 0); --seed of this PRNG
PRND_SEQ : out std_logic_vector(24 downto 0) --result sequence, the "pseudo random" sequence
);
end entity lfsr25;
architecture lfsr_core of lfsr25 is
--internal state used by the internal LFS process
signal state : std_logic_vector(25 downto 1) := (others => '0');
begin
lfsr_step : process
begin
wait until ENABLE = '1' and rising_edge(CLK10I);
if LOAD_SEED = '1' then
state <= SEED_DATA;
else
--left feedback shift + AND with a xnor gate
state <= state(state'left - 1 downto 1) & (state(25) xnor state(22));
end if;
end process lfsr_step;
PRND_SEQ <= state(state'left downto 1); -- wire the result
end architecture lfsr_core;
Raw
lfsr25_tb.vhd
--------------------------------------------------------------------------------
-- Create Date: 08:36:27 04/02/2019
-- Module Name: lfsr25_tb
-- Project Name: Controller
--
-- VHDL Test Bench Created by ISE for module: lfsr25
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity lfsr25_tb is
end lfsr25_tb;
architecture behavior of lfsr25_tb is
-- Component Declaration for the Unit Under Test (UUT)
component lfsr25
port (
CLK10I : in std_logic;
ENABLE : in std_logic;
LOAD_SEED : in std_logic;
SEED_DATA : in std_logic_vector(24 downto 0);
PRND_SEQ : out std_logic_vector(24 downto 0)
);
end component;
--Inputs
signal CLK10I : std_logic := '0';
signal ENABLE : std_logic := '0';
signal LOAD_SEED : std_logic := '0';
signal SEED_DATA : std_logic_vector(24 downto 0) := (others => '0');
--Outputs
signal PRND_SEQ : std_logic_vector(24 downto 0);
-- Clock period definitions
constant CLK10I_period : time := 10 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut : lfsr25 port map(
CLK10I => CLK10I,
ENABLE => ENABLE,
LOAD_SEED => LOAD_SEED,
SEED_DATA => SEED_DATA,
PRND_SEQ => PRND_SEQ
);
-- Clock process definitions
CLK10I_process : process
begin
CLK10I <= '0';
wait for CLK10I_period/2;
CLK10I <= '1';
wait for CLK10I_period/2;
end process;
-- Stimulus process
stim_proc : process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK10I_period * 2;
ENABLE <= '1';
LOAD_SEED <= '1';
SEED_DATA <= "1100010000111000111001111";
wait for CLK10I_period;
LOAD_SEED <= '0';
wait for CLK10I_period * 10;
ENABLE <= '0';
wait for CLK10I_period * 2;
ENABLE <= '1';
LOAD_SEED <= '1';
SEED_DATA <= "1000111000111001111110001";
wait for CLK10I_period;
LOAD_SEED <= '0';
wait for CLK10I_period * 10;
ENABLE <= '0';
wait;
end process;
end;
Raw
synthesis_report.log
Release 13.4 - xst O.87xd (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.05 secs
-->
Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.06 secs
-->
Reading design: ethernet_controller.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "ethernet_controller.prj"
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "ethernet_controller"
Output Format : NGC
Target Device : xc6slx16-3-csg324
---- Source Options
Top Module Name : ethernet_controller
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Shift Register Extraction : YES
ROM Style : Auto
Resource Sharing : YES
Asynchronous To Synchronous : NO
Shift Register Minimum Size : 2
Use DSP Block : Auto
Automatic Register Balancing : No
---- Target Options
LUT Combining : Auto
Reduce Control Sets : Auto
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 16
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Power Reduction : NO
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
INFO:Xst - Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL
=========================================================================
* HDL Parsing *
=========================================================================
Parsing VHDL file "/home/palabra/Documents/XilinxProjects/Controller/lfsr25.vhd" into library work
Parsing entity <lfsr25>.
Parsing architecture <lfsr_core> of entity <lfsr25>.
Parsing VHDL file "/home/palabra/Documents/XilinxProjects/Controller/ethernet_spec.vhd" into library work
Parsing package <ethernet_spec>.
Parsing VHDL file "/home/palabra/Documents/XilinxProjects/Controller/ethernet_controller.vhd" into library work
Parsing entity <ethernet_controller>.
Parsing architecture <ethernet_core> of entity <ethernet_controller>.
=========================================================================
* HDL Elaboration *
=========================================================================
Elaborating entity <ethernet_controller> (architecture <ethernet_core>) from library <work>.
Elaborating entity <lfsr25> (architecture <lfsr_core>) from library <work>.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <ethernet_controller>.
Related source file is "/home/palabra/Documents/XilinxProjects/Controller/ethernet_controller.vhd".
Found 1-bit register for signal <R_BYTEP>.
Found 1-bit register for signal <R_CLEANP>.
Found 1-bit register for signal <R_CVNGP>.
Found 1-bit register for signal <R_DONEP>.
Found 1-bit register for signal <R_SMATIP>.
Found 1-bit register for signal <R_STARTP>.
Found 2-bit register for signal <r_curr_state>.
Found 14-bit register for signal <r_frame_offset>.
Found 3-bit register for signal <r_byte_offset>.
Found 1-bit register for signal <T_STARTP>.
Found 1-bit register for signal <T_DONEP>.
Found 1-bit register for signal <T_READDP>.
Found 8-bit register for signal <T_DATAO>.
Found 4-bit register for signal <t_curr_state>.
Found 14-bit register for signal <t_frame_offset>.
Found 3-bit register for signal <t_byte_offset>.
Found 1-bit register for signal <T_RNSMTP>.
Found 4-bit register for signal <c_retries_cnt>.
Found 1-bit register for signal <T_SECOLP>.
Found 1-bit register for signal <lfsr25_enable>.
Found 1-bit register for signal <lfsr25_load_seed>.
Found 25-bit register for signal <lfsr25_seed_data>.
Found 16-bit register for signal <c_retries_wait_curr>.
Found 16-bit register for signal <c_retries_wait_time>.
Found 1-bit register for signal <T_SOCOLP>.
Found 8-bit register for signal <R_DATAO>.
Found finite state machine <FSM_0> for signal <t_curr_state>.
-----------------------------------------------------------------------
| States | 9 |
| Transitions | 47 |
| Inputs | 11 |
| Outputs | 8 |
| Clock | CLK10I (rising_edge) |
| Reset | RESET_INV_23_o (positive) |
| Reset type | synchronous |
| Reset State | idle_t |
| Power Up State | idle_t |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 3-bit adder for signal <r_byte_offset[2]_GND_5_o_add_103_OUT> created at line 75.
Found 14-bit adder for signal <r_frame_offset[13]_GND_5_o_add_108_OUT> created at line 212.
Found 5-bit adder for signal <n0558> created at line 392.
Found 14-bit adder for signal <t_frame_offset[13]_GND_5_o_add_243_OUT> created at line 396.
Found 3-bit adder for signal <t_byte_offset[2]_GND_5_o_add_255_OUT> created at line 75.
Found 4-bit adder for signal <c_retries_cnt[3]_GND_5_o_add_258_OUT> created at line 407.
Found 16-bit adder for signal <c_retries_wait_curr[15]_GND_5_o_add_259_OUT> created at line 410.
Found 3-bit 3-to-1 multiplexer for signal <r_curr_state[1]_X_5_o_wide_mux_115_OUT> created at line 155.
Found 14-bit 3-to-1 multiplexer for signal <r_curr_state[1]_X_5_o_wide_mux_116_OUT> created at line 155.
Found 2-bit 3-to-1 multiplexer for signal <r_curr_state[1]_X_5_o_wide_mux_117_OUT> created at line 155.
Found 14-bit comparator lessequal for signal <n0011> created at line 177
Found 8-bit comparator equal for signal <MAC_ADDR[0]_INV_12_o> created at line 179
Found 8-bit comparator equal for signal <MAC_ADDR[8]_INV_13_o> created at line 179
Found 8-bit comparator equal for signal <MAC_ADDR[16]_INV_14_o> created at line 179
Found 8-bit comparator equal for signal <MAC_ADDR[24]_INV_15_o> created at line 179
Found 8-bit comparator equal for signal <MAC_ADDR[32]_INV_16_o> created at line 179
Found 8-bit comparator equal for signal <MAC_ADDR[40]_INV_17_o> created at line 179
Found 3-bit comparator greater for signal <n0090> created at line 71
Found 14-bit comparator lessequal for signal <n0094> created at line 205
Found 14-bit comparator lessequal for signal <n0096> created at line 205
Found 4-bit comparator greater for signal <n0177> created at line 254
Found 14-bit comparator greater for signal <n0188> created at line 296
Found 14-bit comparator greater for signal <n0194> created at line 309
Found 14-bit comparator lessequal for signal <n0220> created at line 331
Found 3-bit comparator greater for signal <n0237> created at line 71
Found 14-bit comparator greater for signal <n0239> created at line 376
Found 4-bit comparator lessequal for signal <n0241> created at line 389
Found 16-bit comparator greater for signal <n0288> created at line 405
Summary:
inferred 7 Adder/Subtractor(s).
inferred 127 D-type flip-flop(s).
inferred 18 Comparator(s).
inferred 130 Multiplexer(s).
inferred 1 Finite State Machine(s).
Unit <ethernet_controller> synthesized.
Synthesizing Unit <lfsr25>.
Related source file is "/home/palabra/Documents/XilinxProjects/Controller/lfsr25.vhd".
Found 25-bit register for signal <state>.
Summary:
inferred 25 D-type flip-flop(s).
inferred 1 Multiplexer(s).
Unit <lfsr25> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 7
14-bit adder : 2
16-bit adder : 1
3-bit adder : 2
4-bit adder : 1
5-bit adder : 1
# Registers : 26
1-bit register : 14
14-bit register : 2
16-bit register : 2
2-bit register : 1
25-bit register : 2
3-bit register : 2
4-bit register : 1
8-bit register : 2
# Comparators : 18
14-bit comparator greater : 3
14-bit comparator lessequal : 4
16-bit comparator greater : 1
3-bit comparator greater : 2
4-bit comparator greater : 1
4-bit comparator lessequal : 1
8-bit comparator equal : 6
# Multiplexers : 131
1-bit 2-to-1 multiplexer : 60
14-bit 2-to-1 multiplexer : 23
14-bit 3-to-1 multiplexer : 1
16-bit 2-to-1 multiplexer : 2
2-bit 2-to-1 multiplexer : 14
2-bit 3-to-1 multiplexer : 1
25-bit 2-to-1 multiplexer : 1
3-bit 2-to-1 multiplexer : 17
3-bit 3-to-1 multiplexer : 1
4-bit 2-to-1 multiplexer : 1
8-bit 2-to-1 multiplexer : 10
# FSMs : 1
# Xors : 1
1-bit xor2 : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Synthesizing (advanced) Unit <ethernet_controller>.
The following registers are absorbed into counter <c_retries_cnt>: 1 register on signal <c_retries_cnt>.
Unit <ethernet_controller> synthesized (advanced).
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 6
14-bit adder : 2
16-bit adder : 1
3-bit adder : 2
5-bit adder : 1
# Counters : 1
4-bit up counter : 1
# Registers : 148
Flip-Flops : 148
# Comparators : 18
14-bit comparator greater : 3
14-bit comparator lessequal : 4
16-bit comparator greater : 1
3-bit comparator greater : 2
4-bit comparator greater : 1
4-bit comparator lessequal : 1
8-bit comparator equal : 6
# Multiplexers : 154
1-bit 2-to-1 multiplexer : 85
14-bit 2-to-1 multiplexer : 23
14-bit 3-to-1 multiplexer : 1
16-bit 2-to-1 multiplexer : 2
2-bit 2-to-1 multiplexer : 14
2-bit 3-to-1 multiplexer : 1
3-bit 2-to-1 multiplexer : 17
3-bit 3-to-1 multiplexer : 1
8-bit 2-to-1 multiplexer : 10
# FSMs : 1
# Xors : 1
1-bit xor2 : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <FSM_0> on signal <t_curr_state[1:4]> with user encoding.
------------------------
State | Encoding
------------------------
idle_t | 0000
dst_addr_t | 0001
src_addr_t | 0010
data_t | 0011
lastp_t | 0100
efd_t | 0101
abort_t | 0110
colabort_t | 0111
rwait_t | 1000
------------------------
Optimizing unit <ethernet_controller> ...
Optimizing unit <lfsr25> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block ethernet_controller, actual ratio is 4.
FlipFlop r_curr_state_0 has been replicated 1 time(s)
FlipFlop r_curr_state_1 has been replicated 1 time(s)
FlipFlop r_frame_offset_1 has been replicated 2 time(s)
FlipFlop r_frame_offset_2 has been replicated 2 time(s)
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 162
Flip-Flops : 162
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Design Summary *
=========================================================================
Top Level Output File Name : ethernet_controller.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 469
# GND : 1
# INV : 4
# LUT1 : 41
# LUT2 : 23
# LUT3 : 60
# LUT4 : 35
# LUT5 : 47
# LUT6 : 156
# MUXCY : 51
# MUXF7 : 6
# VCC : 1
# XORCY : 44
# FlipFlops/Latches : 162
# FD : 2
# FDE : 92
# FDR : 10
# FDRE : 58
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 97
# IBUF : 69
# OBUF : 28
Device utilization summary:
---------------------------
Selected Device : 6slx16csg324-3
Slice Logic Utilization:
Number of Slice Registers: 162 out of 18224 0%
Number of Slice LUTs: 366 out of 9112 4%
Number used as Logic: 366 out of 9112 4%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 391
Number with an unused Flip Flop: 229 out of 391 58%
Number with an unused LUT: 25 out of 391 6%
Number of fully used LUT-FF pairs: 137 out of 391 35%
Number of unique control sets: 18
IO Utilization:
Number of IOs: 98
Number of bonded IOBs: 98 out of 232 42%
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 1 out of 16 6%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
CLK10I | BUFGP | 162 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -3
Minimum period: 6.119ns (Maximum Frequency: 163.424MHz)
Minimum input arrival time before clock: 9.079ns
Maximum output required time after clock: 4.338ns
Maximum combinational path delay: No path found
Timing Details:
---------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'CLK10I'
Clock period: 6.119ns (frequency: 163.424MHz)
Total number of paths / destination ports: 9052 / 264
-------------------------------------------------------------------------
Delay: 6.119ns (Levels of Logic = 5)
Source: r_frame_offset_3 (FF)
Destination: r_frame_offset_12 (FF)
Source Clock: CLK10I rising
Destination Clock: CLK10I rising
Data Path: r_frame_offset_3 to r_frame_offset_12
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRE:C->Q 18 0.447 1.050 r_frame_offset_3 (r_frame_offset_3)
LUT4:I3->O 6 0.205 0.849 GND_5_o_r_frame_offset[13]_equal_17_o<13>21 (GND_5_o_r_frame_offset[13]_equal_17_o<13>2)
LUT6:I4->O 12 0.203 1.013 GND_5_o_r_frame_offset[13]_equal_17_o<13>1 (GND_5_o_r_frame_offset[13]_equal_17_o)
LUT6:I4->O 9 0.203 1.058 Mmux_r_curr_state[1]_GND_5_o_mux_126_OUT181 (Mmux_r_curr_state[1]_GND_5_o_mux_126_OUT181)
LUT6:I3->O 1 0.205 0.580 Mmux_r_curr_state[1]_GND_5_o_mux_126_OUT82_SW0 (N91)
LUT6:I5->O 1 0.205 0.000 Mmux_r_curr_state[1]_GND_5_o_mux_126_OUT82 (r_curr_state[1]_GND_5_o_mux_126_OUT<12>)
FDRE:D 0.102 r_frame_offset_12
----------------------------------------
Total 6.119ns (1.570ns logic, 4.549ns route)
(25.7% logic, 74.3% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK10I'
Total number of paths / destination ports: 5848 / 292
-------------------------------------------------------------------------
Offset: 9.079ns (Levels of Logic = 8)
Source: R_DATAI<2> (PAD)
Destination: r_frame_offset_12 (FF)
Destination Clock: CLK10I rising
Data Path: R_DATAI<2> to r_frame_offset_12
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 9 1.222 1.174 R_DATAI_2_IBUF (R_DATAI_2_IBUF)
LUT6:I1->O 1 0.203 0.944 MAC_ADDR[24]_INV_15_o81 (MAC_ADDR[24]_INV_15_o8)
LUT6:I0->O 6 0.203 0.973 MAC_ADDR[24]_INV_15_o83 (MAC_ADDR[24]_INV_15_o)
LUT3:I0->O 2 0.205 0.981 Mmux_r_curr_state[1]_GND_5_o_mux_128_OUT211_SW0 (N45)
LUT6:I0->O 2 0.203 0.617 Mmux_r_curr_state[1]_GND_5_o_mux_126_OUT1221 (Mmux_r_curr_state[1]_GND_5_o_mux_126_OUT122)
LUT6:I5->O 9 0.205 1.058 Mmux_r_curr_state[1]_GND_5_o_mux_126_OUT181 (Mmux_r_curr_state[1]_GND_5_o_mux_126_OUT181)
LUT6:I3->O 1 0.205 0.580 Mmux_r_curr_state[1]_GND_5_o_mux_126_OUT82_SW0 (N91)
LUT6:I5->O 1 0.205 0.000 Mmux_r_curr_state[1]_GND_5_o_mux_126_OUT82 (r_curr_state[1]_GND_5_o_mux_126_OUT<12>)
FDRE:D 0.102 r_frame_offset_12
----------------------------------------
Total 9.079ns (2.753ns logic, 6.326ns route)
(30.3% logic, 69.7% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK10I'
Total number of paths / destination ports: 28 / 28
-------------------------------------------------------------------------
Offset: 4.338ns (Levels of Logic = 1)
Source: int_t_socolp (FF)
Destination: T_SOCOLP (PAD)
Source Clock: CLK10I rising
Data Path: int_t_socolp to T_SOCOLP
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 34 0.447 1.320 int_t_socolp (int_t_socolp)
OBUF:I->O 2.571 T_SOCOLP_OBUF (T_SOCOLP)
----------------------------------------
Total 4.338ns (3.018ns logic, 1.320ns route)
(69.6% logic, 30.4% route)
=========================================================================
Cross Clock Domains Report:
--------------------------
Clock to Setup on destination clock CLK10I
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK10I | 6.119| | | |
---------------+---------+---------+---------+---------+
=========================================================================
Total REAL time to Xst completion: 11.00 secs
Total CPU time to Xst completion: 9.73 secs
-->
Total memory usage is 400376 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 1 ( 0 filtered)
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment