I was trying to understand the clocking mechanism in the stm32l0 (among other stms). I was trying to figure out how I would know to enable, e.g. __HAL_RCC_GPIOA_CLK_ENABLE when modifying certain registers.
I found the answer in memory map section, which specifies which peripheral each memory mapped region belongs. Turns out GPIOH is its own peripheral, (I assume, although not explicitly stated, that 'GPIOH' is the peripheral that handles the multiplexing of physical pins.)
Copied from section 2.2.2 of Stm32l0x reference manual.
Memory map and register boundary addresses
See the datasheet corresponding to your device for a comprehensive diagram of the
memory map.
The following table gives the boundary addresses of the peripherals available in the
devices.
Table 3. STM32L0x1 peripheral register boundary addresses(1)
Bus Boundary address Size (bytes) Peripheral Peripheral register map
IOPORT
0X5000 1C00 - 0X5000 1FFF 1K GPIOH Section 8.4.12: GPIO register
map
0X5000 1400 - 0X5000 1BFF 2 K Reserved -
0X5000 1000 - 0X5000 13FF 1K GPIOE Section 8.4.12: GPIO register
map
0X5000 0C00 - 0X5000 0FFF 1K GPIOD Section 8.4.12: GPIO register
map
0X5000 0800 - 0X5000 0BFF 1K GPIO C Section 8.4.12: GPIO register
map
0X5000 0400 - 0X5000 07FF 1K GPIOB Section 8.4.12: GPIO register
map
0X5000 0000 - 0X5000 03FF 1K GPIOA Section 8.4.12: GPIO register
map
Also, in this adventure, I discovered that APB and AHB are different bus architectures used inside the SoC. Each peripheral is connected to these busses, or other busses. https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture