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October 12, 2021 09:59
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| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::cmsisdap::tools] Searching for CMSIS-DAP probes using libusb\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::cmsisdap::tools] Found 0 CMSIS-DAP probes using libusb, searching HID\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::cmsisdap::tools] Found 0 CMSIS-DAP probes total\n" | |
| "[2021-10-12T09:55:08Z DEBUG jaylink] libusb 1.0.24.11584\n" | |
| "[2021-10-12T09:55:08Z DEBUG jaylink] libusb has capability API: true\n[2021-10-12T09:55:08Z DEBUG jaylink] libusb has HID access: true\n[2021-10-12T09:55:08Z DEBUG jaylink] libusb has hotplug support: true\n[2021-10-12T09:55:08Z DEBUG jaylink] libusb can detach kernel driver: true\n" | |
| "[2021-10-12T09:55:08Z DEBUG jaylink] open_usb: device descriptor: DeviceDescriptor {\n bLength: 0x12,\n bDescriptorType: 0x1,\n bcdUSB: 0x200,\n bDeviceClass: 0x0,\n bDeviceSubClass: 0x0,\n bDeviceProtocol: 0x0,\n bMaxPacketSize: 0x40,\n idVendor: 0x1366,\n idProduct: 0x101,\n bcdDevice: 0x100,\n iManufacturer: 0x1,\n iProduct: 0x2,\n iSerialNumber: 0x3,\n bNumConfigurations: 0x1,\n }\n[2021-10-12T09:55:08Z DEBUG jaylink] scanning 1 interfaces\n[2021-10-12T09:55:08Z DEBUG jaylink] J-Link interface is #0\n" | |
| "[2021-10-12T09:55:08Z DEBUG jaylink] legacy caps: GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx\n" | |
| "[2021-10-12T09:55:08Z DEBUG jaylink::capabilities] unknown ext. capability bits: 0x354FB17C1DB9FF7BBF truncated to 0x1B9FF7BBF (Reserved0 | GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite)\n[2021-10-12T09:55:08Z DEBUG jaylink] extended caps: GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::cmsisdap::tools] Attempting to open 1366:0101 in CMSIS-DAP v1 mode\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::stlink::usb_interface] Acquired libusb context.\n" | |
| "[2021-10-12T09:55:08Z DEBUG jaylink] open_usb: device descriptor: DeviceDescriptor {\n bLength: 0x12,\n bDescriptorType: 0x1,\n bcdUSB: 0x200,\n bDeviceClass: 0x0,\n bDeviceSubClass: 0x0,\n bDeviceProtocol: 0x0,\n bMaxPacketSize: 0x40,\n idVendor: 0x1366,\n idProduct: 0x101,\n bcdDevice: 0x100,\n iManufacturer: 0x1,\n iProduct: 0x2,\n iSerialNumber: 0x3,\n bNumConfigurations: 0x1,\n }\n[2021-10-12T09:55:08Z DEBUG jaylink] scanning 1 interfaces\n[2021-10-12T09:55:08Z DEBUG jaylink] J-Link interface is #0\n" | |
| "[2021-10-12T09:55:08Z DEBUG jaylink] legacy caps: GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx\n" | |
| "[2021-10-12T09:55:08Z DEBUG jaylink::capabilities] unknown ext. capability bits: 0x354FB17C1DB9FF7BBF truncated to 0x1B9FF7BBF (Reserved0 | GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite)\n[2021-10-12T09:55:08Z DEBUG jaylink] extended caps: GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] J-Link returned interface Fine, which is not supported by probe-rs.\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] J-Link returned interface Pic32Icsp, which is not supported by probe-rs.\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] J-Link returned interface Spi, which is not supported by probe-rs.\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] J-Link returned interface C2, which is not supported by probe-rs.\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] J-Link returned interface CJtag, which is not supported by probe-rs.\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] J-Link returned interface Mc2WireJtag, which is not supported by probe-rs.\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::config::registry] Searching registry for chip with name esp32c3\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::config::registry] Exact match for chip name: esp32c3\n[2021-10-12T09:55:08Z WARN probe_rs::config::target] Using custom sequence for ESP32c3\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Attaching to J-Link\n" | |
| "[2021-10-12T09:55:08Z WARN probe_rs::probe::jlink] Protocol SWD is configured, but not supported by the probe. Using protocol JTAG instead\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Attaching with protocol 'JTAG'\n[2021-10-12T09:55:08Z INFO probe_rs::probe::jlink] J-Link: S/N: 260111976\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] J-Link: Capabilities: GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite\n" | |
| "[2021-10-12T09:55:08Z INFO probe_rs::probe::jlink] J-Link: Firmware version: J-Link V10 compiled Jul 23 2019 13:46:10\n" | |
| "[2021-10-12T09:55:08Z INFO probe_rs::probe::jlink] J-Link: Hardware version: J-Link 10.10.0\n" | |
| "[2021-10-12T09:55:08Z INFO probe_rs::probe::jlink] J-Link: Target voltage: 3.26 V\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Resetting JTAG chain using trst\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Resetting JTAG chain by setting tms high for 32 bits\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Response to reset: [false, false, false, false, false, false]\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Read 32 bits from DR\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Read from DR: [0, 0, 0, 0]\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Read 32 bits from DR\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Read from DR: [0, 0, 0, 0]\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Read 32 bits from DR\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Read from DR: [0, 0, 0, 0]\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Read 32 bits from DR\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Read from DR: [0, 0, 0, 0]\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Read 32 bits from DR\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Read from DR: [0, 0, 0, 0]\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Read 32 bits from DR\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Read from DR: [0, 0, 0, 0]\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Read 32 bits from DR\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Read from DR: [0, 0, 0, 0]\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Read 32 bits from DR\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Read from DR: [0, 0, 0, 0]\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Read 32 bits from DR\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Read from DR: [0, 0, 0, 0]\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Read 32 bits from DR\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Read from DR: [37, 92, 0, 0]\n[2021-10-12T09:55:08Z INFO probe_rs::probe::jlink] JTAG IDCODE: 0x00005c25\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Attached succesfully\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write IR: [16], len=5\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Read 32 bits from DR\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Read from DR: [113, 16, 0, 0]\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::dtm] Dtmcs: Dtmcs { .0: 4209, idle: 1, dmistat: 0, abits: 7, version: 1 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Building RISCV interface\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 1, 0], len=32\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write IR: [17], len=5\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write IR: [16], len=5\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 1, 0], len=32\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write IR: [17], len=5\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: c0ca2, impebreak: false, allhavereset: true, anyhavereset: true, allresumeack: false, anyresumeack: false, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] dmstatus: Dmstatus { .0: 789666, impebreak: false, allhavereset: true, anyhavereset: true, allresumeack: false, anyresumeack: false, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: trueDTs, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 1, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 3ffffc1, hartreset: false, hasel: false, hartsello: 3ff, hartselhi: 3ff, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 255, 255, 15, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmcontrol' at 0x00000010\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write IR: [16], len=5\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 1, 0], len=32\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write IR: [17], len=5\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 3ffffc1, hartreset: false, hasel: false, hartsello: 3ff, hartselhi: 3ff, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] HARTSELLEN: 20\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10001, hartreset: false, hasel: false, hartsello: 1, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 4, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: ccca2, impebreak: false, allhavereset: true, anyhavereset: true, allresumeack: false, anyresumeack: false, allnonexistent: true, anynonexistent: true, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Number of harts: 1\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 1, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Program buffer size: 16\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Number of data registers: 2\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'hartinfo' at 0x00000012\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 72, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'hartinfo' at 0x00000012 = Hartinfo { .0: 0, nscratch: 0, dataaccess: false, datasize: 0, dataaddr: 0 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Number of dscratch registers: 0\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractauto' at 0x00000018 = Abstractauto { .0: ffff0003, autoexecprogbuf: ffff, autoexecdata: 3 }\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [14, 0, 252, 255, 99, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractauto' at 0x00000018\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 96, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractauto' at 0x00000018 = Abstractauto { .0: ffff0003, autoexecprogbuf: ffff, autoexecdata: 3 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Support for autoexec: true\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractauto' at 0x00000018 = Abstractauto { .0: 0, autoexecprogbuf: 0, autoexecdata: 0 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 0, 0, 96, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'sbcs' at 0x00000038 = Sbcs { .0: 20040404, sbversion: 1, sbbusyerror: false, sbbusy: false, sbreadonaddr: false, sbaccess: 2, sbautoincrement: false, sbreadondata: false, sberror: 0, sbasize: 20, sbaccess128: false, sbaccess64: false, sbaccess32: true, sbaccess16: false, sbaccess8: false }\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmcontrol' at 0x00000010\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 1, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Dmcontrol { .0: 1, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 80000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 0, 66, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: c03a2, impebreak: false, allhavereset: true, anyhavereset: true, allresumeack: false, anyresumeack: false, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: false, anyrunning: false, allhalted: true, anyhalted: true, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 1, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7b1\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207b1)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [198, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(42000208)\n[2021-10-12T09:55:08Z INFO probe_rs::architecture::riscv::sequences::esp32c3] Disabling esp32c3 watchdogs...\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 50000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: false, sbaccess: 2, sbautoincrement: true, sbreadondata: false, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(600080b0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 20, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [194, 2, 2, 128, 229, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [170, 196, 116, 60, 242, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 140000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: false, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 80, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(600080ac)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [178, 2, 2, 128, 229, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'sbcs' at 0x00000038 = Sbcs { .0: 20140404, sbversion: 1, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: false, sberror: 0, sbasize: 20, sbaccess128: false, sbaccess64: false, sbaccess32: true, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 50000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: false, sbaccess: 2, sbautoincrement: true, sbreadondata: false, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(600080ac)\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 20, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [178, 2, 2, 128, 229, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 192, 18, 242, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 50000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: false, sbaccess: 2, sbautoincrement: true, sbreadondata: false, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(600080b0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 20, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [194, 2, 2, 128, 229, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 50000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: false, sbaccess: 2, sbautoincrement: true, sbreadondata: false, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(6001f064)\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 20, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [146, 193, 7, 128, 229, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [134, 234, 96, 67, 241, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 50000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: false, sbaccess: 2, sbautoincrement: true, sbreadondata: false, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(6001f048)\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 20, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [34, 193, 7, 128, 229, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| Sent DAP Response: Response { | |
| body: None, | |
| command: "launch", | |
| message: None, | |
| request_seq: 2, | |
| seq: 2, | |
| success: true, | |
| type_: "response", | |
| } | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 50000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: false, sbaccess: 2, sbautoincrement: true, sbreadondata: false, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(6001f064)\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 20, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [146, 193, 7, 128, 229, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 50000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: false, sbaccess: 2, sbautoincrement: true, sbreadondata: false, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(60020064)\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 20, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [146, 1, 8, 128, 229, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [134, 234, 96, 67, 241, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 50000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: false, sbaccess: 2, sbautoincrement: true, sbreadondata: false, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(60020048)\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 20, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [34, 1, 8, 128, 229, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 50000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: false, sbaccess: 2, sbautoincrement: true, sbreadondata: false, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(60020064)\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 20, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [146, 1, 8, 128, 229, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 50000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: false, sbaccess: 2, sbautoincrement: true, sbreadondata: false, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(600080a8)\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 20, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [162, 2, 2, 128, 229, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [134, 234, 96, 67, 241, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 50000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: false, sbaccess: 2, sbautoincrement: true, sbreadondata: false, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(60008090)\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 20, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [66, 2, 2, 128, 229, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 50000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: false, sbaccess: 2, sbautoincrement: true, sbreadondata: false, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(600080a8)\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 20, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [162, 2, 2, 128, 229, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Determining number of HW breakpoints supported\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Trying tselect=0\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a0\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a4\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a4)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [146, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:08Z INFO probe_rs::architecture::riscv] Discovered trigger with index 0 and type 2\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Trying tselect=1\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a0\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(1)\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a4\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a4)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [146, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:08Z INFO probe_rs::architecture::riscv] Discovered trigger with index 1 and type 2\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Trying tselect=2\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [10, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a0\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(2)\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a4\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a4)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [146, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:08Z INFO probe_rs::architecture::riscv] Discovered trigger with index 2 and type 2\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Trying tselect=3\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [14, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a0\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(3)\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a4\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a4)\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [146, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:08Z INFO probe_rs::architecture::riscv] Discovered trigger with index 3 and type 2\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Trying tselect=4\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [18, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a0\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a0)\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(4)\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a4\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a4)\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [146, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:08Z INFO probe_rs::architecture::riscv] Discovered trigger with index 4 and type 2\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Trying tselect=5\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [22, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a0\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(5)\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a4\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a4)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [146, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:08Z INFO probe_rs::architecture::riscv] Discovered trigger with index 5 and type 2\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Trying tselect=6\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [26, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a0\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(6)\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a4\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a4)\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [146, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:08Z INFO probe_rs::architecture::riscv] Discovered trigger with index 6 and type 2\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Trying tselect=7\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [30, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a0\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(7)\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a4\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a4)\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [146, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:08Z INFO probe_rs::architecture::riscv] Discovered trigger with index 7 and type 2\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Trying tselect=8\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [34, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a0\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(7)\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Target supports 8 breakpoints.\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:08Z WARN probe_rs::architecture::riscv] Breakpoint 0: Mcontrol { .0: 601882624, type_: 2, dmode: false, maskmax: 31, hit: false, select: false, timing: false, sizelo: 0, action: 0, chain: false, match_: 0, m: false, s: false, u: false, execute: false, store: false, load: false }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:08Z WARN probe_rs::architecture::riscv] Breakpoint 1: Mcontrol { .0: 601882624, type_: 2, dmode: false, maskmax: 31, hit: false, select: false, timing: false, sizelo: 0, action: 0, chain: false, match_: 0, m: false, s: false, u: false, execute: false, store: false, load: false }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [10, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:08Z WARN probe_rs::architecture::riscv] Breakpoint 2: Mcontrol { .0: 601882624, type_: 2, dmode: false, maskmax: 31, hit: false, select: false, timing: false, sizelo: 0, action: 0, chain: false, match_: 0, m: false, s: false, u: false, execute: false, store: false, load: false }\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [14, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:08Z WARN probe_rs::architecture::riscv] Breakpoint 3: Mcontrol { .0: 601882624, type_: 2, dmode: false, maskmax: 31, hit: false, select: false, timing: false, sizelo: 0, action: 0, chain: false, match_: 0, m: false, s: false, u: false, execute: false, store: false, load: false }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [18, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:08Z WARN probe_rs::architecture::riscv] Breakpoint 4: Mcontrol { .0: 601882624, type_: 2, dmode: false, maskmax: 31, hit: false, select: false, timing: false, sizelo: 0, action: 0, chain: false, match_: 0, m: false, s: false, u: false, execute: false, store: false, load: false }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [22, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:08Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:08Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:09Z WARN probe_rs::architecture::riscv] Breakpoint 5: Mcontrol { .0: 601882624, type_: 2, dmode: false, maskmax: 31, hit: false, select: false, timing: false, sizelo: 0, action: 0, chain: false, match_: 0, m: false, s: false, u: false, execute: false, store: false, load: false }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [26, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:09Z WARN probe_rs::architecture::riscv] Breakpoint 6: Mcontrol { .0: 601882624, type_: 2, dmode: false, maskmax: 31, hit: false, select: false, timing: false, sizelo: 0, action: 0, chain: false, match_: 0, m: false, s: false, u: false, execute: false, store: false, load: false }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [30, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:09Z WARN probe_rs::architecture::riscv] Breakpoint 7: Mcontrol { .0: 601882624, type_: 2, dmode: false, maskmax: 31, hit: false, select: false, timing: false, sizelo: 0, action: 0, chain: false, match_: 0, m: false, s: false, u: false, execute: false, store: false, load: false }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmcontrol' at 0x00000010\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 1, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Dmcontrol { .0: 1, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 80000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 0, 66, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 3a2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: false, anyresumeack: false, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: false, anyrunning: false, allhalted: true, anyhalted: true, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 1, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7b1\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207b1)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [198, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(42000208)\n[2021-10-12T09:55:09Z DEBUG probe_rs_debugger::debugger] No RTT configured. Continuing without RTT ...\n" | |
| INFO: Triggered DAP Event: Event { | |
| body: None, | |
| event: "initialized", | |
| seq: 4, | |
| type_: "event", | |
| } | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 3a2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: false, anyresumeack: false, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: false, anyrunning: false, allhalted: true, anyhalted: true, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7b0\n" | |
| Received DAP Request: Request { | |
| arguments: Some( | |
| Object({ | |
| "breakpoints": Array([]), | |
| "lines": Array([]), | |
| "source": Object({ | |
| "name": String( | |
| "lib.rs", | |
| ), | |
| "path": String( | |
| "/home/mabez/.cargo/git/checkouts/riscv-rt-c7af9ee5e393f279/6b55e4a/src/lib.rs", | |
| ), | |
| }), | |
| "sourceModified": Bool( | |
| false, | |
| ), | |
| }), | |
| ), | |
| command: "setBreakpoints", | |
| seq: 3, | |
| type_: "request", | |
| } | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207b0)\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [194, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(c3)\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Determining number of HW breakpoints supported\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Trying tselect=0\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a0\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a0)\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(0)\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a4\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a4)\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [146, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:09Z INFO probe_rs::architecture::riscv] Discovered trigger with index 0 and type 2\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Trying tselect=1\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a0\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a0)\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(1)\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a4\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a4)\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [146, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:09Z INFO probe_rs::architecture::riscv] Discovered trigger with index 1 and type 2\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Trying tselect=2\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [10, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a0)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(2)\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a4\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a4)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [146, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:09Z INFO probe_rs::architecture::riscv] Discovered trigger with index 2 and type 2\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Trying tselect=3\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [14, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a0)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(3)\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a4\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a4)\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [146, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:09Z INFO probe_rs::architecture::riscv] Discovered trigger with index 3 and type 2\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Trying tselect=4\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [18, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a0)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(4)\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a4\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a4)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [146, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:09Z INFO probe_rs::architecture::riscv] Discovered trigger with index 4 and type 2\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Trying tselect=5\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [22, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a0)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(5)\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a4\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a4)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [146, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:09Z INFO probe_rs::architecture::riscv] Discovered trigger with index 5 and type 2\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Trying tselect=6\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [26, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a0)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(6)\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a4\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a4)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [146, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:09Z INFO probe_rs::architecture::riscv] Discovered trigger with index 6 and type 2\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Trying tselect=7\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [30, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a0)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(7)\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a4\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a4)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [146, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:09Z INFO probe_rs::architecture::riscv] Discovered trigger with index 7 and type 2\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Trying tselect=8\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [34, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a0)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(7)\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Target supports 8 breakpoints.\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:09Z WARN probe_rs::architecture::riscv] Breakpoint 0: Mcontrol { .0: 601882624, type_: 2, dmode: false, maskmax: 31, hit: false, select: false, timing: false, sizelo: 0, action: 0, chain: false, match_: 0, m: false, s: false, u: false, execute: false, store: false, load: false }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:09Z WARN probe_rs::architecture::riscv] Breakpoint 1: Mcontrol { .0: 601882624, type_: 2, dmode: false, maskmax: 31, hit: false, select: false, timing: false, sizelo: 0, action: 0, chain: false, match_: 0, m: false, s: false, u: false, execute: false, store: false, load: false }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [10, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:09Z WARN probe_rs::architecture::riscv] Breakpoint 2: Mcontrol { .0: 601882624, type_: 2, dmode: false, maskmax: 31, hit: false, select: false, timing: false, sizelo: 0, action: 0, chain: false, match_: 0, m: false, s: false, u: false, execute: false, store: false, load: false }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [14, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:09Z WARN probe_rs::architecture::riscv] Breakpoint 3: Mcontrol { .0: 601882624, type_: 2, dmode: false, maskmax: 31, hit: false, select: false, timing: false, sizelo: 0, action: 0, chain: false, match_: 0, m: false, s: false, u: false, execute: false, store: false, load: false }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [18, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:09Z WARN probe_rs::architecture::riscv] Breakpoint 4: Mcontrol { .0: 601882624, type_: 2, dmode: false, maskmax: 31, hit: false, select: false, timing: false, sizelo: 0, action: 0, chain: false, match_: 0, m: false, s: false, u: false, execute: false, store: false, load: false }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [22, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:09Z WARN probe_rs::architecture::riscv] Breakpoint 5: Mcontrol { .0: 601882624, type_: 2, dmode: false, maskmax: 31, hit: false, select: false, timing: false, sizelo: 0, action: 0, chain: false, match_: 0, m: false, s: false, u: false, execute: false, store: false, load: false }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [26, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n[2021-10-12T09:55:09Z WARN probe_rs::architecture::riscv] Breakpoint 6: Mcontrol { .0: 601882624, type_: 2, dmode: false, maskmax: 31, hit: false, select: false, timing: false, sizelo: 0, action: 0, chain: false, match_: 0, m: false, s: false, u: false, execute: false, store: false, load: false }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Writing CSR 0x7a0\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [30, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2307a0)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [130, 30, 140, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7a1\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207a1)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [134, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(23e00000)\n" | |
| "[2021-10-12T09:55:09Z WARN probe_rs::architecture::riscv] Breakpoint 7: Mcontrol { .0: 601882624, type_: 2, dmode: false, maskmax: 31, hit: false, select: false, timing: false, sizelo: 0, action: 0, chain: false, match_: 0, m: false, s: false, u: false, execute: false, store: false, load: false }\n" | |
| Sent DAP Response: Response { | |
| body: Some( | |
| Object({ | |
| "breakpoints": Array([]), | |
| }), | |
| ), | |
| command: "setBreakpoints", | |
| message: None, | |
| request_seq: 3, | |
| seq: 3, | |
| success: true, | |
| type_: "response", | |
| } | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 3a2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: false, anyresumeack: false, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: false, anyrunning: false, allhalted: true, anyhalted: true, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7b0\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207b0)\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [194, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(400000c3)\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 40000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 0, 65, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 1, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| Received DAP Request: Request { | |
| arguments: None, | |
| command: "configurationDone", | |
| seq: 4, | |
| type_: "request", | |
| } | |
| Sent DAP Response: Response { | |
| body: Some( | |
| Object({ | |
| "allThreadsContinued": Bool( | |
| true, | |
| ), | |
| }), | |
| ), | |
| command: "configurationDone", | |
| message: None, | |
| request_seq: 4, | |
| seq: 4, | |
| success: true, | |
| type_: "response", | |
| } | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| Received DAP Request: Request { | |
| arguments: None, | |
| command: "threads", | |
| seq: 5, | |
| type_: "request", | |
| } | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| Sent DAP Response: Response { | |
| body: Some( | |
| Object({ | |
| "threads": Array([ | |
| Object({ | |
| "id": Number( | |
| 0, | |
| ), | |
| "name": String( | |
| "0-esp32c3", | |
| ), | |
| }), | |
| ]), | |
| }), | |
| ), | |
| command: "threads", | |
| message: None, | |
| request_seq: 5, | |
| seq: 5, | |
| success: true, | |
| type_: "response", | |
| } | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:09Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:10Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:11Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:12Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:13Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:14Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:15Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 30ca2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: true, anyrunning: true, allhalted: false, anyhalted: false, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmcontrol' at 0x00000010\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 1, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv] Dmcontrol { .0: 1, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 80000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 0, 66, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| Received DAP Request: Request { | |
| arguments: Some( | |
| Object({ | |
| "threadId": Number( | |
| 0, | |
| ), | |
| }), | |
| ), | |
| command: "pause", | |
| seq: 6, | |
| type_: "request", | |
| } | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 303a2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: false, anyrunning: false, allhalted: true, anyhalted: true, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 1, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7b1\n[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207b1)\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [198, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(42000552)\n" | |
| INFO: Triggered DAP Event: Event { | |
| body: Some( | |
| Object({ | |
| "allThreadsStopped": Bool( | |
| true, | |
| ), | |
| "description": String( | |
| "Core is running", | |
| ), | |
| "preserveFocusHint": Bool( | |
| false, | |
| ), | |
| "reason": String( | |
| "pause", | |
| ), | |
| "threadId": Number( | |
| 0, | |
| ), | |
| }), | |
| ), | |
| event: "stopped", | |
| seq: 16, | |
| type_: "event", | |
| } | |
| Sent DAP Response: Response { | |
| body: Some( | |
| String( | |
| "Core stopped at address 0x42000552", | |
| ), | |
| ), | |
| command: "pause", | |
| message: None, | |
| request_seq: 6, | |
| seq: 6, | |
| success: true, | |
| type_: "response", | |
| } | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 303a2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: false, anyrunning: false, allhalted: true, anyhalted: true, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7b0\n[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| Received DAP Request: Request { | |
| arguments: None, | |
| command: "threads", | |
| seq: 7, | |
| type_: "request", | |
| } | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207b0)\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [194, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:16Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(400000c3)\n" | |
| Sent DAP Response: Response { | |
| body: Some( | |
| Object({ | |
| "threads": Array([ | |
| Object({ | |
| "id": Number( | |
| 0, | |
| ), | |
| "name": String( | |
| "0-esp32c3", | |
| ), | |
| }), | |
| ]), | |
| }), | |
| ), | |
| command: "threads", | |
| message: None, | |
| request_seq: 7, | |
| seq: 7, | |
| success: true, | |
| type_: "response", | |
| } | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 303a2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: false, anyrunning: false, allhalted: true, anyhalted: true, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7b0\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207b0)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [194, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(400000c3)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 303a2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: false, anyrunning: false, allhalted: true, anyhalted: true, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7b0\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207b0)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [194, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(400000c3)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7b1\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207b1)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [198, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(42000552)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3fc80000\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3fc80000\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3fc80000)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 32, 255, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| Received DAP Request: Request { | |
| arguments: Some( | |
| Object({ | |
| "levels": Number( | |
| 20, | |
| ), | |
| "startFrame": Number( | |
| 0, | |
| ), | |
| "threadId": Number( | |
| 0, | |
| ), | |
| }), | |
| ), | |
| command: "stackTrace", | |
| seq: 8, | |
| type_: "request", | |
| } | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001384\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001384\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001384)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [18, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001388\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001388\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001388)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [34, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c00138c\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c00138c\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c00138c)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [50, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001390\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001390\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001390)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [66, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001394\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001394\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001394)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [82, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001398\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001398\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001398)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [98, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c00139c\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c00139c\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c00139c)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [114, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c0013a0\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c0013a0\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c0013a0)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [130, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c0013a4\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c0013a4\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c0013a4)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [146, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c0013a8\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c0013a8\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c0013a8)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [162, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c0013ac\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c0013ac\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c0013ac)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [178, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x0\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(220000)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(1)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x1\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(220001)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x2\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(220002)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [10, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x3\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(220003)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [14, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x4\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(220004)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [18, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x5\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(220005)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [22, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(1)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x6\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(220006)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [26, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(220007)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [30, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x8\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(220008)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [34, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x9\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(220009)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [38, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0xa\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(22000a)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [42, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0xb\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(22000b)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [46, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0xc\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(22000c)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [50, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0xd\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(22000d)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [54, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0xe\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(22000e)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [58, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0xf\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(22000f)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [62, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::debug] StackFrame: Unwinding at address 0x42000552\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::debug] Found DIE, now checking for inlined functions: name=Some(\"ExceptionHandler\")\n[2021-10-12T09:55:17Z DEBUG probe_rs::debug] No inlined function found!\n[2021-10-12T09:55:17Z WARN probe_rs::debug] Unable to calculate CFA: Missing value of register 2\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 303a2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: false, anyrunning: false, allhalted: true, anyhalted: true, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7b0\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207b0)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [194, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| Sent DAP Response: Response { | |
| body: Some( | |
| Object({ | |
| "stackFrames": Array([ | |
| Object({ | |
| "column": Number( | |
| 0, | |
| ), | |
| "id": Number( | |
| 1107297618, | |
| ), | |
| "line": Number( | |
| 0, | |
| ), | |
| "name": String( | |
| "<unknown function @ 0x42000552>", | |
| ), | |
| }), | |
| ]), | |
| "totalFrames": Number( | |
| 1, | |
| ), | |
| }), | |
| ), | |
| command: "stackTrace", | |
| message: None, | |
| request_seq: 8, | |
| seq: 8, | |
| success: true, | |
| type_: "response", | |
| } | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(400000c3)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 303a2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: false, anyrunning: false, allhalted: true, anyhalted: true, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7b0\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207b0)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [194, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(400000c3)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7b1\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207b1)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [198, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(42000552)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3fc80000\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3fc80000\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3fc80000)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 32, 255, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001384\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001384\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001384)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [18, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001388\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001388\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001388)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [34, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c00138c\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c00138c\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c00138c)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [50, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001390\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001390\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001390)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| Received DAP Request: Request { | |
| arguments: Some( | |
| Object({ | |
| "levels": Number( | |
| 20, | |
| ), | |
| "startFrame": Number( | |
| 0, | |
| ), | |
| "threadId": Number( | |
| 0, | |
| ), | |
| }), | |
| ), | |
| command: "stackTrace", | |
| seq: 9, | |
| type_: "request", | |
| } | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [66, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001394\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001394\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001394)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [82, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001398\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001398\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001398)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [98, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c00139c\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c00139c\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c00139c)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [114, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c0013a0\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c0013a0\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c0013a0)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [130, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c0013a4\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c0013a4\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c0013a4)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [146, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c0013a8\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c0013a8\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c0013a8)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [162, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c001380\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c001380)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c0013ac\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] read_32 from 0x3c0013ac\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 158000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: true, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbaddress0' at 0x00000039 = Sbaddress0(3c0013ac)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'sbcs' at 0x00000038 = Sbcs { .0: 148000, sbversion: 0, sbbusyerror: false, sbbusy: false, sbreadonaddr: true, sbaccess: 2, sbautoincrement: false, sbreadondata: true, sberror: 0, sbasize: 0, sbaccess128: false, sbaccess64: false, sbaccess32: false, sbaccess16: false, sbaccess8: false }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'sbcs' at 0x00000038\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 86, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [178, 78, 0, 240, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 82, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x0\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(220000)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(1)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x1\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(220001)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x2\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(220002)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [10, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x3\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(220003)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [14, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x4\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(220004)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [18, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x5\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(220005)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [22, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(1)\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x6\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(220006)\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [26, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(220007)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [30, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x8\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(220008)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [34, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x9\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(220009)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [38, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0xa\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(22000a)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [42, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0xb\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(22000b)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [46, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0xc\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(22000c)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [50, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0xd\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(22000d)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [54, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0xe\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(22000e)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [58, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0xf\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(22000f)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [62, 0, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::debug] StackFrame: Unwinding at address 0x42000552\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::debug] Found DIE, now checking for inlined functions: name=Some(\"ExceptionHandler\")\n[2021-10-12T09:55:17Z DEBUG probe_rs::debug] No inlined function found!\n[2021-10-12T09:55:17Z WARN probe_rs::debug] Unable to calculate CFA: Missing value of register 2\n" | |
| Sent DAP Response: Response { | |
| body: Some( | |
| Object({ | |
| "stackFrames": Array([ | |
| Object({ | |
| "column": Number( | |
| 0, | |
| ), | |
| "id": Number( | |
| 1107297618, | |
| ), | |
| "line": Number( | |
| 0, | |
| ), | |
| "name": String( | |
| "<unknown function @ 0x42000552>", | |
| ), | |
| }), | |
| ]), | |
| "totalFrames": Number( | |
| 1, | |
| ), | |
| }), | |
| ), | |
| command: "stackTrace", | |
| message: None, | |
| request_seq: 9, | |
| seq: 9, | |
| success: true, | |
| type_: "response", | |
| } | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'dmstatus' at 0x00000011\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'dmstatus' at 0x00000011 = Dmstatus { .0: 303a2, impebreak: false, allhavereset: false, anyhavereset: false, allresumeack: true, anyresumeack: true, allnonexistent: false, anynonexistent: false, allunavail: false, anyunavail: false, allrunning: false, anyrunning: false, allhalted: true, anyhalted: true, authenticated: true, authbusy: false, hasresethaltreq: true, confstrptrvalid: false, version: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv] Reading CSR 0x7b0\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'dmcontrol' at 0x00000010 = Dmcontrol { .0: 10000001, hartreset: false, hasel: false, hartsello: 0, hartselhi: 0, ndmreset: false, dmactive: true }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [6, 0, 0, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| Received DAP Request: Request { | |
| arguments: Some( | |
| Object({ | |
| "frameId": Number( | |
| 1107297618, | |
| ), | |
| }), | |
| ), | |
| command: "scopes", | |
| seq: 10, | |
| type_: "request", | |
| } | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000302, progbufsize: 10, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstractcs: Abstractcs { .0: 268436226, progbufsize: 16, busy: false, cmderr: 3, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 700, progbufsize: 0, busy: false, cmderr: 7, datacount: 0 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [2, 28, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Write DM register 'command' at 0x00000017 = Command(2207b0)\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [194, 30, 136, 0, 92, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'abstractcs' at 0x00000016\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'abstractcs' at 0x00000016 = Abstractcs { .0: 10000002, progbufsize: 10, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] abstracts: Abstractcs { .0: 268435458, progbufsize: 16, busy: false, cmderr: 0, datacount: 2 }\n[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Reading DM register 'data0' at 0x00000004\n[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [1, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::probe::jlink] Write DR: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], len=41\n" | |
| "[2021-10-12T09:55:17Z DEBUG probe_rs::architecture::riscv::communication_interface] Read DM register 'data0' at 0x00000004 = Data0(400000c3)\n" | |
| No variable information available | |
| INFO: Triggered DAP Event: Event { | |
| body: Some( | |
| Object({ | |
| "message": String( | |
| "No variable information available\n", | |
| ), | |
| "severity": String( | |
| "error", | |
| ), | |
| }), | |
| ), | |
| event: "probe-rs-show-message", | |
| seq: 32, | |
| type_: "event", | |
| } |
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