Created
March 4, 2022 07:57
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GbHDMI project generated by Chisel GbHdmi module. With Gowin synthesis error
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| // | |
| //Written by GowinSynthesis | |
| //Product Version "GowinSynthesis V1.9.7.02Beta" | |
| //Tue Jun 01 10:14:01 2021 | |
| //Source file index table: | |
| //file0 "\D:/Gowin/Gowin_V1.9.7.02Beta/IDE/ipcore/DVI_TX/data/dvi_tx_top.v" | |
| //file1 "\D:/Gowin/Gowin_V1.9.7.02Beta/IDE/ipcore/DVI_TX/data/rgb2dvi.vp" | |
| `timescale 100 ps/100 ps | |
| `pragma protect begin_protected | |
| `pragma protect version=1 | |
| `pragma protect author="default" | |
| `pragma protect author_info="default" | |
| `pragma protect encrypt_agent="Synplify encryptP1735.pl" | |
| `pragma protect encrypt_agent_info="Synplify encryptP1735.pl Version 1.1" | |
| `pragma protect encoding=(enctype="base64", line_length=76, bytes=256) | |
| `pragma protect key_keyowner="Synplicity",key_keyname="SYNP05_001",key_method="rsa" | |
| `pragma protect key_block | |
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| zM9WMmJEKWpI3cjwdbsG15nmf9h9diSQEDQEgQ== | |
| `pragma protect encoding=(enctype="base64", line_length=76, bytes=256) | |
| `pragma protect key_keyowner="GoWin",key_keyname="GoWin001",key_method="rsa" | |
| `pragma protect key_block | |
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| `pragma protect encoding=(enctype="base64", line_length=76, bytes=57376) | |
| `pragma protect data_keyowner="default-ip-vendor" | |
| `pragma protect data_keyname="default-ip-key" | |
| `pragma protect data_method="aes128-cbc" | |
| `pragma protect data_block | |
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| `pragma protect end_protected | |
| module DVI_TX_Top ( | |
| I_rst_n, | |
| I_serial_clk, | |
| I_rgb_clk, | |
| I_rgb_vs, | |
| I_rgb_hs, | |
| I_rgb_de, | |
| I_rgb_r, | |
| I_rgb_g, | |
| I_rgb_b, | |
| O_tmds_clk_p, | |
| O_tmds_clk_n, | |
| O_tmds_data_p, | |
| O_tmds_data_n | |
| ) | |
| ; | |
| input I_rst_n; | |
| input I_serial_clk; | |
| input I_rgb_clk; | |
| input I_rgb_vs; | |
| input I_rgb_hs; | |
| input I_rgb_de; | |
| input [7:0] I_rgb_r; | |
| input [7:0] I_rgb_g; | |
| input [7:0] I_rgb_b; | |
| output O_tmds_clk_p; | |
| output O_tmds_clk_n; | |
| output [2:0] O_tmds_data_p; | |
| output [2:0] O_tmds_data_n; | |
| wire VCC; | |
| wire GND; | |
| \~rgb2dvi.DVI_TX_Top rgb2dvi_inst ( | |
| .I_rgb_clk(I_rgb_clk), | |
| .I_serial_clk(I_serial_clk), | |
| .I_rst_n(I_rst_n), | |
| .I_rgb_de(I_rgb_de), | |
| .I_rgb_vs(I_rgb_vs), | |
| .I_rgb_hs(I_rgb_hs), | |
| .I_rgb_r(I_rgb_r[7:0]), | |
| .I_rgb_g(I_rgb_g[7:0]), | |
| .I_rgb_b(I_rgb_b[7:0]), | |
| .O_tmds_clk_p(O_tmds_clk_p), | |
| .O_tmds_clk_n(O_tmds_clk_n), | |
| .O_tmds_data_p(O_tmds_data_p[2:0]), | |
| .O_tmds_data_n(O_tmds_data_n[2:0]) | |
| ); | |
| VCC VCC_cZ ( | |
| .V(VCC) | |
| ); | |
| GND GND_cZ ( | |
| .G(GND) | |
| ); | |
| GSR GSR ( | |
| .GSRI(VCC) | |
| ); | |
| endmodule /* DVI_TX_Top */ | |
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| //Copyright (C)2014-2020 Gowin Semiconductor Corporation. | |
| //All rights reserved. | |
| //File Title: Physical Constraints file | |
| //GOWIN Version: 1.9.7.01Beta | |
| //Part Number: GW1NSR-LV4CQN48PC7/I6 | |
| //Device: GW1NSR-4C | |
| //Created Time: Fri 06 11 14:54:37 2021 | |
| IO_LOC "O_tmds_clk_p" 28,27; | |
| IO_PORT "O_tmds_clk_p" PULL_MODE=NONE DRIVE=3.5; | |
| IO_LOC "O_tmds_data_0_p" 30,29; | |
| IO_PORT "O_tmds_data_0_p" PULL_MODE=NONE DRIVE=3.5; | |
| IO_LOC "O_tmds_data_1_p" 32,31; | |
| IO_PORT "O_tmds_data_1_p" PULL_MODE=NONE DRIVE=3.5; | |
| IO_LOC "O_tmds_data_2_p" 35,34; | |
| IO_PORT "O_tmds_data_2_p" PULL_MODE=NONE DRIVE=3.5; | |
| IO_LOC "O_led[0]" 10; | |
| IO_PORT "O_led[0]" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8; | |
| IO_LOC "I_reset_n" 14; | |
| IO_PORT "I_reset_n" PULL_MODE=UP; | |
| IO_LOC "I_clk" 45; | |
| IO_PORT "I_clk" IO_TYPE=LVCMOS33 PULL_MODE=UP; | |
| // Gameboy video pinout | |
| IO_PORT "gb_hsync" PULL_MODE=DOWN; | |
| IO_LOC "gb_hsync" 43; | |
| IO_PORT "gb_vsync" PULL_MODE=DOWN; | |
| IO_LOC "gb_vsync" 39; | |
| IO_PORT "gb_clk" PULL_MODE=DOWN; | |
| IO_LOC "gb_clk" 40; | |
| IO_PORT "gb_data[0]" PULL_MODE=DOWN; | |
| IO_LOC "gb_data[0]" 41; | |
| IO_PORT "gb_data[1]" PULL_MODE=DOWN; | |
| IO_LOC "gb_data[1]" 42; | |
| // Gameboy pad pinout | |
| IO_PORT "gbpad_a" PULL_MODE=DOWN; | |
| IO_PORT "gbpad_b" PULL_MODE=DOWN; | |
| IO_PORT "gbpad_select" PULL_MODE=DOWN; | |
| IO_PORT "gbpad_start" PULL_MODE=DOWN; | |
| IO_PORT "gbpad_right" PULL_MODE=DOWN; | |
| IO_PORT "gbpad_left" PULL_MODE=DOWN; | |
| IO_PORT "gbpad_up" PULL_MODE=DOWN; | |
| IO_PORT "gbpad_down" PULL_MODE=DOWN; | |
| IO_LOC "gbpad_a" 16; | |
| IO_LOC "gbpad_b" 13; | |
| IO_LOC "gbpad_select" 17; | |
| IO_LOC "gbpad_start" 18; | |
| IO_LOC "gbpad_right" 19; | |
| IO_LOC "gbpad_left" 20; | |
| IO_LOC "gbpad_up" 21; | |
| IO_LOC "gbpad_down" 22; | |
| // SNES keypad pinout | |
| IO_PORT "snes_dclock" PULL_MODE=DOWN; | |
| IO_PORT "snes_dlatch" PULL_MODE=DOWN; | |
| IO_PORT "snes_sdata" PULL_MODE=DOWN; | |
| IO_LOC "snes_dclock" 47; | |
| IO_LOC "snes_dlatch" 48; | |
| IO_LOC "snes_sdata" 1; |
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| //Copyright (C)2014-2021 GOWIN Semiconductor Corporation. | |
| //All rights reserved. | |
| //File Title: Timing Constraints file | |
| //GOWIN Version: 1.9.7.02 Beta | |
| //Created Time: 2021-06-01 10:34:02 | |
| create_clock -name I_clk -period 37.037 -waveform {0 18.518} [get_ports {I_clk}] -add | |
| create_clock -name serial_clk -period 2.694 -waveform {0 1.347} [get_nets {tmdsPllvr_clkout}] -add | |
| create_clock -name pix_clk -period 13.468 -waveform {0 6.734} [get_nets {clkDiv_CLKOUT}] -add |
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| //Copyright (C)2014-2020 Gowin Semiconductor Corporation. | |
| //All rights reserved. | |
| //File Title: IP file | |
| //GOWIN Version: V1.9.7.01Beta | |
| //Part Number: GW1NSR-LV4CQN48PC7/I6 | |
| //Device: GW1NSR-4C | |
| //Created Time: Tue Nov 03 14:39:26 2020 | |
| module TMDS_PLLVR (clkout, lock, clkoutd, clkin); | |
| output clkout; | |
| output lock; | |
| output clkoutd; | |
| input clkin; | |
| wire clkoutp_o; | |
| wire clkoutd3_o; | |
| wire gw_vcc; | |
| wire gw_gnd; | |
| assign gw_vcc = 1'b1; | |
| assign gw_gnd = 1'b0; | |
| PLLVR pllvr_inst ( | |
| .CLKOUT(clkout), | |
| .LOCK(lock), | |
| .CLKOUTP(clkoutp_o), | |
| .CLKOUTD(clkoutd), | |
| .CLKOUTD3(clkoutd3_o), | |
| .RESET(gw_gnd), | |
| .RESET_P(gw_gnd), | |
| .CLKIN(clkin), | |
| .CLKFB(gw_gnd), | |
| .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), | |
| .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), | |
| .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), | |
| .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), | |
| .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), | |
| .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), | |
| .VREN(gw_vcc) | |
| ); | |
| defparam pllvr_inst.FCLKIN = "27"; | |
| defparam pllvr_inst.DYN_IDIV_SEL = "false"; | |
| defparam pllvr_inst.IDIV_SEL = 3; | |
| defparam pllvr_inst.DYN_FBDIV_SEL = "false"; | |
| defparam pllvr_inst.FBDIV_SEL = 54; | |
| defparam pllvr_inst.DYN_ODIV_SEL = "false"; | |
| defparam pllvr_inst.ODIV_SEL = 2; | |
| defparam pllvr_inst.PSDA_SEL = "0000"; | |
| defparam pllvr_inst.DYN_DA_EN = "false"; | |
| defparam pllvr_inst.DUTYDA_SEL = "1000"; | |
| defparam pllvr_inst.CLKOUT_FT_DIR = 1'b1; | |
| defparam pllvr_inst.CLKOUTP_FT_DIR = 1'b1; | |
| defparam pllvr_inst.CLKOUT_DLY_STEP = 0; | |
| defparam pllvr_inst.CLKOUTP_DLY_STEP = 0; | |
| defparam pllvr_inst.CLKFB_SEL = "internal"; | |
| defparam pllvr_inst.CLKOUT_BYPASS = "false"; | |
| defparam pllvr_inst.CLKOUTP_BYPASS = "false"; | |
| defparam pllvr_inst.CLKOUTD_BYPASS = "false"; | |
| defparam pllvr_inst.DYN_SDIV_SEL = 30; | |
| defparam pllvr_inst.CLKOUTD_SRC = "CLKOUT"; | |
| defparam pllvr_inst.CLKOUTD3_SRC = "CLKOUT"; | |
| defparam pllvr_inst.DEVICE = "GW1NSR-4C"; | |
| endmodule //TMDS_PLLVR |
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| module ChisNesPad( | |
| input clock, | |
| input reset, | |
| output io_dclock, | |
| output io_dlatch, | |
| input io_sdata, | |
| output io_data_valid, | |
| output [15:0] io_data_bits | |
| ); | |
| `ifdef RANDOMIZE_REG_INIT | |
| reg [31:0] _RAND_0; | |
| reg [31:0] _RAND_1; | |
| reg [31:0] _RAND_2; | |
| reg [31:0] _RAND_3; | |
| reg [31:0] _RAND_4; | |
| reg [31:0] _RAND_5; | |
| reg [31:0] _RAND_6; | |
| reg [31:0] _RAND_7; | |
| reg [31:0] _RAND_8; | |
| `endif // RANDOMIZE_REG_INIT | |
| reg [14:0] countReg; // @[chisnespad.scala 23:25] | |
| reg fallReg; // @[chisnespad.scala 24:24] | |
| reg riseReg; // @[chisnespad.scala 25:24] | |
| reg [4:0] regCount; // @[chisnespad.scala 28:25] | |
| reg [15:0] padReg; // @[chisnespad.scala 29:23] | |
| reg [2:0] stateReg; // @[chisnespad.scala 34:25] | |
| reg validReg; // @[chisnespad.scala 35:25] | |
| wire _T_5 = countReg >= 15'h6978; // @[chisnespad.scala 41:19] | |
| wire _T_6 = countReg == 15'h34bc; // @[chisnespad.scala 44:25] | |
| wire [14:0] _countReg_T_1 = countReg + 15'h1; // @[chisnespad.scala 46:28] | |
| wire [14:0] _GEN_1 = countReg == 15'h34bc ? _countReg_T_1 : _countReg_T_1; // @[chisnespad.scala 44:44 46:16 48:16] | |
| wire [14:0] _GEN_2 = countReg >= 15'h6978 ? 15'h0 : _GEN_1; // @[chisnespad.scala 41:33 42:16] | |
| wire _GEN_4 = countReg >= 15'h6978 ? 1'h0 : _T_6; // @[chisnespad.scala 39:11 41:33] | |
| wire [14:0] _GEN_5 = stateReg == 3'h2 | stateReg == 3'h1 | stateReg == 3'h4 ? _GEN_2 : countReg; // @[chisnespad.scala 23:25 40:73] | |
| wire _GEN_6 = (stateReg == 3'h2 | stateReg == 3'h1 | stateReg == 3'h4) & _T_5; // @[chisnespad.scala 38:11 40:73] | |
| wire _GEN_7 = (stateReg == 3'h2 | stateReg == 3'h1 | stateReg == 3'h4) & _GEN_4; // @[chisnespad.scala 39:11 40:73] | |
| wire [4:0] _regCount_T_1 = regCount - 5'h1; // @[chisnespad.scala 54:28] | |
| wire [15:0] _padReg_T_1 = {padReg[14:0],io_sdata}; // @[chisnespad.scala 55:39] | |
| wire [2:0] _GEN_13 = riseReg ? 3'h1 : stateReg; // @[chisnespad.scala 75:20 76:18 34:25] | |
| wire [2:0] _GEN_14 = regCount != 5'h0 ? 3'h2 : 3'h3; // @[chisnespad.scala 82:31 83:20 85:20] | |
| wire [2:0] _GEN_15 = fallReg ? _GEN_14 : stateReg; // @[chisnespad.scala 81:20 34:25] | |
| wire [2:0] _GEN_16 = 3'h3 == stateReg ? 3'h0 : stateReg; // @[chisnespad.scala 61:19 90:16 34:25] | |
| wire [2:0] _GEN_18 = 3'h1 == stateReg ? _GEN_15 : _GEN_16; // @[chisnespad.scala 61:19] | |
| wire _GEN_19 = 3'h1 == stateReg ? 1'h0 : 3'h3 == stateReg; // @[chisnespad.scala 60:12 61:19] | |
| reg io_dclock_REG; // @[chisnespad.scala 95:23] | |
| reg io_dlatch_REG; // @[chisnespad.scala 96:23] | |
| assign io_dclock = io_dclock_REG; // @[chisnespad.scala 95:13] | |
| assign io_dlatch = io_dlatch_REG; // @[chisnespad.scala 96:13] | |
| assign io_data_valid = validReg; // @[chisnespad.scala 98:17] | |
| assign io_data_bits = padReg; // @[chisnespad.scala 97:16] | |
| always @(posedge clock) begin | |
| if (reset) begin // @[chisnespad.scala 23:25] | |
| countReg <= 15'h0; // @[chisnespad.scala 23:25] | |
| end else if (3'h0 == stateReg) begin // @[chisnespad.scala 61:19] | |
| if (~io_data_valid) begin // @[chisnespad.scala 64:44] | |
| countReg <= 15'h0; // @[chisnespad.scala 66:18] | |
| end else begin | |
| countReg <= _GEN_5; | |
| end | |
| end else begin | |
| countReg <= _GEN_5; | |
| end | |
| if (reset) begin // @[chisnespad.scala 24:24] | |
| fallReg <= 1'h0; // @[chisnespad.scala 24:24] | |
| end else begin | |
| fallReg <= _GEN_7; | |
| end | |
| if (reset) begin // @[chisnespad.scala 25:24] | |
| riseReg <= 1'h0; // @[chisnespad.scala 25:24] | |
| end else begin | |
| riseReg <= _GEN_6; | |
| end | |
| if (reset) begin // @[chisnespad.scala 28:25] | |
| regCount <= 5'h11; // @[chisnespad.scala 28:25] | |
| end else if (3'h0 == stateReg) begin // @[chisnespad.scala 61:19] | |
| regCount <= 5'h11; // @[chisnespad.scala 63:16] | |
| end else if (riseReg) begin // @[chisnespad.scala 53:17] | |
| regCount <= _regCount_T_1; // @[chisnespad.scala 54:16] | |
| end | |
| if (reset) begin // @[chisnespad.scala 29:23] | |
| padReg <= 16'h0; // @[chisnespad.scala 29:23] | |
| end else if (riseReg) begin // @[chisnespad.scala 53:17] | |
| padReg <= _padReg_T_1; // @[chisnespad.scala 55:14] | |
| end | |
| if (reset) begin // @[chisnespad.scala 34:25] | |
| stateReg <= 3'h0; // @[chisnespad.scala 34:25] | |
| end else if (3'h0 == stateReg) begin // @[chisnespad.scala 61:19] | |
| if (~io_data_valid) begin // @[chisnespad.scala 64:44] | |
| stateReg <= 3'h4; // @[chisnespad.scala 65:18] | |
| end | |
| end else if (3'h4 == stateReg) begin // @[chisnespad.scala 61:19] | |
| if (riseReg) begin // @[chisnespad.scala 70:20] | |
| stateReg <= 3'h2; // @[chisnespad.scala 71:18] | |
| end | |
| end else if (3'h2 == stateReg) begin // @[chisnespad.scala 61:19] | |
| stateReg <= _GEN_13; | |
| end else begin | |
| stateReg <= _GEN_18; | |
| end | |
| if (reset) begin // @[chisnespad.scala 35:25] | |
| validReg <= 1'h0; // @[chisnespad.scala 35:25] | |
| end else if (3'h0 == stateReg) begin // @[chisnespad.scala 61:19] | |
| validReg <= 1'h0; // @[chisnespad.scala 60:12] | |
| end else if (3'h4 == stateReg) begin // @[chisnespad.scala 61:19] | |
| validReg <= 1'h0; // @[chisnespad.scala 60:12] | |
| end else if (3'h2 == stateReg) begin // @[chisnespad.scala 61:19] | |
| validReg <= 1'h0; // @[chisnespad.scala 60:12] | |
| end else begin | |
| validReg <= _GEN_19; | |
| end | |
| io_dclock_REG <= stateReg == 3'h1; // @[chisnespad.scala 95:33] | |
| io_dlatch_REG <= stateReg == 3'h4; // @[chisnespad.scala 96:33] | |
| end | |
| // Register and memory initialization | |
| `ifdef RANDOMIZE_GARBAGE_ASSIGN | |
| `define RANDOMIZE | |
| `endif | |
| `ifdef RANDOMIZE_INVALID_ASSIGN | |
| `define RANDOMIZE | |
| `endif | |
| `ifdef RANDOMIZE_REG_INIT | |
| `define RANDOMIZE | |
| `endif | |
| `ifdef RANDOMIZE_MEM_INIT | |
| `define RANDOMIZE | |
| `endif | |
| `ifndef RANDOM | |
| `define RANDOM $random | |
| `endif | |
| `ifdef RANDOMIZE_MEM_INIT | |
| integer initvar; | |
| `endif | |
| `ifndef SYNTHESIS | |
| `ifdef FIRRTL_BEFORE_INITIAL | |
| `FIRRTL_BEFORE_INITIAL | |
| `endif | |
| initial begin | |
| `ifdef RANDOMIZE | |
| `ifdef INIT_RANDOM | |
| `INIT_RANDOM | |
| `endif | |
| `ifndef VERILATOR | |
| `ifdef RANDOMIZE_DELAY | |
| #`RANDOMIZE_DELAY begin end | |
| `else | |
| #0.002 begin end | |
| `endif | |
| `endif | |
| `ifdef RANDOMIZE_REG_INIT | |
| _RAND_0 = {1{`RANDOM}}; | |
| countReg = _RAND_0[14:0]; | |
| _RAND_1 = {1{`RANDOM}}; | |
| fallReg = _RAND_1[0:0]; | |
| _RAND_2 = {1{`RANDOM}}; | |
| riseReg = _RAND_2[0:0]; | |
| _RAND_3 = {1{`RANDOM}}; | |
| regCount = _RAND_3[4:0]; | |
| _RAND_4 = {1{`RANDOM}}; | |
| padReg = _RAND_4[15:0]; | |
| _RAND_5 = {1{`RANDOM}}; | |
| stateReg = _RAND_5[2:0]; | |
| _RAND_6 = {1{`RANDOM}}; | |
| validReg = _RAND_6[0:0]; | |
| _RAND_7 = {1{`RANDOM}}; | |
| io_dclock_REG = _RAND_7[0:0]; | |
| _RAND_8 = {1{`RANDOM}}; | |
| io_dlatch_REG = _RAND_8[0:0]; | |
| `endif // RANDOMIZE_REG_INIT | |
| `endif // RANDOMIZE | |
| end // initial | |
| `ifdef FIRRTL_AFTER_INITIAL | |
| `FIRRTL_AFTER_INITIAL | |
| `endif | |
| `endif // SYNTHESIS | |
| endmodule | |
| module GbWrite( | |
| input clock, | |
| input reset, | |
| input io_gb_vsync, | |
| input io_gb_clk, | |
| input [1:0] io_gb_data, | |
| output [14:0] io_Maddr, | |
| output [1:0] io_Mdata, | |
| output io_Mwrite | |
| ); | |
| `ifdef RANDOMIZE_REG_INIT | |
| reg [31:0] _RAND_0; | |
| reg [31:0] _RAND_1; | |
| reg [31:0] _RAND_2; | |
| reg [31:0] _RAND_3; | |
| `endif // RANDOMIZE_REG_INIT | |
| reg [14:0] pixelCount; // @[gbwrite.scala 27:27] | |
| reg [1:0] pixel; // @[gbwrite.scala 31:22] | |
| reg REG; // @[gbinclude.scala 24:42] | |
| wire _T_1 = io_gb_vsync & ~REG; // @[gbinclude.scala 24:31] | |
| reg REG_2; // @[gbinclude.scala 25:43] | |
| wire _T_5 = ~io_gb_clk & REG_2; // @[gbinclude.scala 25:33] | |
| wire [14:0] _pixelCount_T_1 = pixelCount + 15'h1; // @[gbwrite.scala 49:30] | |
| assign io_Maddr = pixelCount; // @[gbwrite.scala 53:12] | |
| assign io_Mdata = pixel; // @[gbwrite.scala 55:12] | |
| assign io_Mwrite = ~io_gb_clk & REG_2; // @[gbinclude.scala 25:33] | |
| always @(posedge clock) begin | |
| if (reset) begin // @[gbwrite.scala 27:27] | |
| pixelCount <= 15'h5a00; // @[gbwrite.scala 27:27] | |
| end else if (_T_5) begin // @[gbwrite.scala 48:27] | |
| pixelCount <= _pixelCount_T_1; // @[gbwrite.scala 49:16] | |
| end else if (_T_1) begin // @[gbwrite.scala 34:28] | |
| pixelCount <= 15'h0; // @[gbwrite.scala 37:16] | |
| end | |
| if (reset) begin // @[gbwrite.scala 31:22] | |
| pixel <= 2'h0; // @[gbwrite.scala 31:22] | |
| end else begin | |
| pixel <= io_gb_data; // @[gbwrite.scala 54:9] | |
| end | |
| REG <= io_gb_vsync; // @[gbinclude.scala 24:42] | |
| REG_2 <= io_gb_clk; // @[gbinclude.scala 25:43] | |
| end | |
| // Register and memory initialization | |
| `ifdef RANDOMIZE_GARBAGE_ASSIGN | |
| `define RANDOMIZE | |
| `endif | |
| `ifdef RANDOMIZE_INVALID_ASSIGN | |
| `define RANDOMIZE | |
| `endif | |
| `ifdef RANDOMIZE_REG_INIT | |
| `define RANDOMIZE | |
| `endif | |
| `ifdef RANDOMIZE_MEM_INIT | |
| `define RANDOMIZE | |
| `endif | |
| `ifndef RANDOM | |
| `define RANDOM $random | |
| `endif | |
| `ifdef RANDOMIZE_MEM_INIT | |
| integer initvar; | |
| `endif | |
| `ifndef SYNTHESIS | |
| `ifdef FIRRTL_BEFORE_INITIAL | |
| `FIRRTL_BEFORE_INITIAL | |
| `endif | |
| initial begin | |
| `ifdef RANDOMIZE | |
| `ifdef INIT_RANDOM | |
| `INIT_RANDOM | |
| `endif | |
| `ifndef VERILATOR | |
| `ifdef RANDOMIZE_DELAY | |
| #`RANDOMIZE_DELAY begin end | |
| `else | |
| #0.002 begin end | |
| `endif | |
| `endif | |
| `ifdef RANDOMIZE_REG_INIT | |
| _RAND_0 = {1{`RANDOM}}; | |
| pixelCount = _RAND_0[14:0]; | |
| _RAND_1 = {1{`RANDOM}}; | |
| pixel = _RAND_1[1:0]; | |
| _RAND_2 = {1{`RANDOM}}; | |
| REG = _RAND_2[0:0]; | |
| _RAND_3 = {1{`RANDOM}}; | |
| REG_2 = _RAND_3[0:0]; | |
| `endif // RANDOMIZE_REG_INIT | |
| `endif // RANDOMIZE | |
| end // initial | |
| `ifdef FIRRTL_AFTER_INITIAL | |
| `FIRRTL_AFTER_INITIAL | |
| `endif | |
| `endif // SYNTHESIS | |
| endmodule | |
| module HVSync( | |
| input clock, | |
| input reset, | |
| output io_hsync, | |
| output io_vsync, | |
| output io_display_on, | |
| output [10:0] io_hpos, | |
| output [9:0] io_vpos | |
| ); | |
| `ifdef RANDOMIZE_REG_INIT | |
| reg [31:0] _RAND_0; | |
| reg [31:0] _RAND_1; | |
| `endif // RANDOMIZE_REG_INIT | |
| wire [10:0] H_SYNC_END = 11'h596 - 11'h1; // @[hvsync.scala 51:51] | |
| wire [10:0] H_MAX = 11'h672 - 11'h1; // @[hvsync.scala 52:60] | |
| wire [9:0] V_SYNC_END = 10'h2e9 - 10'h1; // @[hvsync.scala 54:52] | |
| wire [9:0] V_MAX = 10'h2ee - 10'h1; // @[hvsync.scala 55:60] | |
| reg [10:0] hpos_count; // @[hvsync.scala 62:27] | |
| reg [9:0] vpos_count; // @[hvsync.scala 63:27] | |
| wire _io_hsync_T_1 = hpos_count <= H_SYNC_END; // @[hvsync.scala 71:29] | |
| wire hpos_max = hpos_count == H_MAX; // @[hvsync.scala 73:29] | |
| wire vpos_max = vpos_count == V_MAX; // @[hvsync.scala 74:29] | |
| wire [10:0] _hpos_count_T_1 = hpos_count + 11'h1; // @[hvsync.scala 76:28] | |
| wire _io_vsync_T_1 = vpos_count <= V_SYNC_END; // @[hvsync.scala 83:27] | |
| wire [9:0] _vpos_count_T_1 = vpos_count + 10'h1; // @[hvsync.scala 85:30] | |
| assign io_hsync = ~(hpos_count >= 11'h56e & _io_hsync_T_1); // @[hvsync.scala 70:15] | |
| assign io_vsync = ~(vpos_count >= 10'h2e4 & _io_vsync_T_1); // @[hvsync.scala 82:15] | |
| assign io_display_on = hpos_count < 11'h500 & vpos_count < 10'h2d0; // @[hvsync.scala 67:45] | |
| assign io_hpos = hpos_count; // @[hvsync.scala 65:11] | |
| assign io_vpos = vpos_count; // @[hvsync.scala 64:11] | |
| always @(posedge clock) begin | |
| if (reset) begin // @[hvsync.scala 62:27] | |
| hpos_count <= 11'h0; // @[hvsync.scala 62:27] | |
| end else if (hpos_max) begin // @[hvsync.scala 77:17] | |
| hpos_count <= 11'h0; // @[hvsync.scala 78:16] | |
| end else begin | |
| hpos_count <= _hpos_count_T_1; // @[hvsync.scala 76:14] | |
| end | |
| if (reset) begin // @[hvsync.scala 63:27] | |
| vpos_count <= 10'h0; // @[hvsync.scala 63:27] | |
| end else if (hpos_max) begin // @[hvsync.scala 84:18] | |
| if (vpos_max) begin // @[hvsync.scala 86:20] | |
| vpos_count <= 10'h0; // @[hvsync.scala 87:18] | |
| end else begin | |
| vpos_count <= _vpos_count_T_1; // @[hvsync.scala 85:16] | |
| end | |
| end | |
| end | |
| // Register and memory initialization | |
| `ifdef RANDOMIZE_GARBAGE_ASSIGN | |
| `define RANDOMIZE | |
| `endif | |
| `ifdef RANDOMIZE_INVALID_ASSIGN | |
| `define RANDOMIZE | |
| `endif | |
| `ifdef RANDOMIZE_REG_INIT | |
| `define RANDOMIZE | |
| `endif | |
| `ifdef RANDOMIZE_MEM_INIT | |
| `define RANDOMIZE | |
| `endif | |
| `ifndef RANDOM | |
| `define RANDOM $random | |
| `endif | |
| `ifdef RANDOMIZE_MEM_INIT | |
| integer initvar; | |
| `endif | |
| `ifndef SYNTHESIS | |
| `ifdef FIRRTL_BEFORE_INITIAL | |
| `FIRRTL_BEFORE_INITIAL | |
| `endif | |
| initial begin | |
| `ifdef RANDOMIZE | |
| `ifdef INIT_RANDOM | |
| `INIT_RANDOM | |
| `endif | |
| `ifndef VERILATOR | |
| `ifdef RANDOMIZE_DELAY | |
| #`RANDOMIZE_DELAY begin end | |
| `else | |
| #0.002 begin end | |
| `endif | |
| `endif | |
| `ifdef RANDOMIZE_REG_INIT | |
| _RAND_0 = {1{`RANDOM}}; | |
| hpos_count = _RAND_0[10:0]; | |
| _RAND_1 = {1{`RANDOM}}; | |
| vpos_count = _RAND_1[9:0]; | |
| `endif // RANDOMIZE_REG_INIT | |
| `endif // RANDOMIZE | |
| end // initial | |
| `ifdef FIRRTL_AFTER_INITIAL | |
| `FIRRTL_AFTER_INITIAL | |
| `endif | |
| `endif // SYNTHESIS | |
| endmodule | |
| module MemHdmi( | |
| input clock, | |
| input reset, | |
| output [14:0] io_mem_addr, | |
| input [1:0] io_mem_data, | |
| output io_video_hsync, | |
| output io_video_vsync, | |
| output [7:0] io_video_color_red, | |
| output [7:0] io_video_color_green, | |
| output [7:0] io_video_color_blue, | |
| output io_video_de, | |
| input [1:0] io_pattern_num | |
| ); | |
| `ifdef RANDOMIZE_REG_INIT | |
| reg [31:0] _RAND_0; | |
| reg [31:0] _RAND_1; | |
| reg [31:0] _RAND_2; | |
| reg [31:0] _RAND_3; | |
| `endif // RANDOMIZE_REG_INIT | |
| wire hv_sync_clock; // @[memhdmi.scala 32:25] | |
| wire hv_sync_reset; // @[memhdmi.scala 32:25] | |
| wire hv_sync_io_hsync; // @[memhdmi.scala 32:25] | |
| wire hv_sync_io_vsync; // @[memhdmi.scala 32:25] | |
| wire hv_sync_io_display_on; // @[memhdmi.scala 32:25] | |
| wire [10:0] hv_sync_io_hpos; // @[memhdmi.scala 32:25] | |
| wire [9:0] hv_sync_io_vpos; // @[memhdmi.scala 32:25] | |
| wire [10:0] _xpos_T_1 = 11'h500 - 11'h280; // @[memhdmi.scala 40:35] | |
| wire [10:0] xpos = _xpos_T_1 / 2'h2; // @[memhdmi.scala 40:54] | |
| wire [9:0] _ypos_T_1 = 10'h2d0 - 10'h240; // @[memhdmi.scala 41:35] | |
| wire [9:0] ypos = _ypos_T_1 / 2'h2; // @[memhdmi.scala 41:55] | |
| wire gb_display = hv_sync_io_display_on & hv_sync_io_vpos > ypos & hv_sync_io_hpos > xpos; // @[memhdmi.scala 43:71] | |
| reg [7:0] gblines; // @[memhdmi.scala 45:26] | |
| reg [7:0] gbcols; // @[memhdmi.scala 46:25] | |
| reg [14:0] gbpix; // @[memhdmi.scala 47:24] | |
| reg [1:0] state; // @[memhdmi.scala 51:24] | |
| wire _T_3 = gblines <= 8'h8f; // @[memhdmi.scala 61:22] | |
| wire _T_4 = gbcols >= 8'h9f & _T_3; // @[memhdmi.scala 60:40] | |
| wire [1:0] _GEN_1 = _T_4 ? 2'h2 : state; // @[memhdmi.scala 61:41 62:17 51:24] | |
| wire [1:0] _GEN_3 = gblines < 8'h90 ? 2'h1 : state; // @[memhdmi.scala 73:38 74:19 51:24] | |
| wire [1:0] _GEN_4 = ~hv_sync_io_hsync ? _GEN_3 : state; // @[memhdmi.scala 51:24 72:32] | |
| wire [1:0] _GEN_5 = ~hv_sync_io_vsync ? 2'h0 : _GEN_4; // @[memhdmi.scala 77:32 78:17] | |
| wire [1:0] _GEN_6 = 2'h3 == state ? _GEN_5 : state; // @[memhdmi.scala 53:19 51:24] | |
| wire [10:0] _GEN_0 = hv_sync_io_hpos % 11'h4; // @[memhdmi.scala 84:39] | |
| wire [2:0] _newgbline_T = _GEN_0[2:0]; // @[memhdmi.scala 84:39] | |
| wire newgbline = _newgbline_T == 3'h3; // @[memhdmi.scala 84:49] | |
| wire [9:0] _GEN_2 = hv_sync_io_vpos % 10'h4; // @[memhdmi.scala 85:38] | |
| wire [2:0] _newgbcol_T = _GEN_2[2:0]; // @[memhdmi.scala 85:38] | |
| wire newgbcol = _newgbcol_T == 3'h3; // @[memhdmi.scala 85:48] | |
| wire [14:0] _gbpix_T_1 = gbpix + 15'h1; // @[memhdmi.scala 89:24] | |
| wire [7:0] _gbcols_T_1 = gbcols + 8'h1; // @[memhdmi.scala 90:26] | |
| wire [14:0] _GEN_10 = state == 2'h1 & newgbline ? _gbpix_T_1 : gbpix; // @[memhdmi.scala 88:44 89:15 47:24] | |
| wire [7:0] _GEN_11 = state == 2'h1 & newgbline ? _gbcols_T_1 : gbcols; // @[memhdmi.scala 88:44 90:16 46:25] | |
| wire [7:0] _gblines_T_1 = gblines + 8'h1; // @[memhdmi.scala 94:32] | |
| wire [14:0] _gbpix_T_5 = gbpix - 15'ha0; // @[memhdmi.scala 97:28] | |
| wire [14:0] _gbpix_T_7 = _gbpix_T_5 + 15'h1; // @[memhdmi.scala 97:40] | |
| wire [7:0] _GEN_12 = newgbcol ? _gblines_T_1 : gblines; // @[memhdmi.scala 93:23 94:21 45:26] | |
| wire [14:0] _GEN_13 = newgbcol ? _gbpix_T_1 : _gbpix_T_7; // @[memhdmi.scala 93:23 95:19 97:19] | |
| wire _GEN_74 = 2'h0 == io_pattern_num; // @[gbhdmi.scala 23:{34,34}] | |
| wire _GEN_75 = 2'h1 == io_mem_data; // @[gbhdmi.scala 23:{34,34}] | |
| wire [5:0] _GEN_24 = 2'h0 == io_pattern_num & 2'h1 == io_mem_data ? 6'hc : 6'h26; // @[gbhdmi.scala 23:{34,34}] | |
| wire _GEN_77 = 2'h2 == io_mem_data; // @[gbhdmi.scala 23:{34,34}] | |
| wire [5:0] _GEN_25 = 2'h0 == io_pattern_num & 2'h2 == io_mem_data ? 6'h1e : _GEN_24; // @[gbhdmi.scala 23:{34,34}] | |
| wire _GEN_79 = 2'h3 == io_mem_data; // @[gbhdmi.scala 23:{34,34}] | |
| wire [5:0] _GEN_26 = 2'h0 == io_pattern_num & 2'h3 == io_mem_data ? 6'h3 : _GEN_25; // @[gbhdmi.scala 23:{34,34}] | |
| wire _GEN_80 = 2'h1 == io_pattern_num; // @[gbhdmi.scala 23:{34,34}] | |
| wire _GEN_81 = 2'h0 == io_mem_data; // @[gbhdmi.scala 23:{34,34}] | |
| wire [5:0] _GEN_27 = 2'h1 == io_pattern_num & 2'h0 == io_mem_data ? 6'h3f : _GEN_26; // @[gbhdmi.scala 23:{34,34}] | |
| wire [5:0] _GEN_28 = 2'h1 == io_pattern_num & 2'h1 == io_mem_data ? 6'h2a : _GEN_27; // @[gbhdmi.scala 23:{34,34}] | |
| wire [5:0] _GEN_29 = 2'h1 == io_pattern_num & 2'h2 == io_mem_data ? 6'h15 : _GEN_28; // @[gbhdmi.scala 23:{34,34}] | |
| wire [5:0] _GEN_30 = 2'h1 == io_pattern_num & 2'h3 == io_mem_data ? 6'h0 : _GEN_29; // @[gbhdmi.scala 23:{34,34}] | |
| wire _GEN_88 = 2'h2 == io_pattern_num; // @[gbhdmi.scala 23:{34,34}] | |
| wire [5:0] _GEN_31 = 2'h2 == io_pattern_num & 2'h0 == io_mem_data ? 6'h3d : _GEN_30; // @[gbhdmi.scala 23:{34,34}] | |
| wire [5:0] _GEN_32 = 2'h2 == io_pattern_num & 2'h1 == io_mem_data ? 6'h3e : _GEN_31; // @[gbhdmi.scala 23:{34,34}] | |
| wire [5:0] _GEN_33 = 2'h2 == io_pattern_num & 2'h2 == io_mem_data ? 6'h31 : _GEN_32; // @[gbhdmi.scala 23:{34,34}] | |
| wire [5:0] _GEN_34 = 2'h2 == io_pattern_num & 2'h3 == io_mem_data ? 6'h1b : _GEN_33; // @[gbhdmi.scala 23:{34,34}] | |
| wire _GEN_96 = 2'h3 == io_pattern_num; // @[gbhdmi.scala 23:{34,34}] | |
| wire [5:0] _GEN_35 = 2'h3 == io_pattern_num & 2'h0 == io_mem_data ? 6'h3f : _GEN_34; // @[gbhdmi.scala 23:{34,34}] | |
| wire [5:0] _GEN_36 = 2'h3 == io_pattern_num & 2'h1 == io_mem_data ? 6'h0 : _GEN_35; // @[gbhdmi.scala 23:{34,34}] | |
| wire [5:0] _GEN_37 = 2'h3 == io_pattern_num & 2'h2 == io_mem_data ? 6'h0 : _GEN_36; // @[gbhdmi.scala 23:{34,34}] | |
| wire [5:0] _GEN_38 = 2'h3 == io_pattern_num & 2'h3 == io_mem_data ? 6'h0 : _GEN_37; // @[gbhdmi.scala 23:{34,34}] | |
| wire [7:0] io_video_color_retColors_1_red = {_GEN_38,2'h0}; // @[gbhdmi.scala 23:34] | |
| wire [5:0] _GEN_40 = _GEN_74 & _GEN_75 ? 6'h18 : 6'h2f; // @[gbhdmi.scala 24:{36,36}] | |
| wire [5:0] _GEN_41 = _GEN_74 & _GEN_77 ? 6'h27 : _GEN_40; // @[gbhdmi.scala 24:{36,36}] | |
| wire [5:0] _GEN_42 = _GEN_74 & _GEN_79 ? 6'he : _GEN_41; // @[gbhdmi.scala 24:{36,36}] | |
| wire [5:0] _GEN_43 = _GEN_80 & _GEN_81 ? 6'h3f : _GEN_42; // @[gbhdmi.scala 24:{36,36}] | |
| wire [5:0] _GEN_44 = _GEN_80 & _GEN_75 ? 6'h2a : _GEN_43; // @[gbhdmi.scala 24:{36,36}] | |
| wire [5:0] _GEN_45 = _GEN_80 & _GEN_77 ? 6'h15 : _GEN_44; // @[gbhdmi.scala 24:{36,36}] | |
| wire [5:0] _GEN_46 = _GEN_80 & _GEN_79 ? 6'h0 : _GEN_45; // @[gbhdmi.scala 24:{36,36}] | |
| wire [5:0] _GEN_47 = _GEN_88 & _GEN_81 ? 6'h29 : _GEN_46; // @[gbhdmi.scala 24:{36,36}] | |
| wire [5:0] _GEN_48 = _GEN_88 & _GEN_75 ? 6'h13 : _GEN_47; // @[gbhdmi.scala 24:{36,36}] | |
| wire [5:0] _GEN_49 = _GEN_88 & _GEN_77 ? 6'h1 : _GEN_48; // @[gbhdmi.scala 24:{36,36}] | |
| wire [5:0] _GEN_50 = _GEN_88 & _GEN_79 ? 6'h1 : _GEN_49; // @[gbhdmi.scala 24:{36,36}] | |
| wire [5:0] _GEN_51 = _GEN_96 & _GEN_81 ? 6'h3f : _GEN_50; // @[gbhdmi.scala 24:{36,36}] | |
| wire [5:0] _GEN_52 = _GEN_96 & _GEN_75 ? 6'h3f : _GEN_51; // @[gbhdmi.scala 24:{36,36}] | |
| wire [5:0] _GEN_53 = _GEN_96 & _GEN_77 ? 6'h0 : _GEN_52; // @[gbhdmi.scala 24:{36,36}] | |
| wire [5:0] _GEN_54 = _GEN_96 & _GEN_79 ? 6'h0 : _GEN_53; // @[gbhdmi.scala 24:{36,36}] | |
| wire [7:0] io_video_color_retColors_1_green = {_GEN_54,2'h0}; // @[gbhdmi.scala 24:36] | |
| wire [5:0] _GEN_56 = _GEN_74 & _GEN_75 ? 6'hc : 6'h3; // @[gbhdmi.scala 25:{35,35}] | |
| wire [5:0] _GEN_57 = _GEN_74 & _GEN_77 ? 6'h3 : _GEN_56; // @[gbhdmi.scala 25:{35,35}] | |
| wire [5:0] _GEN_58 = _GEN_74 & _GEN_79 ? 6'h3 : _GEN_57; // @[gbhdmi.scala 25:{35,35}] | |
| wire [5:0] _GEN_59 = _GEN_80 & _GEN_81 ? 6'h3f : _GEN_58; // @[gbhdmi.scala 25:{35,35}] | |
| wire [5:0] _GEN_60 = _GEN_80 & _GEN_75 ? 6'h2a : _GEN_59; // @[gbhdmi.scala 25:{35,35}] | |
| wire [5:0] _GEN_61 = _GEN_80 & _GEN_77 ? 6'h15 : _GEN_60; // @[gbhdmi.scala 25:{35,35}] | |
| wire [5:0] _GEN_62 = _GEN_80 & _GEN_79 ? 6'h0 : _GEN_61; // @[gbhdmi.scala 25:{35,35}] | |
| wire [5:0] _GEN_63 = _GEN_88 & _GEN_81 ? 6'h38 : _GEN_62; // @[gbhdmi.scala 25:{35,35}] | |
| wire [5:0] _GEN_64 = _GEN_88 & _GEN_75 ? 6'h33 : _GEN_63; // @[gbhdmi.scala 25:{35,35}] | |
| wire [5:0] _GEN_65 = _GEN_88 & _GEN_77 ? 6'h25 : _GEN_64; // @[gbhdmi.scala 25:{35,35}] | |
| wire [5:0] _GEN_66 = _GEN_88 & _GEN_79 ? 6'h15 : _GEN_65; // @[gbhdmi.scala 25:{35,35}] | |
| wire [5:0] _GEN_67 = _GEN_96 & _GEN_81 ? 6'h3f : _GEN_66; // @[gbhdmi.scala 25:{35,35}] | |
| wire [5:0] _GEN_68 = _GEN_96 & _GEN_75 ? 6'h3f : _GEN_67; // @[gbhdmi.scala 25:{35,35}] | |
| wire [5:0] _GEN_69 = _GEN_96 & _GEN_77 ? 6'h3f : _GEN_68; // @[gbhdmi.scala 25:{35,35}] | |
| wire [5:0] _GEN_70 = _GEN_96 & _GEN_79 ? 6'h0 : _GEN_69; // @[gbhdmi.scala 25:{35,35}] | |
| wire [7:0] io_video_color_retColors_1_blue = {_GEN_70,2'h0}; // @[gbhdmi.scala 25:35] | |
| HVSync hv_sync ( // @[memhdmi.scala 32:25] | |
| .clock(hv_sync_clock), | |
| .reset(hv_sync_reset), | |
| .io_hsync(hv_sync_io_hsync), | |
| .io_vsync(hv_sync_io_vsync), | |
| .io_display_on(hv_sync_io_display_on), | |
| .io_hpos(hv_sync_io_hpos), | |
| .io_vpos(hv_sync_io_vpos) | |
| ); | |
| assign io_mem_addr = gbpix; // @[memhdmi.scala 117:18] | |
| assign io_video_hsync = hv_sync_io_hsync; // @[memhdmi.scala 33:20] | |
| assign io_video_vsync = hv_sync_io_vsync; // @[memhdmi.scala 34:20] | |
| assign io_video_color_red = gb_display & state != 2'h3 ? io_video_color_retColors_1_red : 8'h0; // @[memhdmi.scala 111:20 112:42 113:22] | |
| assign io_video_color_green = gb_display & state != 2'h3 ? io_video_color_retColors_1_green : 8'h0; // @[memhdmi.scala 111:20 112:42 113:22] | |
| assign io_video_color_blue = gb_display & state != 2'h3 ? io_video_color_retColors_1_blue : 8'h0; // @[memhdmi.scala 111:20 112:42 113:22] | |
| assign io_video_de = hv_sync_io_display_on; // @[memhdmi.scala 35:20] | |
| assign hv_sync_clock = clock; | |
| assign hv_sync_reset = reset; | |
| always @(posedge clock) begin | |
| if (reset) begin // @[memhdmi.scala 45:26] | |
| gblines <= 8'h0; // @[memhdmi.scala 45:26] | |
| end else if (state == 2'h0) begin // @[memhdmi.scala 102:25] | |
| gblines <= 8'h0; // @[memhdmi.scala 105:15] | |
| end else if (gb_display) begin // @[memhdmi.scala 87:21] | |
| if (state == 2'h2) begin // @[memhdmi.scala 92:30] | |
| gblines <= _GEN_12; | |
| end | |
| end | |
| if (reset) begin // @[memhdmi.scala 46:25] | |
| gbcols <= 8'h0; // @[memhdmi.scala 46:25] | |
| end else if (state == 2'h0) begin // @[memhdmi.scala 102:25] | |
| gbcols <= 8'h0; // @[memhdmi.scala 104:14] | |
| end else if (gb_display) begin // @[memhdmi.scala 87:21] | |
| if (state == 2'h2) begin // @[memhdmi.scala 92:30] | |
| gbcols <= 8'h0; // @[memhdmi.scala 99:16] | |
| end else begin | |
| gbcols <= _GEN_11; | |
| end | |
| end | |
| if (reset) begin // @[memhdmi.scala 47:24] | |
| gbpix <= 15'h0; // @[memhdmi.scala 47:24] | |
| end else if (state == 2'h0) begin // @[memhdmi.scala 102:25] | |
| gbpix <= 15'h0; // @[memhdmi.scala 103:13] | |
| end else if (gb_display) begin // @[memhdmi.scala 87:21] | |
| if (state == 2'h2) begin // @[memhdmi.scala 92:30] | |
| gbpix <= _GEN_13; | |
| end else begin | |
| gbpix <= _GEN_10; | |
| end | |
| end | |
| if (reset) begin // @[memhdmi.scala 51:24] | |
| state <= 2'h0; // @[memhdmi.scala 51:24] | |
| end else if (2'h0 == state) begin // @[memhdmi.scala 53:19] | |
| if (gb_display) begin // @[memhdmi.scala 55:25] | |
| state <= 2'h1; // @[memhdmi.scala 56:17] | |
| end | |
| end else if (2'h1 == state) begin // @[memhdmi.scala 53:19] | |
| if (gblines > 8'h8f) begin // @[memhdmi.scala 64:41] | |
| state <= 2'h3; // @[memhdmi.scala 65:17] | |
| end else begin | |
| state <= _GEN_1; | |
| end | |
| end else if (2'h2 == state) begin // @[memhdmi.scala 53:19] | |
| state <= 2'h3; // @[memhdmi.scala 69:19] | |
| end else begin | |
| state <= _GEN_6; | |
| end | |
| end | |
| // Register and memory initialization | |
| `ifdef RANDOMIZE_GARBAGE_ASSIGN | |
| `define RANDOMIZE | |
| `endif | |
| `ifdef RANDOMIZE_INVALID_ASSIGN | |
| `define RANDOMIZE | |
| `endif | |
| `ifdef RANDOMIZE_REG_INIT | |
| `define RANDOMIZE | |
| `endif | |
| `ifdef RANDOMIZE_MEM_INIT | |
| `define RANDOMIZE | |
| `endif | |
| `ifndef RANDOM | |
| `define RANDOM $random | |
| `endif | |
| `ifdef RANDOMIZE_MEM_INIT | |
| integer initvar; | |
| `endif | |
| `ifndef SYNTHESIS | |
| `ifdef FIRRTL_BEFORE_INITIAL | |
| `FIRRTL_BEFORE_INITIAL | |
| `endif | |
| initial begin | |
| `ifdef RANDOMIZE | |
| `ifdef INIT_RANDOM | |
| `INIT_RANDOM | |
| `endif | |
| `ifndef VERILATOR | |
| `ifdef RANDOMIZE_DELAY | |
| #`RANDOMIZE_DELAY begin end | |
| `else | |
| #0.002 begin end | |
| `endif | |
| `endif | |
| `ifdef RANDOMIZE_REG_INIT | |
| _RAND_0 = {1{`RANDOM}}; | |
| gblines = _RAND_0[7:0]; | |
| _RAND_1 = {1{`RANDOM}}; | |
| gbcols = _RAND_1[7:0]; | |
| _RAND_2 = {1{`RANDOM}}; | |
| gbpix = _RAND_2[14:0]; | |
| _RAND_3 = {1{`RANDOM}}; | |
| state = _RAND_3[1:0]; | |
| `endif // RANDOMIZE_REG_INIT | |
| `endif // RANDOMIZE | |
| end // initial | |
| `ifdef FIRRTL_AFTER_INITIAL | |
| `FIRRTL_AFTER_INITIAL | |
| `endif | |
| `endif // SYNTHESIS | |
| endmodule | |
| module TMDSEncoder( | |
| input clock, | |
| input reset, | |
| input io_en, | |
| input [1:0] io_ctrl, | |
| input [7:0] io_din, | |
| output [9:0] io_dout | |
| ); | |
| `ifdef RANDOMIZE_REG_INIT | |
| reg [31:0] _RAND_0; | |
| reg [31:0] _RAND_1; | |
| `endif // RANDOMIZE_REG_INIT | |
| wire [1:0] _n_one_din_T_8 = io_din[0] + io_din[1]; // @[Bitwise.scala 48:55] | |
| wire [1:0] _n_one_din_T_10 = io_din[2] + io_din[3]; // @[Bitwise.scala 48:55] | |
| wire [2:0] _n_one_din_T_12 = _n_one_din_T_8 + _n_one_din_T_10; // @[Bitwise.scala 48:55] | |
| wire [1:0] _n_one_din_T_14 = io_din[4] + io_din[5]; // @[Bitwise.scala 48:55] | |
| wire [1:0] _n_one_din_T_16 = io_din[6] + io_din[7]; // @[Bitwise.scala 48:55] | |
| wire [2:0] _n_one_din_T_18 = _n_one_din_T_14 + _n_one_din_T_16; // @[Bitwise.scala 48:55] | |
| wire [3:0] n_one_din = _n_one_din_T_12 + _n_one_din_T_18; // @[Bitwise.scala 48:55] | |
| wire [6:0] _xored_res_T_8 = {io_din[7],io_din[6],io_din[5],io_din[4],io_din[3],io_din[2],io_din[1]}; // @[TmdsEncoder.scala 21:65] | |
| wire [5:0] _xored_res_res_T_7 = {_xored_res_T_8[6],_xored_res_T_8[5],_xored_res_T_8[4],_xored_res_T_8[3], | |
| _xored_res_T_8[2],_xored_res_T_8[1]}; // @[TmdsEncoder.scala 21:65] | |
| wire [4:0] _xored_res_res_res_T_6 = {_xored_res_res_T_7[5],_xored_res_res_T_7[4],_xored_res_res_T_7[3], | |
| _xored_res_res_T_7[2],_xored_res_res_T_7[1]}; // @[TmdsEncoder.scala 21:65] | |
| wire [3:0] _xored_res_res_res_res_T_5 = {_xored_res_res_res_T_6[4],_xored_res_res_res_T_6[3],_xored_res_res_res_T_6[2] | |
| ,_xored_res_res_res_T_6[1]}; // @[TmdsEncoder.scala 21:65] | |
| wire [2:0] _xored_res_res_res_res_res_T_4 = {_xored_res_res_res_res_T_5[3],_xored_res_res_res_res_T_5[2], | |
| _xored_res_res_res_res_T_5[1]}; // @[TmdsEncoder.scala 21:65] | |
| wire [1:0] _xored_res_res_res_res_res_res_T_3 = {_xored_res_res_res_res_res_T_4[2],_xored_res_res_res_res_res_T_4[1]}; // @[TmdsEncoder.scala 21:65] | |
| wire xored_res_res_res_res_res_res_res = _xored_res_res_res_res_res_res_T_3[1]; // @[TmdsEncoder.scala 21:48] | |
| wire [1:0] _xored_res_res_res_res_res_res_T_7 = {xored_res_res_res_res_res_res_res,xored_res_res_res_res_res_res_res}; // @[TmdsEncoder.scala 22:49] | |
| wire [1:0] _GEN_13 = {{1'd0}, _xored_res_res_res_res_res_res_T_3[0]}; // @[TmdsEncoder.scala 22:30] | |
| wire [1:0] xored_res_res_res_res_res_res = _GEN_13 ^ _xored_res_res_res_res_res_res_T_7; // @[TmdsEncoder.scala 22:30] | |
| wire [2:0] _xored_res_res_res_res_res_T_10 = {xored_res_res_res_res_res_res[0],xored_res_res_res_res_res_res}; // @[TmdsEncoder.scala 22:49] | |
| wire [2:0] _GEN_14 = {{2'd0}, _xored_res_res_res_res_res_T_4[0]}; // @[TmdsEncoder.scala 22:30] | |
| wire [2:0] xored_res_res_res_res_res = _GEN_14 ^ _xored_res_res_res_res_res_T_10; // @[TmdsEncoder.scala 22:30] | |
| wire [3:0] _xored_res_res_res_res_T_13 = {xored_res_res_res_res_res[0],xored_res_res_res_res_res}; // @[TmdsEncoder.scala 22:49] | |
| wire [3:0] _GEN_15 = {{3'd0}, _xored_res_res_res_res_T_5[0]}; // @[TmdsEncoder.scala 22:30] | |
| wire [3:0] xored_res_res_res_res = _GEN_15 ^ _xored_res_res_res_res_T_13; // @[TmdsEncoder.scala 22:30] | |
| wire [4:0] _xored_res_res_res_T_16 = {xored_res_res_res_res[0],xored_res_res_res_res}; // @[TmdsEncoder.scala 22:49] | |
| wire [4:0] _GEN_16 = {{4'd0}, _xored_res_res_res_T_6[0]}; // @[TmdsEncoder.scala 22:30] | |
| wire [4:0] xored_res_res_res = _GEN_16 ^ _xored_res_res_res_T_16; // @[TmdsEncoder.scala 22:30] | |
| wire [5:0] _xored_res_res_T_19 = {xored_res_res_res[0],xored_res_res_res}; // @[TmdsEncoder.scala 22:49] | |
| wire [5:0] _GEN_17 = {{5'd0}, _xored_res_res_T_7[0]}; // @[TmdsEncoder.scala 22:30] | |
| wire [5:0] xored_res_res = _GEN_17 ^ _xored_res_res_T_19; // @[TmdsEncoder.scala 22:30] | |
| wire [6:0] _xored_res_T_22 = {xored_res_res[0],xored_res_res}; // @[TmdsEncoder.scala 22:49] | |
| wire [6:0] _GEN_18 = {{6'd0}, _xored_res_T_8[0]}; // @[TmdsEncoder.scala 22:30] | |
| wire [6:0] xored_res = _GEN_18 ^ _xored_res_T_22; // @[TmdsEncoder.scala 22:30] | |
| wire [7:0] _xored_T_15 = {xored_res[0],xored_res}; // @[TmdsEncoder.scala 22:49] | |
| wire [7:0] _GEN_19 = {{7'd0}, io_din[0]}; // @[TmdsEncoder.scala 22:30] | |
| wire [7:0] _xored_T_16 = _GEN_19 ^ _xored_T_15; // @[TmdsEncoder.scala 22:30] | |
| wire [8:0] xored = {1'h1,_xored_T_16}; // @[TmdsEncoder.scala 25:24] | |
| wire _xnored_res_res_res_res_res_res_T_8 = ~(_xored_res_res_res_res_res_res_T_3[0] ^ | |
| xored_res_res_res_res_res_res_res); // @[TmdsEncoder.scala 32:11] | |
| wire [1:0] xnored_res_res_res_res_res_res = {_xnored_res_res_res_res_res_res_T_8,xored_res_res_res_res_res_res_res}; // @[TmdsEncoder.scala 32:52] | |
| wire _xnored_res_res_res_res_res_T_11 = ~(_xored_res_res_res_res_res_T_4[0] ^ xnored_res_res_res_res_res_res[0]); // @[TmdsEncoder.scala 32:11] | |
| wire [2:0] xnored_res_res_res_res_res = {_xnored_res_res_res_res_res_T_11,_xnored_res_res_res_res_res_res_T_8, | |
| xored_res_res_res_res_res_res_res}; // @[TmdsEncoder.scala 32:52] | |
| wire _xnored_res_res_res_res_T_14 = ~(_xored_res_res_res_res_T_5[0] ^ xnored_res_res_res_res_res[0]); // @[TmdsEncoder.scala 32:11] | |
| wire [3:0] xnored_res_res_res_res = {_xnored_res_res_res_res_T_14,_xnored_res_res_res_res_res_T_11, | |
| _xnored_res_res_res_res_res_res_T_8,xored_res_res_res_res_res_res_res}; // @[TmdsEncoder.scala 32:52] | |
| wire _xnored_res_res_res_T_17 = ~(_xored_res_res_res_T_6[0] ^ xnored_res_res_res_res[0]); // @[TmdsEncoder.scala 32:11] | |
| wire [4:0] xnored_res_res_res = {_xnored_res_res_res_T_17,_xnored_res_res_res_res_T_14, | |
| _xnored_res_res_res_res_res_T_11,_xnored_res_res_res_res_res_res_T_8,xored_res_res_res_res_res_res_res}; // @[TmdsEncoder.scala 32:52] | |
| wire _xnored_res_res_T_20 = ~(_xored_res_res_T_7[0] ^ xnored_res_res_res[0]); // @[TmdsEncoder.scala 32:11] | |
| wire [5:0] xnored_res_res = {_xnored_res_res_T_20,_xnored_res_res_res_T_17,_xnored_res_res_res_res_T_14, | |
| _xnored_res_res_res_res_res_T_11,_xnored_res_res_res_res_res_res_T_8,xored_res_res_res_res_res_res_res}; // @[TmdsEncoder.scala 32:52] | |
| wire _xnored_res_T_23 = ~(_xored_res_T_8[0] ^ xnored_res_res[0]); // @[TmdsEncoder.scala 32:11] | |
| wire [6:0] xnored_res = {_xnored_res_T_23,_xnored_res_res_T_20,_xnored_res_res_res_T_17,_xnored_res_res_res_res_T_14, | |
| _xnored_res_res_res_res_res_T_11,_xnored_res_res_res_res_res_res_T_8,xored_res_res_res_res_res_res_res}; // @[TmdsEncoder.scala 32:52] | |
| wire _xnored_T_16 = ~(io_din[0] ^ xnored_res[0]); // @[TmdsEncoder.scala 32:11] | |
| wire [8:0] xnored = {1'h0,_xnored_T_16,_xnored_res_T_23,_xnored_res_res_T_20,_xnored_res_res_res_T_17, | |
| _xnored_res_res_res_res_T_14,_xnored_res_res_res_res_res_T_11,_xnored_res_res_res_res_res_res_T_8, | |
| xored_res_res_res_res_res_res_res}; // @[TmdsEncoder.scala 35:25] | |
| wire _q_m_T_5 = n_one_din > 4'h4 | n_one_din == 4'h4 & ~io_din[0]; // @[TmdsEncoder.scala 39:23] | |
| wire [8:0] q_m = _q_m_T_5 ? xnored : xored; // @[TmdsEncoder.scala 38:16] | |
| wire [1:0] _diff_T_9 = q_m[0] + q_m[1]; // @[Bitwise.scala 48:55] | |
| wire [1:0] _diff_T_11 = q_m[2] + q_m[3]; // @[Bitwise.scala 48:55] | |
| wire [2:0] _diff_T_13 = _diff_T_9 + _diff_T_11; // @[Bitwise.scala 48:55] | |
| wire [1:0] _diff_T_15 = q_m[4] + q_m[5]; // @[Bitwise.scala 48:55] | |
| wire [1:0] _diff_T_17 = q_m[7] + q_m[8]; // @[Bitwise.scala 48:55] | |
| wire [1:0] _GEN_20 = {{1'd0}, q_m[6]}; // @[Bitwise.scala 48:55] | |
| wire [2:0] _diff_T_19 = _GEN_20 + _diff_T_17; // @[Bitwise.scala 48:55] | |
| wire [2:0] _diff_T_21 = _diff_T_15 + _diff_T_19[1:0]; // @[Bitwise.scala 48:55] | |
| wire [3:0] _diff_T_25 = _diff_T_13 + _diff_T_21; // @[TmdsEncoder.scala 43:28] | |
| wire [3:0] diff = $signed(_diff_T_25) - 4'sh4; // @[TmdsEncoder.scala 43:35] | |
| reg [3:0] disparityReg; // @[TmdsEncoder.scala 47:29] | |
| reg [9:0] doutReg; // @[TmdsEncoder.scala 48:24] | |
| wire [9:0] _GEN_0 = 2'h2 == io_ctrl ? 10'h154 : 10'h2ab; // @[TmdsEncoder.scala 51:13 52:20 55:34] | |
| wire [9:0] _doutReg_T_1 = {2'h2,q_m[7:0]}; // @[TmdsEncoder.scala 61:33] | |
| wire [3:0] _disparityReg_T_2 = $signed(disparityReg) - $signed(diff); // @[TmdsEncoder.scala 62:38] | |
| wire [9:0] _doutReg_T_3 = {2'h1,q_m[7:0]}; // @[TmdsEncoder.scala 64:33] | |
| wire [3:0] _disparityReg_T_5 = $signed(disparityReg) + $signed(diff); // @[TmdsEncoder.scala 65:38] | |
| wire _T_13 = ~diff[3] & ~disparityReg[3]; // @[TmdsEncoder.scala 67:36] | |
| wire [7:0] _doutReg_T_7 = ~q_m[7:0]; // @[TmdsEncoder.scala 69:40] | |
| wire [9:0] _doutReg_T_8 = {1'h1,q_m[8],_doutReg_T_7}; // @[TmdsEncoder.scala 69:37] | |
| wire [3:0] _disparityReg_T_8 = $signed(disparityReg) + 4'sh1; // @[TmdsEncoder.scala 71:38] | |
| wire [3:0] _disparityReg_T_11 = $signed(_disparityReg_T_8) - $signed(diff); // @[TmdsEncoder.scala 71:44] | |
| wire [3:0] _GEN_5 = q_m[8] ? $signed(_disparityReg_T_11) : $signed(_disparityReg_T_2); // @[TmdsEncoder.scala 70:19 71:22 73:22] | |
| wire [9:0] _doutReg_T_9 = {1'h0,q_m}; // @[TmdsEncoder.scala 76:27] | |
| wire [3:0] _disparityReg_T_20 = $signed(disparityReg) - 4'sh1; // @[TmdsEncoder.scala 80:38] | |
| wire [3:0] _disparityReg_T_23 = $signed(_disparityReg_T_20) + $signed(diff); // @[TmdsEncoder.scala 80:44] | |
| wire [3:0] _GEN_6 = q_m[8] ? $signed(_disparityReg_T_5) : $signed(_disparityReg_T_23); // @[TmdsEncoder.scala 77:19 78:22 80:22] | |
| assign io_dout = doutReg; // @[TmdsEncoder.scala 84:11] | |
| always @(posedge clock) begin | |
| if (reset) begin // @[TmdsEncoder.scala 47:29] | |
| disparityReg <= 4'sh0; // @[TmdsEncoder.scala 47:29] | |
| end else if (~io_en) begin // @[TmdsEncoder.scala 49:26] | |
| disparityReg <= 4'sh0; // @[TmdsEncoder.scala 50:18] | |
| end else if ($signed(disparityReg) == 4'sh0 | $signed(diff) == 4'sh0) begin // @[TmdsEncoder.scala 58:47] | |
| if (~q_m[8]) begin // @[TmdsEncoder.scala 60:31] | |
| disparityReg <= _disparityReg_T_2; // @[TmdsEncoder.scala 62:22] | |
| end else begin | |
| disparityReg <= _disparityReg_T_5; // @[TmdsEncoder.scala 65:22] | |
| end | |
| end else if (_T_13 | diff[3] & disparityReg[3]) begin // @[TmdsEncoder.scala 68:72] | |
| disparityReg <= _GEN_5; | |
| end else begin | |
| disparityReg <= _GEN_6; | |
| end | |
| if (reset) begin // @[TmdsEncoder.scala 48:24] | |
| doutReg <= 10'h2ab; // @[TmdsEncoder.scala 48:24] | |
| end else if (~io_en) begin // @[TmdsEncoder.scala 49:26] | |
| if (2'h0 == io_ctrl) begin // @[TmdsEncoder.scala 52:20] | |
| doutReg <= 10'h354; // @[TmdsEncoder.scala 53:34] | |
| end else if (2'h1 == io_ctrl) begin // @[TmdsEncoder.scala 52:20] | |
| doutReg <= 10'hab; // @[TmdsEncoder.scala 54:34] | |
| end else begin | |
| doutReg <= _GEN_0; | |
| end | |
| end else if ($signed(disparityReg) == 4'sh0 | $signed(diff) == 4'sh0) begin // @[TmdsEncoder.scala 58:47] | |
| if (~q_m[8]) begin // @[TmdsEncoder.scala 60:31] | |
| doutReg <= _doutReg_T_1; // @[TmdsEncoder.scala 61:17] | |
| end else begin | |
| doutReg <= _doutReg_T_3; // @[TmdsEncoder.scala 64:17] | |
| end | |
| end else if (_T_13 | diff[3] & disparityReg[3]) begin // @[TmdsEncoder.scala 68:72] | |
| doutReg <= _doutReg_T_8; // @[TmdsEncoder.scala 69:15] | |
| end else begin | |
| doutReg <= _doutReg_T_9; // @[TmdsEncoder.scala 76:15] | |
| end | |
| end | |
| // Register and memory initialization | |
| `ifdef RANDOMIZE_GARBAGE_ASSIGN | |
| `define RANDOMIZE | |
| `endif | |
| `ifdef RANDOMIZE_INVALID_ASSIGN | |
| `define RANDOMIZE | |
| `endif | |
| `ifdef RANDOMIZE_REG_INIT | |
| `define RANDOMIZE | |
| `endif | |
| `ifdef RANDOMIZE_MEM_INIT | |
| `define RANDOMIZE | |
| `endif | |
| `ifndef RANDOM | |
| `define RANDOM $random | |
| `endif | |
| `ifdef RANDOMIZE_MEM_INIT | |
| integer initvar; | |
| `endif | |
| `ifndef SYNTHESIS | |
| `ifdef FIRRTL_BEFORE_INITIAL | |
| `FIRRTL_BEFORE_INITIAL | |
| `endif | |
| initial begin | |
| `ifdef RANDOMIZE | |
| `ifdef INIT_RANDOM | |
| `INIT_RANDOM | |
| `endif | |
| `ifndef VERILATOR | |
| `ifdef RANDOMIZE_DELAY | |
| #`RANDOMIZE_DELAY begin end | |
| `else | |
| #0.002 begin end | |
| `endif | |
| `endif | |
| `ifdef RANDOMIZE_REG_INIT | |
| _RAND_0 = {1{`RANDOM}}; | |
| disparityReg = _RAND_0[3:0]; | |
| _RAND_1 = {1{`RANDOM}}; | |
| doutReg = _RAND_1[9:0]; | |
| `endif // RANDOMIZE_REG_INIT | |
| `endif // RANDOMIZE | |
| end // initial | |
| `ifdef FIRRTL_AFTER_INITIAL | |
| `FIRRTL_AFTER_INITIAL | |
| `endif | |
| `endif // SYNTHESIS | |
| endmodule | |
| module Rgb2Tmds( | |
| input clock, | |
| input reset, | |
| input [7:0] io_videoSig_pixel_red, | |
| input [7:0] io_videoSig_pixel_green, | |
| input [7:0] io_videoSig_pixel_blue, | |
| input io_videoSig_de, | |
| input io_videoSig_hsync, | |
| input io_videoSig_vsync, | |
| output [9:0] io_tmds_blue, | |
| output [9:0] io_tmds_red, | |
| output [9:0] io_tmds_green | |
| ); | |
| wire tbM_clock; // @[Rgb2Tmds.scala 16:19] | |
| wire tbM_reset; // @[Rgb2Tmds.scala 16:19] | |
| wire tbM_io_en; // @[Rgb2Tmds.scala 16:19] | |
| wire [1:0] tbM_io_ctrl; // @[Rgb2Tmds.scala 16:19] | |
| wire [7:0] tbM_io_din; // @[Rgb2Tmds.scala 16:19] | |
| wire [9:0] tbM_io_dout; // @[Rgb2Tmds.scala 16:19] | |
| wire trM_clock; // @[Rgb2Tmds.scala 23:19] | |
| wire trM_reset; // @[Rgb2Tmds.scala 23:19] | |
| wire trM_io_en; // @[Rgb2Tmds.scala 23:19] | |
| wire [1:0] trM_io_ctrl; // @[Rgb2Tmds.scala 23:19] | |
| wire [7:0] trM_io_din; // @[Rgb2Tmds.scala 23:19] | |
| wire [9:0] trM_io_dout; // @[Rgb2Tmds.scala 23:19] | |
| wire tgM_clock; // @[Rgb2Tmds.scala 30:19] | |
| wire tgM_reset; // @[Rgb2Tmds.scala 30:19] | |
| wire tgM_io_en; // @[Rgb2Tmds.scala 30:19] | |
| wire [1:0] tgM_io_ctrl; // @[Rgb2Tmds.scala 30:19] | |
| wire [7:0] tgM_io_din; // @[Rgb2Tmds.scala 30:19] | |
| wire [9:0] tgM_io_dout; // @[Rgb2Tmds.scala 30:19] | |
| TMDSEncoder tbM ( // @[Rgb2Tmds.scala 16:19] | |
| .clock(tbM_clock), | |
| .reset(tbM_reset), | |
| .io_en(tbM_io_en), | |
| .io_ctrl(tbM_io_ctrl), | |
| .io_din(tbM_io_din), | |
| .io_dout(tbM_io_dout) | |
| ); | |
| TMDSEncoder trM ( // @[Rgb2Tmds.scala 23:19] | |
| .clock(trM_clock), | |
| .reset(trM_reset), | |
| .io_en(trM_io_en), | |
| .io_ctrl(trM_io_ctrl), | |
| .io_din(trM_io_din), | |
| .io_dout(trM_io_dout) | |
| ); | |
| TMDSEncoder tgM ( // @[Rgb2Tmds.scala 30:19] | |
| .clock(tgM_clock), | |
| .reset(tgM_reset), | |
| .io_en(tgM_io_en), | |
| .io_ctrl(tgM_io_ctrl), | |
| .io_din(tgM_io_din), | |
| .io_dout(tgM_io_dout) | |
| ); | |
| assign io_tmds_blue = tbM_io_dout; // @[Rgb2Tmds.scala 20:16] | |
| assign io_tmds_red = trM_io_dout; // @[Rgb2Tmds.scala 27:15] | |
| assign io_tmds_green = tgM_io_dout; // @[Rgb2Tmds.scala 34:17] | |
| assign tbM_clock = clock; | |
| assign tbM_reset = reset; | |
| assign tbM_io_en = io_videoSig_de; // @[Rgb2Tmds.scala 17:13] | |
| assign tbM_io_ctrl = {io_videoSig_vsync,io_videoSig_hsync}; // @[Rgb2Tmds.scala 18:36] | |
| assign tbM_io_din = io_videoSig_pixel_blue; // @[Rgb2Tmds.scala 19:14] | |
| assign trM_clock = clock; | |
| assign trM_reset = reset; | |
| assign trM_io_en = io_videoSig_de; // @[Rgb2Tmds.scala 24:13] | |
| assign trM_io_ctrl = 2'h0; // @[Rgb2Tmds.scala 25:15] | |
| assign trM_io_din = io_videoSig_pixel_red; // @[Rgb2Tmds.scala 26:14] | |
| assign tgM_clock = clock; | |
| assign tgM_reset = reset; | |
| assign tgM_io_en = io_videoSig_de; // @[Rgb2Tmds.scala 31:13] | |
| assign tgM_io_ctrl = 2'h0; // @[Rgb2Tmds.scala 32:15] | |
| assign tgM_io_din = io_videoSig_pixel_green; // @[Rgb2Tmds.scala 33:14] | |
| endmodule | |
| module Oser10Module( | |
| input clock, | |
| input reset, | |
| output io_q, | |
| input [9:0] io_data, | |
| input io_fclk | |
| ); | |
| wire osr10_Q; // @[littlebee.scala 57:21] | |
| wire osr10_D0; // @[littlebee.scala 57:21] | |
| wire osr10_D1; // @[littlebee.scala 57:21] | |
| wire osr10_D2; // @[littlebee.scala 57:21] | |
| wire osr10_D3; // @[littlebee.scala 57:21] | |
| wire osr10_D4; // @[littlebee.scala 57:21] | |
| wire osr10_D5; // @[littlebee.scala 57:21] | |
| wire osr10_D6; // @[littlebee.scala 57:21] | |
| wire osr10_D7; // @[littlebee.scala 57:21] | |
| wire osr10_D8; // @[littlebee.scala 57:21] | |
| wire osr10_D9; // @[littlebee.scala 57:21] | |
| wire osr10_PCLK; // @[littlebee.scala 57:21] | |
| wire osr10_FCLK; // @[littlebee.scala 57:21] | |
| wire osr10_RESET; // @[littlebee.scala 57:21] | |
| OSER10 #(.GSREN("false"), .LSREN("true")) osr10 ( // @[littlebee.scala 57:21] | |
| .Q(osr10_Q), | |
| .D0(osr10_D0), | |
| .D1(osr10_D1), | |
| .D2(osr10_D2), | |
| .D3(osr10_D3), | |
| .D4(osr10_D4), | |
| .D5(osr10_D5), | |
| .D6(osr10_D6), | |
| .D7(osr10_D7), | |
| .D8(osr10_D8), | |
| .D9(osr10_D9), | |
| .PCLK(osr10_PCLK), | |
| .FCLK(osr10_FCLK), | |
| .RESET(osr10_RESET) | |
| ); | |
| assign io_q = osr10_Q; // @[littlebee.scala 58:8] | |
| assign osr10_D0 = io_data[0]; // @[littlebee.scala 59:25] | |
| assign osr10_D1 = io_data[1]; // @[littlebee.scala 60:25] | |
| assign osr10_D2 = io_data[2]; // @[littlebee.scala 61:25] | |
| assign osr10_D3 = io_data[3]; // @[littlebee.scala 62:25] | |
| assign osr10_D4 = io_data[4]; // @[littlebee.scala 63:25] | |
| assign osr10_D5 = io_data[5]; // @[littlebee.scala 64:25] | |
| assign osr10_D6 = io_data[6]; // @[littlebee.scala 65:25] | |
| assign osr10_D7 = io_data[7]; // @[littlebee.scala 66:25] | |
| assign osr10_D8 = io_data[8]; // @[littlebee.scala 67:25] | |
| assign osr10_D9 = io_data[9]; // @[littlebee.scala 68:25] | |
| assign osr10_PCLK = clock; // @[littlebee.scala 69:17] | |
| assign osr10_FCLK = io_fclk; // @[littlebee.scala 70:17] | |
| assign osr10_RESET = reset; // @[littlebee.scala 71:17] | |
| endmodule | |
| module GbHdmi( | |
| input clock, | |
| input reset, | |
| input io_gb_vsync, | |
| input io_gb_clk, | |
| input [1:0] io_gb_data, | |
| input io_serClk, | |
| output io_tmds_clk_p, | |
| output io_tmds_clk_n, | |
| output io_tmds_data_0_p, | |
| output io_tmds_data_0_n, | |
| output io_tmds_data_1_p, | |
| output io_tmds_data_1_n, | |
| output io_tmds_data_2_p, | |
| output io_tmds_data_2_n, | |
| input io_pattern_trig | |
| ); | |
| `ifdef RANDOMIZE_GARBAGE_ASSIGN | |
| reg [31:0] _RAND_1; | |
| `endif // RANDOMIZE_GARBAGE_ASSIGN | |
| `ifdef RANDOMIZE_MEM_INIT | |
| reg [31:0] _RAND_0; | |
| `endif // RANDOMIZE_MEM_INIT | |
| `ifdef RANDOMIZE_REG_INIT | |
| reg [31:0] _RAND_2; | |
| reg [31:0] _RAND_3; | |
| reg [31:0] _RAND_4; | |
| `endif // RANDOMIZE_REG_INIT | |
| wire gbwt_clock; // @[gbhdmi.scala 45:20] | |
| wire gbwt_reset; // @[gbhdmi.scala 45:20] | |
| wire gbwt_io_gb_vsync; // @[gbhdmi.scala 45:20] | |
| wire gbwt_io_gb_clk; // @[gbhdmi.scala 45:20] | |
| wire [1:0] gbwt_io_gb_data; // @[gbhdmi.scala 45:20] | |
| wire [14:0] gbwt_io_Maddr; // @[gbhdmi.scala 45:20] | |
| wire [1:0] gbwt_io_Mdata; // @[gbhdmi.scala 45:20] | |
| wire gbwt_io_Mwrite; // @[gbhdmi.scala 45:20] | |
| wire mhdmi_clock; // @[gbhdmi.scala 49:21] | |
| wire mhdmi_reset; // @[gbhdmi.scala 49:21] | |
| wire [14:0] mhdmi_io_mem_addr; // @[gbhdmi.scala 49:21] | |
| wire [1:0] mhdmi_io_mem_data; // @[gbhdmi.scala 49:21] | |
| wire mhdmi_io_video_hsync; // @[gbhdmi.scala 49:21] | |
| wire mhdmi_io_video_vsync; // @[gbhdmi.scala 49:21] | |
| wire [7:0] mhdmi_io_video_color_red; // @[gbhdmi.scala 49:21] | |
| wire [7:0] mhdmi_io_video_color_green; // @[gbhdmi.scala 49:21] | |
| wire [7:0] mhdmi_io_video_color_blue; // @[gbhdmi.scala 49:21] | |
| wire mhdmi_io_video_de; // @[gbhdmi.scala 49:21] | |
| wire [1:0] mhdmi_io_pattern_num; // @[gbhdmi.scala 49:21] | |
| wire rgb2tmds_clock; // @[gbhdmi.scala 82:26] | |
| wire rgb2tmds_reset; // @[gbhdmi.scala 82:26] | |
| wire [7:0] rgb2tmds_io_videoSig_pixel_red; // @[gbhdmi.scala 82:26] | |
| wire [7:0] rgb2tmds_io_videoSig_pixel_green; // @[gbhdmi.scala 82:26] | |
| wire [7:0] rgb2tmds_io_videoSig_pixel_blue; // @[gbhdmi.scala 82:26] | |
| wire rgb2tmds_io_videoSig_de; // @[gbhdmi.scala 82:26] | |
| wire rgb2tmds_io_videoSig_hsync; // @[gbhdmi.scala 82:26] | |
| wire rgb2tmds_io_videoSig_vsync; // @[gbhdmi.scala 82:26] | |
| wire [9:0] rgb2tmds_io_tmds_blue; // @[gbhdmi.scala 82:26] | |
| wire [9:0] rgb2tmds_io_tmds_red; // @[gbhdmi.scala 82:26] | |
| wire [9:0] rgb2tmds_io_tmds_green; // @[gbhdmi.scala 82:26] | |
| wire serdesRed_clock; // @[gbhdmi.scala 92:27] | |
| wire serdesRed_reset; // @[gbhdmi.scala 92:27] | |
| wire serdesRed_io_q; // @[gbhdmi.scala 92:27] | |
| wire [9:0] serdesRed_io_data; // @[gbhdmi.scala 92:27] | |
| wire serdesRed_io_fclk; // @[gbhdmi.scala 92:27] | |
| wire buffDiffRed_O; // @[gbhdmi.scala 95:29] | |
| wire buffDiffRed_OB; // @[gbhdmi.scala 95:29] | |
| wire buffDiffRed_I; // @[gbhdmi.scala 95:29] | |
| wire serdesGreen_clock; // @[gbhdmi.scala 101:29] | |
| wire serdesGreen_reset; // @[gbhdmi.scala 101:29] | |
| wire serdesGreen_io_q; // @[gbhdmi.scala 101:29] | |
| wire [9:0] serdesGreen_io_data; // @[gbhdmi.scala 101:29] | |
| wire serdesGreen_io_fclk; // @[gbhdmi.scala 101:29] | |
| wire buffDiffGreen_O; // @[gbhdmi.scala 104:31] | |
| wire buffDiffGreen_OB; // @[gbhdmi.scala 104:31] | |
| wire buffDiffGreen_I; // @[gbhdmi.scala 104:31] | |
| wire serdesBlue_clock; // @[gbhdmi.scala 110:28] | |
| wire serdesBlue_reset; // @[gbhdmi.scala 110:28] | |
| wire serdesBlue_io_q; // @[gbhdmi.scala 110:28] | |
| wire [9:0] serdesBlue_io_data; // @[gbhdmi.scala 110:28] | |
| wire serdesBlue_io_fclk; // @[gbhdmi.scala 110:28] | |
| wire buffDiffBlue_O; // @[gbhdmi.scala 113:30] | |
| wire buffDiffBlue_OB; // @[gbhdmi.scala 113:30] | |
| wire buffDiffBlue_I; // @[gbhdmi.scala 113:30] | |
| wire serdesClk_clock; // @[gbhdmi.scala 119:27] | |
| wire serdesClk_reset; // @[gbhdmi.scala 119:27] | |
| wire serdesClk_io_q; // @[gbhdmi.scala 119:27] | |
| wire [9:0] serdesClk_io_data; // @[gbhdmi.scala 119:27] | |
| wire serdesClk_io_fclk; // @[gbhdmi.scala 119:27] | |
| wire buffDiffClk_O; // @[gbhdmi.scala 122:29] | |
| wire buffDiffClk_OB; // @[gbhdmi.scala 122:29] | |
| wire buffDiffClk_I; // @[gbhdmi.scala 122:29] | |
| reg [1:0] mem [0:23039]; // @[gbhdmi.scala 129:16] | |
| wire mem_mhdmi_io_mem_data_MPORT_en; // @[gbhdmi.scala 129:16] | |
| wire [14:0] mem_mhdmi_io_mem_data_MPORT_addr; // @[gbhdmi.scala 129:16] | |
| wire [1:0] mem_mhdmi_io_mem_data_MPORT_data; // @[gbhdmi.scala 129:16] | |
| wire [1:0] mem_MPORT_data; // @[gbhdmi.scala 129:16] | |
| wire [14:0] mem_MPORT_addr; // @[gbhdmi.scala 129:16] | |
| wire mem_MPORT_mask; // @[gbhdmi.scala 129:16] | |
| wire mem_MPORT_en; // @[gbhdmi.scala 129:16] | |
| reg [1:0] patternNum; // @[gbhdmi.scala 52:27] | |
| reg REG; // @[gbhdmi.scala 53:16] | |
| wire [1:0] _patternNum_T_1 = patternNum + 2'h1; // @[gbhdmi.scala 54:30] | |
| reg [1:0] mhdmi_io_mem_data_REG; // @[gbhdmi.scala 135:33] | |
| GbWrite gbwt ( // @[gbhdmi.scala 45:20] | |
| .clock(gbwt_clock), | |
| .reset(gbwt_reset), | |
| .io_gb_vsync(gbwt_io_gb_vsync), | |
| .io_gb_clk(gbwt_io_gb_clk), | |
| .io_gb_data(gbwt_io_gb_data), | |
| .io_Maddr(gbwt_io_Maddr), | |
| .io_Mdata(gbwt_io_Mdata), | |
| .io_Mwrite(gbwt_io_Mwrite) | |
| ); | |
| MemHdmi mhdmi ( // @[gbhdmi.scala 49:21] | |
| .clock(mhdmi_clock), | |
| .reset(mhdmi_reset), | |
| .io_mem_addr(mhdmi_io_mem_addr), | |
| .io_mem_data(mhdmi_io_mem_data), | |
| .io_video_hsync(mhdmi_io_video_hsync), | |
| .io_video_vsync(mhdmi_io_video_vsync), | |
| .io_video_color_red(mhdmi_io_video_color_red), | |
| .io_video_color_green(mhdmi_io_video_color_green), | |
| .io_video_color_blue(mhdmi_io_video_color_blue), | |
| .io_video_de(mhdmi_io_video_de), | |
| .io_pattern_num(mhdmi_io_pattern_num) | |
| ); | |
| Rgb2Tmds rgb2tmds ( // @[gbhdmi.scala 82:26] | |
| .clock(rgb2tmds_clock), | |
| .reset(rgb2tmds_reset), | |
| .io_videoSig_pixel_red(rgb2tmds_io_videoSig_pixel_red), | |
| .io_videoSig_pixel_green(rgb2tmds_io_videoSig_pixel_green), | |
| .io_videoSig_pixel_blue(rgb2tmds_io_videoSig_pixel_blue), | |
| .io_videoSig_de(rgb2tmds_io_videoSig_de), | |
| .io_videoSig_hsync(rgb2tmds_io_videoSig_hsync), | |
| .io_videoSig_vsync(rgb2tmds_io_videoSig_vsync), | |
| .io_tmds_blue(rgb2tmds_io_tmds_blue), | |
| .io_tmds_red(rgb2tmds_io_tmds_red), | |
| .io_tmds_green(rgb2tmds_io_tmds_green) | |
| ); | |
| Oser10Module serdesRed ( // @[gbhdmi.scala 92:27] | |
| .clock(serdesRed_clock), | |
| .reset(serdesRed_reset), | |
| .io_q(serdesRed_io_q), | |
| .io_data(serdesRed_io_data), | |
| .io_fclk(serdesRed_io_fclk) | |
| ); | |
| TLVDS_OBUF buffDiffRed ( // @[gbhdmi.scala 95:29] | |
| .O(buffDiffRed_O), | |
| .OB(buffDiffRed_OB), | |
| .I(buffDiffRed_I) | |
| ); | |
| Oser10Module serdesGreen ( // @[gbhdmi.scala 101:29] | |
| .clock(serdesGreen_clock), | |
| .reset(serdesGreen_reset), | |
| .io_q(serdesGreen_io_q), | |
| .io_data(serdesGreen_io_data), | |
| .io_fclk(serdesGreen_io_fclk) | |
| ); | |
| TLVDS_OBUF buffDiffGreen ( // @[gbhdmi.scala 104:31] | |
| .O(buffDiffGreen_O), | |
| .OB(buffDiffGreen_OB), | |
| .I(buffDiffGreen_I) | |
| ); | |
| Oser10Module serdesBlue ( // @[gbhdmi.scala 110:28] | |
| .clock(serdesBlue_clock), | |
| .reset(serdesBlue_reset), | |
| .io_q(serdesBlue_io_q), | |
| .io_data(serdesBlue_io_data), | |
| .io_fclk(serdesBlue_io_fclk) | |
| ); | |
| TLVDS_OBUF buffDiffBlue ( // @[gbhdmi.scala 113:30] | |
| .O(buffDiffBlue_O), | |
| .OB(buffDiffBlue_OB), | |
| .I(buffDiffBlue_I) | |
| ); | |
| Oser10Module serdesClk ( // @[gbhdmi.scala 119:27] | |
| .clock(serdesClk_clock), | |
| .reset(serdesClk_reset), | |
| .io_q(serdesClk_io_q), | |
| .io_data(serdesClk_io_data), | |
| .io_fclk(serdesClk_io_fclk) | |
| ); | |
| TLVDS_OBUF buffDiffClk ( // @[gbhdmi.scala 122:29] | |
| .O(buffDiffClk_O), | |
| .OB(buffDiffClk_OB), | |
| .I(buffDiffClk_I) | |
| ); | |
| assign mem_mhdmi_io_mem_data_MPORT_en = 1'h1; | |
| assign mem_mhdmi_io_mem_data_MPORT_addr = mhdmi_io_mem_addr; | |
| `ifndef RANDOMIZE_GARBAGE_ASSIGN | |
| assign mem_mhdmi_io_mem_data_MPORT_data = mem[mem_mhdmi_io_mem_data_MPORT_addr]; // @[gbhdmi.scala 129:16] | |
| `else | |
| assign mem_mhdmi_io_mem_data_MPORT_data = mem_mhdmi_io_mem_data_MPORT_addr >= 15'h5a00 ? _RAND_1[1:0] : | |
| mem[mem_mhdmi_io_mem_data_MPORT_addr]; // @[gbhdmi.scala 129:16] | |
| `endif // RANDOMIZE_GARBAGE_ASSIGN | |
| assign mem_MPORT_data = gbwt_io_Mdata; | |
| assign mem_MPORT_addr = gbwt_io_Maddr; | |
| assign mem_MPORT_mask = 1'h1; | |
| assign mem_MPORT_en = gbwt_io_Mwrite; | |
| assign io_tmds_clk_p = buffDiffClk_O; // @[gbhdmi.scala 124:19] | |
| assign io_tmds_clk_n = buffDiffClk_OB; // @[gbhdmi.scala 125:19] | |
| assign io_tmds_data_0_p = buffDiffBlue_O; // @[gbhdmi.scala 115:23] | |
| assign io_tmds_data_0_n = buffDiffBlue_OB; // @[gbhdmi.scala 116:23] | |
| assign io_tmds_data_1_p = buffDiffGreen_O; // @[gbhdmi.scala 106:23] | |
| assign io_tmds_data_1_n = buffDiffGreen_OB; // @[gbhdmi.scala 107:23] | |
| assign io_tmds_data_2_p = buffDiffRed_O; // @[gbhdmi.scala 97:23] | |
| assign io_tmds_data_2_n = buffDiffRed_OB; // @[gbhdmi.scala 98:23] | |
| assign gbwt_clock = clock; | |
| assign gbwt_reset = reset; | |
| assign gbwt_io_gb_vsync = io_gb_vsync; // @[gbhdmi.scala 46:14] | |
| assign gbwt_io_gb_clk = io_gb_clk; // @[gbhdmi.scala 46:14] | |
| assign gbwt_io_gb_data = io_gb_data; // @[gbhdmi.scala 46:14] | |
| assign mhdmi_clock = clock; | |
| assign mhdmi_reset = reset; | |
| assign mhdmi_io_mem_data = mhdmi_io_mem_data_REG; // @[gbhdmi.scala 134:27 135:23 138:23] | |
| assign mhdmi_io_pattern_num = patternNum; // @[gbhdmi.scala 56:24] | |
| assign rgb2tmds_clock = clock; | |
| assign rgb2tmds_reset = reset; | |
| assign rgb2tmds_io_videoSig_pixel_red = mhdmi_io_video_color_red; // @[gbhdmi.scala 86:38] | |
| assign rgb2tmds_io_videoSig_pixel_green = mhdmi_io_video_color_green; // @[gbhdmi.scala 87:38] | |
| assign rgb2tmds_io_videoSig_pixel_blue = mhdmi_io_video_color_blue; // @[gbhdmi.scala 88:38] | |
| assign rgb2tmds_io_videoSig_de = mhdmi_io_video_de; // @[gbhdmi.scala 83:29] | |
| assign rgb2tmds_io_videoSig_hsync = mhdmi_io_video_hsync; // @[gbhdmi.scala 84:32] | |
| assign rgb2tmds_io_videoSig_vsync = mhdmi_io_video_vsync; // @[gbhdmi.scala 85:32] | |
| assign serdesRed_clock = clock; | |
| assign serdesRed_reset = reset; | |
| assign serdesRed_io_data = rgb2tmds_io_tmds_red; // @[gbhdmi.scala 93:23] | |
| assign serdesRed_io_fclk = io_serClk; // @[gbhdmi.scala 94:23] | |
| assign buffDiffRed_I = serdesRed_io_q; // @[gbhdmi.scala 96:22] | |
| assign serdesGreen_clock = clock; | |
| assign serdesGreen_reset = reset; | |
| assign serdesGreen_io_data = rgb2tmds_io_tmds_green; // @[gbhdmi.scala 102:25] | |
| assign serdesGreen_io_fclk = io_serClk; // @[gbhdmi.scala 103:25] | |
| assign buffDiffGreen_I = serdesGreen_io_q; // @[gbhdmi.scala 105:24] | |
| assign serdesBlue_clock = clock; | |
| assign serdesBlue_reset = reset; | |
| assign serdesBlue_io_data = rgb2tmds_io_tmds_blue; // @[gbhdmi.scala 111:24] | |
| assign serdesBlue_io_fclk = io_serClk; // @[gbhdmi.scala 112:24] | |
| assign buffDiffBlue_I = serdesBlue_io_q; // @[gbhdmi.scala 114:23] | |
| assign serdesClk_clock = clock; | |
| assign serdesClk_reset = reset; | |
| assign serdesClk_io_data = 10'h3e0; // @[gbhdmi.scala 120:23] | |
| assign serdesClk_io_fclk = io_serClk; // @[gbhdmi.scala 121:23] | |
| assign buffDiffClk_I = serdesClk_io_q; // @[gbhdmi.scala 123:22] | |
| always @(posedge clock) begin | |
| if (mem_MPORT_en & mem_MPORT_mask) begin | |
| mem[mem_MPORT_addr] <= mem_MPORT_data; // @[gbhdmi.scala 129:16] | |
| end | |
| if (reset) begin // @[gbhdmi.scala 52:27] | |
| patternNum <= 2'h0; // @[gbhdmi.scala 52:27] | |
| end else if (~REG & io_pattern_trig) begin // @[gbhdmi.scala 53:52] | |
| patternNum <= _patternNum_T_1; // @[gbhdmi.scala 54:16] | |
| end | |
| REG <= io_pattern_trig; // @[gbhdmi.scala 53:16] | |
| mhdmi_io_mem_data_REG <= mem_mhdmi_io_mem_data_MPORT_data; // @[gbhdmi.scala 135:33] | |
| end | |
| // Register and memory initialization | |
| `ifdef RANDOMIZE_GARBAGE_ASSIGN | |
| `define RANDOMIZE | |
| `endif | |
| `ifdef RANDOMIZE_INVALID_ASSIGN | |
| `define RANDOMIZE | |
| `endif | |
| `ifdef RANDOMIZE_REG_INIT | |
| `define RANDOMIZE | |
| `endif | |
| `ifdef RANDOMIZE_MEM_INIT | |
| `define RANDOMIZE | |
| `endif | |
| `ifndef RANDOM | |
| `define RANDOM $random | |
| `endif | |
| `ifdef RANDOMIZE_MEM_INIT | |
| integer initvar; | |
| `endif | |
| `ifndef SYNTHESIS | |
| `ifdef FIRRTL_BEFORE_INITIAL | |
| `FIRRTL_BEFORE_INITIAL | |
| `endif | |
| initial begin | |
| `ifdef RANDOMIZE | |
| `ifdef INIT_RANDOM | |
| `INIT_RANDOM | |
| `endif | |
| `ifndef VERILATOR | |
| `ifdef RANDOMIZE_DELAY | |
| #`RANDOMIZE_DELAY begin end | |
| `else | |
| #0.002 begin end | |
| `endif | |
| `endif | |
| `ifdef RANDOMIZE_GARBAGE_ASSIGN | |
| _RAND_1 = {1{`RANDOM}}; | |
| `endif // RANDOMIZE_GARBAGE_ASSIGN | |
| `ifdef RANDOMIZE_MEM_INIT | |
| _RAND_0 = {1{`RANDOM}}; | |
| for (initvar = 0; initvar < 23040; initvar = initvar+1) | |
| mem[initvar] = _RAND_0[1:0]; | |
| `endif // RANDOMIZE_MEM_INIT | |
| `ifdef RANDOMIZE_REG_INIT | |
| _RAND_2 = {1{`RANDOM}}; | |
| patternNum = _RAND_2[1:0]; | |
| _RAND_3 = {1{`RANDOM}}; | |
| REG = _RAND_3[0:0]; | |
| _RAND_4 = {1{`RANDOM}}; | |
| mhdmi_io_mem_data_REG = _RAND_4[1:0]; | |
| `endif // RANDOMIZE_REG_INIT | |
| `endif // RANDOMIZE | |
| end // initial | |
| `ifdef FIRRTL_AFTER_INITIAL | |
| `FIRRTL_AFTER_INITIAL | |
| `endif | |
| `endif // SYNTHESIS | |
| endmodule | |
| module TopGbHdmi( | |
| input I_clk, | |
| input I_reset_n, | |
| output [1:0] O_led, | |
| input gb_hsync, | |
| input gb_vsync, | |
| input gb_clk, | |
| input [1:0] gb_data, | |
| output O_tmds_clk_p, | |
| output O_tmds_clk_n, | |
| output O_tmds_data_0_p, | |
| output O_tmds_data_0_n, | |
| output O_tmds_data_1_p, | |
| output O_tmds_data_1_n, | |
| output O_tmds_data_2_p, | |
| output O_tmds_data_2_n, | |
| output snes_dclock, | |
| output snes_dlatch, | |
| input snes_sdata, | |
| output gbpad_a, | |
| output gbpad_b, | |
| output gbpad_select, | |
| output gbpad_start, | |
| output gbpad_right, | |
| output gbpad_left, | |
| output gbpad_up, | |
| output gbpad_down | |
| ); | |
| `ifdef RANDOMIZE_REG_INIT | |
| reg [31:0] _RAND_0; | |
| reg [31:0] _RAND_1; | |
| reg [31:0] _RAND_2; | |
| reg [31:0] _RAND_3; | |
| reg [31:0] _RAND_4; | |
| reg [31:0] _RAND_5; | |
| reg [31:0] _RAND_6; | |
| `endif // RANDOMIZE_REG_INIT | |
| wire clkDiv_RESETN; // @[topgbhdmi.scala 58:24] | |
| wire clkDiv_HCLKIN; // @[topgbhdmi.scala 58:24] | |
| wire clkDiv_CLKOUT; // @[topgbhdmi.scala 58:24] | |
| wire clkDiv_CALIB; // @[topgbhdmi.scala 58:24] | |
| wire tmdsPllvr_clkin; // @[topgbhdmi.scala 65:27] | |
| wire tmdsPllvr_clkout; // @[topgbhdmi.scala 65:27] | |
| wire tmdsPllvr_clkoutd; // @[topgbhdmi.scala 65:27] | |
| wire tmdsPllvr_lock; // @[topgbhdmi.scala 65:27] | |
| wire cnpd_clock; // @[topgbhdmi.scala 73:24] | |
| wire cnpd_reset; // @[topgbhdmi.scala 73:24] | |
| wire cnpd_io_dclock; // @[topgbhdmi.scala 73:24] | |
| wire cnpd_io_dlatch; // @[topgbhdmi.scala 73:24] | |
| wire cnpd_io_sdata; // @[topgbhdmi.scala 73:24] | |
| wire cnpd_io_data_valid; // @[topgbhdmi.scala 73:24] | |
| wire [15:0] cnpd_io_data_bits; // @[topgbhdmi.scala 73:24] | |
| wire gbHdmi_clock; // @[topgbhdmi.scala 105:26] | |
| wire gbHdmi_reset; // @[topgbhdmi.scala 105:26] | |
| wire gbHdmi_io_gb_vsync; // @[topgbhdmi.scala 105:26] | |
| wire gbHdmi_io_gb_clk; // @[topgbhdmi.scala 105:26] | |
| wire [1:0] gbHdmi_io_gb_data; // @[topgbhdmi.scala 105:26] | |
| wire gbHdmi_io_serClk; // @[topgbhdmi.scala 105:26] | |
| wire gbHdmi_io_tmds_clk_p; // @[topgbhdmi.scala 105:26] | |
| wire gbHdmi_io_tmds_clk_n; // @[topgbhdmi.scala 105:26] | |
| wire gbHdmi_io_tmds_data_0_p; // @[topgbhdmi.scala 105:26] | |
| wire gbHdmi_io_tmds_data_0_n; // @[topgbhdmi.scala 105:26] | |
| wire gbHdmi_io_tmds_data_1_p; // @[topgbhdmi.scala 105:26] | |
| wire gbHdmi_io_tmds_data_1_n; // @[topgbhdmi.scala 105:26] | |
| wire gbHdmi_io_tmds_data_2_p; // @[topgbhdmi.scala 105:26] | |
| wire gbHdmi_io_tmds_data_2_n; // @[topgbhdmi.scala 105:26] | |
| wire gbHdmi_io_pattern_trig; // @[topgbhdmi.scala 105:26] | |
| wire pll_lock = tmdsPllvr_lock; // @[topgbhdmi.scala 51:25 68:14] | |
| wire glb_rst = ~(pll_lock & I_reset_n); // @[topgbhdmi.scala 55:19] | |
| wire pix_clk = clkDiv_CLKOUT; // @[topgbhdmi.scala 53:23 61:13] | |
| reg [15:0] sNesPadReg; // @[topgbhdmi.scala 74:31] | |
| wire [15:0] _sNesPadReg_T = ~cnpd_io_data_bits; // @[topgbhdmi.scala 82:23] | |
| reg svsync_r; // @[Reg.scala 16:16] | |
| reg svsync; // @[Reg.scala 16:16] | |
| reg sclk_r; // @[Reg.scala 16:16] | |
| reg sclk; // @[Reg.scala 16:16] | |
| reg [1:0] sdata_r; // @[Reg.scala 16:16] | |
| reg [1:0] sdata; // @[Reg.scala 16:16] | |
| CLKDIV #(.DIV_MODE("5")) clkDiv ( // @[topgbhdmi.scala 58:24] | |
| .RESETN(clkDiv_RESETN), | |
| .HCLKIN(clkDiv_HCLKIN), | |
| .CLKOUT(clkDiv_CLKOUT), | |
| .CALIB(clkDiv_CALIB) | |
| ); | |
| TMDS_PLLVR tmdsPllvr ( // @[topgbhdmi.scala 65:27] | |
| .clkin(tmdsPllvr_clkin), | |
| .clkout(tmdsPllvr_clkout), | |
| .clkoutd(tmdsPllvr_clkoutd), | |
| .lock(tmdsPllvr_lock) | |
| ); | |
| ChisNesPad cnpd ( // @[topgbhdmi.scala 73:24] | |
| .clock(cnpd_clock), | |
| .reset(cnpd_reset), | |
| .io_dclock(cnpd_io_dclock), | |
| .io_dlatch(cnpd_io_dlatch), | |
| .io_sdata(cnpd_io_sdata), | |
| .io_data_valid(cnpd_io_data_valid), | |
| .io_data_bits(cnpd_io_data_bits) | |
| ); | |
| GbHdmi gbHdmi ( // @[topgbhdmi.scala 105:26] | |
| .clock(gbHdmi_clock), | |
| .reset(gbHdmi_reset), | |
| .io_gb_vsync(gbHdmi_io_gb_vsync), | |
| .io_gb_clk(gbHdmi_io_gb_clk), | |
| .io_gb_data(gbHdmi_io_gb_data), | |
| .io_serClk(gbHdmi_io_serClk), | |
| .io_tmds_clk_p(gbHdmi_io_tmds_clk_p), | |
| .io_tmds_clk_n(gbHdmi_io_tmds_clk_n), | |
| .io_tmds_data_0_p(gbHdmi_io_tmds_data_0_p), | |
| .io_tmds_data_0_n(gbHdmi_io_tmds_data_0_n), | |
| .io_tmds_data_1_p(gbHdmi_io_tmds_data_1_p), | |
| .io_tmds_data_1_n(gbHdmi_io_tmds_data_1_n), | |
| .io_tmds_data_2_p(gbHdmi_io_tmds_data_2_p), | |
| .io_tmds_data_2_n(gbHdmi_io_tmds_data_2_n), | |
| .io_pattern_trig(gbHdmi_io_pattern_trig) | |
| ); | |
| assign O_led = {sNesPadReg[11],sNesPadReg[10]}; // @[topgbhdmi.scala 96:31] | |
| assign O_tmds_clk_p = gbHdmi_io_tmds_clk_p; // @[topgbhdmi.scala 116:20] | |
| assign O_tmds_clk_n = gbHdmi_io_tmds_clk_n; // @[topgbhdmi.scala 117:21] | |
| assign O_tmds_data_0_p = gbHdmi_io_tmds_data_0_p; // @[topgbhdmi.scala 118:24] | |
| assign O_tmds_data_0_n = gbHdmi_io_tmds_data_0_n; // @[topgbhdmi.scala 119:24] | |
| assign O_tmds_data_1_p = gbHdmi_io_tmds_data_1_p; // @[topgbhdmi.scala 120:24] | |
| assign O_tmds_data_1_n = gbHdmi_io_tmds_data_1_n; // @[topgbhdmi.scala 121:24] | |
| assign O_tmds_data_2_p = gbHdmi_io_tmds_data_2_p; // @[topgbhdmi.scala 122:24] | |
| assign O_tmds_data_2_n = gbHdmi_io_tmds_data_2_n; // @[topgbhdmi.scala 123:24] | |
| assign snes_dclock = cnpd_io_dclock; // @[topgbhdmi.scala 76:19] | |
| assign snes_dlatch = cnpd_io_dlatch; // @[topgbhdmi.scala 77:19] | |
| assign gbpad_a = sNesPadReg[7]; // @[topgbhdmi.scala 92:33] | |
| assign gbpad_b = sNesPadReg[15]; // @[topgbhdmi.scala 84:33] | |
| assign gbpad_select = sNesPadReg[13]; // @[topgbhdmi.scala 86:33] | |
| assign gbpad_start = sNesPadReg[12]; // @[topgbhdmi.scala 87:33] | |
| assign gbpad_right = sNesPadReg[8]; // @[topgbhdmi.scala 91:33] | |
| assign gbpad_left = sNesPadReg[9]; // @[topgbhdmi.scala 90:33] | |
| assign gbpad_up = sNesPadReg[11]; // @[topgbhdmi.scala 88:33] | |
| assign gbpad_down = sNesPadReg[10]; // @[topgbhdmi.scala 89:33] | |
| assign clkDiv_RESETN = ~glb_rst; // @[topgbhdmi.scala 59:25] | |
| assign clkDiv_HCLKIN = tmdsPllvr_clkout; // @[topgbhdmi.scala 52:26 67:16] | |
| assign clkDiv_CALIB = 1'h1; // @[topgbhdmi.scala 62:21] | |
| assign tmdsPllvr_clkin = I_clk; // @[topgbhdmi.scala 66:24] | |
| assign cnpd_clock = clkDiv_CLKOUT; // @[topgbhdmi.scala 53:23 61:13] | |
| assign cnpd_reset = ~(pll_lock & I_reset_n); // @[topgbhdmi.scala 55:19] | |
| assign cnpd_io_sdata = snes_sdata; // @[topgbhdmi.scala 78:21] | |
| assign gbHdmi_clock = clkDiv_CLKOUT; // @[topgbhdmi.scala 53:23 61:13] | |
| assign gbHdmi_reset = ~(pll_lock & I_reset_n); // @[topgbhdmi.scala 55:19] | |
| assign gbHdmi_io_gb_vsync = svsync; // @[topgbhdmi.scala 110:26] | |
| assign gbHdmi_io_gb_clk = sclk; // @[topgbhdmi.scala 111:26] | |
| assign gbHdmi_io_gb_data = sdata; // @[topgbhdmi.scala 112:26] | |
| assign gbHdmi_io_serClk = tmdsPllvr_clkout; // @[topgbhdmi.scala 52:26 67:16] | |
| assign gbHdmi_io_pattern_trig = sNesPadReg[4] | sNesPadReg[5]; // @[topgbhdmi.scala 107:47] | |
| always @(posedge pix_clk) begin | |
| if (glb_rst) begin // @[topgbhdmi.scala 74:31] | |
| sNesPadReg <= 16'h0; // @[topgbhdmi.scala 74:31] | |
| end else if (cnpd_io_data_valid) begin // @[topgbhdmi.scala 81:31] | |
| sNesPadReg <= _sNesPadReg_T; // @[topgbhdmi.scala 82:20] | |
| end | |
| svsync_r <= gb_vsync; // @[Reg.scala 16:16 17:{18,22}] | |
| svsync <= svsync_r; // @[Reg.scala 16:16 17:{18,22}] | |
| sclk_r <= gb_clk; // @[Reg.scala 16:16 17:{18,22}] | |
| sclk <= sclk_r; // @[Reg.scala 16:16 17:{18,22}] | |
| sdata_r <= gb_data; // @[Reg.scala 16:16 17:{18,22}] | |
| sdata <= sdata_r; // @[Reg.scala 16:16 17:{18,22}] | |
| end | |
| // Register and memory initialization | |
| `ifdef RANDOMIZE_GARBAGE_ASSIGN | |
| `define RANDOMIZE | |
| `endif | |
| `ifdef RANDOMIZE_INVALID_ASSIGN | |
| `define RANDOMIZE | |
| `endif | |
| `ifdef RANDOMIZE_REG_INIT | |
| `define RANDOMIZE | |
| `endif | |
| `ifdef RANDOMIZE_MEM_INIT | |
| `define RANDOMIZE | |
| `endif | |
| `ifndef RANDOM | |
| `define RANDOM $random | |
| `endif | |
| `ifdef RANDOMIZE_MEM_INIT | |
| integer initvar; | |
| `endif | |
| `ifndef SYNTHESIS | |
| `ifdef FIRRTL_BEFORE_INITIAL | |
| `FIRRTL_BEFORE_INITIAL | |
| `endif | |
| initial begin | |
| `ifdef RANDOMIZE | |
| `ifdef INIT_RANDOM | |
| `INIT_RANDOM | |
| `endif | |
| `ifndef VERILATOR | |
| `ifdef RANDOMIZE_DELAY | |
| #`RANDOMIZE_DELAY begin end | |
| `else | |
| #0.002 begin end | |
| `endif | |
| `endif | |
| `ifdef RANDOMIZE_REG_INIT | |
| _RAND_0 = {1{`RANDOM}}; | |
| sNesPadReg = _RAND_0[15:0]; | |
| _RAND_1 = {1{`RANDOM}}; | |
| svsync_r = _RAND_1[0:0]; | |
| _RAND_2 = {1{`RANDOM}}; | |
| svsync = _RAND_2[0:0]; | |
| _RAND_3 = {1{`RANDOM}}; | |
| sclk_r = _RAND_3[0:0]; | |
| _RAND_4 = {1{`RANDOM}}; | |
| sclk = _RAND_4[0:0]; | |
| _RAND_5 = {1{`RANDOM}}; | |
| sdata_r = _RAND_5[1:0]; | |
| _RAND_6 = {1{`RANDOM}}; | |
| sdata = _RAND_6[1:0]; | |
| `endif // RANDOMIZE_REG_INIT | |
| `endif // RANDOMIZE | |
| end // initial | |
| `ifdef FIRRTL_AFTER_INITIAL | |
| `FIRRTL_AFTER_INITIAL | |
| `endif | |
| `endif // SYNTHESIS | |
| endmodule |
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