Chisel multiplication of 2 UInt with same size. Serial addition way of multiplication.

multsum.scala

package multsum

import chisel3._
import chisel3.util._
import chisel3.stage.{ChiselStage, ChiselGeneratorAnnotation}
import chisel3.formal.Formal

/* Unsigned multiplication */
class MultSum(val bsize: Int = 16) extends Module with Formal {
  val io = IO(new Bundle {
    val avalue = Flipped(Decoupled(UInt(bsize.W)))
    val bvalue = Input(UInt(bsize.W))
    val sout = Decoupled(UInt((bsize*2).W))
  })
 
  val multres = RegInit(0.U((2*bsize).W))
  val aReg = RegInit(0.U(bsize.W))
  val bReg = RegInit(0.U(bsize.W))
  val cntReg = RegInit(bsize.U)

  val s_init::s_compute::s_result::Nil = Enum(3)
  val stateReg = RegInit(s_init)

  switch(stateReg){
    is(s_init){
      when(io.avalue.valid & io.avalue.ready){
        stateReg := s_compute
      }
    }
    is(s_compute){
      when(cntReg === 0.U){
        stateReg := s_result
      }
    }
    is(s_result){
      stateReg := s_init
    }
  }

  io.sout.valid := false.B 
  io.avalue.ready := false.B
  when(stateReg === s_init) {
    io.avalue.ready := true.B
    cntReg := (bsize - 1).U
    aReg := io.avalue.bits
    bReg := io.bvalue
    multres := 0.U
  }
  when(stateReg === s_compute) {
    cntReg := cntReg - 1.U
    when(aReg(cntReg)){
      multres := multres + (bReg << cntReg)
    }
  }
  when(stateReg === s_result) {
    io.sout.valid := true.B 
  }

  io.sout.bits := multres
}

object MultSum extends App {
  println("**************************************")
  println("* Generate verilog for MultSum interface *")
  println("**************************************")
  (new chisel3.stage.ChiselStage).execute(
      Array("-X", "verilog"),
      Seq(ChiselGeneratorAnnotation(() => new MultSum()))
    )
}