literki.vhdl

gistfile1.vhdl

-- Design plik
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

-- licznik 4 bitowy
entity counter_4bit is
	port(
    	clk: in std_logic;
        reset: in std_logic := '0';
    	c_begin: in unsigned(3 downto 0) := "0000";
        c_end: in unsigned(3 downto 0) := "1111";
        c_value: out unsigned(3 downto 0)
    );
end counter_4bit;

architecture counter_4bit of counter_4bit is
  	signal value: unsigned(3 downto 0) := "0000";
begin
	process(clk, reset, c_begin, c_end) 
    begin
        -- jesli reset to wyzeruj do begin
    	if reset = '1' then
        	value <= c_begin;
        elsif reset = '0' then
        	if rising_edge(clk) then
            	value <= value + 1;
              	if value = c_end then
                	value <= c_begin; 
              	end if;
            end if;
        end if;
    end process;
    
    c_value <= value;
end counter_4bit;

-- wybiera odpowiedni tytul heks wyswietlacza na podstawie licznika
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity title_shifter is
	port(
    	clk: in std_logic;
        HEX0: out std_logic_vector(6 downto 0);
        HEX1: out std_logic_vector(6 downto 0);
      	HEX2: out std_logic_vector(6 downto 0);	
      	HEX3: out std_logic_vector(6 downto 0);	
      	HEX4: out std_logic_vector(6 downto 0);	
      	HEX5: out std_logic_vector(6 downto 0);	
      	HEX6: out std_logic_vector(6 downto 0);
        HEX7: out std_logic_vector(6 downto 0));
end title_shifter;

architecture title_shifter of title_shifter is
	-- aktualne przesuniecie slowa
	signal word_offset: unsigned(3 downto 0) := "0000";

	-- shifter używa licznika 4bit bo 8 jest ekranow quartus
    component counter_4bit
    	port(
    		clk: in std_logic;
            c_begin: in unsigned(3 downto 0);
            c_end: in unsigned(3 downto 0);
            c_value: out unsigned(3 downto 0));
    end component;
    
    -- zamienia string na liste znaczków dla HEX segment
    type vector_array is array (natural range <>) of std_logic_vector(6 downto 0);

    function to_hex_display(a: string) return vector_array is
        variable ret: vector_array(7 downto 0);
        variable c: std_logic_vector(7 downto 0);
        variable buf: std_logic_vector(6 downto 0);
    begin
        for i in 0 to 7 loop
        	-- nie wiem czemu i+1, inaczej crashuje vmka
            c := std_logic_vector(to_unsigned(character'pos(a(i + 1)), 8));
            
            -- ASCII bezpośrednio na 7-segment, lista poniżej
            -- http://luishernandezengineeringportfoli.weebly.com/electronics-final.html
            -- albo na odwrot bity przed when
            with c select
            	buf := 
                    "1011011" when "01010011", -- S
                    "1111110" when "01001111", -- O
                    "0001110" when "01001100", -- L
                    "0110000" when "01001001", -- I
                    "0000000" when others;
            
        	ret(i) := buf;
        end loop;
        
        return ret;
    end function to_hex_display;
begin
  	shift_clk_process: counter_4bit port map(
    	clk,
        c_begin => "0000",
    	c_end => "0111",
    	c_value => word_offset
  	);
  	
	process(clk)
        variable buf: vector_array(7 downto 0);
        variable title: string(1 to 8);
    begin    
    	-- z counter wybierz jedno i wrzuć do value
        if not rising_edge(clk) and clk = '0' then
        	with word_offset select
            	title := 
                    "---SOLI-" when "0001",
                    "--SOLI--" when "0010",
                    "-SOLI---" when "0011",
                    "SOLI----" when "0100",
                    "OLI----S" when "0101",
                    "LI----SO" when "0110",
                    "I----SOL" when "0111",
                    "----SOLI" when others; 
           	
            -- debug log
            buf := to_hex_display(title);
       
            HEX0 <= buf(0);
            HEX1 <= buf(1);
            HEX2 <= buf(2);
            HEX3 <= buf(3);
            HEX4 <= buf(4);
            HEX5 <= buf(5);
            HEX6 <= buf(6);
            HEX7 <= buf(7);

            report("Wartosc: " & title);
        end if;
    end process;    
end title_shifter;

-- MAIN PLIK
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity ShiftDisplay is
	port(
		HEX0: out std_logic_vector(6 downto 0);
        HEX1: out std_logic_vector(6 downto 0);
      	HEX2: out std_logic_vector(6 downto 0);	
      	HEX3: out std_logic_vector(6 downto 0);	
      	HEX4: out std_logic_vector(6 downto 0);	
      	HEX5: out std_logic_vector(6 downto 0);	
      	HEX6: out std_logic_vector(6 downto 0);
        HEX7: out std_logic_vector(6 downto 0));
end ShiftDisplay;

architecture ShiftArch of ShiftDisplay is
    signal clk_100ms: std_logic := '1';
    signal stop: boolean := false;
    
    component title_shifter
    	port(
          clk: in std_logic;
          HEX0: out std_logic_vector(6 downto 0);
          HEX1: out std_logic_vector(6 downto 0);
          HEX2: out std_logic_vector(6 downto 0);	
          HEX3: out std_logic_vector(6 downto 0);	
          HEX4: out std_logic_vector(6 downto 0);	
          HEX5: out std_logic_vector(6 downto 0);	
          HEX6: out std_logic_vector(6 downto 0);
          HEX7: out std_logic_vector(6 downto 0));
    end component;
    
begin
  	clock_process: process begin
  		while not stop loop
			clk_100ms <= not clk_100ms;
        	wait for 15.625 NS; 
    	end loop;
    	wait;
  	end process;
    
    stop_process: process begin
    	wait for 300 NS;
        stop <= true;
        wait;
    end process;
    
    title_shift_process: title_shifter port map(
    	clk => clk_100ms,
        HEX0 => HEX0, 
        HEX1 => HEX1, 
        HEX2 => HEX2, 
        HEX3 => HEX3, 
        HEX4 => HEX4, 
        HEX5 => HEX5, 
        HEX6 => HEX6, 
        HEX7 => HEX7
    );
end ShiftArch;