JAKIES TOTALNIE NIEPOTRZEBNE RZECZY ALE WYMAGAJĄ

klawierka_xd.vhdl

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity Counter is
	generic (width: integer := 23); 
	port(
		clk: in std_logic;
		reset: in std_logic := '0';
    	c_begin: in unsigned(width downto 0);
      c_end: in unsigned(width downto 0);
      c_value: out unsigned(width downto 0)
    );
end counter;

architecture CounterArch of Counter is
  	signal value: unsigned(width downto 0);
begin
	process(clk, reset, c_begin, c_end)
	begin
		if reset = '1' then
			value <= c_begin;
		elsif reset = '0' then
			if falling_edge(clk) then
				if value = c_end then
					value <= c_begin; 
				else
					value <= value + 1;
				end if;
			end if;
		end if;
   end process;
    
   c_value <= value;
end CounterArch;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;

entity KeyDecoder is
   port(
		k_clk: in std_logic;
		k_data: in std_logic;
		k_out: out std_logic_vector(7 downto 0));
end KeyDecoder;

architecture KeyDecoderArch of KeyDecoder is
	signal ps2_key_buffer: unsigned(10 downto 0) := (others => '0');
	signal ps2_bit_offset: unsigned(3 downto 0) := (others => '0');
	
	component Counter
		generic (width: integer := 3); 
		port(
			clk: in std_logic;
			reset: in std_logic := '0';
			c_begin: in unsigned(width downto 0);
			c_end: in unsigned(width downto 0);
			c_value: out unsigned(width downto 0)
		 );
	end component;
begin
   process (ps2_bit_offset, k_clk)
   begin
		if falling_edge(k_clk) then
			ps2_key_buffer(to_integer(ps2_bit_offset)) <= k_data;
		end if;
   end process;
	
	process (ps2_key_buffer)
	begin
		k_out <= std_logic_vector(ps2_key_buffer)(8 downto 1);
	end process;
	
	counter_process: counter generic map(width => 3) port map(
		clk => k_clk,		
		reset => '0',
		c_begin => "0000",
		c_end => "1010",
		c_value => ps2_bit_offset
	);
end KeyDecoderArch;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity HexEncoder is
	port(
		clk: in std_logic;
		input_data: in std_logic_vector(3 downto 0);
		hex_output: out std_logic_vector(7 downto 0)
    );
end HexEncoder;

architecture HexEncoderArch of HexEncoder is
begin
	process(clk)
	begin
		if falling_edge(clk) then
		end if;
   end process;
end HexEncoderArch;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity Test is
	port(
		PS2_CLK: in std_logic;
		PS2_DAT: in std_logic;
		HEX1: out std_logic_vector(7 downto 0);
		HEX2: out std_logic_vector(7 downto 0);
		LEDR: out std_logic_vector(7 downto 0)
	);
end Test;

architecture KeyboardDisplayArch of Test is
	component KeyDecoder
		port(
			k_clk: in std_logic;
			k_data: in std_logic;
			k_out: out std_logic_vector(7 downto 0));
	end component;
	
	component HexEncoder
		port(
			clk: in std_logic;
			input_data: in std_logic_vector(3 downto 0);
			hex_output: out std_logic_vector(7 downto 0));
	end component;
	
	signal pressed_key: std_logic_vector(7 downto 0) := (others => '0');
begin
	datagram_0: KeyDecoder port map(
		k_clk => PS2_CLK,
		k_data => PS2_DAT,
		k_out => pressed_key
	);
	
	hex_encoder_1: HexEncoder port map(
		clk => PS2_CLK,
		input_data => pressed_key(3 downto 0),
		hex_output => HEX1
	);
	
	hex_encoder_2: HexEncoder port map(
		clk => PS2_CLK,
		input_data => pressed_key(7 downto 4),
		hex_output => HEX2
	);
	
	LEDR <= pressed_key;
end KeyboardDisplayArch;