dupa.vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity jk_flipflop is
   port(j, k: in std_logic;
        clk: in std_logic;
        q: inout std_logic);
end jk_flipflop;

architecture jk_flipflop_logic of jk_flipflop is
begin
   process (clk) 
   begin
      if rising_edge(clk) then                 
			if (j='0' and k='0') then
				q <= q;
			elsif (j='0' and k='1') then
				q <= '0';
			elsif (j='1' and k='0') then
				q <= '1';
			elsif (j='1' and k='1') then
				q <= not q;
			end if;
		end if;
   end process;
end jk_flipflop_logic;


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity counter is
	generic (width: integer := 23); 
	port(
		clk: in std_logic;
		reset: in std_logic := '0';
    	c_begin: in unsigned(width downto 0);
      c_end: in unsigned(width downto 0);
      c_value: out unsigned(width downto 0)
    );
end counter;

architecture counter_logic of counter is
  	signal value: unsigned(width downto 0);
begin
	process(clk, reset, c_begin, c_end)
	begin
		if reset = '1' then
			value <= c_begin;
		elsif reset = '0' then
			if rising_edge(clk) then
				if value = c_end then
					value <= c_begin; 
				else
					value <= value + 1;
				end if;
			end if;
		end if;
   end process;
    
   c_value <= value;
end counter_logic;


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity reg_1bit is
	port(
		clk: in std_logic;
		key: in std_logic;
		operation: in std_logic_vector(1 downto 0);
		x: in std_logic;
		q: inout std_logic
   );
end reg_1bit;

architecture reg_1bit_logic of reg_1bit is
	component jk_flipflop
		port(
		   clk: in std_logic;
			j: in std_logic;
			k: in std_logic;
			q: inout std_logic
		);
	end component;
	
	signal j, k: std_logic;
	
begin
	process(clk) 
	begin
		if rising_edge(clk) and key = '0' then
			case operation is
				-- NASTAWIANIE WARTOSCI
				when "00" => 
					j <= x;
					k <= not x;
					
				-- KASOWANIE
				when "01" => 
					j <= '0';
					k <= '1';
				
				-- SUMA LOGICZNA
				when "10" =>
					j <= q or x;
					k <= '0';
					
				-- AJ DONT KNOF
				when others =>
					j <= j;
					k <= k;
			 end case;
		end if;
   end process;
	
	jk_process: jk_flipflop port map(
		clk,
		j,
		k,
		q
	);
end reg_1bit_logic;