LOL.vhdl

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity counter is
	generic (width: integer := 23); 
	port(
		clk: in std_logic;
		reset: in std_logic := '0';
    	c_begin: in unsigned(width downto 0);
      c_end: in unsigned(width downto 0);
      c_value: out unsigned(width downto 0)
    );
end counter;

architecture counter_logic of counter is
  	signal value: unsigned(width downto 0);
begin
	process(clk, reset, c_begin, c_end)
	begin
		if reset = '1' then
			value <= c_begin;
		elsif reset = '0' then
			if rising_edge(clk) then
				if value = c_end then
					value <= c_begin; 
				else
					value <= value + 1;
				end if;
			end if;
		end if;
   end process;
    
   c_value <= value;
end counter_logic;


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity ShiftDisplay is
	port(
		clk: in std_logic;
		led: out std_logic_vector(0 downto 0);
		sevenSegment: out std_logic_vector(7 downto 0);
		enable: out std_logic_vector(2 downto 0));
end ShiftDisplay;

architecture ShiftArch of ShiftDisplay is
	component counter
		generic (width: integer := 23); 
		port(
			clk: in std_logic;
			reset: in std_logic := '0';
			c_begin: in unsigned(width downto 0);
			c_end: in unsigned(width downto 0);
			c_value: out unsigned(width downto 0)
		 );
	end component;
   
	signal counter_value: unsigned(23 downto 0) := "000000000000000000000000";
	signal miganie: std_logic := '0';
	signal word: unsigned(1 downto 0);
	
	type state is (s0, s1, s2);
	signal test_state: state := s0;
	
	signal LETTER_1: std_logic_vector(7 downto 0) := "00000000";
	signal LETTER_2: std_logic_vector(7 downto 0) := "00000000";
	signal LETTER_3: std_logic_vector(7 downto 0) := "00000000";

begin	
	led_process: process(Clk) begin
		if rising_edge(Clk) then
			if counter_value = 5000000 then
				case word is
				  when "00" =>
				      LETTER_1 <= "11100011";
						LETTER_2 <= "00000011"; -- O
						LETTER_3 <= "11100011";
						word <= "01";
				  when "01" => 
						LETTER_1 <= "11100011";
						LETTER_2 <= "11100011";
						LETTER_3 <= "00000011"; -- O
						word <= "10";
				  when "10" =>
						LETTER_1 <= "00000011"; -- O
						LETTER_2 <= "11100011";
						LETTER_3 <= "11100011";
						word <= "00";
				  when others =>
						word <= "00";
				end case;
				
				miganie <= not miganie;
			end if;
			
			if (counter_value mod 32) = 0 then
				case test_state is
				  when s0 =>
						enable <= "011";
						sevenSegment <= LETTER_1;
						test_state <= s1;
				  when s1 => 
						enable <= "101";
						sevenSegment <= LETTER_2; -- U
						test_state <= s2;
				  when s2 =>
						enable <= "110";
						sevenSegment <= LETTER_3;
						test_state <= s0;
				  when others =>
						enable <= "011";
						test_state <= s0;
				end case;
			end if;
		end if;
	end process;
	
	LED(0) <= miganie;
	
	counter_process: counter generic map(width => 23) port map(
		clk,		
		reset => '0',
		c_begin => "000000000000000000000000",
		c_end => "010011000100101101000000",
		c_value => counter_value
	 );
	 
end ShiftArch;