Created
November 15, 2019 11:52
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| /dts-v1/; | |
| / { | |
| model = "MT6753"; | |
| compatible = "mediatek,MT6735"; | |
| interrupt-parent = <0x1>; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x2>; | |
| chosen { | |
| bootargs = "console=tty0 console=ttyMT3,921600n1 vmalloc=496M androidboot.hardware=mt6735 slub_max_order=0 slub_debug=OFZPU firmware_class.path=/vendor/firmware"; | |
| linux,phandle = <0x4d>; | |
| phandle = <0x4d>; | |
| }; | |
| mtk-msdc.0 { | |
| compatible = "simple-bus"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| ranges = <0x0 0x0 0x0 0xffffffff>; | |
| msdc0@11230000 { | |
| compatible = "mediatek,mt6753-mmc"; | |
| reg = <0x11230000 0x10000 0x10000e84 0x2>; | |
| interrupts = <0x0 0x4f 0x8>; | |
| status = "disabled"; | |
| linux,phandle = <0x4e>; | |
| phandle = <0x4e>; | |
| }; | |
| msdc1@11240000 { | |
| compatible = "mediatek,mt6753-mmc"; | |
| reg = <0x11240000 0x10000 0x10000e84 0x2>; | |
| interrupts = <0x0 0x50 0x8>; | |
| status = "disabled"; | |
| linux,phandle = <0x4f>; | |
| phandle = <0x4f>; | |
| }; | |
| msdc2@11250000 { | |
| compatible = "mediatek,mt6735-mmc"; | |
| reg = <0x11250000 0x10000 0x10000e84 0x2>; | |
| interrupts = <0x0 0x51 0x8>; | |
| status = "disabled"; | |
| clocks = <0x2 0x10>; | |
| clock-names = "MSDC2-CLOCK"; | |
| linux,phandle = <0x50>; | |
| phandle = <0x50>; | |
| }; | |
| msdc3@11260000 { | |
| compatible = "mediatek,mt6735-mmc"; | |
| reg = <0x11260000 0x10000 0x10000e84 0x2>; | |
| interrupts = <0x0 0x52 0x8>; | |
| status = "disabled"; | |
| clocks = <0x2 0x11>; | |
| clock-names = "MSDC3-CLOCK"; | |
| linux,phandle = <0x51>; | |
| phandle = <0x51>; | |
| }; | |
| default { | |
| compatible = "mediatek, msdc1_ins-eint"; | |
| linux,phandle = <0x52>; | |
| phandle = <0x52>; | |
| }; | |
| }; | |
| atf_logger { | |
| compatible = "mediatek,atf_logger"; | |
| interrupts = <0x0 0xf9 0x1>; | |
| }; | |
| psci { | |
| compatible = "arm,psci"; | |
| method = "smc"; | |
| cpu_suspend = <0x84000001>; | |
| cpu_off = <0x84000002>; | |
| cpu_on = <0x84000003>; | |
| affinity_info = <0x84000004>; | |
| }; | |
| MOBICORE { | |
| compatible = "trustonic,mobicore"; | |
| interrupts = <0x0 0xf8 0x1>; | |
| }; | |
| utos { | |
| compatible = "microtrust,utos"; | |
| interrupts = <0x0 0xfc 0x1 0x0 0xfd 0x1>; | |
| }; | |
| utos_tester { | |
| compatible = "microtrust,tester-v1"; | |
| }; | |
| cpus { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| linux,phandle = <0x53>; | |
| phandle = <0x53>; | |
| cpu@000 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53"; | |
| reg = <0x0>; | |
| enable-method = "mt-boot"; | |
| cpu-idle-states = <0x3 0x3 0x4 0x4>; | |
| cpu-release-addr = <0x0 0x40000200>; | |
| clock-frequency = "M|m"; | |
| linux,phandle = <0x5>; | |
| phandle = <0x5>; | |
| }; | |
| cpu@001 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53"; | |
| reg = <0x1>; | |
| enable-method = "mt-boot"; | |
| cpu-idle-states = <0x3 0x3 0x4 0x4>; | |
| cpu-release-addr = <0x0 0x40000200>; | |
| clock-frequency = "M|m"; | |
| linux,phandle = <0x6>; | |
| phandle = <0x6>; | |
| }; | |
| cpu@002 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53"; | |
| reg = <0x2>; | |
| enable-method = "mt-boot"; | |
| cpu-idle-states = <0x3 0x3 0x4 0x4>; | |
| cpu-release-addr = <0x0 0x40000200>; | |
| clock-frequency = "M|m"; | |
| linux,phandle = <0x7>; | |
| phandle = <0x7>; | |
| }; | |
| cpu@003 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53"; | |
| reg = <0x3>; | |
| enable-method = "mt-boot"; | |
| cpu-idle-states = <0x3 0x3 0x4 0x4>; | |
| cpu-release-addr = <0x0 0x40000200>; | |
| clock-frequency = "M|m"; | |
| linux,phandle = <0x8>; | |
| phandle = <0x8>; | |
| }; | |
| cpu@100 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53"; | |
| reg = <0x100>; | |
| enable-method = "mt-boot"; | |
| cpu-idle-states = <0x3 0x3 0x4 0x4>; | |
| cpu-release-addr = <0x0 0x40000200>; | |
| clock-frequency = "M|m"; | |
| linux,phandle = <0x9>; | |
| phandle = <0x9>; | |
| }; | |
| cpu@101 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53"; | |
| reg = <0x101>; | |
| enable-method = "mt-boot"; | |
| cpu-idle-states = <0x3 0x3 0x4 0x4>; | |
| cpu-release-addr = <0x0 0x40000200>; | |
| clock-frequency = "M|m"; | |
| linux,phandle = <0xa>; | |
| phandle = <0xa>; | |
| }; | |
| cpu@102 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53"; | |
| reg = <0x102>; | |
| enable-method = "mt-boot"; | |
| cpu-idle-states = <0x3 0x3 0x4 0x4>; | |
| cpu-release-addr = <0x0 0x40000200>; | |
| clock-frequency = "M|m"; | |
| linux,phandle = <0xb>; | |
| phandle = <0xb>; | |
| }; | |
| cpu@103 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53"; | |
| reg = <0x103>; | |
| enable-method = "mt-boot"; | |
| cpu-idle-states = <0x3 0x3 0x4 0x4>; | |
| cpu-release-addr = <0x0 0x40000200>; | |
| clock-frequency = "M|m"; | |
| linux,phandle = <0xc>; | |
| phandle = <0xc>; | |
| }; | |
| cpu-map { | |
| cluster0 { | |
| core0 { | |
| cpu = <0x5>; | |
| }; | |
| core1 { | |
| cpu = <0x6>; | |
| }; | |
| core2 { | |
| cpu = <0x7>; | |
| }; | |
| core3 { | |
| cpu = <0x8>; | |
| }; | |
| }; | |
| cluster1 { | |
| core0 { | |
| cpu = <0x9>; | |
| }; | |
| core1 { | |
| cpu = <0xa>; | |
| }; | |
| core2 { | |
| cpu = <0xb>; | |
| }; | |
| core3 { | |
| cpu = <0xc>; | |
| }; | |
| }; | |
| }; | |
| idle-states { | |
| entry-method = "arm,psci"; | |
| cpu-sleep-0-0 { | |
| compatible = "arm,idle-state"; | |
| arm,psci-suspend-param = <0x10000>; | |
| entry-latency-us = <0x258>; | |
| exit-latency-us = <0x258>; | |
| min-residency-us = <0x4b0>; | |
| linux,phandle = <0x4>; | |
| phandle = <0x4>; | |
| }; | |
| cluster-sleep-0 { | |
| compatible = "arm,idle-state"; | |
| arm,psci-suspend-param = <0x1010000>; | |
| entry-latency-us = <0x320>; | |
| exit-latency-us = <0x3e8>; | |
| min-residency-us = <0x7d0>; | |
| linux,phandle = <0x3>; | |
| phandle = <0x3>; | |
| }; | |
| }; | |
| }; | |
| memory { | |
| device_type = "memory"; | |
| reg = <0x0 0x40000000 0x0 0x40000000>; | |
| }; | |
| reserved-memory { | |
| #address-cells = <0x2>; | |
| #size-cells = <0x2>; | |
| ranges; | |
| linux,phandle = <0x54>; | |
| phandle = <0x54>; | |
| atf-reserved-memory@43000000 { | |
| compatible = "mediatek,mt6735-atf-reserved-memory", "mediatek,mt6735m-atf-reserved-memory", "mediatek,mt6753-atf-reserved-memory"; | |
| no-map; | |
| reg = <0x0 0x43000000 0x0 0x30000>; | |
| }; | |
| reserve-memory-ccci_md1 { | |
| compatible = "mediatek,reserve-memory-ccci_md1"; | |
| no-map; | |
| size = <0x0 0x3810000>; | |
| alignment = <0x0 0x2000000>; | |
| alloc-ranges = <0x0 0x40000000 0x0 0xc0000000>; | |
| }; | |
| consys-reserve-memory { | |
| compatible = "mediatek,consys-reserve-memory"; | |
| no-map; | |
| size = <0x0 0x100000>; | |
| alignment = <0x0 0x200000>; | |
| }; | |
| spm-reserve-memory { | |
| compatible = "mediatek,spm-reserve-memory"; | |
| no-map; | |
| size = <0x0 0x10000>; | |
| alignment = <0x0 0x10000>; | |
| alloc-ranges = <0x0 0x40000000 0x0 0x60000000>; | |
| }; | |
| ram_console-reserved-memory@43f00000 { | |
| compatible = "mediatek,ram_console"; | |
| reg = <0x0 0x43f00000 0x0 0x10000>; | |
| }; | |
| minirdump-reserved-memory@43ff0000 { | |
| compatible = "mediatek, minirdump"; | |
| reg = <0x0 0x43ff0000 0x0 0x10000>; | |
| }; | |
| pstore-reserved-memory@43f10000 { | |
| compatible = "mediatek,pstore"; | |
| reg = <0x0 0x43f10000 0x0 0xe0000>; | |
| }; | |
| }; | |
| interrupt-controller@10220000 { | |
| compatible = "mediatek,mt6735-gic"; | |
| #interrupt-cells = <0x3>; | |
| #address-cells = <0x0>; | |
| interrupt-controller; | |
| reg = <0x0 0x10221000 0x0 0x1000 0x0 0x10222000 0x0 0x1000 0x0 0x10200620 0x0 0x1000>; | |
| mediatek,wdt_irq = <0xa0>; | |
| linux,phandle = <0x1>; | |
| phandle = <0x1>; | |
| gic-cpuif@0 { | |
| compatible = "arm,gic-cpuif"; | |
| cpuif-id = <0x0>; | |
| cpu = <0x5>; | |
| }; | |
| gic-cpuif@1 { | |
| compatible = "arm,gic-cpuif"; | |
| cpuif-id = <0x1>; | |
| cpu = <0x6>; | |
| }; | |
| gic-cpuif@2 { | |
| compatible = "arm,gic-cpuif"; | |
| cpuif-id = <0x2>; | |
| cpu = <0x7>; | |
| }; | |
| gic-cpuif@3 { | |
| compatible = "arm,gic-cpuif"; | |
| cpuif-id = <0x3>; | |
| cpu = <0x8>; | |
| }; | |
| }; | |
| clocks { | |
| clk_null { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x0>; | |
| clock-frequency = <0x0>; | |
| linux,phandle = <0x55>; | |
| phandle = <0x55>; | |
| }; | |
| clk26m { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x0>; | |
| clock-frequency = <0x18cba80>; | |
| linux,phandle = <0x56>; | |
| phandle = <0x56>; | |
| }; | |
| clk32k { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x0>; | |
| clock-frequency = <0x7d00>; | |
| linux,phandle = <0x57>; | |
| phandle = <0x57>; | |
| }; | |
| }; | |
| soc { | |
| compatible = "simple-bus"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| ranges; | |
| linux,phandle = <0x58>; | |
| phandle = <0x58>; | |
| chipid@08000000 { | |
| compatible = "mediatek,chipid"; | |
| reg = <0x8000000 0x4 0x8000004 0x4 0x8000008 0x4 0x800000c 0x4>; | |
| }; | |
| topckgen@0x10210000 { | |
| compatible = "mediatek,mt6735-topckgen"; | |
| reg = <0x10210000 0x1000>; | |
| #clock-cells = <0x1>; | |
| linux,phandle = <0x23>; | |
| phandle = <0x23>; | |
| }; | |
| infrasys@0x10000000 { | |
| compatible = "mediatek,mt6735-infrasys"; | |
| reg = <0x10000000 0x1000>; | |
| #clock-cells = <0x1>; | |
| linux,phandle = <0xd>; | |
| phandle = <0xd>; | |
| }; | |
| perisys@0x10002000 { | |
| compatible = "mediatek,mt6735-perisys"; | |
| reg = <0x10002000 0x1000>; | |
| #clock-cells = <0x1>; | |
| linux,phandle = <0x2>; | |
| phandle = <0x2>; | |
| }; | |
| gpio { | |
| compatible = "mediatek,gpio_usage_mapping"; | |
| linux,phandle = <0x59>; | |
| phandle = <0x59>; | |
| }; | |
| gpio@10211000 { | |
| compatible = "mediatek,gpio"; | |
| reg = <0x10211000 0x1000>; | |
| linux,phandle = <0x5a>; | |
| phandle = <0x5a>; | |
| }; | |
| dramc_nao@1020e000 { | |
| compatible = "mediatek,mt6735-dramc_nao"; | |
| reg = <0x1020e000 0x1000>; | |
| linux,phandle = <0x5b>; | |
| phandle = <0x5b>; | |
| }; | |
| ddrphy@10213000 { | |
| compatible = "mediatek,mt6735-ddrphy"; | |
| reg = <0x10213000 0x1000>; | |
| linux,phandle = <0x5c>; | |
| phandle = <0x5c>; | |
| }; | |
| dramc@10214000 { | |
| compatible = "mediatek,mt6735-dramc"; | |
| reg = <0x10214000 0x1000>; | |
| clocks = <0xd 0x2>; | |
| clock-names = "infra-cqdma"; | |
| linux,phandle = <0x5d>; | |
| phandle = <0x5d>; | |
| }; | |
| cpuxgpt@10200000 { | |
| compatible = "mediatek,mt6735-cpuxgpt"; | |
| reg = <0x10200000 0x1000>; | |
| interrupts = <0x0 0x40 0x4 0x0 0x41 0x4 0x0 0x42 0x4 0x0 0x43 0x4 0x0 0x44 0x4 0x0 0x45 0x4 0x0 0x46 0x4 0x0 0x47 0x4>; | |
| linux,phandle = <0x5e>; | |
| phandle = <0x5e>; | |
| }; | |
| apxgpt@10004000 { | |
| compatible = "mediatek,mt6735-apxgpt"; | |
| reg = <0x10004000 0x1000>; | |
| interrupts = <0x0 0x98 0x8>; | |
| clock-frequency = <0xc65d40>; | |
| linux,phandle = <0x5f>; | |
| phandle = <0x5f>; | |
| }; | |
| pmu { | |
| compatible = "arm,armv8-pmuv3"; | |
| interrupts = <0x0 0x8 0x8 0x0 0x9 0x8 0x0 0xa 0x8 0x0 0xb 0x8 0x0 0xc 0x8 0x0 0xd 0x8 0x0 0xe 0x8 0x0 0xf 0x8>; | |
| interrupt-affinity = <0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc>; | |
| }; | |
| timer { | |
| compatible = "arm,armv8-timer"; | |
| interrupts = <0x1 0xd 0x8 0x1 0xe 0x8 0x1 0xb 0x8 0x1 0xa 0x8>; | |
| clock-frequency = <0xc65d40>; | |
| }; | |
| mt_pmic_regulator { | |
| compatible = "mediatek,mt_pmic"; | |
| buck_regulators { | |
| compatible = "mediatek,mt_pmic_buck_regulators"; | |
| buck_vpa { | |
| regulator-name = "vpa"; | |
| regulator-min-microvolt = <0x7a120>; | |
| regulator-max-microvolt = <0x37b1d0>; | |
| regulator-ramp-delay = <0xc350>; | |
| regulator-enable-ramp-delay = <0xb4>; | |
| linux,phandle = <0x60>; | |
| phandle = <0x60>; | |
| }; | |
| buck_vproc { | |
| regulator-name = "vproc"; | |
| regulator-min-microvolt = <0x927c0>; | |
| regulator-max-microvolt = <0x154456>; | |
| regulator-ramp-delay = <0x186a>; | |
| regulator-enable-ramp-delay = <0xb4>; | |
| regulator-always-on; | |
| regulator-boot-on; | |
| linux,phandle = <0x61>; | |
| phandle = <0x61>; | |
| }; | |
| buck_vcore1 { | |
| regulator-name = "vcore1"; | |
| regulator-min-microvolt = <0x927c0>; | |
| regulator-max-microvolt = <0x154456>; | |
| regulator-ramp-delay = <0x186a>; | |
| regulator-enable-ramp-delay = <0xb4>; | |
| regulator-always-on; | |
| regulator-boot-on; | |
| linux,phandle = <0x62>; | |
| phandle = <0x62>; | |
| }; | |
| buck_vsys22 { | |
| regulator-name = "vsys22"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x1e6c16>; | |
| regulator-ramp-delay = <0x186a>; | |
| regulator-enable-ramp-delay = <0xb4>; | |
| regulator-always-on; | |
| regulator-boot-on; | |
| linux,phandle = <0x63>; | |
| phandle = <0x63>; | |
| }; | |
| buck_vlte { | |
| regulator-name = "vlte"; | |
| regulator-min-microvolt = <0x927c0>; | |
| regulator-max-microvolt = <0x154456>; | |
| regulator-ramp-delay = <0x186a>; | |
| regulator-enable-ramp-delay = <0xb4>; | |
| regulator-always-on; | |
| regulator-boot-on; | |
| linux,phandle = <0x64>; | |
| phandle = <0x64>; | |
| }; | |
| }; | |
| ldo_regulators { | |
| compatible = "mediatek,mt_pmic_ldo_regulators"; | |
| ldo_vaux18 { | |
| regulator-name = "vaux18"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| regulator-boot-on; | |
| linux,phandle = <0xe>; | |
| phandle = <0xe>; | |
| }; | |
| ldo_vtcxo_0 { | |
| regulator-name = "vtcxo_0"; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-max-microvolt = <0x2ab980>; | |
| regulator-enable-ramp-delay = <0x6e>; | |
| regulator-boot-on; | |
| linux,phandle = <0xf>; | |
| phandle = <0xf>; | |
| }; | |
| ldo_vtcxo_1 { | |
| regulator-name = "vtcxo_1"; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-max-microvolt = <0x2ab980>; | |
| regulator-enable-ramp-delay = <0x6e>; | |
| linux,phandle = <0x10>; | |
| phandle = <0x10>; | |
| }; | |
| ldo_vaud28 { | |
| regulator-name = "vaud28"; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-max-microvolt = <0x2ab980>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| regulator-boot-on; | |
| linux,phandle = <0x11>; | |
| phandle = <0x11>; | |
| }; | |
| ldo_vcn28 { | |
| regulator-name = "vcn28"; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-max-microvolt = <0x2ab980>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x65>; | |
| phandle = <0x65>; | |
| }; | |
| ldo_vcama { | |
| regulator-name = "vcama"; | |
| regulator-min-microvolt = <0x16e360>; | |
| regulator-max-microvolt = <0x2ab980>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x3a>; | |
| phandle = <0x3a>; | |
| }; | |
| ldo_vcn33_bt { | |
| regulator-name = "vcn33_bt"; | |
| regulator-min-microvolt = <0x325aa0>; | |
| regulator-max-microvolt = <0x36ee80>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x66>; | |
| phandle = <0x66>; | |
| }; | |
| ldo_vcn33_wifi { | |
| regulator-name = "vcn33_wifi"; | |
| regulator-min-microvolt = <0x325aa0>; | |
| regulator-max-microvolt = <0x36ee80>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x67>; | |
| phandle = <0x67>; | |
| }; | |
| ldo_vusb33 { | |
| regulator-name = "vusb33"; | |
| regulator-min-microvolt = <0x325aa0>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| regulator-boot-on; | |
| linux,phandle = <0x4a>; | |
| phandle = <0x4a>; | |
| }; | |
| ldo_vefuse { | |
| regulator-name = "vefuse"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x2191c0>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x12>; | |
| phandle = <0x12>; | |
| }; | |
| ldo_vsim1 { | |
| regulator-name = "vsim1"; | |
| regulator-min-microvolt = <0x19f0a0>; | |
| regulator-max-microvolt = <0x200b20>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x13>; | |
| phandle = <0x13>; | |
| }; | |
| ldo_vsim2 { | |
| regulator-name = "vsim2"; | |
| regulator-min-microvolt = <0x19f0a0>; | |
| regulator-max-microvolt = <0x200b20>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x14>; | |
| phandle = <0x14>; | |
| }; | |
| ldo_vemc_3v3 { | |
| regulator-name = "vemc_3v3"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| regulator-boot-on; | |
| linux,phandle = <0x15>; | |
| phandle = <0x15>; | |
| }; | |
| ldo_vmch { | |
| regulator-name = "vmch"; | |
| regulator-min-microvolt = <0x2c4020>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| regulator-enable-ramp-delay = <0x2c>; | |
| linux,phandle = <0x16>; | |
| phandle = <0x16>; | |
| }; | |
| ldo_vtref { | |
| regulator-name = "vtref"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-enable-ramp-delay = <0xf0>; | |
| linux,phandle = <0x17>; | |
| phandle = <0x17>; | |
| }; | |
| ldo_vmc { | |
| regulator-name = "vmc"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| regulator-enable-ramp-delay = <0x2c>; | |
| linux,phandle = <0x18>; | |
| phandle = <0x18>; | |
| }; | |
| ldo_vcamaf { | |
| regulator-name = "vcamaf"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x3c>; | |
| phandle = <0x3c>; | |
| }; | |
| ldo_vio28 { | |
| regulator-name = "vio28"; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-max-microvolt = <0x2ab980>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| regulator-boot-on; | |
| linux,phandle = <0x19>; | |
| phandle = <0x19>; | |
| }; | |
| ldo_vgp1 { | |
| regulator-name = "vgp1"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x4b>; | |
| phandle = <0x4b>; | |
| }; | |
| ldo_vibr { | |
| regulator-name = "vibr"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| regulator-enable-ramp-delay = <0x2c>; | |
| linux,phandle = <0x1a>; | |
| phandle = <0x1a>; | |
| }; | |
| ldo_vcamd { | |
| regulator-name = "vcamd"; | |
| regulator-min-microvolt = <0xdbba0>; | |
| regulator-max-microvolt = <0x16e360>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| linux,phandle = <0x3b>; | |
| phandle = <0x3b>; | |
| }; | |
| ldo_vrf18_0 { | |
| regulator-name = "vrf18_0"; | |
| regulator-min-microvolt = <0x1bd8e8>; | |
| regulator-max-microvolt = <0x1bd8e8>; | |
| regulator-enable-ramp-delay = <0xdc>; | |
| linux,phandle = <0x1b>; | |
| phandle = <0x1b>; | |
| }; | |
| ldo_vrf18_1 { | |
| regulator-name = "vrf18_1"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x1bd8e8>; | |
| regulator-enable-ramp-delay = <0xdc>; | |
| linux,phandle = <0x1c>; | |
| phandle = <0x1c>; | |
| }; | |
| ldo_vio18 { | |
| regulator-name = "vio18"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| regulator-boot-on; | |
| linux,phandle = <0x1d>; | |
| phandle = <0x1d>; | |
| }; | |
| ldo_vcn18 { | |
| regulator-name = "vcn18"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-enable-ramp-delay = <0x2c>; | |
| linux,phandle = <0x68>; | |
| phandle = <0x68>; | |
| }; | |
| ldo_vcamio { | |
| regulator-name = "vcamio"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-enable-ramp-delay = <0xdc>; | |
| linux,phandle = <0x3d>; | |
| phandle = <0x3d>; | |
| }; | |
| ldo_vsram { | |
| regulator-name = "vsram"; | |
| regulator-min-microvolt = <0xaae60>; | |
| regulator-max-microvolt = <0x16caf6>; | |
| regulator-enable-ramp-delay = <0xdc>; | |
| regulator-ramp-delay = <0x186a>; | |
| regulator-boot-on; | |
| linux,phandle = <0x1e>; | |
| phandle = <0x1e>; | |
| }; | |
| ldo_vm { | |
| regulator-name = "vm"; | |
| regulator-min-microvolt = <0x12ebc0>; | |
| regulator-max-microvolt = <0x177fa0>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| regulator-boot-on; | |
| linux,phandle = <0x1f>; | |
| phandle = <0x1f>; | |
| }; | |
| }; | |
| regulators_supply { | |
| compatible = "mediatek,mt_pmic_regulator_supply"; | |
| vaux18-supply = <0xe>; | |
| vtcxo_0-supply = <0xf>; | |
| vtcxo_1-supply = <0x10>; | |
| vaud28-supply = <0x11>; | |
| vefuse-supply = <0x12>; | |
| vsim1-supply = <0x13>; | |
| vsim2-supply = <0x14>; | |
| vemc_3v3-supply = <0x15>; | |
| vmch-supply = <0x16>; | |
| vtref-supply = <0x17>; | |
| vmc-supply = <0x18>; | |
| vio28-supply = <0x19>; | |
| vibr-supply = <0x1a>; | |
| vrf18_0-supply = <0x1b>; | |
| vrf18_1-supply = <0x1c>; | |
| vio18-supply = <0x1d>; | |
| vsram-supply = <0x1e>; | |
| vm-supply = <0x1f>; | |
| }; | |
| }; | |
| sys_cirq@10204000 { | |
| compatible = "mediatek,mt6735-sys_cirq"; | |
| reg = <0x10204000 0x1000>; | |
| interrupts = <0x0 0xe7 0x8>; | |
| mediatek,cirq_num = <0x9f>; | |
| mediatek,spi_start_offset = <0x48>; | |
| linux,phandle = <0x69>; | |
| phandle = <0x69>; | |
| }; | |
| apmixedsys@0x10209000 { | |
| compatible = "mediatek,mt6735-apmixedsys"; | |
| reg = <0x10209000 0x1000>; | |
| #clock-cells = <0x1>; | |
| linux,phandle = <0x6a>; | |
| phandle = <0x6a>; | |
| }; | |
| toprgu@10212000 { | |
| compatible = "mediatek,mt6735-rgu"; | |
| reg = <0x10212000 0x1000>; | |
| interrupts = <0x0 0x80 0x2>; | |
| linux,phandle = <0x6b>; | |
| phandle = <0x6b>; | |
| }; | |
| adc_hw@11001000 { | |
| compatible = "mediatek,mt6735-auxadc"; | |
| reg = <0x11001000 0x1000>; | |
| interrupts = <0x0 0x4c 0x2>; | |
| clocks = <0x2 0x1c>; | |
| clock-names = "auxadc-main"; | |
| linux,phandle = <0x6c>; | |
| phandle = <0x6c>; | |
| }; | |
| audiosys@11220000 { | |
| compatible = "mediatek,mt6735-audiosys"; | |
| reg = <0x11220000 0x10000>; | |
| #clock-cells = <0x1>; | |
| linux,phandle = <0x6d>; | |
| phandle = <0x6d>; | |
| }; | |
| mfgsys@13000000 { | |
| compatible = "mediatek,mt6735-mfgsys"; | |
| reg = <0x13000000 0x1000>; | |
| #clock-cells = <0x1>; | |
| linux,phandle = <0x4c>; | |
| phandle = <0x4c>; | |
| }; | |
| mmsys@14000000 { | |
| compatible = "mediatek,mt6735-mmsys"; | |
| reg = <0x14000000 0x1000>; | |
| #clock-cells = <0x1>; | |
| linux,phandle = <0x20>; | |
| phandle = <0x20>; | |
| }; | |
| imgsys@15000000 { | |
| compatible = "mediatek,mt6735-imgsys"; | |
| reg = <0x15000000 0x1000>; | |
| #clock-cells = <0x1>; | |
| linux,phandle = <0x39>; | |
| phandle = <0x39>; | |
| }; | |
| vdecsys@16000000 { | |
| compatible = "mediatek,mt6735-vdecsys"; | |
| reg = <0x16000000 0x1000>; | |
| interrupts = <0x0 0xb3 0x8>; | |
| #clock-cells = <0x1>; | |
| linux,phandle = <0x21>; | |
| phandle = <0x21>; | |
| }; | |
| vencsys@17000000 { | |
| compatible = "mediatek,mt6735-vencsys"; | |
| reg = <0x17000000 0x1000>; | |
| interrupts = <0x0 0xb4 0x8>; | |
| #clock-cells = <0x1>; | |
| linux,phandle = <0x22>; | |
| phandle = <0x22>; | |
| }; | |
| scpsys@10000000 { | |
| compatible = "mediatek,mt6735-scpsys"; | |
| reg = <0x10000000 0x1000 0x10006000 0x1000>; | |
| #clock-cells = <0x1>; | |
| linux,phandle = <0x24>; | |
| phandle = <0x24>; | |
| }; | |
| vdec_gcon@16000000 { | |
| compatible = "mediatek,mt6735-vdec_gcon"; | |
| reg = <0x16000000 0x1000>; | |
| interrupts = <0x0 0xb3 0x8>; | |
| clocks = <0x20 0x1 0x21 0x1 0x21 0x2 0x22 0x2 0x22 0x1 0x23 0x6 0x23 0x32 0x23 0x33 0x24 0x7 0x24 0x8 0x24 0x4>; | |
| clock-names = "MT_CG_DISP0_SMI_COMMON", "MT_CG_VDEC0_VDEC", "MT_CG_VDEC1_LARB", "MT_CG_VENC_VENC", "MT_CG_VENC_LARB", "MT_CG_TOP_MUX_VDEC", "MT_CG_TOP_SYSPLL1_D2", "MT_CG_TOP_SYSPLL1_D4", "MT_SCP_SYS_VDE", "MT_SCP_SYS_VEN", "MT_SCP_SYS_DIS"; | |
| linux,phandle = <0x6e>; | |
| phandle = <0x6e>; | |
| }; | |
| vdec@16020000 { | |
| compatible = "mediatek,mt6735-vdec"; | |
| reg = <0x16020000 0x10000>; | |
| interrupts = <0x0 0xb3 0x8>; | |
| linux,phandle = <0x6f>; | |
| phandle = <0x6f>; | |
| }; | |
| venc_gcon@17000000 { | |
| compatible = "mediatek,mt6735-venc_gcon"; | |
| reg = <0x17000000 0x1000>; | |
| interrupts = <0x0 0xb4 0x8>; | |
| linux,phandle = <0x70>; | |
| phandle = <0x70>; | |
| }; | |
| venc@17002000 { | |
| compatible = "mediatek,mt6735-venc"; | |
| reg = <0x17002000 0x1000>; | |
| interrupts = <0x0 0xb4 0x8>; | |
| linux,phandle = <0x71>; | |
| phandle = <0x71>; | |
| }; | |
| jpgenc@17003000 { | |
| compatible = "mediatek,jpgenc"; | |
| reg = <0x17003000 0x1000>; | |
| interrupts = <0x0 0xb5 0x8>; | |
| clocks = <0x24 0x4 0x20 0x1 0x24 0x8 0x22 0x1 0x22 0x3>; | |
| clock-names = "disp-mtcmos", "disp-smi", "venc-mtcmos", "venc-larb", "venc-jpgenc"; | |
| }; | |
| jpgdec@17004000 { | |
| compatible = "mediatek,jpgdec"; | |
| reg = <0x17004000 0x1000>; | |
| interrupts = <0x0 0xd1 0x8>; | |
| clocks = <0x24 0x4 0x20 0x1 0x24 0x8 0x22 0x1 0x22 0x4>; | |
| clock-names = "disp-mtcmos", "disp-smi", "venc-mtcmos", "venc-larb", "venc-jpgdec"; | |
| }; | |
| keypad@10003000 { | |
| compatible = "mediatek,mt6735-keypad"; | |
| reg = <0x10003000 0x1000>; | |
| interrupts = <0x0 0xa4 0x2>; | |
| linux,phandle = <0x72>; | |
| phandle = <0x72>; | |
| }; | |
| irtx@11011000 { | |
| compatible = "mediatek,irtx"; | |
| reg = <0x11011000 0x1000>; | |
| interrupts = <0x0 0x7c 0x4>; | |
| pwm_ch = <0x0>; | |
| clock-frequency = <0x18cba80>; | |
| clock-div = <0x1>; | |
| clocks = <0x2 0x1e>; | |
| clock-names = "clk-irtx-main"; | |
| linux,phandle = <0x73>; | |
| phandle = <0x73>; | |
| }; | |
| apuart0@11002000 { | |
| cell-index = <0x0>; | |
| compatible = "mediatek,mt6735-uart"; | |
| reg = <0x11002000 0x1000 0x11000400 0x1000 0x11000480 0x80>; | |
| interrupts = <0x0 0x5b 0x8 0x0 0x67 0x8 0x0 0x68 0x8>; | |
| clock-frequency = <0x18cba80>; | |
| clock-div = <0x1>; | |
| clocks = <0x2 0x12 0x2 0xd>; | |
| clock-names = "uart0-main", "uart-apdma"; | |
| pinctrl-names = "uart0_gpio_default", "uart0_rx_set", "uart0_rx_clear", "uart0_tx_set", "uart0_tx_clear"; | |
| pinctrl-0 = <0x25>; | |
| pinctrl-1 = <0x26>; | |
| pinctrl-2 = <0x27>; | |
| pinctrl-3 = <0x28>; | |
| pinctrl-4 = <0x29>; | |
| linux,phandle = <0x74>; | |
| phandle = <0x74>; | |
| }; | |
| apuart1@11003000 { | |
| cell-index = <0x1>; | |
| compatible = "mediatek,mt6735-uart"; | |
| reg = <0x11003000 0x1000 0x11000500 0x80 0x11000580 0x80>; | |
| interrupts = <0x0 0x5c 0x8 0x0 0x69 0x8 0x0 0x6a 0x8>; | |
| clock-frequency = <0x18cba80>; | |
| clock-div = <0x1>; | |
| clocks = <0x2 0x13>; | |
| clock-names = "uart1-main"; | |
| pinctrl-names = "uart1_gpio_default", "uart1_rx_set", "uart1_rx_clear", "uart1_tx_set", "uart1_tx_clear"; | |
| pinctrl-0 = <0x2a>; | |
| pinctrl-1 = <0x2b>; | |
| pinctrl-2 = <0x2c>; | |
| pinctrl-3 = <0x2d>; | |
| pinctrl-4 = <0x2e>; | |
| linux,phandle = <0x75>; | |
| phandle = <0x75>; | |
| }; | |
| apuart2@11004000 { | |
| cell-index = <0x2>; | |
| compatible = "mediatek,mt6735-uart"; | |
| reg = <0x11004000 0x1000 0x11000600 0x80 0x11000680 0x80>; | |
| interrupts = <0x0 0x5d 0x8 0x0 0x6b 0x8 0x0 0x6c 0x8>; | |
| clock-frequency = <0x18cba80>; | |
| clock-div = <0x1>; | |
| clocks = <0x2 0x14>; | |
| clock-names = "uart2-main"; | |
| pinctrl-names = "uart2_gpio_default", "uart2_rx_set", "uart2_rx_clear", "uart2_tx_set", "uart2_tx_clear"; | |
| pinctrl-0 = <0x2f>; | |
| pinctrl-1 = <0x30>; | |
| pinctrl-2 = <0x31>; | |
| pinctrl-3 = <0x32>; | |
| pinctrl-4 = <0x33>; | |
| linux,phandle = <0x76>; | |
| phandle = <0x76>; | |
| }; | |
| apuart3@11005000 { | |
| cell-index = <0x3>; | |
| compatible = "mediatek,mt6735-uart"; | |
| reg = <0x11005000 0x1000 0x11000700 0x80 0x11000780 0x80>; | |
| interrupts = <0x0 0x5e 0x8 0x0 0x6d 0x8 0x0 0x6e 0x8>; | |
| clock-frequency = <0x18cba80>; | |
| clock-div = <0x1>; | |
| clocks = <0x2 0x15>; | |
| clock-names = "uart3-main"; | |
| pinctrl-names = "uart3_gpio_default", "uart3_rx_set", "uart3_rx_clear", "uart3_tx_set", "uart3_tx_clear"; | |
| pinctrl-0 = <0x34>; | |
| pinctrl-1 = <0x35>; | |
| pinctrl-2 = <0x36>; | |
| pinctrl-3 = <0x37>; | |
| pinctrl-4 = <0x38>; | |
| linux,phandle = <0x77>; | |
| phandle = <0x77>; | |
| }; | |
| THERM_CTRL@0x1100B000 { | |
| compatible = "mediatek,THERM_CTRL"; | |
| reg = <0x1100b000 0x1000>; | |
| interrupts = <0x0 0x4e 0x8>; | |
| }; | |
| ptp_fsm@1100b000 { | |
| compatible = "mediatek,ptp_fsm_v1"; | |
| reg = <0x1100b000 0x1000>; | |
| interrupts = <0x0 0x7d 0x8>; | |
| }; | |
| apuart4@1100d000 { | |
| cell-index = <0x4>; | |
| compatible = "mediatek,mt6735-uart"; | |
| reg = <0x1100d000 0x1000 0x11000800 0x80 0x11000880 0x80>; | |
| interrupts = <0x0 0x5f 0x8 0x0 0x6f 0x8 0x0 0x70 0x8>; | |
| clock-frequency = <0x18cba80>; | |
| clock-div = <0x1>; | |
| clocks = <0x2 0x16>; | |
| clock-names = "uart4-main"; | |
| linux,phandle = <0x78>; | |
| phandle = <0x78>; | |
| }; | |
| spi@1100a000 { | |
| compatible = "mediatek,mt6753-spi"; | |
| cell-index = <0x0>; | |
| spi-padmacro = <0x0>; | |
| reg = <0x1100a000 0x1000>; | |
| interrupts = <0x0 0x76 0x8>; | |
| linux,phandle = <0x79>; | |
| phandle = <0x79>; | |
| }; | |
| btif_tx@11000900 { | |
| compatible = "mediatek,btif_tx"; | |
| reg = <0x11000900 0x80>; | |
| interrupts = <0x0 0x71 0x8>; | |
| linux,phandle = <0x7a>; | |
| phandle = <0x7a>; | |
| }; | |
| btif_rx@11000980 { | |
| compatible = "mediatek,btif_rx"; | |
| reg = <0x11000980 0x80>; | |
| interrupts = <0x0 0x72 0x8>; | |
| linux,phandle = <0x7b>; | |
| phandle = <0x7b>; | |
| }; | |
| btif@1100c000 { | |
| compatible = "mediatek,btif"; | |
| reg = <0x1100c000 0x1000>; | |
| interrupts = <0x0 0x5a 0x8>; | |
| linux,phandle = <0x7c>; | |
| phandle = <0x7c>; | |
| }; | |
| consys@18070000 { | |
| compatible = "mediatek,mt6753-consys", "mediatek,mt6735-consys"; | |
| reg = <0x18070000 0x200 0x10212000 0x100 0x10000000 0x2000 0x10006000 0x1000>; | |
| interrupts = <0x0 0xe5 0x8 0x0 0xe3 0x8>; | |
| linux,phandle = <0x7d>; | |
| phandle = <0x7d>; | |
| }; | |
| met_smi@14017000 { | |
| compatible = "mediatek,met_smi"; | |
| reg = <0x14017000 0x1000 0x14016000 0x1000 0x16010000 0x1000 0x15001000 0x1000 0x17001000 0x1000>; | |
| linux,phandle = <0x7e>; | |
| phandle = <0x7e>; | |
| }; | |
| gce@10217000 { | |
| compatible = "mediatek,gce"; | |
| reg = <0x10217000 0x1000>; | |
| interrupts = <0x0 0x97 0x8 0x0 0x94 0x8>; | |
| disp_mutex_reg = <0x14015000 0x1000>; | |
| g3d_config_base = <0x13000000 0x0 0xffff0000>; | |
| mmsys_config_base = <0x14000000 0x1 0xffff0000>; | |
| disp_dither_base = <0x14010000 0x2 0xffff0000>; | |
| mm_na_base = <0x14020000 0x3 0xffff0000>; | |
| imgsys_base = <0x15000000 0x4 0xffff0000>; | |
| vdec_gcon_base = <0x16000000 0x5 0xffff0000>; | |
| venc_gcon_base = <0x17000000 0x6 0xffff0000>; | |
| conn_peri_base = <0x18000000 0x7 0xffff0000>; | |
| topckgen_base = <0x10000000 0x8 0xffff0000>; | |
| kp_base = <0x10010000 0x9 0xffff0000>; | |
| scp_sram_base = <0x10020000 0xa 0xffff0000>; | |
| infra_na3_base = <0x10030000 0xb 0xffff0000>; | |
| infra_na4_base = <0x10040000 0xc 0xffff0000>; | |
| scp_base = <0x10050000 0xd 0xffff0000>; | |
| mcucfg_base = <0x10200000 0xe 0xffff0000>; | |
| gcpu_base = <0x10210000 0xf 0xffff0000>; | |
| usb0_base = <0x11200000 0x10 0xffff0000>; | |
| usb_sif_base = <0x11210000 0x11 0xffff0000>; | |
| audio_base = <0x11220000 0x12 0xffff0000>; | |
| msdc0_base = <0x11230000 0x13 0xffff0000>; | |
| msdc1_base = <0x11240000 0x14 0xffff0000>; | |
| msdc2_base = <0x11250000 0x15 0xffff0000>; | |
| msdc3_base = <0x11260000 0x16 0xffff0000>; | |
| pwm_sw_base = <0x1100e000 0x63 0xfffff000>; | |
| mdp_rdma0_sof = <0x0>; | |
| mdp_rsz0_sof = <0x1>; | |
| mdp_rsz1_sof = <0x2>; | |
| mdp_tdshp_sof = <0x3>; | |
| mdp_wdma_sof = <0x4>; | |
| mdp_wrot_sof = <0x5>; | |
| disp_ovl0_sof = <0x6>; | |
| disp_ovl1_sof = <0x7>; | |
| disp_rdma0_sof = <0x8>; | |
| disp_rdma1_sof = <0x9>; | |
| disp_wdma0_sof = <0xa>; | |
| disp_ccorr_sof = <0xb>; | |
| disp_color_sof = <0xc>; | |
| disp_aal_sof = <0xd>; | |
| disp_gamma_sof = <0xe>; | |
| disp_dither_sof = <0xf>; | |
| disp_pwm0_sof = <0x11>; | |
| disp_od_sof = <0x12>; | |
| mdp_rdma0_frame_done = <0x13>; | |
| mdp_rsz0_frame_done = <0x14>; | |
| mdp_rsz1_frame_done = <0x15>; | |
| mdp_tdshp_frame_done = <0x16>; | |
| mdp_wdma_frame_done = <0x17>; | |
| mdp_wrot_write_frame_done = <0x18>; | |
| mdp_wrot_read_frame_done = <0x19>; | |
| disp_ovl0_frame_done = <0x1a>; | |
| disp_ovl1_frame_done = <0x1b>; | |
| disp_rdma0_frame_done = <0x1c>; | |
| disp_rdma1_frame_done = <0x1d>; | |
| disp_wdma0_frame_done = <0x1e>; | |
| disp_ccorr_frame_done = <0x1f>; | |
| disp_color_frame_done = <0x20>; | |
| disp_aal_frame_done = <0x21>; | |
| disp_gamma_frame_done = <0x22>; | |
| disp_dither_frame_done = <0x23>; | |
| disp_od_frame_done = <0x25>; | |
| disp_dpi0_frame_done = <0x26>; | |
| disp_dsi0_frame_done = <0x27>; | |
| stream_done_0 = <0x28>; | |
| stream_done_1 = <0x29>; | |
| stream_done_2 = <0x2a>; | |
| stream_done_3 = <0x2b>; | |
| stream_done_4 = <0x2c>; | |
| stream_done_5 = <0x2d>; | |
| stream_done_6 = <0x2e>; | |
| stream_done_7 = <0x2f>; | |
| stream_done_8 = <0x30>; | |
| stream_done_9 = <0x31>; | |
| buf_underrun_event_0 = <0x32>; | |
| buf_underrun_event_1 = <0x33>; | |
| dsi0_te_event = <0x34>; | |
| isp_frame_done_p2_2 = <0x41>; | |
| isp_frame_done_p2_1 = <0x42>; | |
| isp_frame_done_p2_0 = <0x43>; | |
| isp_frame_done_p1_1 = <0x44>; | |
| isp_frame_done_p1_0 = <0x45>; | |
| camsv_2_pass1_done = <0x46>; | |
| camsv_1_pass1_done = <0x47>; | |
| seninf_cam1_2_3_fifo_full = <0x48>; | |
| seninf_cam0_fifo_full = <0x49>; | |
| venc_done = <0x81>; | |
| jpgenc_done = <0x82>; | |
| jpgdec_done = <0x83>; | |
| venc_mb_done = <0x84>; | |
| venc_128byte_cnt_done = <0x85>; | |
| apxgpt2_count = <0x10004028>; | |
| }; | |
| smi_larb0@14016000 { | |
| compatible = "mediatek,smi_larb0"; | |
| reg = <0x14016000 0x1000>; | |
| }; | |
| smi_larb1@16010000 { | |
| compatible = "mediatek,smi_larb1"; | |
| reg = <0x16010000 0x1000>; | |
| interrupts = <0x0 0xb1 0x8>; | |
| }; | |
| smi_larb2@15001000 { | |
| compatible = "mediatek,smi_larb2"; | |
| reg = <0x15001000 0x1000>; | |
| interrupts = <0x0 0xb2 0x8>; | |
| }; | |
| smi_larb3@17001000 { | |
| compatible = "mediatek,smi_larb3"; | |
| reg = <0x17001000 0x1000>; | |
| interrupts = <0x0 0xca 0x8>; | |
| }; | |
| smi_common@14017000 { | |
| compatible = "mediatek,smi_common"; | |
| reg = <0x14017000 0x1000 0x14016000 0x1000 0x16010000 0x1000 0x15001000 0x1000 0x17001000 0x1000>; | |
| clocks = <0x20 0x1 0x20 0x2 0x39 0x1 0x21 0x1 0x21 0x2 0x22 0x1 0x22 0x2 0x24 0x8 0x24 0x7 0x24 0x6 0x24 0x4>; | |
| clock-names = "smi-common", "smi-larb0", "img-larb2", "vdec0-vdec", "vdec1-larb", "venc-larb", "venc-venc", "mtcmos-ven", "mtcmos-vde", "mtcmos-isp", "mtcmos-dis"; | |
| }; | |
| ispsys@15000000 { | |
| compatible = "mediatek,mt6735-ispsys"; | |
| reg = <0x15004000 0x9000 0x1500d000 0x1000 0x15000000 0x10000 0x10215000 0x3000 0x10211000 0x1000>; | |
| interrupts = <0x0 0xb7 0x8 0x0 0xb8 0x8 0x0 0xb9 0x8 0x0 0xce 0x8 0x0 0xcf 0x8>; | |
| }; | |
| kd_camera_hw1@15008000 { | |
| compatible = "mediatek,camera_hw"; | |
| reg = <0x15008000 0x1000>; | |
| vcama-supply = <0x3a>; | |
| vcamd-supply = <0x3b>; | |
| vcamaf-supply = <0x3c>; | |
| vcamio-supply = <0x3d>; | |
| linux,phandle = <0x7f>; | |
| phandle = <0x7f>; | |
| }; | |
| kd_camera_hw2@15008000 { | |
| compatible = "mediatek,camera_hw2"; | |
| reg = <0x15008000 0x1000>; | |
| linux,phandle = <0x80>; | |
| phandle = <0x80>; | |
| }; | |
| SENINF_TOP@0x15008000 { | |
| compatible = "mediatek,SENINF_TOP"; | |
| reg = <0x15008000 0x1000>; | |
| interrupts = <0x0 0xb6 0x8>; | |
| }; | |
| fdvt@1500b000 { | |
| compatible = "mediatek,fdvt"; | |
| reg = <0x1500b000 0x1000>; | |
| interrupts = <0x0 0xd0 0x8>; | |
| clocks = <0x24 0x4 0x24 0x6 0x20 0x1 0x39 0x8>; | |
| clock-names = "FD-SCP_SYS_DIS", "FD-SCP_SYS_ISP", "FD-MM_DISP0_SMI_COMMON", "FD-IMG_IMAGE_FD"; | |
| }; | |
| mmsys_config@14000000 { | |
| compatible = "mediatek,mmsys_config"; | |
| reg = <0x14000000 0x1000>; | |
| interrupts = <0x0 0xcd 0x8>; | |
| }; | |
| mdp_rdma@14001000 { | |
| compatible = "mediatek,mdp_rdma"; | |
| reg = <0x14001000 0x1000>; | |
| interrupts = <0x0 0xbb 0x8>; | |
| }; | |
| mdp_rsz0@14002000 { | |
| compatible = "mediatek,mdp_rsz0"; | |
| reg = <0x14002000 0x1000>; | |
| interrupts = <0x0 0xbc 0x8>; | |
| }; | |
| mdp_rsz1@14003000 { | |
| compatible = "mediatek,mdp_rsz1"; | |
| reg = <0x14003000 0x1000>; | |
| interrupts = <0x0 0xbd 0x8>; | |
| }; | |
| mdp_wdma@14004000 { | |
| compatible = "mediatek,mdp_wdma"; | |
| reg = <0x14004000 0x1000>; | |
| interrupts = <0x0 0xbf 0x8>; | |
| }; | |
| mdp_wrot@14005000 { | |
| compatible = "mediatek,mdp_wrot"; | |
| reg = <0x14005000 0x1000>; | |
| interrupts = <0x0 0xc0 0x8>; | |
| }; | |
| mdp_tdshp@14006000 { | |
| compatible = "mediatek,mdp_tdshp"; | |
| reg = <0x14006000 0x1000>; | |
| interrupts = <0x0 0xbe 0x8>; | |
| }; | |
| hacc@10008000 { | |
| compatible = "mediatek,hacc"; | |
| reg = <0x10008000 0x1000>; | |
| interrupts = <0x0 0xae 0x8>; | |
| linux,phandle = <0x81>; | |
| phandle = <0x81>; | |
| }; | |
| als { | |
| compatible = "mediatek, als-eint"; | |
| linux,phandle = <0x82>; | |
| phandle = <0x82>; | |
| }; | |
| gse_1 { | |
| compatible = "mediatek, gse_1-eint"; | |
| status = "disabled"; | |
| linux,phandle = <0x83>; | |
| phandle = <0x83>; | |
| }; | |
| ext_buck_oc { | |
| compatible = "mediatek, ext_buck_oc-eint"; | |
| status = "disabled"; | |
| linux,phandle = <0x84>; | |
| phandle = <0x84>; | |
| }; | |
| swtp { | |
| compatible = "mediatek, swtp-eint"; | |
| linux,phandle = <0x85>; | |
| phandle = <0x85>; | |
| }; | |
| dsi_te { | |
| compatible = "mediatek, dsi_te_1-eint"; | |
| status = "disabled"; | |
| linux,phandle = <0x86>; | |
| phandle = <0x86>; | |
| }; | |
| }; | |
| vcorefs { | |
| compatible = "mediatek,mt6735-vcorefs"; | |
| clocks = <0x23 0x1 0x23 0x30 0x23 0x33>; | |
| clock-names = "mux_axi", "syspll_d5", "syspll1_d4"; | |
| }; | |
| bus { | |
| compatible = "simple-bus"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| ranges = <0x0 0x0 0x0 0xffffffff>; | |
| linux,phandle = <0x87>; | |
| phandle = <0x87>; | |
| eintc@10005000 { | |
| compatible = "mediatek,mt-eic"; | |
| reg = <0x10005000 0x1000>; | |
| interrupts = <0x0 0x99 0x4>; | |
| #interrupt-cells = <0x2>; | |
| interrupt-controller; | |
| mediatek,max_eint_num = <0xd5>; | |
| mediatek,mapping_table_entry = <0x0>; | |
| mediatek,max_deint_cnt = <0x4>; | |
| mediatek,deint_possible_irq = <0xbb 0xbc 0xbd 0xbe>; | |
| mediatek,debtime_setting_entry = <0xa>; | |
| mediatek,debtime_setting_array = <0x0 0x7d 0x1 0xfa 0x2 0x1f4 0x3 0x3e8 0x4 0x3e80 0x5 0x7d00 0x6 0xfa00 0x7 0x1f400 0x8 0x3e800 0x9 0x7d000>; | |
| linux,phandle = <0x3e>; | |
| phandle = <0x3e>; | |
| pmic@206 { | |
| compatible = "mediatek, pmic-eint"; | |
| interrupt-parent = <0x3e>; | |
| interrupts = <0xce 0x4>; | |
| debounce = <0xce 0x3e8>; | |
| }; | |
| }; | |
| SLEEP@0x10006000 { | |
| compatible = "mediatek,SLEEP"; | |
| reg = <0x10006000 0x1000>; | |
| interrupts = <0x0 0xa5 0x8 0x0 0xa6 0x8 0x0 0xa7 0x8 0x0 0xa8 0x8>; | |
| }; | |
| DEVAPC_AO@10007000 { | |
| compatible = "mediatek,DEVAPC_AO"; | |
| reg = <0x10007000 0x1000>; | |
| }; | |
| dma@11000000 { | |
| compatible = "mediatek,ap_dma"; | |
| reg = <0x11000000 0x1000>; | |
| interrupts = <0x0 0x72 0x8>; | |
| linux,phandle = <0x88>; | |
| phandle = <0x88>; | |
| }; | |
| i2c@11007000 { | |
| compatible = "mediatek,mt6753-i2c"; | |
| cell-index = <0x0>; | |
| reg = <0x11007000 0x1000>; | |
| interrupts = <0x0 0x54 0x8 0x0 0x62 0x8>; | |
| def_speed = <0x64>; | |
| linux,phandle = <0x89>; | |
| phandle = <0x89>; | |
| }; | |
| i2c@11008000 { | |
| compatible = "mediatek,mt6753-i2c"; | |
| cell-index = <0x1>; | |
| reg = <0x11008000 0x1000>; | |
| interrupts = <0x0 0x55 0x8 0x0 0x63 0x8>; | |
| def_speed = <0x64>; | |
| linux,phandle = <0x8a>; | |
| phandle = <0x8a>; | |
| }; | |
| i2c@11009000 { | |
| compatible = "mediatek,mt6753-i2c"; | |
| cell-index = <0x2>; | |
| reg = <0x11009000 0x1000>; | |
| interrupts = <0x0 0x56 0x8 0x0 0x64 0x8>; | |
| def_speed = <0x64>; | |
| linux,phandle = <0x8b>; | |
| phandle = <0x8b>; | |
| }; | |
| i2c@1100f000 { | |
| compatible = "mediatek,mt6753-i2c"; | |
| cell-index = <0x3>; | |
| reg = <0x1100f000 0x1000>; | |
| interrupts = <0x0 0x57 0x8 0x0 0x65 0x8>; | |
| def_speed = <0x64>; | |
| linux,phandle = <0x8c>; | |
| phandle = <0x8c>; | |
| }; | |
| i2c@11012000 { | |
| compatible = "mediatek,mt6753-i2c"; | |
| cell-index = <0x4>; | |
| reg = <0x11012000 0x1000>; | |
| interrupts = <0x0 0x58 0x8 0x0 0x66 0x8>; | |
| def_speed = <0x64>; | |
| linux,phandle = <0x8d>; | |
| phandle = <0x8d>; | |
| }; | |
| MCUCFG@0x10200000 { | |
| compatible = "mediatek,MCUCFG"; | |
| reg = <0x10200000 0x200>; | |
| interrupts = <0x0 0x47 0x4>; | |
| }; | |
| mcucfg@10200000 { | |
| compatible = "mediatek,mt6735-mcucfg"; | |
| reg = <0x10200000 0x200>; | |
| interrupts = <0x0 0x47 0x4>; | |
| linux,phandle = <0x8e>; | |
| phandle = <0x8e>; | |
| }; | |
| INFRACFG_AO@0x10000000 { | |
| compatible = "mediatek,INFRACFG_AO"; | |
| reg = <0x10000000 0x1000>; | |
| }; | |
| CKSYS@0x10210000 { | |
| compatible = "mediatek,CKSYS"; | |
| reg = <0x10210000 0x1000>; | |
| }; | |
| PERICFG@0x10002000 { | |
| compatible = "mediatek,PERICFG"; | |
| reg = <0x10002000 0x1000>; | |
| }; | |
| bat_meter { | |
| compatible = "mediatek,bat_meter"; | |
| linux,phandle = <0x8f>; | |
| phandle = <0x8f>; | |
| }; | |
| bat_notify { | |
| compatible = "mediatek,bat_notify"; | |
| linux,phandle = <0x90>; | |
| phandle = <0x90>; | |
| }; | |
| bat_comm { | |
| compatible = "mediatek,battery"; | |
| linux,phandle = <0x91>; | |
| phandle = <0x91>; | |
| }; | |
| FHCTL@0x10209F00 { | |
| compatible = "mediatek,FHCTL"; | |
| reg = <0x10209f00 0x100>; | |
| }; | |
| gcpu@10216000 { | |
| compatible = "mediatek,gcpu"; | |
| reg = <0x10216000 0x1000>; | |
| interrupts = <0x0 0x96 0x8>; | |
| }; | |
| cqdma@10217c00 { | |
| compatible = "mediatek,cqdma"; | |
| reg = <0x10217c00 0xc00>; | |
| interrupts = <0x0 0x8f 0x8>; | |
| nr_channel = <0x1>; | |
| }; | |
| EMI@0x10203000 { | |
| compatible = "mediatek,EMI"; | |
| reg = <0x10203000 0x1000>; | |
| interrupts = <0x0 0x88 0x4>; | |
| }; | |
| m4u@10205000 { | |
| cell-index = <0x0>; | |
| compatible = "mediatek,m4u"; | |
| reg = <0x10205000 0x1000>; | |
| interrupts = <0x0 0x92 0x8>; | |
| clocks = <0xd 0x9 0x20 0x1 0x20 0x2 0x21 0x1 0x21 0x2 0x39 0x1 0x22 0x2 0x22 0x1 0x24 0x4 0x24 0x7 0x24 0x6 0x24 0x8>; | |
| clock-names = "infra_m4u", "smi_common", "m4u_disp0_smi_larb0", "m4u_vdec0_vdec", "m4u_vdec1_larb", "m4u_img_image_larb2_smi", "m4u_venc_venc", "m4u_venc_larb", "mtcmos-dis", "mtcmos-vde", "mtcmos-isp", "mtcmos-ven"; | |
| }; | |
| ccci_off@0 { | |
| compatible = "mediatek,ccci_off"; | |
| clocks = <0x24 0x1>; | |
| clock-names = "scp-sys-md1-main"; | |
| }; | |
| mdcldma@1000A000 { | |
| compatible = "mediatek,mdcldma"; | |
| reg = <0x1000a000 0x1000 0x1000b000 0x1000 0x1021a000 0x1000 0x1021b000 0x1000 0x1020a000 0x1000 0x1020b000 0x1000>; | |
| interrupts = <0x0 0x91 0x4 0x0 0x8c 0x8 0x0 0xdf 0x2>; | |
| mediatek,md_id = <0x0>; | |
| mediatek,cldma_capability = <0x2>; | |
| mediatek,md_smem_size = <0x10000>; | |
| pinctrl-names = "default", "vsram_output_low", "vsram_output_high", "RFIC0_01_mode", "RFIC0_04_mode"; | |
| pinctrl-0 = <0x3f>; | |
| pinctrl-1 = <0x40>; | |
| pinctrl-2 = <0x41>; | |
| pinctrl-3 = <0x42>; | |
| pinctrl-4 = <0x43>; | |
| linux,phandle = <0x92>; | |
| phandle = <0x92>; | |
| }; | |
| mdc2k@3a00b01c { | |
| compatible = "mediatek,mdc2k"; | |
| reg = <0x3a00b01c 0x10 0x1021c800 0x300 0x1021d800 0x300>; | |
| interrupts = <0x0 0xdd 0x2>; | |
| clocks = <0x24 0x2>; | |
| clock-names = "scp-sys-md2-main"; | |
| }; | |
| c2k_sdio@0 { | |
| compatible = "mediatek,mt6735-c2k_sdio"; | |
| interrupts = <0x0 0xde 0x8>; | |
| }; | |
| dbgapb_base@1011A000 { | |
| compatible = "mediatek,dbgapb_base"; | |
| reg = <0x1011a000 0x100>; | |
| }; | |
| simswitch@0 { | |
| compatible = "mediatek,sim_switch"; | |
| pinctrl-names = "default", "hot_plug_mode1", "hot_plug_mode2", "two_sims_bound_to_md1", "sim1_md3_sim2_md1"; | |
| pinctrl-0 = <0x44>; | |
| pinctrl-1 = <0x45>; | |
| pinctrl-2 = <0x46>; | |
| pinctrl-3 = <0x47>; | |
| pinctrl-4 = <0x48>; | |
| linux,phandle = <0x93>; | |
| phandle = <0x93>; | |
| }; | |
| EFUSEC@10206000 { | |
| compatible = "mediatek,EFUSEC"; | |
| reg = <0x10206000 0x1000>; | |
| }; | |
| DEVAPC@10207000 { | |
| compatible = "mediatek,DEVAPC"; | |
| reg = <0x10207000 0x1000>; | |
| interrupts = <0x0 0x86 0x8>; | |
| }; | |
| bus_dbg@10208000 { | |
| compatible = "mediatek,bus_dbg-v1"; | |
| reg = <0x10208000 0x1000>; | |
| interrupts = <0x0 0x89 0x8>; | |
| }; | |
| APMIXED@0x10209000 { | |
| compatible = "mediatek,APMIXED"; | |
| reg = <0x10209000 0x1000>; | |
| }; | |
| dispsys@14007000 { | |
| compatible = "mediatek,dispsys"; | |
| reg = <0x14007000 0x1000 0x14008000 0x1000 0x14009000 0x1000 0x1400a000 0x1000 0x1400b000 0x1000 0x1400c000 0x1000 0x1400d000 0x1000 0x1400e000 0x1000 0x1400f000 0x1000 0x14010000 0x1000 0x0 0x0 0x1100e000 0x1000 0x0 0x0 0x14015000 0x1000 0x14013000 0x1000 0x14014000 0x1000 0x14000000 0x1000 0x14016000 0x1000 0x14017000 0x1000 0x14018000 0x1000 0x10206000 0x1000 0x10210000 0x1000 0x10211a70 0xc 0x10211974 0xc 0x10211b70 0xc 0x10206044 0xc 0x10206514 0xc 0x10206558 0xc 0x102100a0 0x1000 0x10209260 0x1000 0x10209264 0x1000 0x14012000 0x1000 0x10209000 0x1000>; | |
| interrupts = <0x0 0xc1 0x8 0x0 0xd3 0x8 0x0 0xc2 0x8 0x0 0xc3 0x8 0x0 0xc4 0x8 0x0 0xc5 0x8 0x0 0xc6 0x8 0x0 0xc7 0x8 0x0 0xc8 0x8 0x0 0xc9 0x8 0x0 0x0 0x8 0x0 0x75 0x8 0x0 0x0 0x8 0x0 0xba 0x8 0x0 0xcb 0x8 0x0 0xcc 0x8 0x0 0xcd 0x8 0x0 0xb0 0x8 0x0 0x0 0x8 0x0 0x0 0x8 0x0 0x0 0x8 0x0 0x0 0x8 0x0 0x0 0x8 0x0 0x0 0x8 0x0 0x0 0x8 0x0 0x0 0x8 0x0 0x0 0x8 0x0 0x0 0x8 0x0 0x0 0x8 0x0 0x0 0x8 0x0 0x0 0x8 0x0 0xd2 0x8 0x0 0x0 0x8>; | |
| }; | |
| mhl@0 { | |
| compatible = "mediatek,extd_dev"; | |
| linux,phandle = <0x94>; | |
| phandle = <0x94>; | |
| }; | |
| lcm { | |
| compatible = "mediatek,mt6753p1_64-lcm"; | |
| linux,phandle = <0x95>; | |
| phandle = <0x95>; | |
| }; | |
| lcm_mode { | |
| compatible = "mediatek,lcm_mode"; | |
| linux,phandle = <0x96>; | |
| phandle = <0x96>; | |
| }; | |
| cpu_dbgapb { | |
| compatible = "mediatek,hw_dbg"; | |
| num = <0x8>; | |
| reg = <0x10810000 0x1000 0x10910000 0x1000 0x10a10000 0x1000 0x10b10000 0x1000 0x10c10000 0x1000 0x10d10000 0x1000 0x10e10000 0x1000 0x10f10000 0x1000>; | |
| linux,phandle = <0x97>; | |
| phandle = <0x97>; | |
| }; | |
| syscfg_pctl_a { | |
| compatible = "mediatek,mt6735-pctl-a-syscfg", "syscon"; | |
| reg = <0x0 0x9bceb8 0x0 0x3e8>; | |
| linux,phandle = <0x49>; | |
| phandle = <0x49>; | |
| }; | |
| pinctrl { | |
| compatible = "mediatek,mt6735-pinctrl"; | |
| reg = <0x0 0x9bceb8 0x0 0x3e8>; | |
| mediatek,pctl-regmap = <0x49>; | |
| pins-are-numbered; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| linux,phandle = <0x98>; | |
| phandle = <0x98>; | |
| uart0gpiodefault { | |
| linux,phandle = <0x25>; | |
| phandle = <0x25>; | |
| }; | |
| uart0_rx_set { | |
| linux,phandle = <0x26>; | |
| phandle = <0x26>; | |
| pins_cmd_dat { | |
| pinmux = <0x4a01>; | |
| }; | |
| }; | |
| uart0_rx_clear { | |
| linux,phandle = <0x27>; | |
| phandle = <0x27>; | |
| pins_cmd_dat { | |
| pinmux = <0x4a00>; | |
| slew-rate = <0x1>; | |
| output-high; | |
| }; | |
| }; | |
| uart0_tx_set { | |
| linux,phandle = <0x28>; | |
| phandle = <0x28>; | |
| pins_cmd_dat { | |
| pinmux = <0x4b01>; | |
| }; | |
| }; | |
| uart0_tx_clear { | |
| linux,phandle = <0x29>; | |
| phandle = <0x29>; | |
| pins_cmd_dat { | |
| pinmux = <0x4b00>; | |
| slew-rate = <0x1>; | |
| output-high; | |
| }; | |
| }; | |
| uart1gpiodefault { | |
| linux,phandle = <0x2a>; | |
| phandle = <0x2a>; | |
| }; | |
| uart1_rx_set { | |
| linux,phandle = <0x2b>; | |
| phandle = <0x2b>; | |
| pins_cmd_dat { | |
| pinmux = <0x4c01>; | |
| }; | |
| }; | |
| uart1_rx_clear { | |
| linux,phandle = <0x2c>; | |
| phandle = <0x2c>; | |
| pins_cmd_dat { | |
| pinmux = <0x4c00>; | |
| slew-rate = <0x1>; | |
| output-high; | |
| }; | |
| }; | |
| uart1_tx_set { | |
| linux,phandle = <0x2d>; | |
| phandle = <0x2d>; | |
| pins_cmd_dat { | |
| pinmux = <0x4d01>; | |
| }; | |
| }; | |
| uart1_tx_clear { | |
| linux,phandle = <0x2e>; | |
| phandle = <0x2e>; | |
| pins_cmd_dat { | |
| pinmux = <0x4d00>; | |
| slew-rate = <0x1>; | |
| output-high; | |
| }; | |
| }; | |
| uart2gpiodefault { | |
| linux,phandle = <0x2f>; | |
| phandle = <0x2f>; | |
| }; | |
| uart2_rx_set { | |
| linux,phandle = <0x30>; | |
| phandle = <0x30>; | |
| pins_cmd_dat { | |
| pinmux = <0x3901>; | |
| }; | |
| }; | |
| uart2_rx_clear { | |
| linux,phandle = <0x31>; | |
| phandle = <0x31>; | |
| pins_cmd_dat { | |
| pinmux = <0x3900>; | |
| slew-rate = <0x1>; | |
| output-high; | |
| }; | |
| }; | |
| uart2_tx_set { | |
| linux,phandle = <0x32>; | |
| phandle = <0x32>; | |
| pins_cmd_dat { | |
| pins = <0x3a01>; | |
| }; | |
| }; | |
| uart2_tx_clear { | |
| linux,phandle = <0x33>; | |
| phandle = <0x33>; | |
| pins_cmd_dat { | |
| pinmux = <0x3a00>; | |
| slew-rate = <0x1>; | |
| output-high; | |
| }; | |
| }; | |
| uart3gpiodefault { | |
| linux,phandle = <0x34>; | |
| phandle = <0x34>; | |
| }; | |
| uart3_rx_set { | |
| linux,phandle = <0x35>; | |
| phandle = <0x35>; | |
| pins_cmd_dat { | |
| pinmux = <0x3b01>; | |
| }; | |
| }; | |
| uart3_rx_clear { | |
| linux,phandle = <0x36>; | |
| phandle = <0x36>; | |
| pins_cmd_dat { | |
| pinmux = <0x3b00>; | |
| slew-rate = <0x1>; | |
| output-high; | |
| }; | |
| }; | |
| uart3_tx_set { | |
| linux,phandle = <0x37>; | |
| phandle = <0x37>; | |
| pins_cmd_dat { | |
| pinmux = <0x3c01>; | |
| }; | |
| }; | |
| uart3_tx_clear { | |
| linux,phandle = <0x38>; | |
| phandle = <0x38>; | |
| pins_cmd_dat { | |
| pinmux = <0x3c00>; | |
| slew-rate = <0x1>; | |
| output-high; | |
| }; | |
| }; | |
| ssw0default { | |
| linux,phandle = <0x44>; | |
| phandle = <0x44>; | |
| }; | |
| ssw@1 { | |
| linux,phandle = <0x45>; | |
| phandle = <0x45>; | |
| pins_cmd0_dat { | |
| pins = <0x805>; | |
| }; | |
| pins_cmd1_dat { | |
| pins = <0x904>; | |
| }; | |
| }; | |
| ssw@2 { | |
| linux,phandle = <0x46>; | |
| phandle = <0x46>; | |
| pins_cmd0_dat { | |
| pins = <0x802>; | |
| }; | |
| pins_cmd1_dat { | |
| pins = <0x904>; | |
| }; | |
| }; | |
| ssw@3 { | |
| linux,phandle = <0x47>; | |
| phandle = <0x47>; | |
| pins_cmd0_dat { | |
| pins = <0xa301>; | |
| slew-rate = <0x1>; | |
| }; | |
| pins_cmd1_dat { | |
| pins = <0xa401>; | |
| slew-rate = <0x1>; | |
| }; | |
| pins_cmd2_dat { | |
| pins = <0xa501>; | |
| slew-rate = <0x0>; | |
| bias-pull-up = <0x0>; | |
| }; | |
| pins_cmd3_dat { | |
| pins = <0xa001>; | |
| slew-rate = <0x1>; | |
| }; | |
| pins_cmd4_dat { | |
| pins = <0xa101>; | |
| slew-rate = <0x1>; | |
| }; | |
| pins_cmd5_dat { | |
| pins = <0xa201>; | |
| slew-rate = <0x0>; | |
| bias-pull-up = <0x0>; | |
| }; | |
| }; | |
| ssw@4 { | |
| linux,phandle = <0x48>; | |
| phandle = <0x48>; | |
| pins_cmd0_dat { | |
| pins = <0xa304>; | |
| }; | |
| pins_cmd1_dat { | |
| pins = <0xa404>; | |
| }; | |
| pins_cmd2_dat { | |
| pins = <0xa504>; | |
| }; | |
| pins_cmd3_dat { | |
| pins = <0xa001>; | |
| }; | |
| pins_cmd4_dat { | |
| pins = <0xa101>; | |
| }; | |
| pins_cmd5_dat { | |
| pins = <0xa201>; | |
| }; | |
| }; | |
| vsram0default { | |
| linux,phandle = <0x3f>; | |
| phandle = <0x3f>; | |
| }; | |
| vsram@1 { | |
| linux,phandle = <0x40>; | |
| phandle = <0x40>; | |
| pins_cmd_dat { | |
| pins = <0x8c00>; | |
| slew-rate = <0x1>; | |
| output-low; | |
| }; | |
| }; | |
| vsram@2 { | |
| linux,phandle = <0x41>; | |
| phandle = <0x41>; | |
| pins_cmd_dat { | |
| pins = <0x8c00>; | |
| slew-rate = <0x1>; | |
| output-high; | |
| }; | |
| }; | |
| clockbuf@1 { | |
| linux,phandle = <0x42>; | |
| phandle = <0x42>; | |
| pins_cmd0_dat { | |
| pins = <0x6e01>; | |
| }; | |
| pins_cmd1_dat { | |
| pins = <0x6f01>; | |
| }; | |
| pins_cmd2_dat { | |
| pins = <0x7001>; | |
| }; | |
| pins_cmd3_dat { | |
| pins = <0x7101>; | |
| }; | |
| pins_cmd4_dat { | |
| pins = <0x7201>; | |
| }; | |
| }; | |
| clockbuf@2 { | |
| linux,phandle = <0x43>; | |
| phandle = <0x43>; | |
| pins_cmd0_dat { | |
| pins = <0x6e04>; | |
| }; | |
| pins_cmd1_dat { | |
| pins = <0x6f04>; | |
| }; | |
| pins_cmd2_dat { | |
| pins = <0x7004>; | |
| }; | |
| pins_cmd3_dat { | |
| pins = <0x7104>; | |
| }; | |
| pins_cmd4_dat { | |
| pins = <0x7204>; | |
| }; | |
| }; | |
| }; | |
| nfc@0 { | |
| compatible = "mediatek,nfc-gpio-v2"; | |
| gpio-ven = <0x4>; | |
| gpio-rst = <0x3>; | |
| gpio-eint = <0x1>; | |
| gpio-irq = <0x2>; | |
| linux,phandle = <0x99>; | |
| phandle = <0x99>; | |
| }; | |
| btcvsd@10000000 { | |
| compatible = "mediatek,audio_bt_cvsd"; | |
| offset = <0x700 0x800 0xfd0 0xfd4 0xfd8>; | |
| reg = <0x10000000 0x1000 0x18000000 0x10000 0x18080000 0x8000>; | |
| interrupts = <0x0 0xe6 0x8>; | |
| }; | |
| gps { | |
| compatible = "mediatek,gps"; | |
| }; | |
| wifi@180F0000 { | |
| compatible = "mediatek,wifi"; | |
| reg = <0x180f0000 0x5c>; | |
| interrupts = <0x0 0xe4 0x8>; | |
| }; | |
| usb20@11200000 { | |
| compatible = "mediatek,mt6735-usb20"; | |
| cell-index = <0x0>; | |
| reg = <0x11200000 0x10000 0x11210000 0x10000>; | |
| interrupts = <0x0 0x48 0x8>; | |
| mode = <0x2>; | |
| multipoint = <0x1>; | |
| dyn_fifo = <0x1>; | |
| soft_con = <0x1>; | |
| dma = <0x1>; | |
| num_eps = <0x10>; | |
| dma_channels = <0x8>; | |
| clocks = <0x2 0xb>; | |
| clock-names = "usb0"; | |
| VUSB33-supply = <0x4a>; | |
| iddig_gpio = <0x0 0x1>; | |
| drvvbus_gpio = <0x53 0x2>; | |
| linux,phandle = <0x9a>; | |
| phandle = <0x9a>; | |
| }; | |
| audio@11220000 { | |
| compatible = "mediatek,audio"; | |
| reg = <0x11220000 0x10000>; | |
| interrupts = <0x0 0x90 0x8>; | |
| }; | |
| mt_soc_dl1_pcm@11220000 { | |
| compatible = "mediatek,mt-soc-dl1-pcm"; | |
| reg = <0x11220000 0x1000>; | |
| interrupts = <0x0 0x90 0x8>; | |
| audclk-gpio = <0x8f 0x0>; | |
| audmiso-gpio = <0x90 0x0>; | |
| audmosi-gpio = <0x91 0x0>; | |
| vowclk-gpio = <0x94 0x0>; | |
| extspkamp-gpio = <0x75 0x0>; | |
| i2s1clk-gpio = <0x50 0x0>; | |
| i2s1dat-gpio = <0x4e 0x0>; | |
| i2s1mclk-gpio = <0x9 0x0>; | |
| i2s1ws-gpio = <0x4f 0x0>; | |
| }; | |
| mt_soc_ul1_pcm { | |
| compatible = "mediatek,mt_soc_pcm_capture"; | |
| }; | |
| mt_soc_voice_md1 { | |
| compatible = "mediatek,mt_soc_pcm_voice_md1"; | |
| }; | |
| mt_soc_hdmi_pcm { | |
| compatible = "mediatek,mt_soc_pcm_hdmi"; | |
| }; | |
| mt_soc_uldlloopback_pcm { | |
| compatible = "mediatek,mt_soc_pcm_uldlloopback"; | |
| }; | |
| mt_soc_i2s0_pcm { | |
| compatible = "mediatek,mt_soc_pcm_dl1_i2s0"; | |
| }; | |
| mt_soc_mrgrx_pcm { | |
| compatible = "mediatek,mt_soc_pcm_mrgrx"; | |
| }; | |
| mt_soc_mrgrx_awb_pcm { | |
| compatible = "mediatek,mt_soc_pcm_mrgrx_awb"; | |
| }; | |
| mt_soc_fm_i2s_pcm { | |
| compatible = "mediatek,mt_soc_pcm_fm_i2s"; | |
| }; | |
| mt_soc_fm_i2s_awb_pcm { | |
| compatible = "mediatek,mt_soc_pcm_fm_i2s_awb"; | |
| }; | |
| mt_soc_i2s0dl1_pcm { | |
| compatible = "mediatek,mt_soc_pcm_dl1_i2s0Dl1"; | |
| }; | |
| mt_soc_deep_buffer_dl_pcm { | |
| compatible = "mediatek,mt_soc_pcm_deep_buffer_dl"; | |
| }; | |
| mt_soc_dl1_awb_pcm { | |
| compatible = "mediatek,mt_soc_pcm_dl1_awb"; | |
| }; | |
| mt_soc_voice_md1_bt { | |
| compatible = "mediatek,mt_soc_pcm_voice_md1_bt"; | |
| }; | |
| mt_soc_voip_bt_out { | |
| compatible = "mediatek,mt_soc_pcm_dl1_bt"; | |
| }; | |
| mt_soc_voip_bt_in { | |
| compatible = "mediatek,mt_soc_pcm_bt_dai"; | |
| }; | |
| mt_soc_tdmrx_pcm { | |
| compatible = "mediatek,mt_soc_tdm_capture"; | |
| }; | |
| mt_soc_fm_mrgtx_pcm { | |
| compatible = "mediatek,mt_soc_pcm_fmtx"; | |
| }; | |
| mt_soc_ul2_pcm { | |
| compatible = "mediatek,mt_soc_pcm_capture2"; | |
| }; | |
| mt_soc_i2s0_awb_pcm { | |
| compatible = "mediatek,mt_soc_pcm_i2s0_awb"; | |
| }; | |
| mt_soc_voice_md2 { | |
| compatible = "mediatek,mt_soc_pcm_voice_md2"; | |
| }; | |
| mt_soc_routing_pcm { | |
| compatible = "mediatek,mt_soc_pcm_routing"; | |
| i2s1clk-gpio = <0x7 0x6>; | |
| i2s1dat-gpio = <0x5 0x6>; | |
| i2s1mclk-gpio = <0x9 0x6>; | |
| i2s1ws-gpio = <0x6 0x6>; | |
| }; | |
| mt_soc_voice_md2_bt { | |
| compatible = "mediatek,mt_soc_pcm_voice_md2_bt"; | |
| }; | |
| mt_soc_hp_impedance_pcm { | |
| compatible = "mediatek,Mt_soc_pcm_hp_impedance"; | |
| }; | |
| mt_soc_codec_name { | |
| compatible = "mediatek,mt_soc_codec_63xx"; | |
| }; | |
| mt_soc_dummy_pcm { | |
| compatible = "mediatek,mt_soc_pcm_dummy"; | |
| }; | |
| mt_soc_codec_dummy_name { | |
| compatible = "mediatek,mt_soc_codec_dummy"; | |
| }; | |
| mt_soc_routing_dai_name { | |
| compatible = "mediatek,mt_soc_dai_routing"; | |
| }; | |
| mt_soc_dai_name { | |
| compatible = "mediatek,mt_soc_dai_stub"; | |
| }; | |
| mt_soc_offload_gdma { | |
| compatible = "mediatek,mt_soc_pcm_offload_gdma"; | |
| }; | |
| mt_soc_dl2_pcm { | |
| compatible = "mediatek,mt_soc_pcm_dl2"; | |
| }; | |
| pwrap { | |
| compatible = "mediatek,PWRAP"; | |
| reg = <0x10001000 0x1000>; | |
| interrupts = <0x0 0xa3 0x4>; | |
| }; | |
| touch@ { | |
| compatible = "mediatek,mt6735-touch", "mediatek,mt6735m-touch", "mediatek,mt6753-touch"; | |
| vtouch-supply = <0x4b>; | |
| linux,phandle = <0x9b>; | |
| phandle = <0x9b>; | |
| }; | |
| accdet@ { | |
| compatible = "mediatek,mt6735-accdet", "mediatek,mt6735m-accdet", "mediatek,mt6753-accdet"; | |
| linux,phandle = <0x9c>; | |
| phandle = <0x9c>; | |
| }; | |
| G3D_CONFIG@0x13000000 { | |
| compatible = "mediatek,G3D_CONFIG"; | |
| reg = <0x13000000 0x1000>; | |
| }; | |
| MALI@0x13040000 { | |
| compatible = "arm,malit720", "arm,mali-t72x", "arm,malit7xx", "arm,mali-midgard"; | |
| reg = <0x13040000 0x4000>; | |
| interrupts = <0x0 0xd6 0x8 0x0 0xd5 0x8 0x0 0xd4 0x8>; | |
| interrupt-names = "JOB", "MMU", "GPU"; | |
| clock-frequency = <0x1ad27480>; | |
| clocks = <0x4c 0x1 0x20 0x1 0x24 0x5 0x24 0x4>; | |
| clock-names = "mfg-main", "mfg-smi-common", "mtcmos-mfg", "mtcmos-display"; | |
| }; | |
| pwm@11006000 { | |
| compatible = "mediatek,pwm"; | |
| reg = <0x11006000 0x1000>; | |
| interrupts = <0x0 0x4d 0x8>; | |
| linux,phandle = <0x9d>; | |
| phandle = <0x9d>; | |
| }; | |
| }; | |
| rf_clock_buffer { | |
| compatible = "mediatek,rf_clock_buffer"; | |
| mediatek,clkbuf-quantity = <0x4>; | |
| mediatek,clkbuf-config = <0x2 0x1 0x1 0x1>; | |
| linux,phandle = <0x9e>; | |
| phandle = <0x9e>; | |
| }; | |
| hwmsensor@0 { | |
| compatible = "mediatek,hwmsensor"; | |
| }; | |
| gsensor@0 { | |
| compatible = "mediatek,gsensor"; | |
| }; | |
| als_ps@0 { | |
| compatible = "mediatek,als_ps"; | |
| linux,phandle = <0x9f>; | |
| phandle = <0x9f>; | |
| }; | |
| m_acc_pl@0 { | |
| compatible = "mediatek,m_acc_pl"; | |
| }; | |
| m_alsps_pl@0 { | |
| compatible = "mediatek,m_alsps_pl"; | |
| }; | |
| m_batch_pl@0 { | |
| compatible = "mediatek,m_batch_pl"; | |
| }; | |
| batchsensor@0 { | |
| compatible = "mediatek,batchsensor"; | |
| }; | |
| gyroscope@0 { | |
| compatible = "mediatek,gyroscope"; | |
| linux,phandle = <0xa0>; | |
| phandle = <0xa0>; | |
| }; | |
| m_gyro_pl@0 { | |
| compatible = "mediatek,m_gyro_pl"; | |
| }; | |
| barometer@0 { | |
| compatible = "mediatek,barometer"; | |
| }; | |
| m_baro_pl@0 { | |
| compatible = "mediatek,m_baro_pl"; | |
| }; | |
| msensor@0 { | |
| compatible = "mediatek,msensor"; | |
| }; | |
| m_mag_pl@0 { | |
| compatible = "mediatek,m_mag_pl"; | |
| }; | |
| orientation@0 { | |
| compatible = "mediatek,orientation"; | |
| }; | |
| irq_nfc { | |
| compatible = "mediatek,irq_nfc-eint"; | |
| status = "disabled"; | |
| linux,phandle = <0xa1>; | |
| phandle = <0xa1>; | |
| }; | |
| mt8193ckgen@0 { | |
| compatible = "mediatek,mt8193-ckgen"; | |
| }; | |
| multibridge@0 { | |
| compatible = "mediatek,multibridge"; | |
| }; | |
| firmware { | |
| android { | |
| compatible = "android,firmware"; | |
| fstab { | |
| compatible = "android,fstab"; | |
| system { | |
| compatible = "android,system"; | |
| dev = "/dev/block/platform/mtk-msdc.0/11230000.msdc0/by-name/system"; | |
| type = "ext4"; | |
| mnt_flags = "ro"; | |
| fsmgr_flags = "wait,verify"; | |
| }; | |
| vendor { | |
| compatible = "android,vendor"; | |
| dev = "/dev/block/platform/mtk-msdc.0/11230000.msdc0/by-name/vendor"; | |
| type = "ext4"; | |
| mnt_flags = "ro"; | |
| fsmgr_flags = "wait,verify"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| odm { | |
| compatible = "simple-bus"; | |
| linux,phandle = <0xa2>; | |
| phandle = <0xa2>; | |
| }; | |
| trusty { | |
| compatible = "android,trusty-smc-v1"; | |
| ranges; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x2>; | |
| irq { | |
| compatible = "android,trusty-irq-v1"; | |
| ppi-interrupt-parent = <0x1>; | |
| }; | |
| log { | |
| compatible = "android,trusty-log-v1"; | |
| }; | |
| virtio { | |
| compatible = "android,trusty-virtio-v1"; | |
| }; | |
| mtee { | |
| compatible = "mediatek,trusty-mtee-v1"; | |
| }; | |
| }; | |
| __symbols__ { | |
| chosen = "/chosen"; | |
| mmc0 = "/mtk-msdc.0/msdc0@11230000"; | |
| mmc1 = "/mtk-msdc.0/msdc1@11240000"; | |
| mmc2 = "/mtk-msdc.0/msdc2@11250000"; | |
| mmc3 = "/mtk-msdc.0/msdc3@11260000"; | |
| msdc1_ins = "/mtk-msdc.0/default"; | |
| cpus = "/cpus"; | |
| cpu0 = "/cpus/cpu@000"; | |
| cpu1 = "/cpus/cpu@001"; | |
| cpu2 = "/cpus/cpu@002"; | |
| cpu3 = "/cpus/cpu@003"; | |
| cpu4 = "/cpus/cpu@100"; | |
| cpu5 = "/cpus/cpu@101"; | |
| cpu6 = "/cpus/cpu@102"; | |
| cpu7 = "/cpus/cpu@103"; | |
| cpu_sleep_0_0 = "/cpus/idle-states/cpu-sleep-0-0"; | |
| cluster_sleep_0 = "/cpus/idle-states/cluster-sleep-0"; | |
| reserved_memory = "/reserved-memory"; | |
| gic = "/interrupt-controller@10220000"; | |
| clk_null = "/clocks/clk_null"; | |
| clk26m = "/clocks/clk26m"; | |
| clk32k = "/clocks/clk32k"; | |
| soc = "/soc"; | |
| topckgen = "/soc/topckgen@0x10210000"; | |
| infrasys = "/soc/infrasys@0x10000000"; | |
| perisys = "/soc/perisys@0x10002000"; | |
| gpio_usage_mapping = "/soc/gpio"; | |
| gpio = "/soc/gpio@10211000"; | |
| dramc_nao = "/soc/dramc_nao@1020e000"; | |
| ddrphy = "/soc/ddrphy@10213000"; | |
| dramc = "/soc/dramc@10214000"; | |
| cpuxgpt = "/soc/cpuxgpt@10200000"; | |
| apxgpt = "/soc/apxgpt@10004000"; | |
| mt_pmic_vpa_buck_reg = "/soc/mt_pmic_regulator/buck_regulators/buck_vpa"; | |
| mt_pmic_vproc_buck_reg = "/soc/mt_pmic_regulator/buck_regulators/buck_vproc"; | |
| mt_pmic_vcore1_buck_reg = "/soc/mt_pmic_regulator/buck_regulators/buck_vcore1"; | |
| mt_pmic_vsys22_buck_reg = "/soc/mt_pmic_regulator/buck_regulators/buck_vsys22"; | |
| mt_pmic_vlte_buck_reg = "/soc/mt_pmic_regulator/buck_regulators/buck_vlte"; | |
| mt_pmic_vaux18_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vaux18"; | |
| mt_pmic_vtcxo_0_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vtcxo_0"; | |
| mt_pmic_vtcxo_1_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vtcxo_1"; | |
| mt_pmic_vaud28_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vaud28"; | |
| mt_pmic_vcn28_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vcn28"; | |
| mt_pmic_vcama_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vcama"; | |
| mt_pmic_vcn33_bt_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vcn33_bt"; | |
| mt_pmic_vcn33_wifi_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vcn33_wifi"; | |
| mt_pmic_vusb33_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vusb33"; | |
| mt_pmic_vefuse_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vefuse"; | |
| mt_pmic_vsim1_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vsim1"; | |
| mt_pmic_vsim2_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vsim2"; | |
| mt_pmic_vemc33_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vemc_3v3"; | |
| mt_pmic_vmch_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vmch"; | |
| mt_pmic_vtref_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vtref"; | |
| mt_pmic_vmc_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vmc"; | |
| mt_pmic_vcam_af_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vcamaf"; | |
| mt_pmic_vio28_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vio28"; | |
| mt_pmic_vgp1_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vgp1"; | |
| mt_pmic_vibr_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vibr"; | |
| mt_pmic_vcamd_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vcamd"; | |
| mt_pmic_vrf18_0_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vrf18_0"; | |
| mt_pmic_vrf18_1_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vrf18_1"; | |
| mt_pmic_vio18_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vio18"; | |
| mt_pmic_vcn18_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vcn18"; | |
| mt_pmic_vcam_io_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vcamio"; | |
| mt_pmic_vsram_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vsram"; | |
| mt_pmic_vm_ldo_reg = "/soc/mt_pmic_regulator/ldo_regulators/ldo_vm"; | |
| sys_cirq = "/soc/sys_cirq@10204000"; | |
| apmixedsys = "/soc/apmixedsys@0x10209000"; | |
| toprgu = "/soc/toprgu@10212000"; | |
| auxadc = "/soc/adc_hw@11001000"; | |
| audiosys = "/soc/audiosys@11220000"; | |
| mfgsys = "/soc/mfgsys@13000000"; | |
| mmsys = "/soc/mmsys@14000000"; | |
| imgsys = "/soc/imgsys@15000000"; | |
| vdecsys = "/soc/vdecsys@16000000"; | |
| vencsys = "/soc/vencsys@17000000"; | |
| scpsys = "/soc/scpsys@10000000"; | |
| vdec_gcon = "/soc/vdec_gcon@16000000"; | |
| vdec = "/soc/vdec@16020000"; | |
| venc_gcon = "/soc/venc_gcon@17000000"; | |
| venc = "/soc/venc@17002000"; | |
| keypad = "/soc/keypad@10003000"; | |
| apirtx = "/soc/irtx@11011000"; | |
| apuart0 = "/soc/apuart0@11002000"; | |
| apuart1 = "/soc/apuart1@11003000"; | |
| apuart2 = "/soc/apuart2@11004000"; | |
| apuart3 = "/soc/apuart3@11005000"; | |
| apuart4 = "/soc/apuart4@1100d000"; | |
| spi0 = "/soc/spi@1100a000"; | |
| btif_tx = "/soc/btif_tx@11000900"; | |
| btif_rx = "/soc/btif_rx@11000980"; | |
| btif = "/soc/btif@1100c000"; | |
| consys = "/soc/consys@18070000"; | |
| met_smi = "/soc/met_smi@14017000"; | |
| kd_camera_hw1 = "/soc/kd_camera_hw1@15008000"; | |
| kd_camera_hw2 = "/soc/kd_camera_hw2@15008000"; | |
| hacc = "/soc/hacc@10008000"; | |
| als = "/soc/als"; | |
| gse_1 = "/soc/gse_1"; | |
| ext_buck_oc = "/soc/ext_buck_oc"; | |
| swtp = "/soc/swtp"; | |
| dsi_te = "/soc/dsi_te"; | |
| bus = "/bus"; | |
| eintc = "/bus/eintc@10005000"; | |
| ap_dma = "/bus/dma@11000000"; | |
| i2c0 = "/bus/i2c@11007000"; | |
| i2c1 = "/bus/i2c@11008000"; | |
| i2c2 = "/bus/i2c@11009000"; | |
| i2c3 = "/bus/i2c@1100f000"; | |
| i2c4 = "/bus/i2c@11012000"; | |
| mcucfg = "/bus/mcucfg@10200000"; | |
| bat_meter = "/bus/bat_meter"; | |
| bat_notify = "/bus/bat_notify"; | |
| bat_comm = "/bus/bat_comm"; | |
| mdcldma = "/bus/mdcldma@1000A000"; | |
| ssw = "/bus/simswitch@0"; | |
| mhl = "/bus/mhl@0"; | |
| lcm = "/bus/lcm"; | |
| lcm_mode = "/bus/lcm_mode"; | |
| cpu_dbgapb = "/bus/cpu_dbgapb"; | |
| syscfg_pctl_a = "/bus/syscfg_pctl_a"; | |
| pio = "/bus/pinctrl"; | |
| uart0_gpio_def_cfg = "/bus/pinctrl/uart0gpiodefault"; | |
| uart0_rx_set_cfg = "/bus/pinctrl/uart0_rx_set"; | |
| uart0_rx_clr_cfg = "/bus/pinctrl/uart0_rx_clear"; | |
| uart0_tx_set_cfg = "/bus/pinctrl/uart0_tx_set"; | |
| uart0_tx_clr_cfg = "/bus/pinctrl/uart0_tx_clear"; | |
| uart1_gpio_def_cfg = "/bus/pinctrl/uart1gpiodefault"; | |
| uart1_rx_set_cfg = "/bus/pinctrl/uart1_rx_set"; | |
| uart1_rx_clr_cfg = "/bus/pinctrl/uart1_rx_clear"; | |
| uart1_tx_set_cfg = "/bus/pinctrl/uart1_tx_set"; | |
| uart1_tx_clr_cfg = "/bus/pinctrl/uart1_tx_clear"; | |
| uart2_gpio_def_cfg = "/bus/pinctrl/uart2gpiodefault"; | |
| uart2_rx_set_cfg = "/bus/pinctrl/uart2_rx_set"; | |
| uart2_rx_clr_cfg = "/bus/pinctrl/uart2_rx_clear"; | |
| uart2_tx_set_cfg = "/bus/pinctrl/uart2_tx_set"; | |
| uart2_tx_clr_cfg = "/bus/pinctrl/uart2_tx_clear"; | |
| uart3_gpio_def_cfg = "/bus/pinctrl/uart3gpiodefault"; | |
| uart3_rx_set_cfg = "/bus/pinctrl/uart3_rx_set"; | |
| uart3_rx_clr_cfg = "/bus/pinctrl/uart3_rx_clear"; | |
| uart3_tx_set_cfg = "/bus/pinctrl/uart3_tx_set"; | |
| uart3_tx_clr_cfg = "/bus/pinctrl/uart3_tx_clear"; | |
| ssw_default = "/bus/pinctrl/ssw0default"; | |
| ssw_hot_plug_mode1 = "/bus/pinctrl/ssw@1"; | |
| ssw_hot_plug_mode2 = "/bus/pinctrl/ssw@2"; | |
| ssw_two_sims_bound_to_md1 = "/bus/pinctrl/ssw@3"; | |
| ssw_sim1_md3_sim2_md1 = "/bus/pinctrl/ssw@4"; | |
| vsram_default = "/bus/pinctrl/vsram0default"; | |
| vsram_output_low = "/bus/pinctrl/vsram@1"; | |
| vsram_output_high = "/bus/pinctrl/vsram@2"; | |
| RFIC0_01_mode = "/bus/pinctrl/clockbuf@1"; | |
| RFIC0_04_mode = "/bus/pinctrl/clockbuf@2"; | |
| nfc = "/bus/nfc@0"; | |
| usb0 = "/bus/usb20@11200000"; | |
| touch = "/bus/touch@"; | |
| accdet = "/bus/accdet@"; | |
| pwm = "/bus/pwm@11006000"; | |
| rf_clock_buffer_ctrl = "/rf_clock_buffer"; | |
| alsps = "/als_ps@0"; | |
| gyro = "/gyroscope@0"; | |
| irq_nfc = "/irq_nfc"; | |
| odm = "/odm"; | |
| }; | |
| }; |
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