ATMEGA328P Timer2 notes - for setting up RTC tick source

gistfile1.txt

PRTIM2 bit in ”Minimizing Power Consumption” on page 41 must be written to zero to enable Timer/Counter2
module.

Timer has storage registers;
- TCNT2 counting register
- OCR2A output compare register A
- OCR2B output compare register B
(OCR2A/B compared to TCNT2, can drive waveform generator)

Control registers;
- ASSR aynchronous status register
- 

Timer2 Interrupt Flags; TIFR2
Timer2 Interrupt Enables; TIMSK2

Timer counts to 0xFF, or to the number stored in one of the OCRs

Clock source; (CLK_t2)
- By default, the microcontroller clock. (called CLK_io for some reason)
- If ASSR.AS2 is set, use the TOSC1 TOSC2 pins instead

Pipeling to timer goes;
- TOSC1/TOSC2+oscillator or CLK_io
- multiplexer
- Prescaler
- Control logic (inputs; at-bottom, at-top, controls; direction, count, clear)
- TCNT2
(something about CS22:0? - to select clock source?)

Counting sequence, overflow	(TIFR2.TOV2) behaviour;
TCCR2A.WGM20, TCCR2A.WGM21, TCCR2B.WGM22 bits

Output compare; TIFR2 bits set, (OCF2A OCF2B)
- Cleared by interrupt OR
- "Cleared by writing 1 to TIFR2 bit" ...?
Waveform generation;
Set by WGM22:0 and COM2x1:0 ... (more on p147)

....
Modes: (wgm = waveform generation mode)
WGM22:0 = 000; Normal mode
 - Count up to 0xFF, TOV2 triggered on overflow.
WGM22:0 = 010; Clear timer on compare match
 - Count up to OCR2A, OCF2A triggered on match and TCNT2 cleared. (if set lower than TCNT2, won't trigger til overflow)
 - If compare output mode set to 1, waveform generated is 50% duty of variable freq
WGM22:0 = 011, 111, Fast PWM
WGM22:0 = 001, 101, Phase correct PWM

Asynch:
Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer
Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching clock source is:
a. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2.
b. Select clock source by setting AS2 as appropriate.
c. Write new values to TCNT2, OCR2x, and TCCR2x.
d. To switch to asynchronous operation: Wait for TCN2xUB, OCR2xUB, and TCR2xUB. ... ?
e. Clear the Timer/Counter2 Interrupt Flags.
f. Enable interrupts, if needed.
(In asynchronous mode TCNT2 and other registers not reliable to read accurately)

Prescaling: Fig 18.12
ClK_t2 = (AS2 ? TOSC1 : CLK_io) / [0,1,8,32,64,128,256,1024][CS22:0]; 

------------------------------------------------------------
For RTC source:

TCCR2A
 - COM2A1:0 = 00 - Normal operation, output disconnected
 - COM2B1:0 = 00 - Normal operation, output disconnected
 - WGM21 = 0 // Normal
 - WGM20 = 0 // Normal
TCRCR2B
 - FOC2A = 0 - No output compare
 - FOC2B = 0 - No output compare
 - WGM22 = 0 // Normal
 - CS22:0 = 101 - /128 scaling, according to table 18/9
TCNT2
 - Will increment as timer counts
OCR2A, OCR2B
 - Not used
TIMSK
 - OCIE2B = 0 - No output compare interrupt on B
 - OCIE2A = 0 - No output compare interrupt on A
 - TOIE2 = 1 - Interrupt on overflow
TIFR2
 - OCF2B - Not used
 - OCF2A - Not used
 - TOV2 - Is set when overflow occurs... not needed if interrupting?
ASSR
 - EXCLK = 0 - If set, assumes an external TTL clock source
 - AS2 = 1 - Set; so CLK_t2 is clocked from TOSC1/2 crystal
 - TCN2UB / OCR2AUB / OCR2BUB / TCR2AUB / TCR2BUB ; Set when busy doing an update ... not used?
GTCCR
 - Not used
...and set the SREG 'I' bit.