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Switches Led on and off according to a clock.
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// Module to receive USART letters from the PC and toggle | |
// 4 leds. | |
// Rafael Arce Nazario 2017 | |
// Israel O. Dilan Pantojas | |
// Jose A. Reyes Zayas | |
// 22-Marzo-2017 | |
// Expirento 4 Parte B | |
module top | |
( | |
input wire clk, | |
input wire ftdi_rx, | |
output reg [3:0] led = 4'b0000 | |
); | |
wire uart_valid; | |
wire [7:0] uart_data_rx; | |
wire letter_a, letter_s; | |
integer n; | |
integer t; | |
integer c; | |
// Combinational logic | |
assign letter_a = uart_valid && (uart_data_rx == 8'h61); | |
assign letter_s = uart_valid && (uart_data_rx == 8'h73); | |
// Module instantiation | |
uart_rx rx0 ( | |
.clk(clk), | |
.rst(1'b0), | |
.din(ftdi_rx), | |
.data_out(uart_data_rx), | |
.valid(uart_valid) | |
); | |
// Whenever the signals letter_a, etc pulse then | |
// toggle the corresponding output. | |
initial begin | |
n = 0; | |
t = 1; | |
c = 0; | |
end | |
always @(posedge clk) begin | |
begin | |
c <= c + t; | |
if (t <= 0) | |
begin | |
t <= 1; | |
end | |
end | |
begin | |
if (n == 4) begin n <= 0; end | |
if (c >= 32000000) | |
begin | |
led[n] <= ~led[n]; | |
n <= n+1; | |
c <= 0; | |
end | |
end | |
begin | |
if (letter_a && t > 0) | |
begin | |
t <= t/2; | |
end | |
if (letter_s && t < 32000000) | |
begin | |
t <= t*2; | |
end | |
end | |
end | |
endmodule |
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