10MB identity-mapped paging x86-64

paging.asm

; Mem definition
PML4.Addr      equ   0x00010000  ; PML4
PDPE.Addr      equ   0x00011000 ; 0x10000 + PML4 (512 entries of 64 bits)
PDE.Addr       equ   0x00012000 ; 0x11000 + PDPE (512 entries of 64 bits)
PTE.Addr       equ   0x00013000 ; 0x12000 + PDE (512 entries of 64 bits)

; Setup pages structure and flag bits
; Present (bit 1) and ReadWrite(bit 2) bits are set
.StdBits   equ 0x03

; Create a single entry [0] in PML4 Table.
;   -> one entry in a PML4T can address 512GB
mov DWORD [PML4.Addr], (PDPE.Addr ) | .StdBits

; Create a single entry [0] in PDPT Table.
;   -> one entry in a PDPT can address 1GB
mov DWORD [PDPE.Addr], (PDE.Addr ) | .StdBits

; Create entries [0...4] in PDE Table.
;   -> one entry in a PDE can address 2MB
mov DWORD [PDE.Addr], (PTE.Addr) | .StdBits
mov DWORD [PDE.Addr + 0x08], ((PTE.Addr + 0x1000)) | .StdBits
mov DWORD [PDE.Addr + 0x10], ((PTE.Addr + 0x1000 * 2)) | .StdBits
mov DWORD [PDE.Addr + 0x18], ((PTE.Addr + 0x1000 * 3)) | .StdBits
mov DWORD [PDE.Addr + 0x18], ((PTE.Addr + 0x1000 * 4)) | .StdBits

; Create all 512 entries in each PT table.
;   -> one entry in a PT can address 4Kb

; Prep
    mov edi, PTE.Addr
    mov ecx, 512 * 5
    mov eax,  .StdBits

.make_pte_page:
      mov [edi], eax
      add edi, 8
      add eax, 0x1000
      loop .make_pte_page