gistfile1.txt

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <[email protected]>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.46+11 (git sha1 0200a7680, g++ 14.2.1 -march=x86-64 -mtune=generic -O2 -fno-plt -fexceptions -fstack-clash-protection -fcf-protection -fPIC -O3)

-- Parsing `test.v' using frontend ` -vlog2k' --

1. Executing Verilog-2005 frontend: test.v
Parsing Verilog input from `test.v' to AST representation.
Storing AST representation for module `$abstract\test'.
Successfully finished Verilog frontend.

-- Running command `synth_ice40' --

2. Executing SYNTH_ICE40 pass.

2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\SB_IO'.
Generating RTLIL representation for module `\SB_GB_IO'.
Generating RTLIL representation for module `\SB_GB'.
Generating RTLIL representation for module `\SB_LUT4'.
Generating RTLIL representation for module `\SB_CARRY'.
Generating RTLIL representation for module `\SB_DFF'.
Generating RTLIL representation for module `\SB_DFFE'.
Generating RTLIL representation for module `\SB_DFFSR'.
Generating RTLIL representation for module `\SB_DFFR'.
Generating RTLIL representation for module `\SB_DFFSS'.
Generating RTLIL representation for module `\SB_DFFS'.
Generating RTLIL representation for module `\SB_DFFESR'.
Generating RTLIL representation for module `\SB_DFFER'.
Generating RTLIL representation for module `\SB_DFFESS'.
Generating RTLIL representation for module `\SB_DFFES'.
Generating RTLIL representation for module `\SB_DFFN'.
Generating RTLIL representation for module `\SB_DFFNE'.
Generating RTLIL representation for module `\SB_DFFNSR'.
Generating RTLIL representation for module `\SB_DFFNR'.
Generating RTLIL representation for module `\SB_DFFNSS'.
Generating RTLIL representation for module `\SB_DFFNS'.
Generating RTLIL representation for module `\SB_DFFNESR'.
Generating RTLIL representation for module `\SB_DFFNER'.
Generating RTLIL representation for module `\SB_DFFNESS'.
Generating RTLIL representation for module `\SB_DFFNES'.
Generating RTLIL representation for module `\SB_RAM40_4K'.
Generating RTLIL representation for module `\SB_RAM40_4KNR'.
Generating RTLIL representation for module `\SB_RAM40_4KNW'.
Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
Generating RTLIL representation for module `\ICESTORM_LC'.
Generating RTLIL representation for module `\SB_PLL40_CORE'.
Generating RTLIL representation for module `\SB_PLL40_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
Generating RTLIL representation for module `\SB_WARMBOOT'.
Generating RTLIL representation for module `\SB_SPRAM256KA'.
Generating RTLIL representation for module `\SB_HFOSC'.
Generating RTLIL representation for module `\SB_LFOSC'.
Generating RTLIL representation for module `\SB_RGBA_DRV'.
Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
Generating RTLIL representation for module `\SB_RGB_DRV'.
Generating RTLIL representation for module `\SB_I2C'.
Generating RTLIL representation for module `\SB_SPI'.
Generating RTLIL representation for module `\SB_LEDDA_IP'.
Generating RTLIL representation for module `\SB_FILTER_50NS'.
Generating RTLIL representation for module `\SB_IO_I3C'.
Generating RTLIL representation for module `\SB_IO_OD'.
Generating RTLIL representation for module `\SB_MAC16'.
Generating RTLIL representation for module `\ICESTORM_RAM'.
Successfully finished Verilog frontend.

2.2. Executing HIERARCHY pass (managing design hierarchy).

2.2.1. Executing AST frontend in derive mode using pre-parsed AST for module `\test'.
Generating RTLIL representation for module `\test'.

2.2.2. Finding top of design hierarchy..
root of   0 design levels: test                
Automatically selected test as design top module.

2.2.3. Analyzing design hierarchy..
Top module:  \test

2.2.4. Analyzing design hierarchy..
Top module:  \test
Removed 0 unused modules.

2.3. Executing PROC pass (convert processes to netlists).

2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR.
Removed a total of 0 dead cases.

2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 8 redundant assignments.
Promoted 22 assignments to connections.

2.3.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
  Set init value: \Q = 1'0

2.3.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.

2.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~18 debug messages>

2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.

2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
  created $adff cell `$procdff$429' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
  created $dff cell `$procdff$430' with negative edge clock.
Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
  created $adff cell `$procdff$433' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
  created $dff cell `$procdff$434' with negative edge clock.
Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
  created $adff cell `$procdff$437' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
  created $dff cell `$procdff$438' with negative edge clock.
Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
  created $adff cell `$procdff$441' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
  created $dff cell `$procdff$442' with negative edge clock.
Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
  created $dff cell `$procdff$443' with negative edge clock.
Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
  created $dff cell `$procdff$444' with negative edge clock.
Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
  created $adff cell `$procdff$447' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
  created $dff cell `$procdff$448' with positive edge clock.
Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
  created $adff cell `$procdff$451' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
  created $dff cell `$procdff$452' with positive edge clock.
Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
  created $adff cell `$procdff$455' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
  created $dff cell `$procdff$456' with positive edge clock.
Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
  created $adff cell `$procdff$459' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
  created $dff cell `$procdff$460' with positive edge clock.
Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
  created $dff cell `$procdff$461' with positive edge clock.
Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
  created $dff cell `$procdff$462' with positive edge clock.

2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
Cleaned up 18 empty switches.

2.3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
Couldn't topologically sort cells, optimizing module test may take a longer time.

2.4. Executing FLATTEN pass (flatten design).

2.5. Executing TRIBUF pass.

2.6. Executing DEMINOUT pass (demote inout ports to input or output).

2.7. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
Couldn't topologically sort cells, optimizing module test may take a longer time.
Couldn't topologically sort cells, optimizing module test may take a longer time.

2.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..
Removed 0 unused cells and 2 unused wires.
<suppressed ~1 debug messages>

2.9. Executing CHECK pass (checking for obvious problems).
Checking module test...
Warning: found logic loop in module test:
    cell $ternary$test.v:7$382 ($mux) source: test.v:7.12-7.21
      S[0] --> Y[1]
    wire \q [1] source: test.v:3.26-3.27
    cell $ternary$test.v:6$381 ($mux) source: test.v:6.12-6.27
      A[0] --> Y[0]
    wire \s source: test.v:5.6-5.7
Warning: found logic loop in module test:
    cell $ternary$test.v:6$381 ($mux) source: test.v:6.12-6.27
      B[0] --> Y[0]
    wire \s source: test.v:5.6-5.7
    cell $ternary$test.v:7$382 ($mux) source: test.v:7.12-7.21
      S[0] --> Y[0]
    wire \q [0] source: test.v:3.26-3.27
Found and reported 2 problems.

2.10. Executing OPT pass (performing simple optimizations).

2.10.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
Couldn't topologically sort cells, optimizing module test may take a longer time.
Couldn't topologically sort cells, optimizing module test may take a longer time.

2.10.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \test..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~2 debug messages>

2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \test.
Performed a total of 0 changes.

2.10.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

2.10.6. Executing OPT_DFF pass (perform DFF optimizations).

2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..

2.10.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
Couldn't topologically sort cells, optimizing module test may take a longer time.
Couldn't topologically sort cells, optimizing module test may take a longer time.

2.10.9. Finished OPT passes. (There is nothing left to do.)

2.11. Executing FSM pass (extract and optimize FSM).

2.11.1. Executing FSM_DETECT pass (finding FSMs in design).

2.11.2. Executing FSM_EXTRACT pass (extracting FSM from design).

2.11.3. Executing FSM_OPT pass (simple optimizations of FSMs).

2.11.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..

2.11.5. Executing FSM_OPT pass (simple optimizations of FSMs).

2.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

2.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

2.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

2.12. Executing OPT pass (performing simple optimizations).

2.12.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
Couldn't topologically sort cells, optimizing module test may take a longer time.
Couldn't topologically sort cells, optimizing module test may take a longer time.

2.12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \test..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~2 debug messages>

2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \test.
Performed a total of 0 changes.

2.12.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

2.12.6. Executing OPT_DFF pass (perform DFF optimizations).

2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..

2.12.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
Couldn't topologically sort cells, optimizing module test may take a longer time.
Couldn't topologically sort cells, optimizing module test may take a longer time.

2.12.9. Finished OPT passes. (There is nothing left to do.)

2.13. Executing WREDUCE pass (reducing word size of cells).

2.14. Executing PEEPOPT pass (run peephole optimizers).

2.15. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..

2.16. Executing SHARE pass (SAT-based resource sharing).

2.17. Executing TECHMAP pass (map to technology primitives).

2.17.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

2.17.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~6 debug messages>

2.18. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
Couldn't topologically sort cells, optimizing module test may take a longer time.
Couldn't topologically sort cells, optimizing module test may take a longer time.

2.19. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..

2.20. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module test:
  created 0 $alu and 0 $macc cells.

2.21. Executing OPT pass (performing simple optimizations).

2.21.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
Couldn't topologically sort cells, optimizing module test may take a longer time.
Couldn't topologically sort cells, optimizing module test may take a longer time.

2.21.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

2.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \test..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~2 debug messages>

2.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \test.
Performed a total of 0 changes.

2.21.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

2.21.6. Executing OPT_DFF pass (perform DFF optimizations).

2.21.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..

2.21.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
Couldn't topologically sort cells, optimizing module test may take a longer time.
Couldn't topologically sort cells, optimizing module test may take a longer time.

2.21.9. Finished OPT passes. (There is nothing left to do.)

2.22. Executing MEMORY pass.

2.22.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

2.22.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

2.22.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).

2.22.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

2.22.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).

2.22.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..

2.22.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

2.22.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

2.22.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..

2.22.10. Executing MEMORY_COLLECT pass (generating $mem cells).

2.23. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..

2.24. Executing MEMORY_LIBMAP pass (mapping memories to cells).

2.25. Executing TECHMAP pass (map to technology primitives).

2.25.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ICE40_RAM4K_'.
Successfully finished Verilog frontend.

2.25.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation.
Generating RTLIL representation for module `\$__ICE40_SPRAM_'.
Successfully finished Verilog frontend.

2.25.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

2.26. Executing ICE40_BRAMINIT pass.

2.27. Executing OPT pass (performing simple optimizations).

2.27.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
Couldn't topologically sort cells, optimizing module test may take a longer time.
Couldn't topologically sort cells, optimizing module test may take a longer time.

2.27.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

2.27.3. Executing OPT_DFF pass (perform DFF optimizations).

2.27.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..

2.27.5. Finished fast OPT passes.

2.28. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

2.29. Executing OPT pass (performing simple optimizations).

2.29.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
Couldn't topologically sort cells, optimizing module test may take a longer time.
Couldn't topologically sort cells, optimizing module test may take a longer time.

2.29.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

2.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \test..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~2 debug messages>

2.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \test.
Performed a total of 0 changes.

2.29.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

2.29.6. Executing OPT_DFF pass (perform DFF optimizations).

2.29.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..

2.29.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
Couldn't topologically sort cells, optimizing module test may take a longer time.
Couldn't topologically sort cells, optimizing module test may take a longer time.

2.29.9. Finished OPT passes. (There is nothing left to do.)

2.30. Executing ICE40_WRAPCARRY pass (wrap carries).

2.31. Executing TECHMAP pass (map to technology primitives).

2.31.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

2.31.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ice40_alu'.
Successfully finished Verilog frontend.

2.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~75 debug messages>

2.32. Executing OPT pass (performing simple optimizations).

2.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
Couldn't topologically sort cells, optimizing module test may take a longer time.
Couldn't topologically sort cells, optimizing module test may take a longer time.

2.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

2.32.3. Executing OPT_DFF pass (perform DFF optimizations).

2.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..

2.32.5. Finished fast OPT passes.

2.33. Executing ICE40_OPT pass (performing simple optimizations).

2.33.1. Running ICE40 specific optimizations.

2.33.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
Couldn't topologically sort cells, optimizing module test may take a longer time.
Couldn't topologically sort cells, optimizing module test may take a longer time.

2.33.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

2.33.4. Executing OPT_DFF pass (perform DFF optimizations).

2.33.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..

2.33.6. Finished OPT passes. (There is nothing left to do.)

2.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

2.35. Executing TECHMAP pass (map to technology primitives).

2.35.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
Successfully finished Verilog frontend.

2.35.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~22 debug messages>

2.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
Couldn't topologically sort cells, optimizing module test may take a longer time.
Couldn't topologically sort cells, optimizing module test may take a longer time.

2.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

2.38. Executing ICE40_OPT pass (performing simple optimizations).

2.38.1. Running ICE40 specific optimizations.

2.38.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
Couldn't topologically sort cells, optimizing module test may take a longer time.
Couldn't topologically sort cells, optimizing module test may take a longer time.

2.38.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

2.38.4. Executing OPT_DFF pass (perform DFF optimizations).

2.38.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..

2.38.6. Finished OPT passes. (There is nothing left to do.)

2.39. Executing TECHMAP pass (map to technology primitives).

2.39.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

2.39.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

2.40. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/abc9_model.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ICE40_CARRY_WRAPPER'.
Successfully finished Verilog frontend.

2.41. Executing ABC9 pass.

2.41.1. Executing ABC9_OPS pass (helper functions for ABC9).

2.41.2. Executing ABC9_OPS pass (helper functions for ABC9).

2.41.3. Executing SCC pass (detecting logic loops).
Found an SCC: $auto$simplemap.cc:267:simplemap_mux$565 $auto$simplemap.cc:267:simplemap_mux$564 $auto$simplemap.cc:267:simplemap_mux$566
Found 1 SCCs in module test.
Found 1 SCCs.

2.41.4. Executing ABC9_OPS pass (helper functions for ABC9).

2.41.5. Executing PROC pass (convert processes to netlists).

2.41.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.41.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.41.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

2.41.5.4. Executing PROC_INIT pass (extract init attributes).

2.41.5.5. Executing PROC_ARST pass (detect async resets in processes).

2.41.5.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.41.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

2.41.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.41.5.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.41.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.41.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.41.5.12. Executing OPT_EXPR pass (perform const folding).

2.41.6. Executing TECHMAP pass (map to technology primitives).

2.41.6.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

2.41.6.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~125 debug messages>

2.41.7. Executing OPT pass (performing simple optimizations).

2.41.7.1. Executing OPT_EXPR pass (perform const folding).

2.41.7.2. Executing OPT_MERGE pass (detect identical cells).
Removed a total of 0 cells.

2.41.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Removed 0 multiplexer ports.

2.41.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Performed a total of 0 changes.

2.41.7.5. Executing OPT_MERGE pass (detect identical cells).
Removed a total of 0 cells.

2.41.7.6. Executing OPT_DFF pass (perform DFF optimizations).

2.41.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).

2.41.7.8. Executing OPT_EXPR pass (perform const folding).

2.41.7.9. Finished OPT passes. (There is nothing left to do.)

2.41.8. Executing TECHMAP pass (map to technology primitives).

2.41.8.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/abc9_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

2.41.8.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~2 debug messages>

2.41.9. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/abc9_model.v
Parsing Verilog input from `/usr/bin/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

2.41.10. Executing ABC9_OPS pass (helper functions for ABC9).

2.41.11. Executing ABC9_OPS pass (helper functions for ABC9).

2.41.12. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

2.41.13. Executing AIGMAP pass (map logic to AIG).
Module test: replaced 3 cells with 21 new cells, skipped 1 cells.
  replaced 1 cell types:
       3 $_MUX_
  not replaced 1 cell types:
       1 $__ABC9_SCC_BREAKER

2.41.13.1. Executing ABC9_OPS pass (helper functions for ABC9).

2.41.13.2. Executing ABC9_OPS pass (helper functions for ABC9).

2.41.13.3. Executing XAIGER backend.