mstflint dc firmware config dump from an IBM CX312A NIC

fw_config_IBM1080111023.ini

;; Generated automatically by iniprep tool on Tue Sep 24 11:00:15 EEST 2013 from ./cx3-1_MCX312A.prs
;;
;; PRS  FILE FOR HAWK 3G
;; $Id$



[PS_INFO]
Name = 00D9691_Ax
Description = Mellanox ConnectX-3 EN Dual-port SFP+ 10GbE Adapter

[ADAPTER]
PSID = IBM1080111023
pcie_gen2_speed_supported = true
pcie_gen3_speed_supported = true
adapter_dev_id = 0x1003
silicon_rev = 0x01

gpio_mode1       = 0x08000001
gpio_mode0       = 0x04d06afe
gpio_default_val = 0x0e78421f
gpio_pull_up     = 0xff2baf1f
gpio_pull_enable = 0x00001000

receiver_detect_en = true

[HCA]
hca_header_device_id = 0x1003
hca_header_subsystem_id = 0x0077
hca_header_class_code = 0x020000
dpdp_en = false
eth_xfi_en = true
mdio_en_port1 = 0

[IB]
mlpn_en_port0 = true
mlpn_en_port1 = true
phy_type_port1 = XFI
phy_type_port2 = XFI

eye_open_machine_measure_time =0xd

ext_phy_board_port1 = HAWK3
ext_phy_board_port2 = HAWK3
gen_guids_from_mac = true
do_sense = false

new_gpio_scheme_en = true
read_cable_params_port1_en = true
read_cable_params_port2_en = true

port1_802_3ap_kx4_ability = false
port1_802_3ap_kx4_enable  = false
port2_802_3ap_kx4_ability = false
port2_802_3ap_kx4_enable  = false

center_mix90phase = true

;;Logic lane to Serdes mapping
tx_logic_0_serdes = 0
tx_logic_1_serdes = 1
tx_logic_2_serdes = 2
tx_logic_3_serdes = 3
rx_logic_0_serdes = 0
rx_logic_1_serdes = 1
rx_logic_2_serdes = 2
rx_logic_3_serdes = 3

tx_logic_4_serdes = 4
tx_logic_5_serdes = 5
tx_logic_6_serdes = 6
tx_logic_7_serdes = 7
rx_logic_4_serdes = 4
rx_logic_5_serdes = 5
rx_logic_6_serdes = 6
rx_logic_7_serdes = 7

eth_tx_lane_polarity_port1 = 0x1
eth_tx_lane_polarity_port2 = 0x1
eth_rx_lane_polarity_port1 = 0x0
eth_rx_lane_polarity_port2 = 0x1

; start of '#include "include_sfpp_serdes_prams.h"'

;;Serdes parameters
;; force 7 - XFI
force_rx7_slicer_ind_en = 0xeb
force_rx7_slicer1_enable = 0x0
force_rx7_slicer2_enable = 0x0
force_rx7_ffe_tap0 = 0x64
force_rx7_ffe_tap1 = 0x80
force_rx7_ffe_tap2 = 0xde
force_rx7_ffe_tap3 = 0x80
force_rx7_ffe_tap4 = 0x46

force_tx7_ob_bias = 0xd
force_tx7_ob_preemp_pre = 0x20
force_tx7_ob_preemp_post = 0x0
force_tx7_ob_preemp_main = 0x7f
force_tx7_preemp = 0x0
force_tx7_pre_polarity = 0x1
force_tx7_post_polarity = 0x1
force_tx7_main_polarity = 0x0

;; negotiation IB
nego_rx1_slicer_ind_en = 0xeb
nego_rx1_slicer1_enable=0
nego_rx1_slicer2_enable=0
nego_rx1_ffe_tap0=0x78
nego_rx1_ffe_tap1=0x80
nego_rx1_ffe_tap2=0xde
nego_rx1_ffe_tap3=0x80
nego_rx1_ffe_tap4=0x3c

;; negotiation ETH
nego_eth_rx12_slicer_ind_en = 0xff
nego_eth_rx12_slicer1_enable= 0x8
nego_eth_rx12_slicer2_enable= 0x8
nego_eth_rx12_ffe_tap0=241
nego_eth_rx12_ffe_tap1=128
nego_eth_rx12_ffe_tap2=61
nego_eth_rx12_ffe_tap3=99
nego_eth_rx12_ffe_tap4=128


parallel_detect_rx0_slicer_ind_en = 0xeb
parallel_detect_rx0_slicer1_enable = 0x0
parallel_detect_rx0_slicer2_enable = 0x0
parallel_detect_rx0_ffe_tap0 = 0x64
parallel_detect_rx0_ffe_tap1 = 0x80
parallel_detect_rx0_ffe_tap2 = 0xde
parallel_detect_rx0_ffe_tap3 = 0x80
parallel_detect_rx0_ffe_tap4 = 0x46

;; ETH connected to third party device
aba_non_mlpn_tx8_ob_preemp_pre = 5
aba_non_mlpn_tx8_ob_preemp_post = 0
aba_non_mlpn_tx8_ob_preemp_main = 65
aba_non_mlpn_tx8_ob_bias = 8
aba_non_mlpn_tx8_pre_polarity = 1
aba_non_mlpn_tx8_post_polarity = 1
aba_non_mlpn_tx8_main_polarity = 0
aba_non_mlpn_tx8_preemp = 0


; end of '#include "include_sfpp_serdes_prams.h"'

[PLL]
lbist_en  = 0
lbist_shift_freq  = 3
flash_div = 0x3
lbist_array_bypass = 1
lbist_pat_cnt_lsb = 0x2
core_f = 42
core_r = 12
core_od = 2

[FW]