Ravenslofty

// Copyright (C) 2019, Dan Ravensloft
// SPDX-License-Identifier: GPL-3.0-or-later
library(74series) {
    // 7400 quad 2-input NAND gate
    cell(7400_4xNAND2) {
        area: 3;
        pin(A) { direction: input; }
        pin(B) { direction: input; }
        pin(Y) { direction: output; function: "(A*B)'"; }
     }

Ravenslofty

`timescale 1 ns/1 ns

module sn74153(
    input n_enable,
    input [1:0] select,
    input [3:0] table1,
    input [3:0] table2,
    output reg [1:0] out
);

Ravenslofty

//! Program for controlling a Corsair M65 Pro.

// This is going to be written in a literate style to explain how the protocol works as best as I
// can. I appreciate some people find this style noisy, but I hope it serves a useful purpose.

// We will need to provide a timeout `Duration` for USB operations in case they fail.
use std::time;

// We need to sleep the thread between packets to give the device time to catch up.
use std::thread;

Ravenslofty

git bisect start
# good: [ef84b434a529fc8bc76ececbd531b5ddd39a4392] Merge pull request #913 from smunaut/fix_proc_mux
git bisect good ef84b434a529fc8bc76ececbd531b5ddd39a4392
# bad: [98925f6c4be611434e75f0ccf645a7ef8adcfc63] Merge pull request #963 from YosysHQ/eddie/synth_xilinx_fine
git bisect bad 98925f6c4be611434e75f0ccf645a7ef8adcfc63
# good: [d99422411f568d6d8d7de7d11346718e70012df4] Use new pmux2shiftx from #944, remove my old attempt
git bisect good d99422411f568d6d8d7de7d11346718e70012df4
# good: [99d5435650c38fb96dc364c0fd4ac6250a4871ea] Merge pull request #905 from christian-krieg/feature/python_bindings
git bisect good 99d5435650c38fb96dc364c0fd4ac6250a4871ea
# bad: [314ff1e4ca00ef8024bbb0d2f031efd78b01f9a1] Merge pull request #960 from YosysHQ/eddie/equiv_opt_undef

Ravenslofty

from nmigen import Const, Elaboratable, Module, Repl, Signal
from nmigen.cli import main


class PositiveAttacks(Elaboratable):
    def __init__(self, shift, mask):
        self.gen = Signal(64)
        self.prop = Signal(64)
        self.output = Signal(64)

Ravenslofty

from nmigen import Const, Elaboratable, Module, Repl, Signal
from nmigen.cli import main


class PositiveAttacks(Elaboratable):
    def __init__(self, shift, mask):
        self.gen = Signal(64)
        self.prop = Signal(64)
        self.output = Signal(64)

Ravenslofty

Traceback (most recent call last):
  File "wrapper.py", line 49, in <module>
    rvfi = RVFI()
  File "wrapper.py", line 33, in __init__
    self.mem_rmask = Signal(NRET * XLEN/8)
  File "/usr/local/lib/python3.6/dist-packages/nmigen-0.1-py3.6.egg/nmigen/hdl/ast.py", line 606, in __init__
    self.nbits, self.signed = shape
TypeError: 'float' object is not iterable

Ravenslofty

from nmigen import Cat, Module, Repl, Signal
from nmigen.cli import main


class Adder:
    def __init__(self, width):
        self.a = Signal(width)
        self.b = Signal(width)
        self.subtract = Signal()

Ravenslofty

Traceback (most recent call last):
  File "alu.py", line 97, in <module>
    main(alu)
  File "/usr/local/lib/python3.6/dist-packages/nmigen-0.1-py3.6.egg/nmigen/cli.py", line 76, in main
    main_runner(parser, parser.parse_args(), *args, **kwargs)
  File "/usr/local/lib/python3.6/dist-packages/nmigen-0.1-py3.6.egg/nmigen/cli.py", line 58, in main_runner
    output = verilog.convert(fragment, name=name, ports=ports)
  File "/usr/local/lib/python3.6/dist-packages/nmigen-0.1-py3.6.egg/nmigen/back/verilog.py", line 29, in convert
    il_text = rtlil.convert(*args, **kwargs)
  File "/usr/local/lib/python3.6/dist-packages/nmigen-0.1-py3.6.egg/nmigen/back/rtlil.py", line 854, in convert

Ravenslofty

#!/usr/bin/env python3

from migen import Array, Cat, Module, Signal
from migen import sim
from migen.fhdl import verilog

# 74LS153 dual 4:1 multiplexer
class IC74153(Module):
    def __init__(self):
        self.table0 = Array(Signal() for a in range(4))