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ReubenBond/jitdisasm.txt

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jitdisasm.txt
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****** START compiling Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this (MethodHash=011f4f14)
Generating code for Windows x64
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = true
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
IL to import:
IL_0000 00 nop
IL_0001 d0 fd 00 00 1b ldtoken 0x1B0000FD
IL_0006 28 85 00 00 0a call 0xA000085
IL_000b d0 b4 01 00 1b ldtoken 0x1B0001B4
IL_0010 28 85 00 00 0a call 0xA000085
IL_0015 28 1f 01 00 0a call 0xA00011F
IL_001a 2d 1b brtrue.s 27 (IL_0037)
IL_001c d0 fd 00 00 1b ldtoken 0x1B0000FD
IL_0021 28 85 00 00 0a call 0xA000085
IL_0026 d0 18 01 00 02 ldtoken 0x2000118
IL_002b 28 85 00 00 0a call 0xA000085
IL_0030 28 1f 01 00 0a call 0xA00011F
IL_0035 2b 01 br.s 1 (IL_0038)
IL_0037 17 ldc.i4.1
IL_0038 0a stloc.0
IL_0039 06 ldloc.0
IL_003a 2c 45 brfalse.s 69 (IL_0081)
IL_003c 00 nop
IL_003d 02 ldarg.0
IL_003e 7b 93 04 00 0a ldfld 0xA000493
IL_0043 0b stloc.1
IL_0044 02 ldarg.0
IL_0045 7b 92 04 00 0a ldfld 0xA000492
IL_004a 0c stloc.2
IL_004b 07 ldloc.1
IL_004c 12 02 ldloca.s 0x2
IL_004e 28 24 01 00 0a call 0xA000124
IL_0053 fe 05 clt.un
IL_0055 16 ldc.i4.0
IL_0056 fe 01 ceq
IL_0058 13 04 stloc.s 0x4
IL_005a 11 04 ldloc.s 0x4
IL_005c 2c 0b brfalse.s 11 (IL_0069)
IL_005e 00 nop
IL_005f 02 ldarg.0
IL_0060 28 a6 04 00 0a call 0xA0004A6
IL_0065 13 05 stloc.s 0x5
IL_0067 2b 4b br.s 75 (IL_00b4)
IL_0069 12 02 ldloca.s 0x2
IL_006b 07 ldloc.1
IL_006c 28 ac 01 00 0a call 0xA0001AC
IL_0071 47 ldind.u1
IL_0072 0d stloc.3
IL_0073 02 ldarg.0
IL_0074 07 ldloc.1
IL_0075 17 ldc.i4.1
IL_0076 58 add
IL_0077 7d 93 04 00 0a stfld 0xA000493
IL_007c 09 ldloc.3
IL_007d 13 05 stloc.s 0x5
IL_007f 2b 33 br.s 51 (IL_00b4)
IL_0081 02 ldarg.0
IL_0082 7b 8e 04 00 0a ldfld 0xA00048E
IL_0087 8c fd 00 00 1b box 0x1B0000FD
IL_008c 75 15 01 00 02 isinst 0x2000115
IL_0091 13 06 stloc.s 0x6
IL_0093 11 06 ldloc.s 0x6
IL_0095 14 ldnull
IL_0096 fe 03 cgt.un
IL_0098 13 07 stloc.s 0x7
IL_009a 11 07 ldloc.s 0x7
IL_009c 2c 0c brfalse.s 12 (IL_00aa)
IL_009e 00 nop
IL_009f 11 06 ldloc.s 0x6
IL_00a1 6f bf 04 00 06 callvirt 0x60004BF
IL_00a6 13 05 stloc.s 0x5
IL_00a8 2b 0a br.s 10 (IL_00b4)
IL_00aa 00 nop
IL_00ab 28 41 01 00 2b call 0x2B000141
IL_00b0 13 05 stloc.s 0x5
IL_00b2 2b 00 br.s 0 (IL_00b4)
IL_00b4 11 05 ldloc.s 0x5
IL_00b6 2a ret
'this' passed in register rcx
lvaSetClass: setting class for V07 to (00007FF93B569758) Hagar.Buffers.ReaderInput
lvaGrabTemp returning 9 (V09 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
; Initial local variable assignments
;
; V00 this byref this
; V01 loc0 bool
; V02 loc1 int
; V03 loc2 struct <System.ReadOnlySpan`1[Byte], 16>
; V04 loc3 ubyte
; V05 loc4 bool
; V06 loc5 ubyte
; V07 loc6 ref class-hnd
; V08 loc7 bool
; V09 OutArgs lclBlk <na> "OutgoingArgSpace"
*************** In compInitDebuggingInfo() for Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 9
VarNum LVNum Name Beg End
0: 00h 00h V00 this 000h 0B7h
1: 01h 01h V01 loc0 000h 0B7h
2: 02h 02h V02 loc1 000h 0B7h
3: 03h 03h V03 loc2 000h 0B7h
4: 04h 04h V04 loc3 000h 0B7h
5: 05h 05h V05 loc4 000h 0B7h
6: 06h 06h V06 loc5 000h 0B7h
7: 07h 07h V07 loc6 000h 0B7h
8: 08h 08h V08 loc7 000h 0B7h
New Basic Block BB01 [0000] created.
New scratch BB01
Debuggable code - Add new BB01 [0000] to perform initialization of variables
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE )
*************** In fgFindBasicBlocks() for Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this
Marked V01 as a single def local
Marked V02 as a single def local
Marked V04 as a single def local
Marked V05 as a single def local
Marked V07 as a single def local
Marked V08 as a single def local
Jump targets:
IL_0037
IL_0038
IL_0069
IL_0081
IL_00aa
IL_00b4
New Basic Block BB02 [0001] created.
BB02 [000..01C)
New Basic Block BB03 [0002] created.
BB03 [01C..037)
New Basic Block BB04 [0003] created.
BB04 [037..038)
New Basic Block BB05 [0004] created.
BB05 [038..03C)
New Basic Block BB06 [0005] created.
BB06 [03C..05E)
New Basic Block BB07 [0006] created.
BB07 [05E..069)
New Basic Block BB08 [0007] created.
BB08 [069..081)
New Basic Block BB09 [0008] created.
BB09 [081..09E)
New Basic Block BB10 [0009] created.
BB10 [09E..0AA)
New Basic Block BB11 [0010] created.
BB11 [0AA..0B4)
New Basic Block BB12 [0011] created.
BB12 [0B4..0B7)
CLFLG_MINOPT set for method Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this
IL Code Size,Instr 183, 73, Basic Block count 12, Local Variable Num,Ref count 10, 28 for method Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this
IL Code Size,Instr 183, 73, Basic Block count 12, Local Variable Num,Ref count 10, 28 for method Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this
OPTIONS: opts.MinOpts() == true
Basic block list for 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target
BB02 [0001] 1 1 [000..01C)-> BB04 ( cond )
BB03 [0002] 1 1 [01C..037)-> BB05 (always)
BB04 [0003] 1 1 [037..038)
BB05 [0004] 2 1 [038..03C)-> BB09 ( cond )
BB06 [0005] 1 1 [03C..05E)-> BB08 ( cond )
BB07 [0006] 1 1 [05E..069)-> BB12 (always)
BB08 [0007] 1 1 [069..081)-> BB12 (always)
BB09 [0008] 1 1 [081..09E)-> BB11 ( cond )
BB10 [0009] 1 1 [09E..0AA)-> BB12 (always)
BB11 [0010] 1 1 [0AA..0B4)-> BB12 (always)
BB12 [0011] 4 1 [0B4..0B7) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Pre-import
*************** Finishing PHASE Pre-import
*************** Starting PHASE Importation
*************** In impImport() for Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this
Marking leading BBF_INTERNAL block BB01 as BBF_IMPORTED
impImportBlockPending for BB02
Importing BB02 (PC=000) of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
[ 0] 0 (0x000) nop
STMT00001 (IL 0x000... ???)
[000001] ------------ * NO_OP void
[ 0] 1 (0x001) ldtoken
[ 1] 6 (0x006) call 0A000085
In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0
Calling impNormStructVal on:
[000003] --C-G------- * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000002] H----------- arg0 \--* CNS_INT(h) long 0x7ff93af7cd80 class
lvaGrabTemp returning 10 (V10 tmp1) called for struct address for call/obj.
STMT00002 (IL 0x001... ???)
[000007] -AC-G------- * ASG struct (copy)
[000005] D------N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
[000003] --C-G------- \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000002] H----------- arg0 \--* CNS_INT(h) long 0x7ff93af7cd80 class
resulting tree:
[000010] n----------- * OBJ struct<System.RuntimeTypeHandle, 8>
[000009] ------------ \--* ADDR byref
[000008] -------N---- \--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
lvaGrabTemp returning 11 (V11 tmp2) called for impSpillStackEnsure.
STMT00003 (IL ???... ???)
[000012] -AC-G------- * ASG ref
[000011] D------N---- +--* LCL_VAR ref V11 tmp2
[000004] --C-G------- \--* CALL ref System.Type.GetTypeFromHandle
[000010] n----------- arg0 \--* OBJ struct<System.RuntimeTypeHandle, 8>
[000009] ------------ \--* ADDR byref
[000008] -------N---- \--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
Marked V11 as a single def temp
lvaSetClass: setting class for V11 to (00007FF9388372B0) System.Type
[ 1] 11 (0x00b) ldtoken
[ 2] 16 (0x010) call 0A000085
In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0
Calling impNormStructVal on:
[000015] --C-G------- * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000014] H----------- arg0 \--* CNS_INT(h) long 0x7ff93af7cd80 class
lvaGrabTemp returning 12 (V12 tmp3) called for struct address for call/obj.
STMT00004 (IL 0x00B... ???)
[000019] -AC-G------- * ASG struct (copy)
[000017] D------N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
[000015] --C-G------- \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000014] H----------- arg0 \--* CNS_INT(h) long 0x7ff93af7cd80 class
resulting tree:
[000022] n----------- * OBJ struct<System.RuntimeTypeHandle, 8>
[000021] ------------ \--* ADDR byref
[000020] -------N---- \--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
lvaGrabTemp returning 13 (V13 tmp4) called for impSpillStackEnsure.
STMT00005 (IL ???... ???)
[000024] -AC-G------- * ASG ref
[000023] D------N---- +--* LCL_VAR ref V13 tmp4
[000016] --C-G------- \--* CALL ref System.Type.GetTypeFromHandle
[000022] n----------- arg0 \--* OBJ struct<System.RuntimeTypeHandle, 8>
[000021] ------------ \--* ADDR byref
[000020] -------N---- \--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
Marked V13 as a single def temp
lvaSetClass: setting class for V13 to (00007FF9388372B0) System.Type
[ 2] 21 (0x015) call 0A00011F
In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0
lvaGrabTemp returning 14 (V14 tmp5) called for impSpillStackEnsure.
STMT00006 (IL 0x015... ???)
[000028] -AC-G------- * ASG int
[000027] D------N---- +--* LCL_VAR int V14 tmp5
[000026] --C-G------- \--* CALL int System.Type.op_Equality
[000013] ------------ arg0 +--* LCL_VAR ref V11 tmp2
[000025] ------------ arg1 \--* LCL_VAR ref V13 tmp4
[ 1] 26 (0x01a) brtrue.s
STMT00007 (IL 0x01A... ???)
[000032] ------------ * JTRUE void
[000031] ------------ \--* NE int
[000029] ------------ +--* LCL_VAR int V14 tmp5
[000030] ------------ \--* CNS_INT int 0
impImportBlockPending for BB03
impImportBlockPending for BB04
Importing BB04 (PC=055) of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
[ 0] 55 (0x037) ldc.i4.1 1
*************** In impGetSpillTmpBase(BB04)
lvaGrabTemps(1) returning 15..15 (long lifetime temps) called for IL Stack Entries
*************** In fgComputeCheapPreds()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target
BB02 [0001] 1 1 [000..01C)-> BB04 ( cond ) i
BB03 [0002] 1 1 [01C..037)-> BB05 (always)
BB04 [0003] 1 1 [037..038)
BB05 [0004] 2 1 [038..03C)-> BB09 ( cond )
BB06 [0005] 1 1 [03C..05E)-> BB08 ( cond )
BB07 [0006] 1 1 [05E..069)-> BB12 (always)
BB08 [0007] 1 1 [069..081)-> BB12 (always)
BB09 [0008] 1 1 [081..09E)-> BB11 ( cond )
BB10 [0009] 1 1 [09E..0AA)-> BB12 (always)
BB11 [0010] 1 1 [0AA..0B4)-> BB12 (always)
BB12 [0011] 4 1 [0B4..0B7) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputeCheapPreds()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd cheap preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target
BB02 [0001] 1 BB01 1 [000..01C)-> BB04 ( cond ) i
BB03 [0002] 1 BB02 1 [01C..037)-> BB05 (always)
BB04 [0003] 1 BB02 1 [037..038)
BB05 [0004] 2 BB04,BB03 1 [038..03C)-> BB09 ( cond )
BB06 [0005] 1 BB05 1 [03C..05E)-> BB08 ( cond )
BB07 [0006] 1 BB06 1 [05E..069)-> BB12 (always)
BB08 [0007] 1 BB06 1 [069..081)-> BB12 (always)
BB09 [0008] 1 BB05 1 [081..09E)-> BB11 ( cond )
BB10 [0009] 1 BB09 1 [09E..0AA)-> BB12 (always)
BB11 [0010] 1 BB09 1 [0AA..0B4)-> BB12 (always)
BB12 [0011] 4 BB11,BB10,BB08,BB07 1 [0B4..0B7) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
Spilling stack entries into temps
STMT00008 (IL 0x037... ???)
[000035] -A---------- * ASG int
[000034] D------N---- +--* LCL_VAR int V15 tmp6
[000033] ------------ \--* CNS_INT int 1
impImportBlockPending for BB05
Importing BB05 (PC=056) of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
[ 1] 56 (0x038) stloc.0
STMT00009 (IL ???... ???)
[000039] -A---------- * ASG int
[000038] D------N---- +--* LCL_VAR int V01 loc0
[000037] ------------ \--* LCL_VAR int V15 tmp6
[ 0] 57 (0x039) ldloc.0
[ 1] 58 (0x03a) brfalse.s
STMT00010 (IL 0x039... ???)
[000043] ------------ * JTRUE void
[000042] ------------ \--* EQ int
[000040] ------------ +--* LCL_VAR int V01 loc0
[000041] ------------ \--* CNS_INT int 0
impImportBlockPending for BB06
impImportBlockPending for BB09
Importing BB09 (PC=129) of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
[ 0] 129 (0x081) ldarg.0
[ 1] 130 (0x082) ldfld 0A00048E
[ 1] 135 (0x087) box 1B0000FD
Compiler::impImportAndPushBox -- handling BOX(value class) via helper call because: optimizing for size
[ 1] 140 (0x08c) isinst 02000115
Expanding isinst as call because inline expansion not legal
[ 1] 145 (0x091) stloc.s 6
STMT00011 (IL 0x081... ???)
[000052] -ACXG------- * ASG ref
[000051] D------N---- +--* LCL_VAR ref V07 loc6
[000050] --CXG------- \--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS
[000049] H------N---- arg0 +--* CNS_INT(h) long 0x7ff93b569758 class
[000048] --CXG------- arg1 \--* CALL help ref HELPER.CORINFO_HELP_BOX
[000046] H----------- arg0 +--* CNS_INT(h) long 0x7ff93af7cd80 class
[000047] ---XG------- arg1 \--* ADDR byref
[000045] ---XG--N---- \--* FIELD struct _input
[000044] ------------ \--* LCL_VAR byref V00 this
[ 0] 147 (0x093) ldloc.s 6
[ 1] 149 (0x095) ldnull
[ 2] 150 (0x096) cgt.un
[ 1] 152 (0x098) stloc.s 7
STMT00012 (IL 0x093... ???)
[000057] -A---------- * ASG int
[000056] D------N---- +--* LCL_VAR int V08 loc7
[000055] N--------U-- \--* GT int
[000053] ------------ +--* LCL_VAR ref V07 loc6
[000054] ------------ \--* CNS_INT ref null
[ 0] 154 (0x09a) ldloc.s 7
[ 1] 156 (0x09c) brfalse.s
STMT00013 (IL 0x09A... ???)
[000061] ------------ * JTRUE void
[000060] ------------ \--* EQ int
[000058] ------------ +--* LCL_VAR int V08 loc7
[000059] ------------ \--* CNS_INT int 0
impImportBlockPending for BB10
impImportBlockPending for BB11
Importing BB11 (PC=170) of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
[ 0] 170 (0x0aa) nop
STMT00014 (IL 0x0AA... ???)
[000062] ------------ * NO_OP void
[ 0] 171 (0x0ab) call 2B000141
In Compiler::impImportCall: opcode is call, kind=0, callRetType is ubyte, structSize is 0
lvaGrabTemp returning 16 (V16 tmp7) called for impSpillStackEnsure.
STMT00015 (IL 0x0AB... ???)
[000065] -AC-G------- * ASG int
[000064] D------N---- +--* LCL_VAR int V16 tmp7
[000063] --C-G------- \--* CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].ThrowNotSupportedInput
[ 1] 176 (0x0b0) stloc.s 5
STMT00016 (IL 0x0B0... ???)
[000068] -A---------- * ASG int
[000067] D------N---- +--* LCL_VAR int V06 loc5
[000066] ------------ \--* LCL_VAR int V16 tmp7
[ 0] 178 (0x0b2) br.s
STMT00017 (IL 0x0B2... ???)
[000069] ------------ * NOP void
impImportBlockPending for BB12
Importing BB12 (PC=180) of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
[ 0] 180 (0x0b4) ldloc.s 5
[ 1] 182 (0x0b6) ret
STMT00018 (IL 0x0B4... ???)
[000071] ------------ * RETURN int
[000070] ------------ \--* LCL_VAR int V06 loc5
Importing BB10 (PC=158) of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
[ 0] 158 (0x09e) nop
STMT00019 (IL 0x09E... ???)
[000072] ------------ * NO_OP void
[ 0] 159 (0x09f) ldloc.s 6
[ 1] 161 (0x0a1) callvirt 060004BF
In Compiler::impImportCall: opcode is callvirt, kind=4, callRetType is ubyte, structSize is 0
lvaGrabTemp returning 17 (V17 tmp8) called for impSpillStackEnsure.
STMT00020 (IL 0x09F... ???)
[000076] -AC-G------- * ASG int
[000075] D------N---- +--* LCL_VAR int V17 tmp8
[000074] --C-G------- \--* CALLV ind int Hagar.Buffers.ReaderInput.ReadByte
[000073] ------------ this in rcx \--* LCL_VAR ref V07 loc6
[ 1] 166 (0x0a6) stloc.s 5
STMT00021 (IL 0x0A6... ???)
[000079] -A---------- * ASG int
[000078] D------N---- +--* LCL_VAR int V06 loc5
[000077] ------------ \--* LCL_VAR int V17 tmp8
[ 0] 168 (0x0a8) br.s
STMT00022 (IL 0x0A8... ???)
[000080] ------------ * NOP void
impImportBlockPending for BB12
Importing BB06 (PC=060) of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
[ 0] 60 (0x03c) nop
STMT00023 (IL 0x03C... ???)
[000081] ------------ * NO_OP void
[ 0] 61 (0x03d) ldarg.0
[ 1] 62 (0x03e) ldfld 0A000493
[ 1] 67 (0x043) stloc.1
STMT00024 (IL 0x03D... ???)
[000085] -A-XG------- * ASG int
[000084] D------N---- +--* LCL_VAR int V02 loc1
[000083] ---XG------- \--* FIELD int _bufferPos
[000082] ------------ \--* LCL_VAR byref V00 this
[ 0] 68 (0x044) ldarg.0
[ 1] 69 (0x045) ldfld 0A000492
[ 1] 74 (0x04a) stloc.2
STMT00025 (IL 0x044... ???)
[000090] -A-XG------- * ASG struct (copy)
[000088] D------N---- +--* LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16> V03 loc2
[000087] ---XG------- \--* FIELD struct _currentSpan
[000086] ------------ \--* LCL_VAR byref V00 this
[ 0] 75 (0x04b) ldloc.1
[ 1] 76 (0x04c) ldloca.s 2
[ 2] 78 (0x04e) call 0A000124
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
lvaGrabTemp returning 18 (V18 tmp9) called for impSpillStackEnsure.
STMT00026 (IL 0x04B... ???)
[000096] -A---------- * ASG int
[000095] D------N---- +--* LCL_VAR int V18 tmp9
[000091] ------------ \--* LCL_VAR int V02 loc1
lvaGrabTemp returning 19 (V19 tmp10) called for impSpillStackEnsure.
STMT00027 (IL ???... ???)
[000099] -AC-G------- * ASG int
[000098] D------N---- +--* LCL_VAR int V19 tmp10
[000094] --C-G------- \--* CALL int System.ReadOnlySpan`1[Byte][System.Byte].get_Length
[000093] ------------ this in rcx \--* ADDR byref
[000092] -------N---- \--* LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16> V03 loc2
[ 2] 83 (0x053) clt.un
[ 1] 85 (0x055) ldc.i4.0 0
[ 2] 86 (0x056) ceq
[ 1] 88 (0x058) stloc.s 4
STMT00028 (IL 0x053... ???)
[000105] -A---------- * ASG int
[000104] D------N---- +--* LCL_VAR int V05 loc4
[000103] ------------ \--* EQ int
[000101] N--------U-- +--* LT int
[000097] ------------ | +--* LCL_VAR int V18 tmp9
[000100] ------------ | \--* LCL_VAR int V19 tmp10
[000102] ------------ \--* CNS_INT int 0
[ 0] 90 (0x05a) ldloc.s 4
[ 1] 92 (0x05c) brfalse.s
STMT00029 (IL 0x05A... ???)
[000109] ------------ * JTRUE void
[000108] ------------ \--* EQ int
[000106] ------------ +--* LCL_VAR int V05 loc4
[000107] ------------ \--* CNS_INT int 0
impImportBlockPending for BB07
impImportBlockPending for BB08
Importing BB08 (PC=105) of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
[ 0] 105 (0x069) ldloca.s 2
[ 1] 107 (0x06b) ldloc.1
[ 2] 108 (0x06c) call 0A0001AC
In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0
lvaGrabTemp returning 20 (V20 tmp11) called for impSpillStackEnsure.
STMT00030 (IL 0x069... ???)
[000115] -AC-G------- * ASG byref
[000114] D------N---- +--* LCL_VAR byref V20 tmp11
[000113] --C-G------- \--* CALL byref System.ReadOnlySpan`1[Byte][System.Byte].get_Item
[000111] ------------ this in rcx +--* ADDR byref
[000110] -------N---- | \--* LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16> V03 loc2
[000112] ------------ arg1 \--* LCL_VAR int V02 loc1
[ 1] 113 (0x071) ldind.u1
[ 1] 114 (0x072) stloc.3
STMT00031 (IL 0x071... ???)
[000119] -A-XG------- * ASG int
[000118] D------N---- +--* LCL_VAR int V04 loc3
[000117] *--XG------- \--* IND ubyte
[000116] ------------ \--* LCL_VAR byref V20 tmp11
[ 0] 115 (0x073) ldarg.0
[ 1] 116 (0x074) ldloc.1
[ 2] 117 (0x075) ldc.i4.1 1
[ 3] 118 (0x076) add
[ 2] 119 (0x077) stfld 0A000493
STMT00032 (IL 0x073... ???)
[000125] -A-XG------- * ASG int
[000124] ---XG--N---- +--* FIELD int _bufferPos
[000120] ------------ | \--* LCL_VAR byref V00 this
[000123] ------------ \--* ADD int
[000121] ------------ +--* LCL_VAR int V02 loc1
[000122] ------------ \--* CNS_INT int 1
[ 0] 124 (0x07c) ldloc.3
[ 1] 125 (0x07d) stloc.s 5
STMT00033 (IL 0x07C... ???)
[000128] -A---------- * ASG int
[000127] D------N---- +--* LCL_VAR int V06 loc5
[000126] ------------ \--* LCL_VAR int V04 loc3
[ 0] 127 (0x07f) br.s
STMT00034 (IL 0x07F... ???)
[000129] ------------ * NOP void
impImportBlockPending for BB12
Importing BB07 (PC=094) of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
[ 0] 94 (0x05e) nop
STMT00035 (IL 0x05E... ???)
[000130] ------------ * NO_OP void
[ 0] 95 (0x05f) ldarg.0
[ 1] 96 (0x060) call 0A0004A6
In Compiler::impImportCall: opcode is call, kind=0, callRetType is ubyte, structSize is 0
lvaGrabTemp returning 21 (V21 tmp12) called for impSpillStackEnsure.
STMT00036 (IL 0x05F... ???)
[000134] -AC-G------- * ASG int
[000133] D------N---- +--* LCL_VAR int V21 tmp12
[000132] --C-G------- \--* CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].<ReadByte>g__ReadByteSlow|18_0
[000131] ------------ arg0 \--* LCL_VAR byref V00 this
[ 1] 101 (0x065) stloc.s 5
STMT00037 (IL 0x065... ???)
[000137] -A---------- * ASG int
[000136] D------N---- +--* LCL_VAR int V06 loc5
[000135] ------------ \--* LCL_VAR int V21 tmp12
[ 0] 103 (0x067) br.s
STMT00038 (IL 0x067... ???)
[000138] ------------ * NOP void
impImportBlockPending for BB12
Importing BB03 (PC=028) of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
[ 0] 28 (0x01c) ldtoken
[ 1] 33 (0x021) call 0A000085
In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0
Calling impNormStructVal on:
[000140] --C-G------- * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000139] H----------- arg0 \--* CNS_INT(h) long 0x7ff93af7cd80 class
lvaGrabTemp returning 22 (V22 tmp13) called for struct address for call/obj.
STMT00039 (IL 0x01C... ???)
[000144] -AC-G------- * ASG struct (copy)
[000142] D------N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
[000140] --C-G------- \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000139] H----------- arg0 \--* CNS_INT(h) long 0x7ff93af7cd80 class
resulting tree:
[000147] n----------- * OBJ struct<System.RuntimeTypeHandle, 8>
[000146] ------------ \--* ADDR byref
[000145] -------N---- \--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
lvaGrabTemp returning 23 (V23 tmp14) called for impSpillStackEnsure.
STMT00040 (IL ???... ???)
[000149] -AC-G------- * ASG ref
[000148] D------N---- +--* LCL_VAR ref V23 tmp14
[000141] --C-G------- \--* CALL ref System.Type.GetTypeFromHandle
[000147] n----------- arg0 \--* OBJ struct<System.RuntimeTypeHandle, 8>
[000146] ------------ \--* ADDR byref
[000145] -------N---- \--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
Marked V23 as a single def temp
lvaSetClass: setting class for V23 to (00007FF9388372B0) System.Type
[ 1] 38 (0x026) ldtoken
[ 2] 43 (0x02b) call 0A000085
In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0
Calling impNormStructVal on:
[000152] --C-G------- * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000151] H----------- arg0 \--* CNS_INT(h) long 0x7ff93b56a7f8 class
lvaGrabTemp returning 24 (V24 tmp15) called for struct address for call/obj.
STMT00041 (IL 0x026... ???)
[000156] -AC-G------- * ASG struct (copy)
[000154] D------N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
[000152] --C-G------- \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000151] H----------- arg0 \--* CNS_INT(h) long 0x7ff93b56a7f8 class
resulting tree:
[000159] n----------- * OBJ struct<System.RuntimeTypeHandle, 8>
[000158] ------------ \--* ADDR byref
[000157] -------N---- \--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
lvaGrabTemp returning 25 (V25 tmp16) called for impSpillStackEnsure.
STMT00042 (IL ???... ???)
[000161] -AC-G------- * ASG ref
[000160] D------N---- +--* LCL_VAR ref V25 tmp16
[000153] --C-G------- \--* CALL ref System.Type.GetTypeFromHandle
[000159] n----------- arg0 \--* OBJ struct<System.RuntimeTypeHandle, 8>
[000158] ------------ \--* ADDR byref
[000157] -------N---- \--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
Marked V25 as a single def temp
lvaSetClass: setting class for V25 to (00007FF9388372B0) System.Type
[ 2] 48 (0x030) call 0A00011F
In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0
lvaGrabTemp returning 26 (V26 tmp17) called for impSpillStackEnsure.
STMT00043 (IL 0x030... ???)
[000165] -AC-G------- * ASG int
[000164] D------N---- +--* LCL_VAR int V26 tmp17
[000163] --C-G------- \--* CALL int System.Type.op_Equality
[000150] ------------ arg0 +--* LCL_VAR ref V23 tmp14
[000162] ------------ arg1 \--* LCL_VAR ref V25 tmp16
[ 1] 53 (0x035) br.s
STMT00044 (IL 0x035... ???)
[000167] ------------ * NOP void
Spilling stack entries into temps
STMT00045 (IL ???... ???)
[000169] -A---------- * ASG int
[000168] D------N---- +--* LCL_VAR int V15 tmp6
[000166] ------------ \--* LCL_VAR int V26 tmp17
impImportBlockPending for BB05
*************** Finishing PHASE Importation
Trees after Importation
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target
BB02 [0001] 1 1 [000..01C)-> BB04 ( cond ) i
BB03 [0002] 1 1 [01C..037)-> BB05 (always) i
BB04 [0003] 1 1 [037..038) i
BB05 [0004] 2 1 [038..03C)-> BB09 ( cond ) i
BB06 [0005] 1 1 [03C..05E)-> BB08 ( cond ) i
BB07 [0006] 1 1 [05E..069)-> BB12 (always) i
BB08 [0007] 1 1 [069..081)-> BB12 (always) i
BB09 [0008] 1 1 [081..09E)-> BB11 ( cond ) i
BB10 [0009] 1 1 [09E..0AA)-> BB12 (always) i
BB11 [0010] 1 1 [0AA..0B4)-> BB12 (always) i
BB12 [0011] 4 1 [0B4..0B7) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
***** BB01
STMT00000 (IL ???... ???)
[000000] ------------ * NOP void
------------ BB02 [000..01C) -> BB04 (cond), preds={} succs={BB03,BB04}
***** BB02
STMT00001 (IL 0x000...0x000)
[000001] ------------ * NO_OP void
***** BB02
STMT00002 (IL 0x001...0x01A)
[000007] -AC-G------- * ASG struct (copy)
[000005] D------N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
[000003] --C-G------- \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000002] H----------- arg0 \--* CNS_INT(h) long 0x7ff93af7cd80 class
***** BB02
STMT00003 (IL ???... ???)
[000012] -AC-G------- * ASG ref
[000011] D------N---- +--* LCL_VAR ref V11 tmp2
[000004] --C-G------- \--* CALL ref System.Type.GetTypeFromHandle
[000010] n----------- arg0 \--* OBJ struct<System.RuntimeTypeHandle, 8>
[000009] ------------ \--* ADDR byref
[000008] -------N---- \--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
***** BB02
STMT00004 (IL 0x00B... ???)
[000019] -AC-G------- * ASG struct (copy)
[000017] D------N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
[000015] --C-G------- \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000014] H----------- arg0 \--* CNS_INT(h) long 0x7ff93af7cd80 class
***** BB02
STMT00005 (IL ???... ???)
[000024] -AC-G------- * ASG ref
[000023] D------N---- +--* LCL_VAR ref V13 tmp4
[000016] --C-G------- \--* CALL ref System.Type.GetTypeFromHandle
[000022] n----------- arg0 \--* OBJ struct<System.RuntimeTypeHandle, 8>
[000021] ------------ \--* ADDR byref
[000020] -------N---- \--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
***** BB02
STMT00006 (IL 0x015... ???)
[000028] -AC-G------- * ASG int
[000027] D------N---- +--* LCL_VAR int V14 tmp5
[000026] --C-G------- \--* CALL int System.Type.op_Equality
[000013] ------------ arg0 +--* LCL_VAR ref V11 tmp2
[000025] ------------ arg1 \--* LCL_VAR ref V13 tmp4
***** BB02
STMT00007 (IL 0x01A... ???)
[000032] ------------ * JTRUE void
[000031] ------------ \--* NE int
[000029] ------------ +--* LCL_VAR int V14 tmp5
[000030] ------------ \--* CNS_INT int 0
------------ BB03 [01C..037) -> BB05 (always), preds={} succs={BB05}
***** BB03
STMT00039 (IL 0x01C...0x035)
[000144] -AC-G------- * ASG struct (copy)
[000142] D------N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
[000140] --C-G------- \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000139] H----------- arg0 \--* CNS_INT(h) long 0x7ff93af7cd80 class
***** BB03
STMT00040 (IL ???... ???)
[000149] -AC-G------- * ASG ref
[000148] D------N---- +--* LCL_VAR ref V23 tmp14
[000141] --C-G------- \--* CALL ref System.Type.GetTypeFromHandle
[000147] n----------- arg0 \--* OBJ struct<System.RuntimeTypeHandle, 8>
[000146] ------------ \--* ADDR byref
[000145] -------N---- \--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
***** BB03
STMT00041 (IL 0x026... ???)
[000156] -AC-G------- * ASG struct (copy)
[000154] D------N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
[000152] --C-G------- \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000151] H----------- arg0 \--* CNS_INT(h) long 0x7ff93b56a7f8 class
***** BB03
STMT00042 (IL ???... ???)
[000161] -AC-G------- * ASG ref
[000160] D------N---- +--* LCL_VAR ref V25 tmp16
[000153] --C-G------- \--* CALL ref System.Type.GetTypeFromHandle
[000159] n----------- arg0 \--* OBJ struct<System.RuntimeTypeHandle, 8>
[000158] ------------ \--* ADDR byref
[000157] -------N---- \--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
***** BB03
STMT00043 (IL 0x030... ???)
[000165] -AC-G------- * ASG int
[000164] D------N---- +--* LCL_VAR int V26 tmp17
[000163] --C-G------- \--* CALL int System.Type.op_Equality
[000150] ------------ arg0 +--* LCL_VAR ref V23 tmp14
[000162] ------------ arg1 \--* LCL_VAR ref V25 tmp16
***** BB03
STMT00044 (IL 0x035... ???)
[000167] ------------ * NOP void
***** BB03
STMT00045 (IL ???... ???)
[000169] -A---------- * ASG int
[000168] D------N---- +--* LCL_VAR int V15 tmp6
[000166] ------------ \--* LCL_VAR int V26 tmp17
------------ BB04 [037..038), preds={} succs={BB05}
***** BB04
STMT00008 (IL 0x037...0x037)
[000035] -A---------- * ASG int
[000034] D------N---- +--* LCL_VAR int V15 tmp6
[000033] ------------ \--* CNS_INT int 1
------------ BB05 [038..03C) -> BB09 (cond), preds={} succs={BB06,BB09}
***** BB05
STMT00009 (IL ???...0x038)
[000039] -A---------- * ASG int
[000038] D------N---- +--* LCL_VAR int V01 loc0
[000037] ------------ \--* LCL_VAR int V15 tmp6
***** BB05
STMT00010 (IL 0x039...0x03A)
[000043] ------------ * JTRUE void
[000042] ------------ \--* EQ int
[000040] ------------ +--* LCL_VAR int V01 loc0
[000041] ------------ \--* CNS_INT int 0
------------ BB06 [03C..05E) -> BB08 (cond), preds={} succs={BB07,BB08}
***** BB06
STMT00023 (IL 0x03C...0x03C)
[000081] ------------ * NO_OP void
***** BB06
STMT00024 (IL 0x03D...0x043)
[000085] -A-XG------- * ASG int
[000084] D------N---- +--* LCL_VAR int V02 loc1
[000083] ---XG------- \--* FIELD int _bufferPos
[000082] ------------ \--* LCL_VAR byref V00 this
***** BB06
STMT00025 (IL 0x044...0x04A)
[000090] -A-XG------- * ASG struct (copy)
[000088] D------N---- +--* LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16> V03 loc2
[000087] ---XG------- \--* FIELD struct _currentSpan
[000086] ------------ \--* LCL_VAR byref V00 this
***** BB06
STMT00026 (IL 0x04B...0x058)
[000096] -A---------- * ASG int
[000095] D------N---- +--* LCL_VAR int V18 tmp9
[000091] ------------ \--* LCL_VAR int V02 loc1
***** BB06
STMT00027 (IL ???... ???)
[000099] -AC-G------- * ASG int
[000098] D------N---- +--* LCL_VAR int V19 tmp10
[000094] --C-G------- \--* CALL int System.ReadOnlySpan`1[Byte][System.Byte].get_Length
[000093] ------------ this in rcx \--* ADDR byref
[000092] -------N---- \--* LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16> V03 loc2
***** BB06
STMT00028 (IL 0x053... ???)
[000105] -A---------- * ASG int
[000104] D------N---- +--* LCL_VAR int V05 loc4
[000103] ------------ \--* EQ int
[000101] N--------U-- +--* LT int
[000097] ------------ | +--* LCL_VAR int V18 tmp9
[000100] ------------ | \--* LCL_VAR int V19 tmp10
[000102] ------------ \--* CNS_INT int 0
***** BB06
STMT00029 (IL 0x05A...0x05C)
[000109] ------------ * JTRUE void
[000108] ------------ \--* EQ int
[000106] ------------ +--* LCL_VAR int V05 loc4
[000107] ------------ \--* CNS_INT int 0
------------ BB07 [05E..069) -> BB12 (always), preds={} succs={BB12}
***** BB07
STMT00035 (IL 0x05E...0x05E)
[000130] ------------ * NO_OP void
***** BB07
STMT00036 (IL 0x05F...0x065)
[000134] -AC-G------- * ASG int
[000133] D------N---- +--* LCL_VAR int V21 tmp12
[000132] --C-G------- \--* CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].<ReadByte>g__ReadByteSlow|18_0
[000131] ------------ arg0 \--* LCL_VAR byref V00 this
***** BB07
STMT00037 (IL 0x065... ???)
[000137] -A---------- * ASG int
[000136] D------N---- +--* LCL_VAR int V06 loc5
[000135] ------------ \--* LCL_VAR int V21 tmp12
***** BB07
STMT00038 (IL 0x067...0x067)
[000138] ------------ * NOP void
------------ BB08 [069..081) -> BB12 (always), preds={} succs={BB12}
***** BB08
STMT00030 (IL 0x069...0x072)
[000115] -AC-G------- * ASG byref
[000114] D------N---- +--* LCL_VAR byref V20 tmp11
[000113] --C-G------- \--* CALL byref System.ReadOnlySpan`1[Byte][System.Byte].get_Item
[000111] ------------ this in rcx +--* ADDR byref
[000110] -------N---- | \--* LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16> V03 loc2
[000112] ------------ arg1 \--* LCL_VAR int V02 loc1
***** BB08
STMT00031 (IL 0x071... ???)
[000119] -A-XG------- * ASG int
[000118] D------N---- +--* LCL_VAR int V04 loc3
[000117] *--XG------- \--* IND ubyte
[000116] ------------ \--* LCL_VAR byref V20 tmp11
***** BB08
STMT00032 (IL 0x073...0x077)
[000125] -A-XG------- * ASG int
[000124] ---XG--N---- +--* FIELD int _bufferPos
[000120] ------------ | \--* LCL_VAR byref V00 this
[000123] ------------ \--* ADD int
[000121] ------------ +--* LCL_VAR int V02 loc1
[000122] ------------ \--* CNS_INT int 1
***** BB08
STMT00033 (IL 0x07C...0x07D)
[000128] -A---------- * ASG int
[000127] D------N---- +--* LCL_VAR int V06 loc5
[000126] ------------ \--* LCL_VAR int V04 loc3
***** BB08
STMT00034 (IL 0x07F...0x07F)
[000129] ------------ * NOP void
------------ BB09 [081..09E) -> BB11 (cond), preds={} succs={BB10,BB11}
***** BB09
STMT00011 (IL 0x081...0x091)
[000052] -ACXG------- * ASG ref
[000051] D------N---- +--* LCL_VAR ref V07 loc6
[000050] --CXG------- \--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS
[000049] H------N---- arg0 +--* CNS_INT(h) long 0x7ff93b569758 class
[000048] --CXG------- arg1 \--* CALL help ref HELPER.CORINFO_HELP_BOX
[000046] H----------- arg0 +--* CNS_INT(h) long 0x7ff93af7cd80 class
[000047] ---XG------- arg1 \--* ADDR byref
[000045] ---XG--N---- \--* FIELD struct _input
[000044] ------------ \--* LCL_VAR byref V00 this
***** BB09
STMT00012 (IL 0x093...0x098)
[000057] -A---------- * ASG int
[000056] D------N---- +--* LCL_VAR int V08 loc7
[000055] N--------U-- \--* GT int
[000053] ------------ +--* LCL_VAR ref V07 loc6
[000054] ------------ \--* CNS_INT ref null
***** BB09
STMT00013 (IL 0x09A...0x09C)
[000061] ------------ * JTRUE void
[000060] ------------ \--* EQ int
[000058] ------------ +--* LCL_VAR int V08 loc7
[000059] ------------ \--* CNS_INT int 0
------------ BB10 [09E..0AA) -> BB12 (always), preds={} succs={BB12}
***** BB10
STMT00019 (IL 0x09E...0x09E)
[000072] ------------ * NO_OP void
***** BB10
STMT00020 (IL 0x09F...0x0A6)
[000076] -AC-G------- * ASG int
[000075] D------N---- +--* LCL_VAR int V17 tmp8
[000074] --C-G------- \--* CALLV ind int Hagar.Buffers.ReaderInput.ReadByte
[000073] ------------ this in rcx \--* LCL_VAR ref V07 loc6
***** BB10
STMT00021 (IL 0x0A6... ???)
[000079] -A---------- * ASG int
[000078] D------N---- +--* LCL_VAR int V06 loc5
[000077] ------------ \--* LCL_VAR int V17 tmp8
***** BB10
STMT00022 (IL 0x0A8...0x0A8)
[000080] ------------ * NOP void
------------ BB11 [0AA..0B4) -> BB12 (always), preds={} succs={BB12}
***** BB11
STMT00014 (IL 0x0AA...0x0AA)
[000062] ------------ * NO_OP void
***** BB11
STMT00015 (IL 0x0AB...0x0B0)
[000065] -AC-G------- * ASG int
[000064] D------N---- +--* LCL_VAR int V16 tmp7
[000063] --C-G------- \--* CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].ThrowNotSupportedInput
***** BB11
STMT00016 (IL 0x0B0... ???)
[000068] -A---------- * ASG int
[000067] D------N---- +--* LCL_VAR int V06 loc5
[000066] ------------ \--* LCL_VAR int V16 tmp7
***** BB11
STMT00017 (IL 0x0B2...0x0B2)
[000069] ------------ * NOP void
------------ BB12 [0B4..0B7) (return), preds={} succs={}
***** BB12
STMT00018 (IL 0x0B4...0x0B6)
[000071] ------------ * RETURN int
[000070] ------------ \--* LCL_VAR int V06 loc5
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Indirect call transform
-- no candidates to transform
*************** Finishing PHASE Indirect call transform [no changes]
*************** Starting PHASE Expand patchpoints
-- no patchpoints to transform
*************** Finishing PHASE Expand patchpoints [no changes]
*************** Starting PHASE Post-import
*************** Finishing PHASE Post-import
*************** Starting PHASE Morph - Init
New BlockSet epoch 1, # of blocks (including unused BB00): 13, bitset array size: 1 (short)
*************** In fgRemoveEmptyBlocks
*************** Finishing PHASE Morph - Init
*************** In fgDebugCheckBBlist
*************** Starting PHASE Morph - Inlining
*************** Finishing PHASE Morph - Inlining [no changes]
*************** Starting PHASE Allocate Objects
no newobjs in this method; punting
*************** Finishing PHASE Allocate Objects [no changes]
*************** Starting PHASE Morph - Add internal blocks
*************** After fgAddInternal()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target
BB02 [0001] 1 1 [000..01C)-> BB04 ( cond ) i
BB03 [0002] 1 1 [01C..037)-> BB05 (always) i
BB04 [0003] 1 1 [037..038) i
BB05 [0004] 2 1 [038..03C)-> BB09 ( cond ) i
BB06 [0005] 1 1 [03C..05E)-> BB08 ( cond ) i
BB07 [0006] 1 1 [05E..069)-> BB12 (always) i
BB08 [0007] 1 1 [069..081)-> BB12 (always) i
BB09 [0008] 1 1 [081..09E)-> BB11 ( cond ) i
BB10 [0009] 1 1 [09E..0AA)-> BB12 (always) i
BB11 [0010] 1 1 [0AA..0B4)-> BB12 (always) i
BB12 [0011] 4 1 [0B4..0B7) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** Finishing PHASE Morph - Add internal blocks
*************** Starting PHASE Remove empty try
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try [no changes]
*************** Starting PHASE Remove empty finally
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally [no changes]
*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.
*************** Finishing PHASE Merge callfinally chains [no changes]
*************** Starting PHASE Clone finally
No EH in this method, no cloning.
*************** Finishing PHASE Clone finally [no changes]
*************** Starting PHASE Compute preds
Renumbering the basic blocks for fgComputePred
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target
BB02 [0001] 1 1 [000..01C)-> BB04 ( cond ) i
BB03 [0002] 1 1 [01C..037)-> BB05 (always) i
BB04 [0003] 1 1 [037..038) i
BB05 [0004] 2 1 [038..03C)-> BB09 ( cond ) i
BB06 [0005] 1 1 [03C..05E)-> BB08 ( cond ) i
BB07 [0006] 1 1 [05E..069)-> BB12 (always) i
BB08 [0007] 1 1 [069..081)-> BB12 (always) i
BB09 [0008] 1 1 [081..09E)-> BB11 ( cond ) i
BB10 [0009] 1 1 [09E..0AA)-> BB12 (always) i
BB11 [0010] 1 1 [0AA..0B4)-> BB12 (always) i
BB12 [0011] 4 1 [0B4..0B7) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
*************** In fgComputePreds()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target
BB02 [0001] 1 1 [000..01C)-> BB04 ( cond ) i
BB03 [0002] 1 1 [01C..037)-> BB05 (always) i
BB04 [0003] 1 1 [037..038) i
BB05 [0004] 2 1 [038..03C)-> BB09 ( cond ) i
BB06 [0005] 1 1 [03C..05E)-> BB08 ( cond ) i
BB07 [0006] 1 1 [05E..069)-> BB12 (always) i
BB08 [0007] 1 1 [069..081)-> BB12 (always) i
BB09 [0008] 1 1 [081..09E)-> BB11 ( cond ) i
BB10 [0009] 1 1 [09E..0AA)-> BB12 (always) i
BB11 [0010] 1 1 [0AA..0B4)-> BB12 (always) i
BB12 [0011] 4 1 [0B4..0B7) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputePreds()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target
BB02 [0001] 1 BB01 1 [000..01C)-> BB04 ( cond ) i
BB03 [0002] 1 BB02 1 [01C..037)-> BB05 (always) i
BB04 [0003] 1 BB02 1 [037..038) i label target
BB05 [0004] 2 BB03,BB04 1 [038..03C)-> BB09 ( cond ) i label target
BB06 [0005] 1 BB05 1 [03C..05E)-> BB08 ( cond ) i
BB07 [0006] 1 BB06 1 [05E..069)-> BB12 (always) i
BB08 [0007] 1 BB06 1 [069..081)-> BB12 (always) i label target
BB09 [0008] 1 BB05 1 [081..09E)-> BB11 ( cond ) i label target
BB10 [0009] 1 BB09 1 [09E..0AA)-> BB12 (always) i
BB11 [0010] 1 BB09 1 [0AA..0B4)-> BB12 (always) i label target
BB12 [0011] 4 BB07,BB08,BB10,BB11 1 [0B4..0B7) (return) i label target
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Compute preds
*************** Starting PHASE Morph - Promote Structs
*************** In fgResetImplicitByRefRefCount()
*************** In fgPromoteStructs()
promotion opt flag not enabled
*************** Finishing PHASE Morph - Promote Structs
*************** Starting PHASE Morph - Structs/AddrExp
*************** In fgMarkAddressExposedLocals()
LocalAddressVisitor visiting statement:
STMT00000 (IL ???... ???)
[000000] ------------ * NOP void
LocalAddressVisitor visiting statement:
STMT00046 (IL ???... ???)
[000178] --C-G------- * QMARK void
[000174] Q----------- if +--* EQ int
[000172] ------------ | +--* IND int
[000171] H----------- | | \--* CNS_INT(h) long 0x7ff9392a5420 global ptr
[000173] ------------ | \--* CNS_INT int 0
[000177] --C-G------- if \--* COLON void
[000175] --C-G------- else +--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
[000176] ------------ then \--* NOP void
LocalAddressVisitor visiting statement:
STMT00001 (IL 0x000...0x000)
[000001] ------------ * NO_OP void
LocalAddressVisitor visiting statement:
STMT00002 (IL 0x001...0x01A)
[000007] -AC-G------- * ASG struct (copy)
[000005] D------N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
[000003] --C-G------- \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000002] H----------- arg0 \--* CNS_INT(h) long 0x7ff93af7cd80 class
LocalAddressVisitor visiting statement:
STMT00003 (IL ???... ???)
[000012] -AC-G------- * ASG ref
[000011] D------N---- +--* LCL_VAR ref V11 tmp2
[000004] --C-G------- \--* CALL ref System.Type.GetTypeFromHandle
[000010] n----------- arg0 \--* OBJ struct<System.RuntimeTypeHandle, 8>
[000009] ------------ \--* ADDR byref
[000008] -------N---- \--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
LocalAddressVisitor visiting statement:
STMT00004 (IL 0x00B... ???)
[000019] -AC-G------- * ASG struct (copy)
[000017] D------N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
[000015] --C-G------- \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000014] H----------- arg0 \--* CNS_INT(h) long 0x7ff93af7cd80 class
LocalAddressVisitor visiting statement:
STMT00005 (IL ???... ???)
[000024] -AC-G------- * ASG ref
[000023] D------N---- +--* LCL_VAR ref V13 tmp4
[000016] --C-G------- \--* CALL ref System.Type.GetTypeFromHandle
[000022] n----------- arg0 \--* OBJ struct<System.RuntimeTypeHandle, 8>
[000021] ------------ \--* ADDR byref
[000020] -------N---- \--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
LocalAddressVisitor visiting statement:
STMT00006 (IL 0x015... ???)
[000028] -AC-G------- * ASG int
[000027] D------N---- +--* LCL_VAR int V14 tmp5
[000026] --C-G------- \--* CALL int System.Type.op_Equality
[000013] ------------ arg0 +--* LCL_VAR ref V11 tmp2
[000025] ------------ arg1 \--* LCL_VAR ref V13 tmp4
LocalAddressVisitor visiting statement:
STMT00007 (IL 0x01A... ???)
[000032] ------------ * JTRUE void
[000031] ------------ \--* NE int
[000029] ------------ +--* LCL_VAR int V14 tmp5
[000030] ------------ \--* CNS_INT int 0
LocalAddressVisitor visiting statement:
STMT00039 (IL 0x01C...0x035)
[000144] -AC-G------- * ASG struct (copy)
[000142] D------N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
[000140] --C-G------- \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000139] H----------- arg0 \--* CNS_INT(h) long 0x7ff93af7cd80 class
LocalAddressVisitor visiting statement:
STMT00040 (IL ???... ???)
[000149] -AC-G------- * ASG ref
[000148] D------N---- +--* LCL_VAR ref V23 tmp14
[000141] --C-G------- \--* CALL ref System.Type.GetTypeFromHandle
[000147] n----------- arg0 \--* OBJ struct<System.RuntimeTypeHandle, 8>
[000146] ------------ \--* ADDR byref
[000145] -------N---- \--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
LocalAddressVisitor visiting statement:
STMT00041 (IL 0x026... ???)
[000156] -AC-G------- * ASG struct (copy)
[000154] D------N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
[000152] --C-G------- \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000151] H----------- arg0 \--* CNS_INT(h) long 0x7ff93b56a7f8 class
LocalAddressVisitor visiting statement:
STMT00042 (IL ???... ???)
[000161] -AC-G------- * ASG ref
[000160] D------N---- +--* LCL_VAR ref V25 tmp16
[000153] --C-G------- \--* CALL ref System.Type.GetTypeFromHandle
[000159] n----------- arg0 \--* OBJ struct<System.RuntimeTypeHandle, 8>
[000158] ------------ \--* ADDR byref
[000157] -------N---- \--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
LocalAddressVisitor visiting statement:
STMT00043 (IL 0x030... ???)
[000165] -AC-G------- * ASG int
[000164] D------N---- +--* LCL_VAR int V26 tmp17
[000163] --C-G------- \--* CALL int System.Type.op_Equality
[000150] ------------ arg0 +--* LCL_VAR ref V23 tmp14
[000162] ------------ arg1 \--* LCL_VAR ref V25 tmp16
LocalAddressVisitor visiting statement:
STMT00044 (IL 0x035... ???)
[000167] ------------ * NOP void
LocalAddressVisitor visiting statement:
STMT00045 (IL ???... ???)
[000169] -A---------- * ASG int
[000168] D------N---- +--* LCL_VAR int V15 tmp6
[000166] ------------ \--* LCL_VAR int V26 tmp17
LocalAddressVisitor visiting statement:
STMT00008 (IL 0x037...0x037)
[000035] -A---------- * ASG int
[000034] D------N---- +--* LCL_VAR int V15 tmp6
[000033] ------------ \--* CNS_INT int 1
LocalAddressVisitor visiting statement:
STMT00009 (IL ???...0x038)
[000039] -A---------- * ASG int
[000038] D------N---- +--* LCL_VAR int V01 loc0
[000037] ------------ \--* LCL_VAR int V15 tmp6
LocalAddressVisitor visiting statement:
STMT00010 (IL 0x039...0x03A)
[000043] ------------ * JTRUE void
[000042] ------------ \--* EQ int
[000040] ------------ +--* LCL_VAR int V01 loc0
[000041] ------------ \--* CNS_INT int 0
LocalAddressVisitor visiting statement:
STMT00023 (IL 0x03C...0x03C)
[000081] ------------ * NO_OP void
LocalAddressVisitor visiting statement:
STMT00024 (IL 0x03D...0x043)
[000085] -A-XG------- * ASG int
[000084] D------N---- +--* LCL_VAR int V02 loc1
[000083] ---XG------- \--* FIELD int _bufferPos
[000082] ------------ \--* LCL_VAR byref V00 this
LocalAddressVisitor visiting statement:
STMT00025 (IL 0x044...0x04A)
[000090] -A-XG------- * ASG struct (copy)
[000088] D------N---- +--* LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16> V03 loc2
[000087] ---XG------- \--* FIELD struct _currentSpan
[000086] ------------ \--* LCL_VAR byref V00 this
LocalAddressVisitor visiting statement:
STMT00026 (IL 0x04B...0x058)
[000096] -A---------- * ASG int
[000095] D------N---- +--* LCL_VAR int V18 tmp9
[000091] ------------ \--* LCL_VAR int V02 loc1
LocalAddressVisitor visiting statement:
STMT00027 (IL ???... ???)
[000099] -AC-G------- * ASG int
[000098] D------N---- +--* LCL_VAR int V19 tmp10
[000094] --C-G------- \--* CALL int System.ReadOnlySpan`1[Byte][System.Byte].get_Length
[000093] ------------ this in rcx \--* ADDR byref
[000092] -------N---- \--* LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16> V03 loc2
Local V03 should not be enregistered because: it is address exposed
LocalAddressVisitor modified statement:
STMT00027 (IL ???... ???)
[000099] -AC-G------- * ASG int
[000098] D------N---- +--* LCL_VAR int V19 tmp10
[000094] --C-G------- \--* CALL int System.ReadOnlySpan`1[Byte][System.Byte].get_Length
[000093] ------------ this in rcx \--* LCL_VAR_ADDR byref V03 loc2
LocalAddressVisitor visiting statement:
STMT00028 (IL 0x053... ???)
[000105] -A---------- * ASG int
[000104] D------N---- +--* LCL_VAR int V05 loc4
[000103] ------------ \--* EQ int
[000101] N--------U-- +--* LT int
[000097] ------------ | +--* LCL_VAR int V18 tmp9
[000100] ------------ | \--* LCL_VAR int V19 tmp10
[000102] ------------ \--* CNS_INT int 0
LocalAddressVisitor visiting statement:
STMT00029 (IL 0x05A...0x05C)
[000109] ------------ * JTRUE void
[000108] ------------ \--* EQ int
[000106] ------------ +--* LCL_VAR int V05 loc4
[000107] ------------ \--* CNS_INT int 0
LocalAddressVisitor visiting statement:
STMT00035 (IL 0x05E...0x05E)
[000130] ------------ * NO_OP void
LocalAddressVisitor visiting statement:
STMT00036 (IL 0x05F...0x065)
[000134] -AC-G------- * ASG int
[000133] D------N---- +--* LCL_VAR int V21 tmp12
[000132] --C-G------- \--* CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].<ReadByte>g__ReadByteSlow|18_0
[000131] ------------ arg0 \--* LCL_VAR byref V00 this
LocalAddressVisitor visiting statement:
STMT00037 (IL 0x065... ???)
[000137] -A---------- * ASG int
[000136] D------N---- +--* LCL_VAR int V06 loc5
[000135] ------------ \--* LCL_VAR int V21 tmp12
LocalAddressVisitor visiting statement:
STMT00038 (IL 0x067...0x067)
[000138] ------------ * NOP void
LocalAddressVisitor visiting statement:
STMT00030 (IL 0x069...0x072)
[000115] -AC-G------- * ASG byref
[000114] D------N---- +--* LCL_VAR byref V20 tmp11
[000113] --C-G------- \--* CALL byref System.ReadOnlySpan`1[Byte][System.Byte].get_Item
[000111] ------------ this in rcx +--* ADDR byref
[000110] -------N---- | \--* LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16>(AX) V03 loc2
[000112] ------------ arg1 \--* LCL_VAR int V02 loc1
Local V03 should not be enregistered because: it is address exposed
LocalAddressVisitor modified statement:
STMT00030 (IL 0x069...0x072)
[000115] -AC-G------- * ASG byref
[000114] D------N---- +--* LCL_VAR byref V20 tmp11
[000113] --C-G------- \--* CALL byref System.ReadOnlySpan`1[Byte][System.Byte].get_Item
[000111] ------------ this in rcx +--* LCL_VAR_ADDR byref V03 loc2
[000112] ------------ arg1 \--* LCL_VAR int V02 loc1
LocalAddressVisitor visiting statement:
STMT00031 (IL 0x071... ???)
[000119] -A-XG------- * ASG int
[000118] D------N---- +--* LCL_VAR int V04 loc3
[000117] *--XG------- \--* IND ubyte
[000116] ------------ \--* LCL_VAR byref V20 tmp11
LocalAddressVisitor visiting statement:
STMT00032 (IL 0x073...0x077)
[000125] -A-XG------- * ASG int
[000124] ---XG--N---- +--* FIELD int _bufferPos
[000120] ------------ | \--* LCL_VAR byref V00 this
[000123] ------------ \--* ADD int
[000121] ------------ +--* LCL_VAR int V02 loc1
[000122] ------------ \--* CNS_INT int 1
LocalAddressVisitor visiting statement:
STMT00033 (IL 0x07C...0x07D)
[000128] -A---------- * ASG int
[000127] D------N---- +--* LCL_VAR int V06 loc5
[000126] ------------ \--* LCL_VAR int V04 loc3
LocalAddressVisitor visiting statement:
STMT00034 (IL 0x07F...0x07F)
[000129] ------------ * NOP void
LocalAddressVisitor visiting statement:
STMT00011 (IL 0x081...0x091)
[000052] -ACXG------- * ASG ref
[000051] D------N---- +--* LCL_VAR ref V07 loc6
[000050] --CXG------- \--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS
[000049] H------N---- arg0 +--* CNS_INT(h) long 0x7ff93b569758 class
[000048] --CXG------- arg1 \--* CALL help ref HELPER.CORINFO_HELP_BOX
[000046] H----------- arg0 +--* CNS_INT(h) long 0x7ff93af7cd80 class
[000047] ---XG------- arg1 \--* ADDR byref
[000045] ---XG--N---- \--* FIELD struct _input
[000044] ------------ \--* LCL_VAR byref V00 this
LocalAddressVisitor visiting statement:
STMT00012 (IL 0x093...0x098)
[000057] -A---------- * ASG int
[000056] D------N---- +--* LCL_VAR int V08 loc7
[000055] N--------U-- \--* GT int
[000053] ------------ +--* LCL_VAR ref V07 loc6
[000054] ------------ \--* CNS_INT ref null
LocalAddressVisitor visiting statement:
STMT00013 (IL 0x09A...0x09C)
[000061] ------------ * JTRUE void
[000060] ------------ \--* EQ int
[000058] ------------ +--* LCL_VAR int V08 loc7
[000059] ------------ \--* CNS_INT int 0
LocalAddressVisitor visiting statement:
STMT00019 (IL 0x09E...0x09E)
[000072] ------------ * NO_OP void
LocalAddressVisitor visiting statement:
STMT00020 (IL 0x09F...0x0A6)
[000076] -AC-G------- * ASG int
[000075] D------N---- +--* LCL_VAR int V17 tmp8
[000074] --C-G------- \--* CALLV ind int Hagar.Buffers.ReaderInput.ReadByte
[000073] ------------ this in rcx \--* LCL_VAR ref V07 loc6
LocalAddressVisitor visiting statement:
STMT00021 (IL 0x0A6... ???)
[000079] -A---------- * ASG int
[000078] D------N---- +--* LCL_VAR int V06 loc5
[000077] ------------ \--* LCL_VAR int V17 tmp8
LocalAddressVisitor visiting statement:
STMT00022 (IL 0x0A8...0x0A8)
[000080] ------------ * NOP void
LocalAddressVisitor visiting statement:
STMT00014 (IL 0x0AA...0x0AA)
[000062] ------------ * NO_OP void
LocalAddressVisitor visiting statement:
STMT00015 (IL 0x0AB...0x0B0)
[000065] -AC-G------- * ASG int
[000064] D------N---- +--* LCL_VAR int V16 tmp7
[000063] --C-G------- \--* CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].ThrowNotSupportedInput
LocalAddressVisitor visiting statement:
STMT00016 (IL 0x0B0... ???)
[000068] -A---------- * ASG int
[000067] D------N---- +--* LCL_VAR int V06 loc5
[000066] ------------ \--* LCL_VAR int V16 tmp7
LocalAddressVisitor visiting statement:
STMT00017 (IL 0x0B2...0x0B2)
[000069] ------------ * NOP void
LocalAddressVisitor visiting statement:
STMT00018 (IL 0x0B4...0x0B6)
[000071] ------------ * RETURN int
[000070] ------------ \--* LCL_VAR int V06 loc5
*************** Finishing PHASE Morph - Structs/AddrExp
*************** Starting PHASE Morph - ByRefs
*************** In fgRetypeImplicitByRefArgs()
*************** Finishing PHASE Morph - ByRefs
*************** Starting PHASE Morph - Global
*************** In fgMorphBlocks()
Morphing BB01 of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
fgMorphTree BB01, STMT00000 (before)
[000000] ------------ * NOP void
fgMorphTree BB01, STMT00046 (before)
[000178] --C-G------- * QMARK void
[000174] Q----------- if +--* EQ int
[000172] ------------ | +--* IND int
[000171] H----------- | | \--* CNS_INT(h) long 0x7ff9392a5420 global ptr
[000173] ------------ | \--* CNS_INT int 0
[000177] --C-G------- if \--* COLON void
[000175] --C-G------- else +--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
[000176] ------------ then \--* NOP void
Initializing arg info for 175.CALL:
ArgTable for 175.CALL after fgInitArgInfo:
Morphing args for 175.CALL:
argSlots=0, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32
ArgTable for 175.CALL after fgMorphArgs:
Morphing BB02 of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
fgMorphTree BB02, STMT00001 (before)
[000001] ------------ * NO_OP void
fgMorphTree BB02, STMT00002 (before)
[000007] -AC-G------- * ASG struct (copy)
[000005] D------N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
[000003] --C-G------- \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000002] H----------- arg0 \--* CNS_INT(h) long 0x7ff93af7cd80 class
Initializing arg info for 3.CALL:
ArgTable for 3.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 2.CNS_INT long (By ref), 1 reg: rcx, byteAlignment=8]
Morphing args for 3.CALL:
argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rcx'):
[000002] H----+------ * CNS_INT(h) long 0x7ff93af7cd80 class
Replaced with placeholder node:
[000179] ----------L- * ARGPLACE long
Shuffled argument table: rcx
ArgTable for 3.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 2.CNS_INT long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed]
fgMorphCopyBlock:
fgMorphBlkNode for dst tree, before:
[000005] D----+-N---- * LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
fgMorphBlkNode after:
[000005] D----+-N---- * LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
fgMorphBlkNode for src tree, before:
[000003] --C-G+------ * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000002] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
fgMorphBlkNode after:
[000003] --C-G+------ * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000002] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
block assignment to morph:
[000007] -AC-G------- * ASG struct (copy)
[000005] D----+-N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
[000003] --C-G+------ \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000002] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
src is a call this requires a CopyBlock.
Local V10 should not be enregistered because: written in a block op
fgMorphCopyBlock (after):
[000007] -AC-G------- * ASG struct (copy)
[000005] D----+-N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
[000003] --C-G+------ \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000002] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
fgMorphTree BB02, STMT00002 (after)
[000007] -AC-G+------ * ASG struct (copy)
[000005] D----+-N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
[000003] --C-G+------ \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000002] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
fgMorphTree BB02, STMT00003 (before)
[000012] -AC-G------- * ASG ref
[000011] D------N---- +--* LCL_VAR ref V11 tmp2
[000004] --C-G------- \--* CALL ref System.Type.GetTypeFromHandle
[000010] n----------- arg0 \--* OBJ struct<System.RuntimeTypeHandle, 8>
[000009] ------------ \--* ADDR byref
[000008] -------N---- \--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
Initializing arg info for 4.CALL:
ArgTable for 4.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 10.OBJ ref (By value), 1 reg: rcx, byteAlignment=8, isStruct]
Morphing args for 4.CALL:
argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rcx'):
[000008] -----+------ * LCL_FLD ref V10 tmp1 [+0]
Replaced with placeholder node:
[000180] ----------L- * ARGPLACE ref
Shuffled argument table: rcx
ArgTable for 4.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 8.LCL_FLD ref (By value), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed, isStruct]
fgMorphTree BB02, STMT00003 (after)
[000012] -ACXG+------ * ASG ref
[000011] D----+-N---- +--* LCL_VAR ref V11 tmp2
[000004] --CXG+------ \--* CALL ref System.Type.GetTypeFromHandle
[000008] -----+------ arg0 in rcx \--* LCL_FLD ref V10 tmp1 [+0]
fgMorphTree BB02, STMT00004 (before)
[000019] -AC-G------- * ASG struct (copy)
[000017] D------N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
[000015] --C-G------- \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000014] H----------- arg0 \--* CNS_INT(h) long 0x7ff93af7cd80 class
Initializing arg info for 15.CALL:
ArgTable for 15.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 14.CNS_INT long (By ref), 1 reg: rcx, byteAlignment=8]
Morphing args for 15.CALL:
argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rcx'):
[000014] H----+------ * CNS_INT(h) long 0x7ff93af7cd80 class
Replaced with placeholder node:
[000181] ----------L- * ARGPLACE long
Shuffled argument table: rcx
ArgTable for 15.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 14.CNS_INT long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed]
fgMorphCopyBlock:
fgMorphBlkNode for dst tree, before:
[000017] D----+-N---- * LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
fgMorphBlkNode after:
[000017] D----+-N---- * LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
fgMorphBlkNode for src tree, before:
[000015] --C-G+------ * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000014] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
fgMorphBlkNode after:
[000015] --C-G+------ * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000014] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
block assignment to morph:
[000019] -AC-G------- * ASG struct (copy)
[000017] D----+-N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
[000015] --C-G+------ \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000014] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
src is a call this requires a CopyBlock.
Local V12 should not be enregistered because: written in a block op
fgMorphCopyBlock (after):
[000019] -AC-G------- * ASG struct (copy)
[000017] D----+-N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
[000015] --C-G+------ \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000014] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
fgMorphTree BB02, STMT00004 (after)
[000019] -AC-G+------ * ASG struct (copy)
[000017] D----+-N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
[000015] --C-G+------ \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000014] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
fgMorphTree BB02, STMT00005 (before)
[000024] -AC-G------- * ASG ref
[000023] D------N---- +--* LCL_VAR ref V13 tmp4
[000016] --C-G------- \--* CALL ref System.Type.GetTypeFromHandle
[000022] n----------- arg0 \--* OBJ struct<System.RuntimeTypeHandle, 8>
[000021] ------------ \--* ADDR byref
[000020] -------N---- \--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
Initializing arg info for 16.CALL:
ArgTable for 16.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 22.OBJ ref (By value), 1 reg: rcx, byteAlignment=8, isStruct]
Morphing args for 16.CALL:
argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rcx'):
[000020] -----+------ * LCL_FLD ref V12 tmp3 [+0]
Replaced with placeholder node:
[000182] ----------L- * ARGPLACE ref
Shuffled argument table: rcx
ArgTable for 16.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 20.LCL_FLD ref (By value), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed, isStruct]
fgMorphTree BB02, STMT00005 (after)
[000024] -ACXG+------ * ASG ref
[000023] D----+-N---- +--* LCL_VAR ref V13 tmp4
[000016] --CXG+------ \--* CALL ref System.Type.GetTypeFromHandle
[000020] -----+------ arg0 in rcx \--* LCL_FLD ref V12 tmp3 [+0]
fgMorphTree BB02, STMT00006 (before)
[000028] -AC-G------- * ASG int
[000027] D------N---- +--* LCL_VAR int V14 tmp5
[000026] --C-G------- \--* CALL int System.Type.op_Equality
[000013] ------------ arg0 +--* LCL_VAR ref V11 tmp2
[000025] ------------ arg1 \--* LCL_VAR ref V13 tmp4
Initializing arg info for 26.CALL:
ArgTable for 26.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 13.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8]
fgArgTabEntry[arg 1 25.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8]
Morphing args for 26.CALL:
argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rcx'):
[000013] -----+------ * LCL_VAR ref V11 tmp2
Replaced with placeholder node:
[000183] ----------L- * ARGPLACE ref
Deferred argument ('rdx'):
[000025] -----+------ * LCL_VAR ref V13 tmp4
Replaced with placeholder node:
[000184] ----------L- * ARGPLACE ref
Shuffled argument table: rcx rdx
ArgTable for 26.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 13.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed]
fgArgTabEntry[arg 1 25.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed]
fgMorphTree BB02, STMT00006 (after)
[000028] -ACXG+------ * ASG int
[000027] D----+-N---- +--* LCL_VAR int V14 tmp5
[000026] --CXG+------ \--* CALL int System.Type.op_Equality
[000013] -----+------ arg0 in rcx +--* LCL_VAR ref V11 tmp2
[000025] -----+------ arg1 in rdx \--* LCL_VAR ref V13 tmp4
fgMorphTree BB02, STMT00007 (before)
[000032] ------------ * JTRUE void
[000031] ------------ \--* NE int
[000029] ------------ +--* LCL_VAR int V14 tmp5
[000030] ------------ \--* CNS_INT int 0
Morphing BB03 of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
fgMorphTree BB03, STMT00039 (before)
[000144] -AC-G------- * ASG struct (copy)
[000142] D------N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
[000140] --C-G------- \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000139] H----------- arg0 \--* CNS_INT(h) long 0x7ff93af7cd80 class
Initializing arg info for 140.CALL:
ArgTable for 140.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 139.CNS_INT long (By ref), 1 reg: rcx, byteAlignment=8]
Morphing args for 140.CALL:
argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rcx'):
[000139] H----+------ * CNS_INT(h) long 0x7ff93af7cd80 class
Replaced with placeholder node:
[000185] ----------L- * ARGPLACE long
Shuffled argument table: rcx
ArgTable for 140.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 139.CNS_INT long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed]
fgMorphCopyBlock:
fgMorphBlkNode for dst tree, before:
[000142] D----+-N---- * LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
fgMorphBlkNode after:
[000142] D----+-N---- * LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
fgMorphBlkNode for src tree, before:
[000140] --C-G+------ * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000139] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
fgMorphBlkNode after:
[000140] --C-G+------ * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000139] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
block assignment to morph:
[000144] -AC-G------- * ASG struct (copy)
[000142] D----+-N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
[000140] --C-G+------ \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000139] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
src is a call this requires a CopyBlock.
Local V22 should not be enregistered because: written in a block op
fgMorphCopyBlock (after):
[000144] -AC-G------- * ASG struct (copy)
[000142] D----+-N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
[000140] --C-G+------ \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000139] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
fgMorphTree BB03, STMT00039 (after)
[000144] -AC-G+------ * ASG struct (copy)
[000142] D----+-N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
[000140] --C-G+------ \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000139] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
fgMorphTree BB03, STMT00040 (before)
[000149] -AC-G------- * ASG ref
[000148] D------N---- +--* LCL_VAR ref V23 tmp14
[000141] --C-G------- \--* CALL ref System.Type.GetTypeFromHandle
[000147] n----------- arg0 \--* OBJ struct<System.RuntimeTypeHandle, 8>
[000146] ------------ \--* ADDR byref
[000145] -------N---- \--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
Initializing arg info for 141.CALL:
ArgTable for 141.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 147.OBJ ref (By value), 1 reg: rcx, byteAlignment=8, isStruct]
Morphing args for 141.CALL:
argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rcx'):
[000145] -----+------ * LCL_FLD ref V22 tmp13 [+0]
Replaced with placeholder node:
[000186] ----------L- * ARGPLACE ref
Shuffled argument table: rcx
ArgTable for 141.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 145.LCL_FLD ref (By value), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed, isStruct]
fgMorphTree BB03, STMT00040 (after)
[000149] -ACXG+------ * ASG ref
[000148] D----+-N---- +--* LCL_VAR ref V23 tmp14
[000141] --CXG+------ \--* CALL ref System.Type.GetTypeFromHandle
[000145] -----+------ arg0 in rcx \--* LCL_FLD ref V22 tmp13 [+0]
fgMorphTree BB03, STMT00041 (before)
[000156] -AC-G------- * ASG struct (copy)
[000154] D------N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
[000152] --C-G------- \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000151] H----------- arg0 \--* CNS_INT(h) long 0x7ff93b56a7f8 class
Initializing arg info for 152.CALL:
ArgTable for 152.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 151.CNS_INT long (By ref), 1 reg: rcx, byteAlignment=8]
Morphing args for 152.CALL:
argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rcx'):
[000151] H----+------ * CNS_INT(h) long 0x7ff93b56a7f8 class
Replaced with placeholder node:
[000187] ----------L- * ARGPLACE long
Shuffled argument table: rcx
ArgTable for 152.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 151.CNS_INT long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed]
fgMorphCopyBlock:
fgMorphBlkNode for dst tree, before:
[000154] D----+-N---- * LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
fgMorphBlkNode after:
[000154] D----+-N---- * LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
fgMorphBlkNode for src tree, before:
[000152] --C-G+------ * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000151] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93b56a7f8 class
fgMorphBlkNode after:
[000152] --C-G+------ * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000151] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93b56a7f8 class
block assignment to morph:
[000156] -AC-G------- * ASG struct (copy)
[000154] D----+-N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
[000152] --C-G+------ \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000151] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93b56a7f8 class
src is a call this requires a CopyBlock.
Local V24 should not be enregistered because: written in a block op
fgMorphCopyBlock (after):
[000156] -AC-G------- * ASG struct (copy)
[000154] D----+-N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
[000152] --C-G+------ \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000151] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93b56a7f8 class
fgMorphTree BB03, STMT00041 (after)
[000156] -AC-G+------ * ASG struct (copy)
[000154] D----+-N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
[000152] --C-G+------ \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000151] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93b56a7f8 class
fgMorphTree BB03, STMT00042 (before)
[000161] -AC-G------- * ASG ref
[000160] D------N---- +--* LCL_VAR ref V25 tmp16
[000153] --C-G------- \--* CALL ref System.Type.GetTypeFromHandle
[000159] n----------- arg0 \--* OBJ struct<System.RuntimeTypeHandle, 8>
[000158] ------------ \--* ADDR byref
[000157] -------N---- \--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
Initializing arg info for 153.CALL:
ArgTable for 153.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 159.OBJ ref (By value), 1 reg: rcx, byteAlignment=8, isStruct]
Morphing args for 153.CALL:
argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rcx'):
[000157] -----+------ * LCL_FLD ref V24 tmp15 [+0]
Replaced with placeholder node:
[000188] ----------L- * ARGPLACE ref
Shuffled argument table: rcx
ArgTable for 153.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 157.LCL_FLD ref (By value), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed, isStruct]
fgMorphTree BB03, STMT00042 (after)
[000161] -ACXG+------ * ASG ref
[000160] D----+-N---- +--* LCL_VAR ref V25 tmp16
[000153] --CXG+------ \--* CALL ref System.Type.GetTypeFromHandle
[000157] -----+------ arg0 in rcx \--* LCL_FLD ref V24 tmp15 [+0]
fgMorphTree BB03, STMT00043 (before)
[000165] -AC-G------- * ASG int
[000164] D------N---- +--* LCL_VAR int V26 tmp17
[000163] --C-G------- \--* CALL int System.Type.op_Equality
[000150] ------------ arg0 +--* LCL_VAR ref V23 tmp14
[000162] ------------ arg1 \--* LCL_VAR ref V25 tmp16
Initializing arg info for 163.CALL:
ArgTable for 163.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 150.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8]
fgArgTabEntry[arg 1 162.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8]
Morphing args for 163.CALL:
argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rcx'):
[000150] -----+------ * LCL_VAR ref V23 tmp14
Replaced with placeholder node:
[000189] ----------L- * ARGPLACE ref
Deferred argument ('rdx'):
[000162] -----+------ * LCL_VAR ref V25 tmp16
Replaced with placeholder node:
[000190] ----------L- * ARGPLACE ref
Shuffled argument table: rcx rdx
ArgTable for 163.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 150.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed]
fgArgTabEntry[arg 1 162.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed]
fgMorphTree BB03, STMT00043 (after)
[000165] -ACXG+------ * ASG int
[000164] D----+-N---- +--* LCL_VAR int V26 tmp17
[000163] --CXG+------ \--* CALL int System.Type.op_Equality
[000150] -----+------ arg0 in rcx +--* LCL_VAR ref V23 tmp14
[000162] -----+------ arg1 in rdx \--* LCL_VAR ref V25 tmp16
fgMorphTree BB03, STMT00044 (before)
[000167] ------------ * NOP void
fgMorphTree BB03, STMT00045 (before)
[000169] -A---------- * ASG int
[000168] D------N---- +--* LCL_VAR int V15 tmp6
[000166] ------------ \--* LCL_VAR int V26 tmp17
Morphing BB04 of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
fgMorphTree BB04, STMT00008 (before)
[000035] -A---------- * ASG int
[000034] D------N---- +--* LCL_VAR int V15 tmp6
[000033] ------------ \--* CNS_INT int 1
Morphing BB05 of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
fgMorphTree BB05, STMT00009 (before)
[000039] -A---------- * ASG int
[000038] D------N---- +--* LCL_VAR int V01 loc0
[000037] ------------ \--* LCL_VAR int V15 tmp6
fgMorphTree BB05, STMT00009 (after)
[000039] -A---+------ * ASG int
[000038] D----+-N---- +--* LCL_VAR int V01 loc0
[000191] -----+------ \--* CAST int <- bool <- int
[000037] -----+------ \--* LCL_VAR int V15 tmp6
fgMorphTree BB05, STMT00010 (before)
[000043] ------------ * JTRUE void
[000042] ------------ \--* EQ int
[000040] ------------ +--* LCL_VAR int V01 loc0
[000041] ------------ \--* CNS_INT int 0
Morphing BB06 of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
fgMorphTree BB06, STMT00023 (before)
[000081] ------------ * NO_OP void
fgMorphTree BB06, STMT00024 (before)
[000085] -A-XG------- * ASG int
[000084] D------N---- +--* LCL_VAR int V02 loc1
[000083] ---XG------- \--* FIELD int _bufferPos
[000082] ------------ \--* LCL_VAR byref V00 this
Final value of Compiler::fgMorphField after calling fgMorphSmpOp:
[000083] *--XG------- * IND int
[000193] -----+------ \--* ADD byref
[000082] -----+------ +--* LCL_VAR byref V00 this
[000192] -----+------ \--* CNS_INT long 24 field offset Fseq[_bufferPos]
fgMorphTree BB06, STMT00024 (after)
[000085] -A-XG+------ * ASG int
[000084] D----+-N---- +--* LCL_VAR int V02 loc1
[000083] *--XG+------ \--* IND int
[000193] -----+------ \--* ADD byref
[000082] -----+------ +--* LCL_VAR byref V00 this
[000192] -----+------ \--* CNS_INT long 24 field offset Fseq[_bufferPos]
fgMorphTree BB06, STMT00025 (before)
[000090] -A-XG------- * ASG struct (copy)
[000088] D------N---- +--* LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16>(AX) V03 loc2
[000087] ---XG------- \--* FIELD struct _currentSpan
[000086] ------------ \--* LCL_VAR byref V00 this
Final value of Compiler::fgMorphField after calling fgMorphSmpOp:
[000087] *--XG------- * IND struct
[000195] -----+------ \--* ADD byref
[000086] -----+------ +--* LCL_VAR byref V00 this
[000194] -----+------ \--* CNS_INT long 32 field offset Fseq[_currentSpan]
fgMorphCopyBlock:
fgMorphBlkNode for dst tree, before:
[000088] D---G+-N---- * LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16>(AX) V03 loc2
fgMorphBlkNode after:
[000088] D---G+-N---- * LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16>(AX) V03 loc2
fgMorphBlkNode for src tree, before:
[000087] *--XG+------ * IND struct
[000195] -----+------ \--* ADD byref
[000086] -----+------ +--* LCL_VAR byref V00 this
[000194] -----+------ \--* CNS_INT long 32 field offset Fseq[_currentSpan]
fgMorphBlkNode after:
[000087] *--XG+------ * IND struct
[000195] -----+------ \--* ADD byref
[000086] -----+------ +--* LCL_VAR byref V00 this
[000194] -----+------ \--* CNS_INT long 32 field offset Fseq[_currentSpan]
block assignment to morph:
[000090] -A-XG------- * ASG struct (copy)
[000088] D---G+-N---- +--* LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16>(AX) V03 loc2
[000087] *--XG+------ \--* IND struct
[000195] -----+------ \--* ADD byref
[000086] -----+------ +--* LCL_VAR byref V00 this
[000194] -----+------ \--* CNS_INT long 32 field offset Fseq[_currentSpan]
with no promoted structs this requires a CopyBlock.
Local V03 should not be enregistered because: written in a block op
fgMorphCopyBlock (after):
[000090] -A-XG------- * ASG struct (copy)
[000088] D---G+-N---- +--* LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16>(AX) V03 loc2
[000087] *--XG+------ \--* IND struct
[000195] -----+------ \--* ADD byref
[000086] -----+------ +--* LCL_VAR byref V00 this
[000194] -----+------ \--* CNS_INT long 32 field offset Fseq[_currentSpan]
fgMorphTree BB06, STMT00025 (after)
[000090] -A-XG+------ * ASG struct (copy)
[000088] D---G+-N---- +--* LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16>(AX) V03 loc2
[000087] *--XG+------ \--* IND struct
[000195] -----+------ \--* ADD byref
[000086] -----+------ +--* LCL_VAR byref V00 this
[000194] -----+------ \--* CNS_INT long 32 field offset Fseq[_currentSpan]
fgMorphTree BB06, STMT00026 (before)
[000096] -A---------- * ASG int
[000095] D------N---- +--* LCL_VAR int V18 tmp9
[000091] ------------ \--* LCL_VAR int V02 loc1
fgMorphTree BB06, STMT00027 (before)
[000099] -AC-G------- * ASG int
[000098] D------N---- +--* LCL_VAR int V19 tmp10
[000094] --C-G------- \--* CALL int System.ReadOnlySpan`1[Byte][System.Byte].get_Length
[000093] ------------ this in rcx \--* LCL_VAR_ADDR byref V03 loc2
Initializing arg info for 94.CALL:
ArgTable for 94.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 93.LCL_VAR_ADDR byref (By ref), 1 reg: rcx, byteAlignment=8]
Morphing args for 94.CALL:
argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rcx'):
[000093] -----+------ * LCL_VAR_ADDR byref V03 loc2
Replaced with placeholder node:
[000196] ----------L- * ARGPLACE byref
Shuffled argument table: rcx
ArgTable for 94.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 93.LCL_VAR_ADDR byref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed]
fgMorphTree BB06, STMT00027 (after)
[000099] -ACXG+------ * ASG int
[000098] D----+-N---- +--* LCL_VAR int V19 tmp10
[000094] --CXG+------ \--* CALL int System.ReadOnlySpan`1[Byte][System.Byte].get_Length
[000093] -----+------ this in rcx \--* LCL_VAR_ADDR byref V03 loc2
fgMorphTree BB06, STMT00028 (before)
[000105] -A---------- * ASG int
[000104] D------N---- +--* LCL_VAR int V05 loc4
[000103] ------------ \--* EQ int
[000101] N--------U-- +--* LT int
[000097] ------------ | +--* LCL_VAR int V18 tmp9
[000100] ------------ | \--* LCL_VAR int V19 tmp10
[000102] ------------ \--* CNS_INT int 0
fgMorphTree BB06, STMT00028 (after)
[000105] -A---+------ * ASG int
[000104] D----+-N---- +--* LCL_VAR int V05 loc4
[000101] N----+---U-- \--* GE int
[000097] -----+------ +--* LCL_VAR int V18 tmp9
[000100] -----+------ \--* LCL_VAR int V19 tmp10
fgMorphTree BB06, STMT00029 (before)
[000109] ------------ * JTRUE void
[000108] ------------ \--* EQ int
[000106] ------------ +--* LCL_VAR int V05 loc4
[000107] ------------ \--* CNS_INT int 0
Morphing BB07 of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
fgMorphTree BB07, STMT00035 (before)
[000130] ------------ * NO_OP void
fgMorphTree BB07, STMT00036 (before)
[000134] -AC-G------- * ASG int
[000133] D------N---- +--* LCL_VAR int V21 tmp12
[000132] --C-G------- \--* CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].<ReadByte>g__ReadByteSlow|18_0
[000131] ------------ arg0 \--* LCL_VAR byref V00 this
Initializing arg info for 132.CALL:
ArgTable for 132.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 131.LCL_VAR byref (By ref), 1 reg: rcx, byteAlignment=8]
Morphing args for 132.CALL:
argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rcx'):
[000131] -----+------ * LCL_VAR byref V00 this
Replaced with placeholder node:
[000197] ----------L- * ARGPLACE byref
Shuffled argument table: rcx
ArgTable for 132.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 131.LCL_VAR byref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed]
fgMorphTree BB07, STMT00036 (after)
[000134] -ACXG+------ * ASG int
[000133] D----+-N---- +--* LCL_VAR int V21 tmp12
[000132] --CXG+------ \--* CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].<ReadByte>g__ReadByteSlow|18_0
[000131] -----+------ arg0 in rcx \--* LCL_VAR byref V00 this
fgMorphTree BB07, STMT00037 (before)
[000137] -A---------- * ASG int
[000136] D------N---- +--* LCL_VAR int V06 loc5
[000135] ------------ \--* LCL_VAR int V21 tmp12
fgMorphTree BB07, STMT00037 (after)
[000137] -A---+------ * ASG int
[000136] D----+-N---- +--* LCL_VAR int V06 loc5
[000198] -----+------ \--* CAST int <- ubyte <- int
[000135] -----+------ \--* LCL_VAR int V21 tmp12
fgMorphTree BB07, STMT00038 (before)
[000138] ------------ * NOP void
Morphing BB08 of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
fgMorphTree BB08, STMT00030 (before)
[000115] -AC-G------- * ASG byref
[000114] D------N---- +--* LCL_VAR byref V20 tmp11
[000113] --C-G------- \--* CALL byref System.ReadOnlySpan`1[Byte][System.Byte].get_Item
[000111] ------------ this in rcx +--* LCL_VAR_ADDR byref V03 loc2
[000112] ------------ arg1 \--* LCL_VAR int V02 loc1
Initializing arg info for 113.CALL:
ArgTable for 113.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 111.LCL_VAR_ADDR byref (By ref), 1 reg: rcx, byteAlignment=8]
fgArgTabEntry[arg 1 112.LCL_VAR int (By ref), 1 reg: rdx, byteAlignment=8]
Morphing args for 113.CALL:
argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rcx'):
[000111] -----+------ * LCL_VAR_ADDR byref V03 loc2
Replaced with placeholder node:
[000199] ----------L- * ARGPLACE byref
Deferred argument ('rdx'):
[000112] -----+------ * LCL_VAR int V02 loc1
Replaced with placeholder node:
[000200] ----------L- * ARGPLACE int
Shuffled argument table: rcx rdx
ArgTable for 113.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 111.LCL_VAR_ADDR byref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed]
fgArgTabEntry[arg 1 112.LCL_VAR int (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed]
fgMorphTree BB08, STMT00030 (after)
[000115] -ACXG+------ * ASG byref
[000114] D----+-N---- +--* LCL_VAR byref V20 tmp11
[000113] --CXG+------ \--* CALL byref System.ReadOnlySpan`1[Byte][System.Byte].get_Item
[000111] -----+------ this in rcx +--* LCL_VAR_ADDR byref V03 loc2
[000112] -----+------ arg1 in rdx \--* LCL_VAR int V02 loc1
fgMorphTree BB08, STMT00031 (before)
[000119] -A-XG------- * ASG int
[000118] D------N---- +--* LCL_VAR int V04 loc3
[000117] *--XG------- \--* IND ubyte
[000116] ------------ \--* LCL_VAR byref V20 tmp11
fgMorphTree BB08, STMT00032 (before)
[000125] -A-XG------- * ASG int
[000124] ---XG--N---- +--* FIELD int _bufferPos
[000120] ------------ | \--* LCL_VAR byref V00 this
[000123] ------------ \--* ADD int
[000121] ------------ +--* LCL_VAR int V02 loc1
[000122] ------------ \--* CNS_INT int 1
Final value of Compiler::fgMorphField after calling fgMorphSmpOp:
[000124] *--XG--N---- * IND int
[000202] -----+------ \--* ADD byref
[000120] -----+------ +--* LCL_VAR byref V00 this
[000201] -----+------ \--* CNS_INT long 24 field offset Fseq[_bufferPos]
fgMorphTree BB08, STMT00032 (after)
[000125] -A-XG+------ * ASG int
[000124] *--XG+-N---- +--* IND int
[000202] -----+------ | \--* ADD byref
[000120] -----+------ | +--* LCL_VAR byref V00 this
[000201] -----+------ | \--* CNS_INT long 24 field offset Fseq[_bufferPos]
[000123] -----+------ \--* ADD int
[000121] -----+------ +--* LCL_VAR int V02 loc1
[000122] -----+------ \--* CNS_INT int 1
fgMorphTree BB08, STMT00033 (before)
[000128] -A---------- * ASG int
[000127] D------N---- +--* LCL_VAR int V06 loc5
[000126] ------------ \--* LCL_VAR int V04 loc3
fgMorphTree BB08, STMT00034 (before)
[000129] ------------ * NOP void
Morphing BB09 of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
fgMorphTree BB09, STMT00011 (before)
[000052] -ACXG------- * ASG ref
[000051] D------N---- +--* LCL_VAR ref V07 loc6
[000050] --CXG------- \--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS
[000049] H------N---- arg0 +--* CNS_INT(h) long 0x7ff93b569758 class
[000048] --CXG------- arg1 \--* CALL help ref HELPER.CORINFO_HELP_BOX
[000046] H----------- arg0 +--* CNS_INT(h) long 0x7ff93af7cd80 class
[000047] ---XG------- arg1 \--* ADDR byref
[000045] ---XG--N---- \--* FIELD struct _input
[000044] ------------ \--* LCL_VAR byref V00 this
Initializing arg info for 50.CALL:
ArgTable for 50.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 49.CNS_INT long (By ref), 1 reg: rcx, byteAlignment=8]
fgArgTabEntry[arg 1 48.CALL ref (By ref), 1 reg: rdx, byteAlignment=8]
Morphing args for 50.CALL:
Initializing arg info for 48.CALL:
ArgTable for 48.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 46.CNS_INT long (By ref), 1 reg: rcx, byteAlignment=8]
fgArgTabEntry[arg 1 47.ADDR byref (By ref), 1 reg: rdx, byteAlignment=8]
Morphing args for 48.CALL:
Before explicit null check morphing:
[000045] ---XG--N---- * FIELD struct _input
[000044] ------------ \--* LCL_VAR byref V00 this
After adding explicit null check:
[000045] *--XG--N---- * IND struct
[000209] ---X-------- \--* COMMA byref
[000205] ---X---N---- +--* NULLCHECK byte
[000204] ------------ | \--* LCL_VAR byref V00 this
[000208] ------------ \--* ADD byref
[000206] ------------ +--* LCL_VAR byref V00 this
[000207] ------------ \--* CNS_INT long 64 field offset Fseq[_input]
Final value of Compiler::fgMorphField after calling fgMorphSmpOp:
[000209] ---XG+-N---- * COMMA struct
[000205] ---X-+-N---- +--* NULLCHECK byte
[000204] -----+------ | \--* LCL_VAR byref V00 this
[000210] *--X-+-N---- \--* IND struct
[000208] -----+------ \--* ADD byref
[000206] -----+------ +--* LCL_VAR byref V00 this
[000207] -----+------ \--* CNS_INT long 64 field offset Fseq[_input]
argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rdx'):
[000209] ---XG+-N---- * COMMA byref
[000205] ---X-+-N---- +--* NULLCHECK byte
[000204] -----+------ | \--* LCL_VAR byref V00 this
[000208] -----+------ \--* ADD byref
[000206] -----+------ +--* LCL_VAR byref V00 this
[000207] -----+------ \--* CNS_INT long 64 field offset Fseq[_input]
Replaced with placeholder node:
[000211] ----------L- * ARGPLACE byref
Deferred argument ('rcx'):
[000046] H----+------ * CNS_INT(h) long 0x7ff93af7cd80 class
Replaced with placeholder node:
[000212] ----------L- * ARGPLACE long
Shuffled argument table: rdx rcx
ArgTable for 48.CALL after fgMorphArgs:
fgArgTabEntry[arg 1 209.COMMA byref (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=0, processed]
fgArgTabEntry[arg 0 46.CNS_INT long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=1, processed]
argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32
Sorting the arguments:
Argument with 'side effect'...
[000048] --CXG+------ * CALL help ref HELPER.CORINFO_HELP_BOX
[000209] ---XG+-N---- arg1 in rdx +--* COMMA byref
[000205] ---X-+-N---- | +--* NULLCHECK byte
[000204] -----+------ | | \--* LCL_VAR byref V00 this
[000208] -----+------ | \--* ADD byref
[000206] -----+------ | +--* LCL_VAR byref V00 this
[000207] -----+------ | \--* CNS_INT long 64 field offset Fseq[_input]
[000046] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
lvaGrabTemp returning 27 (V27 tmp18) called for argument with side effect.
Evaluate to a temp:
[000214] -ACXG-----L- * ASG ref
[000213] D------N---- +--* LCL_VAR ref V27 tmp18
[000048] --CXG+------ \--* CALL help ref HELPER.CORINFO_HELP_BOX
[000209] ---XG+-N---- arg1 in rdx +--* COMMA byref
[000205] ---X-+-N---- | +--* NULLCHECK byte
[000204] -----+------ | | \--* LCL_VAR byref V00 this
[000208] -----+------ | \--* ADD byref
[000206] -----+------ | +--* LCL_VAR byref V00 this
[000207] -----+------ | \--* CNS_INT long 64 field offset Fseq[_input]
[000046] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
Deferred argument ('rcx'):
[000049] H----+-N---- * CNS_INT(h) long 0x7ff93b569758 class
Replaced with placeholder node:
[000216] ----------L- * ARGPLACE long
Shuffled argument table: rdx rcx
ArgTable for 50.CALL after fgMorphArgs:
fgArgTabEntry[arg 1 215.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=0, tmpNum=V27, isTmp, processed]
fgArgTabEntry[arg 0 49.CNS_INT long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=1, processed]
fgMorphTree BB09, STMT00011 (after)
[000052] -ACXG+------ * ASG ref
[000051] D----+-N---- +--* LCL_VAR ref V07 loc6
[000050] --CXG+------ \--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS
[000214] -ACXG-----L- arg1 SETUP +--* ASG ref
[000213] D------N---- | +--* LCL_VAR ref V27 tmp18
[000048] --CXG+------ | \--* CALL help ref HELPER.CORINFO_HELP_BOX
[000209] ---XG+-N---- arg1 in rdx | +--* COMMA byref
[000205] ---X-+-N---- | | +--* NULLCHECK byte
[000204] -----+------ | | | \--* LCL_VAR byref V00 this
[000208] -----+------ | | \--* ADD byref
[000206] -----+------ | | +--* LCL_VAR byref V00 this
[000207] -----+------ | | \--* CNS_INT long 64 field offset Fseq[_input]
[000046] H----+------ arg0 in rcx | \--* CNS_INT(h) long 0x7ff93af7cd80 class
[000215] ------------ arg1 in rdx +--* LCL_VAR ref V27 tmp18
[000049] H----+-N---- arg0 in rcx \--* CNS_INT(h) long 0x7ff93b569758 class
fgMorphTree BB09, STMT00012 (before)
[000057] -A---------- * ASG int
[000056] D------N---- +--* LCL_VAR int V08 loc7
[000055] N--------U-- \--* GT int
[000053] ------------ +--* LCL_VAR ref V07 loc6
[000054] ------------ \--* CNS_INT ref null
fgMorphTree BB09, STMT00012 (after)
[000057] -A---+------ * ASG int
[000056] D----+-N---- +--* LCL_VAR int V08 loc7
[000055] N----+------ \--* NE int
[000053] -----+------ +--* LCL_VAR ref V07 loc6
[000054] -----+------ \--* CNS_INT ref null
fgMorphTree BB09, STMT00013 (before)
[000061] ------------ * JTRUE void
[000060] ------------ \--* EQ int
[000058] ------------ +--* LCL_VAR int V08 loc7
[000059] ------------ \--* CNS_INT int 0
Morphing BB10 of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
fgMorphTree BB10, STMT00019 (before)
[000072] ------------ * NO_OP void
fgMorphTree BB10, STMT00020 (before)
[000076] -AC-G------- * ASG int
[000075] D------N---- +--* LCL_VAR int V17 tmp8
[000074] --C-G------- \--* CALLV ind int Hagar.Buffers.ReaderInput.ReadByte
[000073] ------------ this in rcx \--* LCL_VAR ref V07 loc6
Initializing arg info for 74.CALL:
ArgTable for 74.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 73.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8]
Morphing args for 74.CALL:
argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rcx'):
[000073] -----+------ * LCL_VAR ref V07 loc6
Replaced with placeholder node:
[000217] ----------L- * ARGPLACE ref
Shuffled argument table: rcx
ArgTable for 74.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 73.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed]
fgMorphTree BB10, STMT00020 (after)
[000076] -ACXG+------ * ASG int
[000075] D----+-N---- +--* LCL_VAR int V17 tmp8
[000074] --CXG+------ \--* CALLV ind int Hagar.Buffers.ReaderInput.ReadByte
[000073] -----+------ this in rcx \--* LCL_VAR ref V07 loc6
fgMorphTree BB10, STMT00021 (before)
[000079] -A---------- * ASG int
[000078] D------N---- +--* LCL_VAR int V06 loc5
[000077] ------------ \--* LCL_VAR int V17 tmp8
fgMorphTree BB10, STMT00021 (after)
[000079] -A---+------ * ASG int
[000078] D----+-N---- +--* LCL_VAR int V06 loc5
[000218] -----+------ \--* CAST int <- ubyte <- int
[000077] -----+------ \--* LCL_VAR int V17 tmp8
fgMorphTree BB10, STMT00022 (before)
[000080] ------------ * NOP void
Morphing BB11 of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
fgMorphTree BB11, STMT00014 (before)
[000062] ------------ * NO_OP void
fgMorphTree BB11, STMT00015 (before)
[000065] -AC-G------- * ASG int
[000064] D------N---- +--* LCL_VAR int V16 tmp7
[000063] --C-G------- \--* CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].ThrowNotSupportedInput
Initializing arg info for 63.CALL:
ArgTable for 63.CALL after fgInitArgInfo:
Morphing args for 63.CALL:
argSlots=0, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32
ArgTable for 63.CALL after fgMorphArgs:
fgMorphTree BB11, STMT00016 (before)
[000068] -A---------- * ASG int
[000067] D------N---- +--* LCL_VAR int V06 loc5
[000066] ------------ \--* LCL_VAR int V16 tmp7
fgMorphTree BB11, STMT00016 (after)
[000068] -A---+------ * ASG int
[000067] D----+-N---- +--* LCL_VAR int V06 loc5
[000219] -----+------ \--* CAST int <- ubyte <- int
[000066] -----+------ \--* LCL_VAR int V16 tmp7
fgMorphTree BB11, STMT00017 (before)
[000069] ------------ * NOP void
Morphing BB12 of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
fgMorphTree BB12, STMT00018 (before)
[000071] ------------ * RETURN int
[000070] ------------ \--* LCL_VAR int V06 loc5
Expanding top-level qmark in BB01 (before)
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target hascall
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
***** BB01
STMT00000 (IL ???... ???)
[000000] -----+------ * NOP void
***** BB01
STMT00046 (IL ???... ???)
[000178] --C-G+------ * QMARK void
[000174] J----+-N---- if +--* EQ int
[000172] n----+------ | +--* IND int
[000171] H----+------ | | \--* CNS_INT(h) long 0x7ff9392a5420 global ptr
[000173] -----+------ | \--* CNS_INT int 0
[000177] --C-G+?----- if \--* COLON void
[000175] --C-G+?----- else +--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
[000176] -----+?----- then \--* NOP void
-------------------------------------------------------------------------------------------------------------------
New Basic Block BB13 [0012] created.
BB02 previous predecessor was BB01, now is BB13
New Basic Block BB14 [0013] created.
New Basic Block BB15 [0014] created.
Removing statement STMT00046 (IL ???... ???)
[000178] --C-G+------ * QMARK void
[000174] J----+-N---- if +--* EQ int
[000172] n----+------ | +--* IND int
[000171] H----+------ | | \--* CNS_INT(h) long 0x7ff9392a5420 global ptr
[000173] -----+------ | \--* CNS_INT int 0
[000177] --C-G+?----- if \--* COLON void
[000175] --C-G+?----- else +--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
[000176] -----+?----- then \--* NOP void
in BB01 as useless:
Expanding top-level qmark in BB01 (after)
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target hascall
BB14 [0013] 1 BB01 1 [???..???)-> BB13 ( cond ) internal
BB15 [0014] 1 BB14 0.50 [???..???) internal
BB13 [0012] 2 BB14,BB15 1 [???..???) i internal label target hascall
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB14}
***** BB01
STMT00000 (IL ???... ???)
[000000] -----+------ * NOP void
------------ BB14 [???..???) -> BB13 (cond), preds={BB01} succs={BB15,BB13}
***** BB14
STMT00047 (IL ???... ???)
[000221] ------------ * JTRUE void
[000174] J----+-N---- \--* EQ int
[000172] n----+------ +--* IND int
[000171] H----+------ | \--* CNS_INT(h) long 0x7ff9392a5420 global ptr
[000173] -----+------ \--* CNS_INT int 0
------------ BB15 [???..???), preds={BB14} succs={BB13}
***** BB15
STMT00048 (IL ???... ???)
[000175] --C-G+?----- * CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
------------ BB13 [???..???), preds={BB14,BB15} succs={BB02}
-------------------------------------------------------------------------------------------------------------------
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target hascall
BB14 [0013] 1 BB01 1 [???..???)-> BB13 ( cond ) internal
BB15 [0014] 1 BB14 0.50 [???..???) internal
BB13 [0012] 2 BB14,BB15 1 [???..???) i internal label target hascall
BB02 [0001] 1 BB13 1 [000..01C)-> BB04 ( cond ) i hascall
BB03 [0002] 1 BB02 1 [01C..037)-> BB05 (always) i hascall
BB04 [0003] 1 BB02 1 [037..038) i label target
BB05 [0004] 2 BB03,BB04 1 [038..03C)-> BB09 ( cond ) i label target
BB06 [0005] 1 BB05 1 [03C..05E)-> BB08 ( cond ) i hascall
BB07 [0006] 1 BB06 1 [05E..069)-> BB12 (always) i hascall gcsafe
BB08 [0007] 1 BB06 1 [069..081)-> BB12 (always) i label target hascall
BB09 [0008] 1 BB05 1 [081..09E)-> BB11 ( cond ) i label target hascall nullcheck
BB10 [0009] 1 BB09 1 [09E..0AA)-> BB12 (always) i hascall gcsafe
BB11 [0010] 1 BB09 1 [0AA..0B4)-> BB12 (always) i label target hascall gcsafe
BB12 [0011] 4 BB07,BB08,BB10,BB11 1 [0B4..0B7) (return) i label target
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
Renumber BB14 to BB02
Renumber BB15 to BB03
Renumber BB13 to BB04
Renumber BB02 to BB05
Renumber BB03 to BB06
Renumber BB04 to BB07
Renumber BB05 to BB08
Renumber BB06 to BB09
Renumber BB07 to BB10
Renumber BB08 to BB11
Renumber BB09 to BB12
Renumber BB10 to BB13
Renumber BB11 to BB14
Renumber BB12 to BB15
*************** After renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target hascall
BB02 [0013] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
BB03 [0014] 1 BB02 0.50 [???..???) internal
BB04 [0012] 2 BB02,BB03 1 [???..???) i internal label target hascall
BB05 [0001] 1 BB04 1 [000..01C)-> BB07 ( cond ) i hascall
BB06 [0002] 1 BB05 1 [01C..037)-> BB08 (always) i hascall
BB07 [0003] 1 BB05 1 [037..038) i label target
BB08 [0004] 2 BB06,BB07 1 [038..03C)-> BB12 ( cond ) i label target
BB09 [0005] 1 BB08 1 [03C..05E)-> BB11 ( cond ) i hascall
BB10 [0006] 1 BB09 1 [05E..069)-> BB15 (always) i hascall gcsafe
BB11 [0007] 1 BB09 1 [069..081)-> BB15 (always) i label target hascall
BB12 [0008] 1 BB08 1 [081..09E)-> BB14 ( cond ) i label target hascall nullcheck
BB13 [0009] 1 BB12 1 [09E..0AA)-> BB15 (always) i hascall gcsafe
BB14 [0010] 1 BB12 1 [0AA..0B4)-> BB15 (always) i label target hascall gcsafe
BB15 [0011] 4 BB10,BB11,BB13,BB14 1 [0B4..0B7) (return) i label target
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
New BlockSet epoch 2, # of blocks (including unused BB00): 16, bitset array size: 1 (short)
*************** Finishing PHASE Morph - Global
Trees after Morph - Global
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target hascall
BB02 [0013] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
BB03 [0014] 1 BB02 0.50 [???..???) internal
BB04 [0012] 2 BB02,BB03 1 [???..???) i internal label target hascall
BB05 [0001] 1 BB04 1 [000..01C)-> BB07 ( cond ) i hascall
BB06 [0002] 1 BB05 1 [01C..037)-> BB08 (always) i hascall
BB07 [0003] 1 BB05 1 [037..038) i label target
BB08 [0004] 2 BB06,BB07 1 [038..03C)-> BB12 ( cond ) i label target
BB09 [0005] 1 BB08 1 [03C..05E)-> BB11 ( cond ) i hascall
BB10 [0006] 1 BB09 1 [05E..069)-> BB15 (always) i hascall gcsafe
BB11 [0007] 1 BB09 1 [069..081)-> BB15 (always) i label target hascall
BB12 [0008] 1 BB08 1 [081..09E)-> BB14 ( cond ) i label target hascall nullcheck
BB13 [0009] 1 BB12 1 [09E..0AA)-> BB15 (always) i hascall gcsafe
BB14 [0010] 1 BB12 1 [0AA..0B4)-> BB15 (always) i label target hascall gcsafe
BB15 [0011] 4 BB10,BB11,BB13,BB14 1 [0B4..0B7) (return) i label target
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
***** BB01
STMT00000 (IL ???... ???)
[000000] -----+------ * NOP void
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00047 (IL ???... ???)
[000221] ------------ * JTRUE void
[000174] J----+-N---- \--* EQ int
[000172] n----+------ +--* IND int
[000171] H----+------ | \--* CNS_INT(h) long 0x7ff9392a5420 global ptr
[000173] -----+------ \--* CNS_INT int 0
------------ BB03 [???..???), preds={BB02} succs={BB04}
***** BB03
STMT00048 (IL ???... ???)
[000175] --C-G+?----- * CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
------------ BB05 [000..01C) -> BB07 (cond), preds={BB04} succs={BB06,BB07}
***** BB05
STMT00001 (IL 0x000...0x000)
[000001] -----+------ * NO_OP void
***** BB05
STMT00002 (IL 0x001...0x01A)
[000007] -AC-G+------ * ASG struct (copy)
[000005] D----+-N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
[000003] --C-G+------ \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000002] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
***** BB05
STMT00003 (IL ???... ???)
[000012] -ACXG+------ * ASG ref
[000011] D----+-N---- +--* LCL_VAR ref V11 tmp2
[000004] --CXG+------ \--* CALL ref System.Type.GetTypeFromHandle
[000008] -----+------ arg0 in rcx \--* LCL_FLD ref V10 tmp1 [+0]
***** BB05
STMT00004 (IL 0x00B... ???)
[000019] -AC-G+------ * ASG struct (copy)
[000017] D----+-N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
[000015] --C-G+------ \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000014] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
***** BB05
STMT00005 (IL ???... ???)
[000024] -ACXG+------ * ASG ref
[000023] D----+-N---- +--* LCL_VAR ref V13 tmp4
[000016] --CXG+------ \--* CALL ref System.Type.GetTypeFromHandle
[000020] -----+------ arg0 in rcx \--* LCL_FLD ref V12 tmp3 [+0]
***** BB05
STMT00006 (IL 0x015... ???)
[000028] -ACXG+------ * ASG int
[000027] D----+-N---- +--* LCL_VAR int V14 tmp5
[000026] --CXG+------ \--* CALL int System.Type.op_Equality
[000013] -----+------ arg0 in rcx +--* LCL_VAR ref V11 tmp2
[000025] -----+------ arg1 in rdx \--* LCL_VAR ref V13 tmp4
***** BB05
STMT00007 (IL 0x01A... ???)
[000032] -----+------ * JTRUE void
[000031] J----+-N---- \--* NE int
[000029] -----+------ +--* LCL_VAR int V14 tmp5
[000030] -----+------ \--* CNS_INT int 0
------------ BB06 [01C..037) -> BB08 (always), preds={BB05} succs={BB08}
***** BB06
STMT00039 (IL 0x01C...0x035)
[000144] -AC-G+------ * ASG struct (copy)
[000142] D----+-N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
[000140] --C-G+------ \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000139] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
***** BB06
STMT00040 (IL ???... ???)
[000149] -ACXG+------ * ASG ref
[000148] D----+-N---- +--* LCL_VAR ref V23 tmp14
[000141] --CXG+------ \--* CALL ref System.Type.GetTypeFromHandle
[000145] -----+------ arg0 in rcx \--* LCL_FLD ref V22 tmp13 [+0]
***** BB06
STMT00041 (IL 0x026... ???)
[000156] -AC-G+------ * ASG struct (copy)
[000154] D----+-N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
[000152] --C-G+------ \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
[000151] H----+------ arg0 in rcx \--* CNS_INT(h) long 0x7ff93b56a7f8 class
***** BB06
STMT00042 (IL ???... ???)
[000161] -ACXG+------ * ASG ref
[000160] D----+-N---- +--* LCL_VAR ref V25 tmp16
[000153] --CXG+------ \--* CALL ref System.Type.GetTypeFromHandle
[000157] -----+------ arg0 in rcx \--* LCL_FLD ref V24 tmp15 [+0]
***** BB06
STMT00043 (IL 0x030... ???)
[000165] -ACXG+------ * ASG int
[000164] D----+-N---- +--* LCL_VAR int V26 tmp17
[000163] --CXG+------ \--* CALL int System.Type.op_Equality
[000150] -----+------ arg0 in rcx +--* LCL_VAR ref V23 tmp14
[000162] -----+------ arg1 in rdx \--* LCL_VAR ref V25 tmp16
***** BB06
STMT00044 (IL 0x035... ???)
[000167] -----+------ * NOP void
***** BB06
STMT00045 (IL ???... ???)
[000169] -A---+------ * ASG int
[000168] D----+-N---- +--* LCL_VAR int V15 tmp6
[000166] -----+------ \--* LCL_VAR int V26 tmp17
------------ BB07 [037..038), preds={BB05} succs={BB08}
***** BB07
STMT00008 (IL 0x037...0x037)
[000035] -A---+------ * ASG int
[000034] D----+-N---- +--* LCL_VAR int V15 tmp6
[000033] -----+------ \--* CNS_INT int 1
------------ BB08 [038..03C) -> BB12 (cond), preds={BB06,BB07} succs={BB09,BB12}
***** BB08
STMT00009 (IL ???...0x038)
[000039] -A---+------ * ASG int
[000038] D----+-N---- +--* LCL_VAR int V01 loc0
[000191] -----+------ \--* CAST int <- bool <- int
[000037] -----+------ \--* LCL_VAR int V15 tmp6
***** BB08
STMT00010 (IL 0x039...0x03A)
[000043] -----+------ * JTRUE void
[000042] J----+-N---- \--* EQ int
[000040] -----+------ +--* LCL_VAR int V01 loc0
[000041] -----+------ \--* CNS_INT int 0
------------ BB09 [03C..05E) -> BB11 (cond), preds={BB08} succs={BB10,BB11}
***** BB09
STMT00023 (IL 0x03C...0x03C)
[000081] -----+------ * NO_OP void
***** BB09
STMT00024 (IL 0x03D...0x043)
[000085] -A-XG+------ * ASG int
[000084] D----+-N---- +--* LCL_VAR int V02 loc1
[000083] *--XG+------ \--* IND int
[000193] -----+------ \--* ADD byref
[000082] -----+------ +--* LCL_VAR byref V00 this
[000192] -----+------ \--* CNS_INT long 24 field offset Fseq[_bufferPos]
***** BB09
STMT00025 (IL 0x044...0x04A)
[000090] -A-XG+------ * ASG struct (copy)
[000088] D---G+-N---- +--* LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16>(AX) V03 loc2
[000087] *--XG+------ \--* IND struct
[000195] -----+------ \--* ADD byref
[000086] -----+------ +--* LCL_VAR byref V00 this
[000194] -----+------ \--* CNS_INT long 32 field offset Fseq[_currentSpan]
***** BB09
STMT00026 (IL 0x04B...0x058)
[000096] -A---+------ * ASG int
[000095] D----+-N---- +--* LCL_VAR int V18 tmp9
[000091] -----+------ \--* LCL_VAR int V02 loc1
***** BB09
STMT00027 (IL ???... ???)
[000099] -ACXG+------ * ASG int
[000098] D----+-N---- +--* LCL_VAR int V19 tmp10
[000094] --CXG+------ \--* CALL int System.ReadOnlySpan`1[Byte][System.Byte].get_Length
[000093] -----+------ this in rcx \--* LCL_VAR_ADDR byref V03 loc2
***** BB09
STMT00028 (IL 0x053... ???)
[000105] -A---+------ * ASG int
[000104] D----+-N---- +--* LCL_VAR int V05 loc4
[000101] N----+---U-- \--* GE int
[000097] -----+------ +--* LCL_VAR int V18 tmp9
[000100] -----+------ \--* LCL_VAR int V19 tmp10
***** BB09
STMT00029 (IL 0x05A...0x05C)
[000109] -----+------ * JTRUE void
[000108] J----+-N---- \--* EQ int
[000106] -----+------ +--* LCL_VAR int V05 loc4
[000107] -----+------ \--* CNS_INT int 0
------------ BB10 [05E..069) -> BB15 (always), preds={BB09} succs={BB15}
***** BB10
STMT00035 (IL 0x05E...0x05E)
[000130] -----+------ * NO_OP void
***** BB10
STMT00036 (IL 0x05F...0x065)
[000134] -ACXG+------ * ASG int
[000133] D----+-N---- +--* LCL_VAR int V21 tmp12
[000132] --CXG+------ \--* CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].<ReadByte>g__ReadByteSlow|18_0
[000131] -----+------ arg0 in rcx \--* LCL_VAR byref V00 this
***** BB10
STMT00037 (IL 0x065... ???)
[000137] -A---+------ * ASG int
[000136] D----+-N---- +--* LCL_VAR int V06 loc5
[000198] -----+------ \--* CAST int <- ubyte <- int
[000135] -----+------ \--* LCL_VAR int V21 tmp12
***** BB10
STMT00038 (IL 0x067...0x067)
[000138] -----+------ * NOP void
------------ BB11 [069..081) -> BB15 (always), preds={BB09} succs={BB15}
***** BB11
STMT00030 (IL 0x069...0x072)
[000115] -ACXG+------ * ASG byref
[000114] D----+-N---- +--* LCL_VAR byref V20 tmp11
[000113] --CXG+------ \--* CALL byref System.ReadOnlySpan`1[Byte][System.Byte].get_Item
[000111] -----+------ this in rcx +--* LCL_VAR_ADDR byref V03 loc2
[000112] -----+------ arg1 in rdx \--* LCL_VAR int V02 loc1
***** BB11
STMT00031 (IL 0x071... ???)
[000119] -A-XG+------ * ASG int
[000118] D----+-N---- +--* LCL_VAR int V04 loc3
[000117] *--XG+------ \--* IND ubyte
[000116] -----+------ \--* LCL_VAR byref V20 tmp11
***** BB11
STMT00032 (IL 0x073...0x077)
[000125] -A-XG+------ * ASG int
[000124] *--XG+-N---- +--* IND int
[000202] -----+------ | \--* ADD byref
[000120] -----+------ | +--* LCL_VAR byref V00 this
[000201] -----+------ | \--* CNS_INT long 24 field offset Fseq[_bufferPos]
[000123] -----+------ \--* ADD int
[000121] -----+------ +--* LCL_VAR int V02 loc1
[000122] -----+------ \--* CNS_INT int 1
***** BB11
STMT00033 (IL 0x07C...0x07D)
[000128] -A---+------ * ASG int
[000127] D----+-N---- +--* LCL_VAR int V06 loc5
[000126] -----+------ \--* LCL_VAR int V04 loc3
***** BB11
STMT00034 (IL 0x07F...0x07F)
[000129] -----+------ * NOP void
------------ BB12 [081..09E) -> BB14 (cond), preds={BB08} succs={BB13,BB14}
***** BB12
STMT00011 (IL 0x081...0x091)
[000052] -ACXG+------ * ASG ref
[000051] D----+-N---- +--* LCL_VAR ref V07 loc6
[000050] --CXG+------ \--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS
[000214] -ACXG-----L- arg1 SETUP +--* ASG ref
[000213] D------N---- | +--* LCL_VAR ref V27 tmp18
[000048] --CXG+------ | \--* CALL help ref HELPER.CORINFO_HELP_BOX
[000209] ---XG+-N---- arg1 in rdx | +--* COMMA byref
[000205] ---X-+-N---- | | +--* NULLCHECK byte
[000204] -----+------ | | | \--* LCL_VAR byref V00 this
[000208] -----+------ | | \--* ADD byref
[000206] -----+------ | | +--* LCL_VAR byref V00 this
[000207] -----+------ | | \--* CNS_INT long 64 field offset Fseq[_input]
[000046] H----+------ arg0 in rcx | \--* CNS_INT(h) long 0x7ff93af7cd80 class
[000215] ------------ arg1 in rdx +--* LCL_VAR ref V27 tmp18
[000049] H----+-N---- arg0 in rcx \--* CNS_INT(h) long 0x7ff93b569758 class
***** BB12
STMT00012 (IL 0x093...0x098)
[000057] -A---+------ * ASG int
[000056] D----+-N---- +--* LCL_VAR int V08 loc7
[000055] N----+------ \--* NE int
[000053] -----+------ +--* LCL_VAR ref V07 loc6
[000054] -----+------ \--* CNS_INT ref null
***** BB12
STMT00013 (IL 0x09A...0x09C)
[000061] -----+------ * JTRUE void
[000060] J----+-N---- \--* EQ int
[000058] -----+------ +--* LCL_VAR int V08 loc7
[000059] -----+------ \--* CNS_INT int 0
------------ BB13 [09E..0AA) -> BB15 (always), preds={BB12} succs={BB15}
***** BB13
STMT00019 (IL 0x09E...0x09E)
[000072] -----+------ * NO_OP void
***** BB13
STMT00020 (IL 0x09F...0x0A6)
[000076] -ACXG+------ * ASG int
[000075] D----+-N---- +--* LCL_VAR int V17 tmp8
[000074] --CXG+------ \--* CALLV ind int Hagar.Buffers.ReaderInput.ReadByte
[000073] -----+------ this in rcx \--* LCL_VAR ref V07 loc6
***** BB13
STMT00021 (IL 0x0A6... ???)
[000079] -A---+------ * ASG int
[000078] D----+-N---- +--* LCL_VAR int V06 loc5
[000218] -----+------ \--* CAST int <- ubyte <- int
[000077] -----+------ \--* LCL_VAR int V17 tmp8
***** BB13
STMT00022 (IL 0x0A8...0x0A8)
[000080] -----+------ * NOP void
------------ BB14 [0AA..0B4) -> BB15 (always), preds={BB12} succs={BB15}
***** BB14
STMT00014 (IL 0x0AA...0x0AA)
[000062] -----+------ * NO_OP void
***** BB14
STMT00015 (IL 0x0AB...0x0B0)
[000065] -ACXG+------ * ASG int
[000064] D----+-N---- +--* LCL_VAR int V16 tmp7
[000063] --CXG+------ \--* CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].ThrowNotSupportedInput
***** BB14
STMT00016 (IL 0x0B0... ???)
[000068] -A---+------ * ASG int
[000067] D----+-N---- +--* LCL_VAR int V06 loc5
[000219] -----+------ \--* CAST int <- ubyte <- int
[000066] -----+------ \--* LCL_VAR int V16 tmp7
***** BB14
STMT00017 (IL 0x0B2...0x0B2)
[000069] -----+------ * NOP void
------------ BB15 [0B4..0B7) (return), preds={BB10,BB11,BB13,BB14} succs={}
***** BB15
STMT00018 (IL 0x0B4...0x0B6)
[000071] -----+------ * RETURN int
[000070] -----+------ \--* LCL_VAR int V06 loc5
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE GS Cookie
No GS security needed
*************** Finishing PHASE GS Cookie
*************** Starting PHASE Compute edge weights (1, false)
*************** In fgComputeBlockAndEdgeWeights()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target hascall
BB02 [0013] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
BB03 [0014] 1 BB02 0.50 [???..???) internal
BB04 [0012] 2 BB02,BB03 1 [???..???) i internal label target hascall
BB05 [0001] 1 BB04 1 [000..01C)-> BB07 ( cond ) i hascall
BB06 [0002] 1 BB05 1 [01C..037)-> BB08 (always) i hascall
BB07 [0003] 1 BB05 1 [037..038) i label target
BB08 [0004] 2 BB06,BB07 1 [038..03C)-> BB12 ( cond ) i label target
BB09 [0005] 1 BB08 1 [03C..05E)-> BB11 ( cond ) i hascall
BB10 [0006] 1 BB09 1 [05E..069)-> BB15 (always) i hascall gcsafe
BB11 [0007] 1 BB09 1 [069..081)-> BB15 (always) i label target hascall
BB12 [0008] 1 BB08 1 [081..09E)-> BB14 ( cond ) i label target hascall nullcheck
BB13 [0009] 1 BB12 1 [09E..0AA)-> BB15 (always) i hascall gcsafe
BB14 [0010] 1 BB12 1 [0AA..0B4)-> BB15 (always) i label target hascall gcsafe
BB15 [0011] 4 BB10,BB11,BB13,BB14 1 [0B4..0B7) (return) i label target
-----------------------------------------------------------------------------------------------------------------------------------------
-- no profile data, so using default called count
-- not optimizing or no profile data, so not computing edge weights
*************** Finishing PHASE Compute edge weights (1, false)
*************** Starting PHASE Create EH funclets
*************** In fgCreateFunclets()
After fgCreateFunclets()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target hascall
BB02 [0013] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
BB03 [0014] 1 BB02 0.50 [???..???) internal
BB04 [0012] 2 BB02,BB03 1 [???..???) i internal label target hascall
BB05 [0001] 1 BB04 1 [000..01C)-> BB07 ( cond ) i hascall
BB06 [0002] 1 BB05 1 [01C..037)-> BB08 (always) i hascall
BB07 [0003] 1 BB05 1 [037..038) i label target
BB08 [0004] 2 BB06,BB07 1 [038..03C)-> BB12 ( cond ) i label target
BB09 [0005] 1 BB08 1 [03C..05E)-> BB11 ( cond ) i hascall
BB10 [0006] 1 BB09 1 [05E..069)-> BB15 (always) i hascall gcsafe
BB11 [0007] 1 BB09 1 [069..081)-> BB15 (always) i label target hascall
BB12 [0008] 1 BB08 1 [081..09E)-> BB14 ( cond ) i label target hascall nullcheck
BB13 [0009] 1 BB12 1 [09E..0AA)-> BB15 (always) i hascall gcsafe
BB14 [0010] 1 BB12 1 [0AA..0B4)-> BB15 (always) i label target hascall gcsafe
BB15 [0011] 4 BB10,BB11,BB13,BB14 1 [0B4..0B7) (return) i label target
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Create EH funclets
*************** Starting PHASE Mark local vars
*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***
*************** Finishing PHASE Mark local vars
*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()
*************** Finishing PHASE Find oper order
*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has 18 tree nodes
*************** Finishing PHASE Set block order
*************** Starting PHASE Insert GC Polls
*************** Finishing PHASE Insert GC Polls [no changes]
*************** Starting PHASE Determine first cold block
*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method
*************** Finishing PHASE Determine first cold block
Trees before Rationalize IR
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target hascall
BB02 [0013] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
BB03 [0014] 1 BB02 0.50 [???..???) internal
BB04 [0012] 2 BB02,BB03 1 [???..???) i internal label target hascall
BB05 [0001] 1 BB04 1 [000..01C)-> BB07 ( cond ) i hascall
BB06 [0002] 1 BB05 1 [01C..037)-> BB08 (always) i hascall
BB07 [0003] 1 BB05 1 [037..038) i label target
BB08 [0004] 2 BB06,BB07 1 [038..03C)-> BB12 ( cond ) i label target
BB09 [0005] 1 BB08 1 [03C..05E)-> BB11 ( cond ) i hascall
BB10 [0006] 1 BB09 1 [05E..069)-> BB15 (always) i hascall gcsafe
BB11 [0007] 1 BB09 1 [069..081)-> BB15 (always) i label target hascall
BB12 [0008] 1 BB08 1 [081..09E)-> BB14 ( cond ) i label target hascall nullcheck
BB13 [0009] 1 BB12 1 [09E..0AA)-> BB15 (always) i hascall gcsafe
BB14 [0010] 1 BB12 1 [0AA..0B4)-> BB15 (always) i label target hascall gcsafe
BB15 [0011] 4 BB10,BB11,BB13,BB14 1 [0B4..0B7) (return) i label target
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
***** BB01
STMT00000 (IL ???... ???)
N001 ( 0, 0) [000000] ------------ * NOP void
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00047 (IL ???... ???)
N005 ( 8, 16) [000221] ------------ * JTRUE void
N004 ( 6, 14) [000174] J------N---- \--* EQ int
N002 ( 4, 12) [000172] n----------- +--* IND int
N001 ( 2, 10) [000171] H----------- | \--* CNS_INT(h) long 0x7ff9392a5420 global ptr
N003 ( 1, 1) [000173] ------------ \--* CNS_INT int 0
------------ BB03 [???..???), preds={BB02} succs={BB04}
***** BB03
STMT00048 (IL ???... ???)
N001 ( 14, 5) [000175] --C-G-?----- * CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
------------ BB05 [000..01C) -> BB07 (cond), preds={BB04} succs={BB06,BB07}
***** BB05
STMT00001 (IL 0x000...0x000)
N001 ( 1, 1) [000001] ------------ * NO_OP void
***** BB05
STMT00002 (IL 0x001...0x01A)
N005 ( 20, 19) [000007] -AC-G---R--- * ASG struct (copy)
N004 ( 3, 2) [000005] D------N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
N003 ( 16, 16) [000003] --C-G------- \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
N002 ( 2, 10) [000002] H----------- arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
***** BB05
STMT00003 (IL ???... ???)
N005 ( 21, 13) [000012] -ACXG---R--- * ASG ref
N004 ( 3, 2) [000011] D------N---- +--* LCL_VAR ref V11 tmp2
N003 ( 17, 10) [000004] --CXG------- \--* CALL ref System.Type.GetTypeFromHandle
N002 ( 3, 4) [000008] ------------ arg0 in rcx \--* LCL_FLD ref V10 tmp1 [+0]
***** BB05
STMT00004 (IL 0x00B... ???)
N005 ( 20, 19) [000019] -AC-G---R--- * ASG struct (copy)
N004 ( 3, 2) [000017] D------N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
N003 ( 16, 16) [000015] --C-G------- \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
N002 ( 2, 10) [000014] H----------- arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
***** BB05
STMT00005 (IL ???... ???)
N005 ( 21, 13) [000024] -ACXG---R--- * ASG ref
N004 ( 3, 2) [000023] D------N---- +--* LCL_VAR ref V13 tmp4
N003 ( 17, 10) [000016] --CXG------- \--* CALL ref System.Type.GetTypeFromHandle
N002 ( 3, 4) [000020] ------------ arg0 in rcx \--* LCL_FLD ref V12 tmp3 [+0]
***** BB05
STMT00006 (IL 0x015... ???)
N007 ( 24, 14) [000028] -ACXG---R--- * ASG int
N006 ( 3, 2) [000027] D------N---- +--* LCL_VAR int V14 tmp5
N005 ( 20, 11) [000026] --CXG------- \--* CALL int System.Type.op_Equality
N003 ( 3, 2) [000013] ------------ arg0 in rcx +--* LCL_VAR ref V11 tmp2
N004 ( 3, 2) [000025] ------------ arg1 in rdx \--* LCL_VAR ref V13 tmp4
***** BB05
STMT00007 (IL 0x01A... ???)
N004 ( 7, 6) [000032] ------------ * JTRUE void
N003 ( 5, 4) [000031] J------N---- \--* NE int
N001 ( 3, 2) [000029] ------------ +--* LCL_VAR int V14 tmp5
N002 ( 1, 1) [000030] ------------ \--* CNS_INT int 0
------------ BB06 [01C..037) -> BB08 (always), preds={BB05} succs={BB08}
***** BB06
STMT00039 (IL 0x01C...0x035)
N005 ( 20, 19) [000144] -AC-G---R--- * ASG struct (copy)
N004 ( 3, 2) [000142] D------N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
N003 ( 16, 16) [000140] --C-G------- \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
N002 ( 2, 10) [000139] H----------- arg0 in rcx \--* CNS_INT(h) long 0x7ff93af7cd80 class
***** BB06
STMT00040 (IL ???... ???)
N005 ( 21, 13) [000149] -ACXG---R--- * ASG ref
N004 ( 3, 2) [000148] D------N---- +--* LCL_VAR ref V23 tmp14
N003 ( 17, 10) [000141] --CXG------- \--* CALL ref System.Type.GetTypeFromHandle
N002 ( 3, 4) [000145] ------------ arg0 in rcx \--* LCL_FLD ref V22 tmp13 [+0]
***** BB06
STMT00041 (IL 0x026... ???)
N005 ( 20, 19) [000156] -AC-G---R--- * ASG struct (copy)
N004 ( 3, 2) [000154] D------N---- +--* LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
N003 ( 16, 16) [000152] --C-G------- \--* CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
N002 ( 2, 10) [000151] H----------- arg0 in rcx \--* CNS_INT(h) long 0x7ff93b56a7f8 class
***** BB06
STMT00042 (IL ???... ???)
N005 ( 21, 13) [000161] -ACXG---R--- * ASG ref
N004 ( 3, 2) [000160] D------N---- +--* LCL_VAR ref V25 tmp16
N003 ( 17, 10) [000153] --CXG------- \--* CALL ref System.Type.GetTypeFromHandle
N002 ( 3, 4) [000157] ------------ arg0 in rcx \--* LCL_FLD ref V24 tmp15 [+0]
***** BB06
STMT00043 (IL 0x030... ???)
N007 ( 24, 14) [000165] -ACXG---R--- * ASG int
N006 ( 3, 2) [000164] D------N---- +--* LCL_VAR int V26 tmp17
N005 ( 20, 11) [000163] --CXG------- \--* CALL int System.Type.op_Equality
N003 ( 3, 2) [000150] ------------ arg0 in rcx +--* LCL_VAR ref V23 tmp14
N004 ( 3, 2) [000162] ------------ arg1 in rdx \--* LCL_VAR ref V25 tmp16
***** BB06
STMT00044 (IL 0x035... ???)
N001 ( 0, 0) [000167] ------------ * NOP void
***** BB06
STMT00045 (IL ???... ???)
N003 ( 7, 5) [000169] -A------R--- * ASG int
N002 ( 3, 2) [000168] D------N---- +--* LCL_VAR int V15 tmp6
N001 ( 3, 2) [000166] ------------ \--* LCL_VAR int V26 tmp17
------------ BB07 [037..038), preds={BB05} succs={BB08}
***** BB07
STMT00008 (IL 0x037...0x037)
N003 ( 5, 4) [000035] -A------R--- * ASG int
N002 ( 3, 2) [000034] D------N---- +--* LCL_VAR int V15 tmp6
N001 ( 1, 1) [000033] ------------ \--* CNS_INT int 1
------------ BB08 [038..03C) -> BB12 (cond), preds={BB06,BB07} succs={BB09,BB12}
***** BB08
STMT00009 (IL ???...0x038)
N004 ( 8, 7) [000039] -A------R--- * ASG int
N003 ( 3, 2) [000038] D------N---- +--* LCL_VAR int V01 loc0
N002 ( 4, 4) [000191] ------------ \--* CAST int <- bool <- int
N001 ( 3, 2) [000037] ------------ \--* LCL_VAR int V15 tmp6
***** BB08
STMT00010 (IL 0x039...0x03A)
N004 ( 7, 6) [000043] ------------ * JTRUE void
N003 ( 5, 4) [000042] J------N---- \--* EQ int
N001 ( 3, 2) [000040] ------------ +--* LCL_VAR int V01 loc0
N002 ( 1, 1) [000041] ------------ \--* CNS_INT int 0
------------ BB09 [03C..05E) -> BB11 (cond), preds={BB08} succs={BB10,BB11}
***** BB09
STMT00023 (IL 0x03C...0x03C)
N001 ( 1, 1) [000081] ------------ * NO_OP void
***** BB09
STMT00024 (IL 0x03D...0x043)
N006 ( 10, 8) [000085] -A-XG---R--- * ASG int
N005 ( 3, 2) [000084] D------N---- +--* LCL_VAR int V02 loc1
N004 ( 6, 5) [000083] *--XG------- \--* IND int
N003 ( 4, 3) [000193] -------N---- \--* ADD byref
N001 ( 3, 2) [000082] ------------ +--* LCL_VAR byref V00 this
N002 ( 1, 1) [000192] ------------ \--* CNS_INT long 24 field offset Fseq[_bufferPos]
***** BB09
STMT00025 (IL 0x044...0x04A)
N006 ( 12, 9) [000090] -A-XG---R--- * ASG struct (copy)
N005 ( 3, 2) [000088] D---G--N---- +--* LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16>(AX) V03 loc2
N004 ( 8, 6) [000087] *--XG------- \--* IND struct
N003 ( 5, 4) [000195] ------------ \--* ADD byref
N001 ( 3, 2) [000086] ------------ +--* LCL_VAR byref V00 this
N002 ( 1, 1) [000194] ------------ \--* CNS_INT long 32 field offset Fseq[_currentSpan]
***** BB09
STMT00026 (IL 0x04B...0x058)
N003 ( 7, 5) [000096] -A------R--- * ASG int
N002 ( 3, 2) [000095] D------N---- +--* LCL_VAR int V18 tmp9
N001 ( 3, 2) [000091] ------------ \--* LCL_VAR int V02 loc1
***** BB09
STMT00027 (IL ???... ???)
N005 ( 21, 13) [000099] -ACXG---R--- * ASG int
N004 ( 3, 2) [000098] D------N---- +--* LCL_VAR int V19 tmp10
N003 ( 17, 10) [000094] --CXG------- \--* CALL int System.ReadOnlySpan`1[Byte][System.Byte].get_Length
N002 ( 3, 3) [000093] ------------ this in rcx \--* LCL_VAR_ADDR byref V03 loc2
***** BB09
STMT00028 (IL 0x053... ???)
N005 ( 14, 8) [000105] -A------R--- * ASG int
N004 ( 3, 2) [000104] D------N---- +--* LCL_VAR int V05 loc4
N003 ( 10, 5) [000101] N--------U-- \--* GE int
N001 ( 3, 2) [000097] ------------ +--* LCL_VAR int V18 tmp9
N002 ( 3, 2) [000100] ------------ \--* LCL_VAR int V19 tmp10
***** BB09
STMT00029 (IL 0x05A...0x05C)
N004 ( 7, 6) [000109] ------------ * JTRUE void
N003 ( 5, 4) [000108] J------N---- \--* EQ int
N001 ( 3, 2) [000106] ------------ +--* LCL_VAR int V05 loc4
N002 ( 1, 1) [000107] ------------ \--* CNS_INT int 0
------------ BB10 [05E..069) -> BB15 (always), preds={BB09} succs={BB15}
***** BB10
STMT00035 (IL 0x05E...0x05E)
N001 ( 1, 1) [000130] ------------ * NO_OP void
***** BB10
STMT00036 (IL 0x05F...0x065)
N005 ( 21, 11) [000134] -ACXG---R--- * ASG int
N004 ( 3, 2) [000133] D------N---- +--* LCL_VAR int V21 tmp12
N003 ( 17, 8) [000132] --CXG------- \--* CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].<ReadByte>g__ReadByteSlow|18_0
N002 ( 3, 2) [000131] ------------ arg0 in rcx \--* LCL_VAR byref V00 this
***** BB10
STMT00037 (IL 0x065... ???)
N004 ( 8, 7) [000137] -A------R--- * ASG int
N003 ( 3, 2) [000136] D------N---- +--* LCL_VAR int V06 loc5
N002 ( 4, 4) [000198] ------------ \--* CAST int <- ubyte <- int
N001 ( 3, 2) [000135] ------------ \--* LCL_VAR int V21 tmp12
***** BB10
STMT00038 (IL 0x067...0x067)
N001 ( 0, 0) [000138] ------------ * NOP void
------------ BB11 [069..081) -> BB15 (always), preds={BB09} succs={BB15}
***** BB11
STMT00030 (IL 0x069...0x072)
N007 ( 24, 16) [000115] -ACXG---R--- * ASG byref
N006 ( 3, 2) [000114] D------N---- +--* LCL_VAR byref V20 tmp11
N005 ( 20, 13) [000113] --CXG------- \--* CALL byref System.ReadOnlySpan`1[Byte][System.Byte].get_Item
N003 ( 3, 3) [000111] ------------ this in rcx +--* LCL_VAR_ADDR byref V03 loc2
N004 ( 3, 2) [000112] ------------ arg1 in rdx \--* LCL_VAR int V02 loc1
***** BB11
STMT00031 (IL 0x071... ???)
N004 ( 11, 8) [000119] -A-XG---R--- * ASG int
N003 ( 3, 2) [000118] D------N---- +--* LCL_VAR int V04 loc3
N002 ( 7, 5) [000117] *--XG------- \--* IND ubyte
N001 ( 3, 2) [000116] ------------ \--* LCL_VAR byref V20 tmp11
***** BB11
STMT00032 (IL 0x073...0x077)
N008 ( 12, 10) [000125] -A-XG---R--- * ASG int
N007 ( 6, 5) [000124] *--XG--N---- +--* IND int
N006 ( 4, 3) [000202] -------N---- | \--* ADD byref
N004 ( 3, 2) [000120] ------------ | +--* LCL_VAR byref V00 this
N005 ( 1, 1) [000201] ------------ | \--* CNS_INT long 24 field offset Fseq[_bufferPos]
N003 ( 5, 4) [000123] ------------ \--* ADD int
N001 ( 3, 2) [000121] ------------ +--* LCL_VAR int V02 loc1
N002 ( 1, 1) [000122] ------------ \--* CNS_INT int 1
***** BB11
STMT00033 (IL 0x07C...0x07D)
N003 ( 7, 5) [000128] -A------R--- * ASG int
N002 ( 3, 2) [000127] D------N---- +--* LCL_VAR int V06 loc5
N001 ( 3, 2) [000126] ------------ \--* LCL_VAR int V04 loc3
***** BB11
STMT00034 (IL 0x07F...0x07F)
N001 ( 0, 0) [000129] ------------ * NOP void
------------ BB12 [081..09E) -> BB14 (cond), preds={BB08} succs={BB13,BB14}
***** BB12
STMT00011 (IL 0x081...0x091)
N018 ( 55, 49) [000052] -ACXG---R--- * ASG ref
N017 ( 3, 2) [000051] D------N---- +--* LCL_VAR ref V07 loc6
N016 ( 51, 46) [000050] --CXG------- \--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS
N013 ( 29, 27) [000214] -ACXG---R-L- arg1 SETUP +--* ASG ref
N012 ( 3, 2) [000213] D------N---- | +--* LCL_VAR ref V27 tmp18
N011 ( 25, 24) [000048] --CXG------- | \--* CALL help ref HELPER.CORINFO_HELP_BOX
N009 ( 9, 7) [000209] ---XG--N---- arg1 in rdx | +--* COMMA byref
N005 ( 4, 3) [000205] ---X---N---- | | +--* NULLCHECK byte
N004 ( 3, 2) [000204] ------------ | | | \--* LCL_VAR byref V00 this
N008 ( 5, 4) [000208] ------------ | | \--* ADD byref
N006 ( 3, 2) [000206] ------------ | | +--* LCL_VAR byref V00 this
N007 ( 1, 1) [000207] ------------ | | \--* CNS_INT long 64 field offset Fseq[_input]
N010 ( 2, 10) [000046] H----------- arg0 in rcx | \--* CNS_INT(h) long 0x7ff93af7cd80 class
N014 ( 3, 2) [000215] ------------ arg1 in rdx +--* LCL_VAR ref V27 tmp18
N015 ( 2, 10) [000049] H------N---- arg0 in rcx \--* CNS_INT(h) long 0x7ff93b569758 class
***** BB12
STMT00012 (IL 0x093...0x098)
N005 ( 12, 7) [000057] -A------R--- * ASG int
N004 ( 3, 2) [000056] D------N---- +--* LCL_VAR int V08 loc7
N003 ( 8, 4) [000055] N----------- \--* NE int
N001 ( 3, 2) [000053] ------------ +--* LCL_VAR ref V07 loc6
N002 ( 1, 1) [000054] ------------ \--* CNS_INT ref null
***** BB12
STMT00013 (IL 0x09A...0x09C)
N004 ( 7, 6) [000061] ------------ * JTRUE void
N003 ( 5, 4) [000060] J------N---- \--* EQ int
N001 ( 3, 2) [000058] ------------ +--* LCL_VAR int V08 loc7
N002 ( 1, 1) [000059] ------------ \--* CNS_INT int 0
------------ BB13 [09E..0AA) -> BB15 (always), preds={BB12} succs={BB15}
***** BB13
STMT00019 (IL 0x09E...0x09E)
N001 ( 1, 1) [000072] ------------ * NO_OP void
***** BB13
STMT00020 (IL 0x09F...0x0A6)
N005 ( 27, 14) [000076] -ACXG---R--- * ASG int
N004 ( 3, 2) [000075] D------N---- +--* LCL_VAR int V17 tmp8
N003 ( 23, 11) [000074] --CXG------- \--* CALLV ind int Hagar.Buffers.ReaderInput.ReadByte
N002 ( 3, 2) [000073] ------------ this in rcx \--* LCL_VAR ref V07 loc6
***** BB13
STMT00021 (IL 0x0A6... ???)
N004 ( 8, 7) [000079] -A------R--- * ASG int
N003 ( 3, 2) [000078] D------N---- +--* LCL_VAR int V06 loc5
N002 ( 4, 4) [000218] ------------ \--* CAST int <- ubyte <- int
N001 ( 3, 2) [000077] ------------ \--* LCL_VAR int V17 tmp8
***** BB13
STMT00022 (IL 0x0A8...0x0A8)
N001 ( 0, 0) [000080] ------------ * NOP void
------------ BB14 [0AA..0B4) -> BB15 (always), preds={BB12} succs={BB15}
***** BB14
STMT00014 (IL 0x0AA...0x0AA)
N001 ( 1, 1) [000062] ------------ * NO_OP void
***** BB14
STMT00015 (IL 0x0AB...0x0B0)
N003 ( 18, 8) [000065] -ACXG---R--- * ASG int
N002 ( 3, 2) [000064] D------N---- +--* LCL_VAR int V16 tmp7
N001 ( 14, 5) [000063] --CXG------- \--* CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].ThrowNotSupportedInput
***** BB14
STMT00016 (IL 0x0B0... ???)
N004 ( 8, 7) [000068] -A------R--- * ASG int
N003 ( 3, 2) [000067] D------N---- +--* LCL_VAR int V06 loc5
N002 ( 4, 4) [000219] ------------ \--* CAST int <- ubyte <- int
N001 ( 3, 2) [000066] ------------ \--* LCL_VAR int V16 tmp7
***** BB14
STMT00017 (IL 0x0B2...0x0B2)
N001 ( 0, 0) [000069] ------------ * NOP void
------------ BB15 [0B4..0B7) (return), preds={BB10,BB11,BB13,BB14} succs={}
***** BB15
STMT00018 (IL 0x0B4...0x0B6)
N002 ( 4, 3) [000071] ------------ * RETURN int
N001 ( 3, 2) [000070] ------------ \--* LCL_VAR int V06 loc5
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Rationalize IR
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 20, 19) [000007] DAC-G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 21, 13) [000012] DACXG------- * STORE_LCL_VAR ref V11 tmp2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 20, 19) [000019] DAC-G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 21, 13) [000024] DACXG------- * STORE_LCL_VAR ref V13 tmp4
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 24, 14) [000028] DACXG------- * STORE_LCL_VAR int V14 tmp5
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 20, 19) [000144] DAC-G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 21, 13) [000149] DACXG------- * STORE_LCL_VAR ref V23 tmp14
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 20, 19) [000156] DAC-G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 21, 13) [000161] DACXG------- * STORE_LCL_VAR ref V25 tmp16
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 24, 14) [000165] DACXG------- * STORE_LCL_VAR int V26 tmp17
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 7, 5) [000169] DA---------- * STORE_LCL_VAR int V15 tmp6
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 5, 4) [000035] DA---------- * STORE_LCL_VAR int V15 tmp6
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N004 ( 8, 7) [000039] DA---------- * STORE_LCL_VAR int V01 loc0
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N006 ( 10, 8) [000085] DA-XG------- * STORE_LCL_VAR int V02 loc1
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N006 ( 12, 9) [000090] DA-XG------- * STORE_LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16>(AX) V03 loc2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 7, 5) [000096] DA---------- * STORE_LCL_VAR int V18 tmp9
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 21, 13) [000099] DACXG------- * STORE_LCL_VAR int V19 tmp10
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 14, 8) [000105] DA---------- * STORE_LCL_VAR int V05 loc4
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 21, 11) [000134] DACXG------- * STORE_LCL_VAR int V21 tmp12
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N004 ( 8, 7) [000137] DA---------- * STORE_LCL_VAR int V06 loc5
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 24, 16) [000115] DACXG------- * STORE_LCL_VAR byref V20 tmp11
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N004 ( 11, 8) [000119] DA-XG------- * STORE_LCL_VAR int V04 loc3
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 7, 5) [000128] DA---------- * STORE_LCL_VAR int V06 loc5
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N013 ( 29, 27) [000214] DACXG-----L- * STORE_LCL_VAR ref V27 tmp18
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N018 ( 55, 49) [000052] DACXG------- * STORE_LCL_VAR ref V07 loc6
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 12, 7) [000057] DA---------- * STORE_LCL_VAR int V08 loc7
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 27, 14) [000076] DACXG------- * STORE_LCL_VAR int V17 tmp8
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N004 ( 8, 7) [000079] DA---------- * STORE_LCL_VAR int V06 loc5
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 18, 8) [000065] DACXG------- * STORE_LCL_VAR int V16 tmp7
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N004 ( 8, 7) [000068] DA---------- * STORE_LCL_VAR int V06 loc5
*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target hascall LIR
BB02 [0013] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
BB03 [0014] 1 BB02 0.50 [???..???) internal LIR
BB04 [0012] 2 BB02,BB03 1 [???..???) i internal label target hascall LIR
BB05 [0001] 1 BB04 1 [000..01C)-> BB07 ( cond ) i hascall LIR
BB06 [0002] 1 BB05 1 [01C..037)-> BB08 (always) i hascall LIR
BB07 [0003] 1 BB05 1 [037..038) i label target LIR
BB08 [0004] 2 BB06,BB07 1 [038..03C)-> BB12 ( cond ) i label target LIR
BB09 [0005] 1 BB08 1 [03C..05E)-> BB11 ( cond ) i hascall LIR
BB10 [0006] 1 BB09 1 [05E..069)-> BB15 (always) i hascall gcsafe LIR
BB11 [0007] 1 BB09 1 [069..081)-> BB15 (always) i label target hascall LIR
BB12 [0008] 1 BB08 1 [081..09E)-> BB14 ( cond ) i label target hascall nullcheck LIR
BB13 [0009] 1 BB12 1 [09E..0AA)-> BB15 (always) i hascall gcsafe LIR
BB14 [0010] 1 BB12 1 [0AA..0B4)-> BB15 (always) i label target hascall gcsafe LIR
BB15 [0011] 4 BB10,BB11,BB13,BB14 1 [0B4..0B7) (return) i label target LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
N001 ( 0, 0) [000000] ------------ NOP void
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
N001 ( 2, 10) [000171] H----------- t171 = CNS_INT(h) long 0x7ff9392a5420 global ptr
/--* t171 long
N002 ( 4, 12) [000172] n----------- t172 = * IND int
N003 ( 1, 1) [000173] ------------ t173 = CNS_INT int 0
/--* t172 int
+--* t173 int
N004 ( 6, 14) [000174] J------N---- t174 = * EQ int
/--* t174 int
N005 ( 8, 16) [000221] ------------ * JTRUE void
------------ BB03 [???..???), preds={BB02} succs={BB04}
N001 ( 14, 5) [000175] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
------------ BB05 [000..01C) -> BB07 (cond), preds={BB04} succs={BB06,BB07}
[000222] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000001] ------------ NO_OP void
[000223] ------------ IL_OFFSET void IL offset: 0x1
N002 ( 2, 10) [000002] H----------- t2 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t2 long arg0 in rcx
N003 ( 16, 16) [000003] --C-G------- t3 = * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t3 struct
N005 ( 20, 19) [000007] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
N002 ( 3, 4) [000008] ------------ t8 = LCL_FLD ref V10 tmp1 [+0]
/--* t8 ref arg0 in rcx
N003 ( 17, 10) [000004] --CXG------- t4 = * CALL ref System.Type.GetTypeFromHandle
/--* t4 ref
N005 ( 21, 13) [000012] DA-XG------- * STORE_LCL_VAR ref V11 tmp2
[000224] ------------ IL_OFFSET void IL offset: 0xb
N002 ( 2, 10) [000014] H----------- t14 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t14 long arg0 in rcx
N003 ( 16, 16) [000015] --C-G------- t15 = * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t15 struct
N005 ( 20, 19) [000019] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
N002 ( 3, 4) [000020] ------------ t20 = LCL_FLD ref V12 tmp3 [+0]
/--* t20 ref arg0 in rcx
N003 ( 17, 10) [000016] --CXG------- t16 = * CALL ref System.Type.GetTypeFromHandle
/--* t16 ref
N005 ( 21, 13) [000024] DA-XG------- * STORE_LCL_VAR ref V13 tmp4
[000225] ------------ IL_OFFSET void IL offset: 0x15
N003 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V11 tmp2
N004 ( 3, 2) [000025] ------------ t25 = LCL_VAR ref V13 tmp4
/--* t13 ref arg0 in rcx
+--* t25 ref arg1 in rdx
N005 ( 20, 11) [000026] --CXG------- t26 = * CALL int System.Type.op_Equality
/--* t26 int
N007 ( 24, 14) [000028] DA-XG------- * STORE_LCL_VAR int V14 tmp5
[000226] ------------ IL_OFFSET void IL offset: 0x1a
N001 ( 3, 2) [000029] ------------ t29 = LCL_VAR int V14 tmp5
N002 ( 1, 1) [000030] ------------ t30 = CNS_INT int 0
/--* t29 int
+--* t30 int
N003 ( 5, 4) [000031] J------N---- t31 = * NE int
/--* t31 int
N004 ( 7, 6) [000032] ------------ * JTRUE void
------------ BB06 [01C..037) -> BB08 (always), preds={BB05} succs={BB08}
[000227] ------------ IL_OFFSET void IL offset: 0x1c
N002 ( 2, 10) [000139] H----------- t139 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t139 long arg0 in rcx
N003 ( 16, 16) [000140] --C-G------- t140 = * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t140 struct
N005 ( 20, 19) [000144] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
N002 ( 3, 4) [000145] ------------ t145 = LCL_FLD ref V22 tmp13 [+0]
/--* t145 ref arg0 in rcx
N003 ( 17, 10) [000141] --CXG------- t141 = * CALL ref System.Type.GetTypeFromHandle
/--* t141 ref
N005 ( 21, 13) [000149] DA-XG------- * STORE_LCL_VAR ref V23 tmp14
[000228] ------------ IL_OFFSET void IL offset: 0x26
N002 ( 2, 10) [000151] H----------- t151 = CNS_INT(h) long 0x7ff93b56a7f8 class
/--* t151 long arg0 in rcx
N003 ( 16, 16) [000152] --C-G------- t152 = * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t152 struct
N005 ( 20, 19) [000156] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
N002 ( 3, 4) [000157] ------------ t157 = LCL_FLD ref V24 tmp15 [+0]
/--* t157 ref arg0 in rcx
N003 ( 17, 10) [000153] --CXG------- t153 = * CALL ref System.Type.GetTypeFromHandle
/--* t153 ref
N005 ( 21, 13) [000161] DA-XG------- * STORE_LCL_VAR ref V25 tmp16
[000229] ------------ IL_OFFSET void IL offset: 0x30
N003 ( 3, 2) [000150] ------------ t150 = LCL_VAR ref V23 tmp14
N004 ( 3, 2) [000162] ------------ t162 = LCL_VAR ref V25 tmp16
/--* t150 ref arg0 in rcx
+--* t162 ref arg1 in rdx
N005 ( 20, 11) [000163] --CXG------- t163 = * CALL int System.Type.op_Equality
/--* t163 int
N007 ( 24, 14) [000165] DA-XG------- * STORE_LCL_VAR int V26 tmp17
[000230] ------------ IL_OFFSET void IL offset: 0x35
N001 ( 0, 0) [000167] ------------ NOP void
N001 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V26 tmp17
/--* t166 int
N003 ( 7, 5) [000169] DA---------- * STORE_LCL_VAR int V15 tmp6
------------ BB07 [037..038), preds={BB05} succs={BB08}
[000231] ------------ IL_OFFSET void IL offset: 0x37
N001 ( 1, 1) [000033] ------------ t33 = CNS_INT int 1
/--* t33 int
N003 ( 5, 4) [000035] DA---------- * STORE_LCL_VAR int V15 tmp6
------------ BB08 [038..03C) -> BB12 (cond), preds={BB06,BB07} succs={BB09,BB12}
N001 ( 3, 2) [000037] ------------ t37 = LCL_VAR int V15 tmp6
/--* t37 int
N002 ( 4, 4) [000191] ------------ t191 = * CAST int <- bool <- int
/--* t191 int
N004 ( 8, 7) [000039] DA---------- * STORE_LCL_VAR int V01 loc0
[000232] ------------ IL_OFFSET void IL offset: 0x39
N001 ( 3, 2) [000040] ------------ t40 = LCL_VAR int V01 loc0
N002 ( 1, 1) [000041] ------------ t41 = CNS_INT int 0
/--* t40 int
+--* t41 int
N003 ( 5, 4) [000042] J------N---- t42 = * EQ int
/--* t42 int
N004 ( 7, 6) [000043] ------------ * JTRUE void
------------ BB09 [03C..05E) -> BB11 (cond), preds={BB08} succs={BB10,BB11}
[000233] ------------ IL_OFFSET void IL offset: 0x3c
N001 ( 1, 1) [000081] ------------ NO_OP void
[000234] ------------ IL_OFFSET void IL offset: 0x3d
N001 ( 3, 2) [000082] ------------ t82 = LCL_VAR byref V00 this
N002 ( 1, 1) [000192] ------------ t192 = CNS_INT long 24 field offset Fseq[_bufferPos]
/--* t82 byref
+--* t192 long
N003 ( 4, 3) [000193] -------N---- t193 = * ADD byref
/--* t193 byref
N004 ( 6, 5) [000083] *--XG------- t83 = * IND int
/--* t83 int
N006 ( 10, 8) [000085] DA-XG------- * STORE_LCL_VAR int V02 loc1
[000235] ------------ IL_OFFSET void IL offset: 0x44
N001 ( 3, 2) [000086] ------------ t86 = LCL_VAR byref V00 this
N002 ( 1, 1) [000194] ------------ t194 = CNS_INT long 32 field offset Fseq[_currentSpan]
/--* t86 byref
+--* t194 long
N003 ( 5, 4) [000195] ------------ t195 = * ADD byref
/--* t195 byref
N004 ( 8, 6) [000087] *--XG------- t87 = * IND struct
/--* t87 struct
N006 ( 12, 9) [000090] DA-XG------- * STORE_LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16>(AX) V03 loc2
[000236] ------------ IL_OFFSET void IL offset: 0x4b
N001 ( 3, 2) [000091] ------------ t91 = LCL_VAR int V02 loc1
/--* t91 int
N003 ( 7, 5) [000096] DA---------- * STORE_LCL_VAR int V18 tmp9
N002 ( 3, 3) [000093] ------------ t93 = LCL_VAR_ADDR byref V03 loc2
/--* t93 byref this in rcx
N003 ( 17, 10) [000094] --CXG------- t94 = * CALL int System.ReadOnlySpan`1[Byte][System.Byte].get_Length
/--* t94 int
N005 ( 21, 13) [000099] DA-XG------- * STORE_LCL_VAR int V19 tmp10
[000237] ------------ IL_OFFSET void IL offset: 0x53
N001 ( 3, 2) [000097] ------------ t97 = LCL_VAR int V18 tmp9
N002 ( 3, 2) [000100] ------------ t100 = LCL_VAR int V19 tmp10
/--* t97 int
+--* t100 int
N003 ( 10, 5) [000101] N--------U-- t101 = * GE int
/--* t101 int
N005 ( 14, 8) [000105] DA---------- * STORE_LCL_VAR int V05 loc4
[000238] ------------ IL_OFFSET void IL offset: 0x5a
N001 ( 3, 2) [000106] ------------ t106 = LCL_VAR int V05 loc4
N002 ( 1, 1) [000107] ------------ t107 = CNS_INT int 0
/--* t106 int
+--* t107 int
N003 ( 5, 4) [000108] J------N---- t108 = * EQ int
/--* t108 int
N004 ( 7, 6) [000109] ------------ * JTRUE void
------------ BB10 [05E..069) -> BB15 (always), preds={BB09} succs={BB15}
[000239] ------------ IL_OFFSET void IL offset: 0x5e
N001 ( 1, 1) [000130] ------------ NO_OP void
[000240] ------------ IL_OFFSET void IL offset: 0x5f
N002 ( 3, 2) [000131] ------------ t131 = LCL_VAR byref V00 this
/--* t131 byref arg0 in rcx
N003 ( 17, 8) [000132] --CXG------- t132 = * CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].<ReadByte>g__ReadByteSlow|18_0
/--* t132 int
N005 ( 21, 11) [000134] DA-XG------- * STORE_LCL_VAR int V21 tmp12
[000241] ------------ IL_OFFSET void IL offset: 0x65
N001 ( 3, 2) [000135] ------------ t135 = LCL_VAR int V21 tmp12
/--* t135 int
N002 ( 4, 4) [000198] ------------ t198 = * CAST int <- ubyte <- int
/--* t198 int
N004 ( 8, 7) [000137] DA---------- * STORE_LCL_VAR int V06 loc5
[000242] ------------ IL_OFFSET void IL offset: 0x67
N001 ( 0, 0) [000138] ------------ NOP void
------------ BB11 [069..081) -> BB15 (always), preds={BB09} succs={BB15}
[000243] ------------ IL_OFFSET void IL offset: 0x69
N003 ( 3, 3) [000111] ------------ t111 = LCL_VAR_ADDR byref V03 loc2
N004 ( 3, 2) [000112] ------------ t112 = LCL_VAR int V02 loc1
/--* t111 byref this in rcx
+--* t112 int arg1 in rdx
N005 ( 20, 13) [000113] --CXG------- t113 = * CALL byref System.ReadOnlySpan`1[Byte][System.Byte].get_Item
/--* t113 byref
N007 ( 24, 16) [000115] DA-XG------- * STORE_LCL_VAR byref V20 tmp11
[000244] ------------ IL_OFFSET void IL offset: 0x71
N001 ( 3, 2) [000116] ------------ t116 = LCL_VAR byref V20 tmp11
/--* t116 byref
N002 ( 7, 5) [000117] *--XG------- t117 = * IND ubyte
/--* t117 ubyte
N004 ( 11, 8) [000119] DA-XG------- * STORE_LCL_VAR int V04 loc3
[000245] ------------ IL_OFFSET void IL offset: 0x73
N001 ( 3, 2) [000121] ------------ t121 = LCL_VAR int V02 loc1
N002 ( 1, 1) [000122] ------------ t122 = CNS_INT int 1
/--* t121 int
+--* t122 int
N003 ( 5, 4) [000123] ------------ t123 = * ADD int
N004 ( 3, 2) [000120] ------------ t120 = LCL_VAR byref V00 this
N005 ( 1, 1) [000201] ------------ t201 = CNS_INT long 24 field offset Fseq[_bufferPos]
/--* t120 byref
+--* t201 long
N006 ( 4, 3) [000202] -------N---- t202 = * ADD byref
/--* t202 byref
+--* t123 int
[000246] -A-XG------- * STOREIND int
[000247] ------------ IL_OFFSET void IL offset: 0x7c
N001 ( 3, 2) [000126] ------------ t126 = LCL_VAR int V04 loc3
/--* t126 int
N003 ( 7, 5) [000128] DA---------- * STORE_LCL_VAR int V06 loc5
[000248] ------------ IL_OFFSET void IL offset: 0x7f
N001 ( 0, 0) [000129] ------------ NOP void
------------ BB12 [081..09E) -> BB14 (cond), preds={BB08} succs={BB13,BB14}
[000249] ------------ IL_OFFSET void IL offset: 0x81
N004 ( 3, 2) [000204] ------------ t204 = LCL_VAR byref V00 this
/--* t204 byref
N005 ( 4, 3) [000205] ---X---N---- * NULLCHECK byte
N006 ( 3, 2) [000206] ------------ t206 = LCL_VAR byref V00 this
N007 ( 1, 1) [000207] ------------ t207 = CNS_INT long 64 field offset Fseq[_input]
/--* t206 byref
+--* t207 long
N008 ( 5, 4) [000208] ------------ t208 = * ADD byref
N010 ( 2, 10) [000046] H----------- t46 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t208 byref arg1 in rdx
+--* t46 long arg0 in rcx
N011 ( 25, 24) [000048] --CXG------- t48 = * CALL help ref HELPER.CORINFO_HELP_BOX
/--* t48 ref
N013 ( 29, 27) [000214] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp18
N014 ( 3, 2) [000215] ------------ t215 = LCL_VAR ref V27 tmp18
N015 ( 2, 10) [000049] H------N---- t49 = CNS_INT(h) long 0x7ff93b569758 class
/--* t215 ref arg1 in rdx
+--* t49 long arg0 in rcx
N016 ( 51, 46) [000050] --CXG------- t50 = * CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS
/--* t50 ref
N018 ( 55, 49) [000052] DA-XG------- * STORE_LCL_VAR ref V07 loc6
[000250] ------------ IL_OFFSET void IL offset: 0x93
N001 ( 3, 2) [000053] ------------ t53 = LCL_VAR ref V07 loc6
N002 ( 1, 1) [000054] ------------ t54 = CNS_INT ref null
/--* t53 ref
+--* t54 ref
N003 ( 8, 4) [000055] N----------- t55 = * NE int
/--* t55 int
N005 ( 12, 7) [000057] DA---------- * STORE_LCL_VAR int V08 loc7
[000251] ------------ IL_OFFSET void IL offset: 0x9a
N001 ( 3, 2) [000058] ------------ t58 = LCL_VAR int V08 loc7
N002 ( 1, 1) [000059] ------------ t59 = CNS_INT int 0
/--* t58 int
+--* t59 int
N003 ( 5, 4) [000060] J------N---- t60 = * EQ int
/--* t60 int
N004 ( 7, 6) [000061] ------------ * JTRUE void
------------ BB13 [09E..0AA) -> BB15 (always), preds={BB12} succs={BB15}
[000252] ------------ IL_OFFSET void IL offset: 0x9e
N001 ( 1, 1) [000072] ------------ NO_OP void
[000253] ------------ IL_OFFSET void IL offset: 0x9f
N002 ( 3, 2) [000073] ------------ t73 = LCL_VAR ref V07 loc6
/--* t73 ref this in rcx
N003 ( 23, 11) [000074] --CXG------- t74 = * CALLV ind int Hagar.Buffers.ReaderInput.ReadByte
/--* t74 int
N005 ( 27, 14) [000076] DA-XG------- * STORE_LCL_VAR int V17 tmp8
[000254] ------------ IL_OFFSET void IL offset: 0xa6
N001 ( 3, 2) [000077] ------------ t77 = LCL_VAR int V17 tmp8
/--* t77 int
N002 ( 4, 4) [000218] ------------ t218 = * CAST int <- ubyte <- int
/--* t218 int
N004 ( 8, 7) [000079] DA---------- * STORE_LCL_VAR int V06 loc5
[000255] ------------ IL_OFFSET void IL offset: 0xa8
N001 ( 0, 0) [000080] ------------ NOP void
------------ BB14 [0AA..0B4) -> BB15 (always), preds={BB12} succs={BB15}
[000256] ------------ IL_OFFSET void IL offset: 0xaa
N001 ( 1, 1) [000062] ------------ NO_OP void
[000257] ------------ IL_OFFSET void IL offset: 0xab
N001 ( 14, 5) [000063] --CXG------- t63 = CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].ThrowNotSupportedInput
/--* t63 int
N003 ( 18, 8) [000065] DA-XG------- * STORE_LCL_VAR int V16 tmp7
[000258] ------------ IL_OFFSET void IL offset: 0xb0
N001 ( 3, 2) [000066] ------------ t66 = LCL_VAR int V16 tmp7
/--* t66 int
N002 ( 4, 4) [000219] ------------ t219 = * CAST int <- ubyte <- int
/--* t219 int
N004 ( 8, 7) [000068] DA---------- * STORE_LCL_VAR int V06 loc5
[000259] ------------ IL_OFFSET void IL offset: 0xb2
N001 ( 0, 0) [000069] ------------ NOP void
------------ BB15 [0B4..0B7) (return), preds={BB10,BB11,BB13,BB14} succs={}
[000260] ------------ IL_OFFSET void IL offset: 0xb4
N001 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V06 loc5
/--* t70 int
N002 ( 4, 3) [000071] ------------ * RETURN int
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Do 'simple' lowering
Bumping outgoingArgSpaceSize to 32 for call [000175]
outgoingArgSpaceSize 32 sufficient for call [000003], which needs 32
outgoingArgSpaceSize 32 sufficient for call [000004], which needs 32
outgoingArgSpaceSize 32 sufficient for call [000015], which needs 32
outgoingArgSpaceSize 32 sufficient for call [000016], which needs 32
outgoingArgSpaceSize 32 sufficient for call [000026], which needs 32
outgoingArgSpaceSize 32 sufficient for call [000140], which needs 32
outgoingArgSpaceSize 32 sufficient for call [000141], which needs 32
outgoingArgSpaceSize 32 sufficient for call [000152], which needs 32
outgoingArgSpaceSize 32 sufficient for call [000153], which needs 32
outgoingArgSpaceSize 32 sufficient for call [000163], which needs 32
outgoingArgSpaceSize 32 sufficient for call [000094], which needs 32
outgoingArgSpaceSize 32 sufficient for call [000132], which needs 32
outgoingArgSpaceSize 32 sufficient for call [000113], which needs 32
outgoingArgSpaceSize 32 sufficient for call [000048], which needs 32
outgoingArgSpaceSize 32 sufficient for call [000050], which needs 32
outgoingArgSpaceSize 32 sufficient for call [000074], which needs 32
outgoingArgSpaceSize 32 sufficient for call [000063], which needs 32
*************** Finishing PHASE Do 'simple' lowering
*************** In fgDebugCheckBBlist
Trees before Lowering nodeinfo
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target hascall LIR
BB02 [0013] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
BB03 [0014] 1 BB02 0.50 [???..???) internal LIR
BB04 [0012] 2 BB02,BB03 1 [???..???) i internal label target hascall LIR
BB05 [0001] 1 BB04 1 [000..01C)-> BB07 ( cond ) i hascall LIR
BB06 [0002] 1 BB05 1 [01C..037)-> BB08 (always) i hascall LIR
BB07 [0003] 1 BB05 1 [037..038) i label target LIR
BB08 [0004] 2 BB06,BB07 1 [038..03C)-> BB12 ( cond ) i label target LIR
BB09 [0005] 1 BB08 1 [03C..05E)-> BB11 ( cond ) i hascall LIR
BB10 [0006] 1 BB09 1 [05E..069)-> BB15 (always) i hascall gcsafe LIR
BB11 [0007] 1 BB09 1 [069..081)-> BB15 (always) i label target hascall LIR
BB12 [0008] 1 BB08 1 [081..09E)-> BB14 ( cond ) i label target hascall nullcheck LIR
BB13 [0009] 1 BB12 1 [09E..0AA)-> BB15 (always) i hascall gcsafe LIR
BB14 [0010] 1 BB12 1 [0AA..0B4)-> BB15 (always) i label target hascall gcsafe LIR
BB15 [0011] 4 BB10,BB11,BB13,BB14 1 [0B4..0B7) (return) i label target LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
N001 ( 0, 0) [000000] ------------ NOP void
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
N001 ( 2, 10) [000171] H----------- t171 = CNS_INT(h) long 0x7ff9392a5420 global ptr
/--* t171 long
N002 ( 4, 12) [000172] n----------- t172 = * IND int
N003 ( 1, 1) [000173] ------------ t173 = CNS_INT int 0
/--* t172 int
+--* t173 int
N004 ( 6, 14) [000174] J------N---- t174 = * EQ int
/--* t174 int
N005 ( 8, 16) [000221] ------------ * JTRUE void
------------ BB03 [???..???), preds={BB02} succs={BB04}
N001 ( 14, 5) [000175] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
------------ BB05 [000..01C) -> BB07 (cond), preds={BB04} succs={BB06,BB07}
[000222] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000001] ------------ NO_OP void
[000223] ------------ IL_OFFSET void IL offset: 0x1
N002 ( 2, 10) [000002] H----------- t2 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t2 long arg0 in rcx
N003 ( 16, 16) [000003] --C-G------- t3 = * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t3 struct
N005 ( 20, 19) [000007] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
N002 ( 3, 4) [000008] ------------ t8 = LCL_FLD ref V10 tmp1 [+0]
/--* t8 ref arg0 in rcx
N003 ( 17, 10) [000004] --CXG------- t4 = * CALL ref System.Type.GetTypeFromHandle
/--* t4 ref
N005 ( 21, 13) [000012] DA-XG------- * STORE_LCL_VAR ref V11 tmp2
[000224] ------------ IL_OFFSET void IL offset: 0xb
N002 ( 2, 10) [000014] H----------- t14 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t14 long arg0 in rcx
N003 ( 16, 16) [000015] --C-G------- t15 = * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t15 struct
N005 ( 20, 19) [000019] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
N002 ( 3, 4) [000020] ------------ t20 = LCL_FLD ref V12 tmp3 [+0]
/--* t20 ref arg0 in rcx
N003 ( 17, 10) [000016] --CXG------- t16 = * CALL ref System.Type.GetTypeFromHandle
/--* t16 ref
N005 ( 21, 13) [000024] DA-XG------- * STORE_LCL_VAR ref V13 tmp4
[000225] ------------ IL_OFFSET void IL offset: 0x15
N003 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V11 tmp2
N004 ( 3, 2) [000025] ------------ t25 = LCL_VAR ref V13 tmp4
/--* t13 ref arg0 in rcx
+--* t25 ref arg1 in rdx
N005 ( 20, 11) [000026] --CXG------- t26 = * CALL int System.Type.op_Equality
/--* t26 int
N007 ( 24, 14) [000028] DA-XG------- * STORE_LCL_VAR int V14 tmp5
[000226] ------------ IL_OFFSET void IL offset: 0x1a
N001 ( 3, 2) [000029] ------------ t29 = LCL_VAR int V14 tmp5
N002 ( 1, 1) [000030] ------------ t30 = CNS_INT int 0
/--* t29 int
+--* t30 int
N003 ( 5, 4) [000031] J------N---- t31 = * NE int
/--* t31 int
N004 ( 7, 6) [000032] ------------ * JTRUE void
------------ BB06 [01C..037) -> BB08 (always), preds={BB05} succs={BB08}
[000227] ------------ IL_OFFSET void IL offset: 0x1c
N002 ( 2, 10) [000139] H----------- t139 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t139 long arg0 in rcx
N003 ( 16, 16) [000140] --C-G------- t140 = * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t140 struct
N005 ( 20, 19) [000144] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
N002 ( 3, 4) [000145] ------------ t145 = LCL_FLD ref V22 tmp13 [+0]
/--* t145 ref arg0 in rcx
N003 ( 17, 10) [000141] --CXG------- t141 = * CALL ref System.Type.GetTypeFromHandle
/--* t141 ref
N005 ( 21, 13) [000149] DA-XG------- * STORE_LCL_VAR ref V23 tmp14
[000228] ------------ IL_OFFSET void IL offset: 0x26
N002 ( 2, 10) [000151] H----------- t151 = CNS_INT(h) long 0x7ff93b56a7f8 class
/--* t151 long arg0 in rcx
N003 ( 16, 16) [000152] --C-G------- t152 = * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t152 struct
N005 ( 20, 19) [000156] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
N002 ( 3, 4) [000157] ------------ t157 = LCL_FLD ref V24 tmp15 [+0]
/--* t157 ref arg0 in rcx
N003 ( 17, 10) [000153] --CXG------- t153 = * CALL ref System.Type.GetTypeFromHandle
/--* t153 ref
N005 ( 21, 13) [000161] DA-XG------- * STORE_LCL_VAR ref V25 tmp16
[000229] ------------ IL_OFFSET void IL offset: 0x30
N003 ( 3, 2) [000150] ------------ t150 = LCL_VAR ref V23 tmp14
N004 ( 3, 2) [000162] ------------ t162 = LCL_VAR ref V25 tmp16
/--* t150 ref arg0 in rcx
+--* t162 ref arg1 in rdx
N005 ( 20, 11) [000163] --CXG------- t163 = * CALL int System.Type.op_Equality
/--* t163 int
N007 ( 24, 14) [000165] DA-XG------- * STORE_LCL_VAR int V26 tmp17
[000230] ------------ IL_OFFSET void IL offset: 0x35
N001 ( 0, 0) [000167] ------------ NOP void
N001 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V26 tmp17
/--* t166 int
N003 ( 7, 5) [000169] DA---------- * STORE_LCL_VAR int V15 tmp6
------------ BB07 [037..038), preds={BB05} succs={BB08}
[000231] ------------ IL_OFFSET void IL offset: 0x37
N001 ( 1, 1) [000033] ------------ t33 = CNS_INT int 1
/--* t33 int
N003 ( 5, 4) [000035] DA---------- * STORE_LCL_VAR int V15 tmp6
------------ BB08 [038..03C) -> BB12 (cond), preds={BB06,BB07} succs={BB09,BB12}
N001 ( 3, 2) [000037] ------------ t37 = LCL_VAR int V15 tmp6
/--* t37 int
N002 ( 4, 4) [000191] ------------ t191 = * CAST int <- bool <- int
/--* t191 int
N004 ( 8, 7) [000039] DA---------- * STORE_LCL_VAR int V01 loc0
[000232] ------------ IL_OFFSET void IL offset: 0x39
N001 ( 3, 2) [000040] ------------ t40 = LCL_VAR int V01 loc0
N002 ( 1, 1) [000041] ------------ t41 = CNS_INT int 0
/--* t40 int
+--* t41 int
N003 ( 5, 4) [000042] J------N---- t42 = * EQ int
/--* t42 int
N004 ( 7, 6) [000043] ------------ * JTRUE void
------------ BB09 [03C..05E) -> BB11 (cond), preds={BB08} succs={BB10,BB11}
[000233] ------------ IL_OFFSET void IL offset: 0x3c
N001 ( 1, 1) [000081] ------------ NO_OP void
[000234] ------------ IL_OFFSET void IL offset: 0x3d
N001 ( 3, 2) [000082] ------------ t82 = LCL_VAR byref V00 this
N002 ( 1, 1) [000192] ------------ t192 = CNS_INT long 24 field offset Fseq[_bufferPos]
/--* t82 byref
+--* t192 long
N003 ( 4, 3) [000193] -------N---- t193 = * ADD byref
/--* t193 byref
N004 ( 6, 5) [000083] *--XG------- t83 = * IND int
/--* t83 int
N006 ( 10, 8) [000085] DA-XG------- * STORE_LCL_VAR int V02 loc1
[000235] ------------ IL_OFFSET void IL offset: 0x44
N001 ( 3, 2) [000086] ------------ t86 = LCL_VAR byref V00 this
N002 ( 1, 1) [000194] ------------ t194 = CNS_INT long 32 field offset Fseq[_currentSpan]
/--* t86 byref
+--* t194 long
N003 ( 5, 4) [000195] ------------ t195 = * ADD byref
/--* t195 byref
N004 ( 8, 6) [000087] *--XG------- t87 = * IND struct
/--* t87 struct
N006 ( 12, 9) [000090] DA-XG------- * STORE_LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16>(AX) V03 loc2
[000236] ------------ IL_OFFSET void IL offset: 0x4b
N001 ( 3, 2) [000091] ------------ t91 = LCL_VAR int V02 loc1
/--* t91 int
N003 ( 7, 5) [000096] DA---------- * STORE_LCL_VAR int V18 tmp9
N002 ( 3, 3) [000093] ------------ t93 = LCL_VAR_ADDR byref V03 loc2
/--* t93 byref this in rcx
N003 ( 17, 10) [000094] --CXG------- t94 = * CALL int System.ReadOnlySpan`1[Byte][System.Byte].get_Length
/--* t94 int
N005 ( 21, 13) [000099] DA-XG------- * STORE_LCL_VAR int V19 tmp10
[000237] ------------ IL_OFFSET void IL offset: 0x53
N001 ( 3, 2) [000097] ------------ t97 = LCL_VAR int V18 tmp9
N002 ( 3, 2) [000100] ------------ t100 = LCL_VAR int V19 tmp10
/--* t97 int
+--* t100 int
N003 ( 10, 5) [000101] N--------U-- t101 = * GE int
/--* t101 int
N005 ( 14, 8) [000105] DA---------- * STORE_LCL_VAR int V05 loc4
[000238] ------------ IL_OFFSET void IL offset: 0x5a
N001 ( 3, 2) [000106] ------------ t106 = LCL_VAR int V05 loc4
N002 ( 1, 1) [000107] ------------ t107 = CNS_INT int 0
/--* t106 int
+--* t107 int
N003 ( 5, 4) [000108] J------N---- t108 = * EQ int
/--* t108 int
N004 ( 7, 6) [000109] ------------ * JTRUE void
------------ BB10 [05E..069) -> BB15 (always), preds={BB09} succs={BB15}
[000239] ------------ IL_OFFSET void IL offset: 0x5e
N001 ( 1, 1) [000130] ------------ NO_OP void
[000240] ------------ IL_OFFSET void IL offset: 0x5f
N002 ( 3, 2) [000131] ------------ t131 = LCL_VAR byref V00 this
/--* t131 byref arg0 in rcx
N003 ( 17, 8) [000132] --CXG------- t132 = * CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].<ReadByte>g__ReadByteSlow|18_0
/--* t132 int
N005 ( 21, 11) [000134] DA-XG------- * STORE_LCL_VAR int V21 tmp12
[000241] ------------ IL_OFFSET void IL offset: 0x65
N001 ( 3, 2) [000135] ------------ t135 = LCL_VAR int V21 tmp12
/--* t135 int
N002 ( 4, 4) [000198] ------------ t198 = * CAST int <- ubyte <- int
/--* t198 int
N004 ( 8, 7) [000137] DA---------- * STORE_LCL_VAR int V06 loc5
[000242] ------------ IL_OFFSET void IL offset: 0x67
N001 ( 0, 0) [000138] ------------ NOP void
------------ BB11 [069..081) -> BB15 (always), preds={BB09} succs={BB15}
[000243] ------------ IL_OFFSET void IL offset: 0x69
N003 ( 3, 3) [000111] ------------ t111 = LCL_VAR_ADDR byref V03 loc2
N004 ( 3, 2) [000112] ------------ t112 = LCL_VAR int V02 loc1
/--* t111 byref this in rcx
+--* t112 int arg1 in rdx
N005 ( 20, 13) [000113] --CXG------- t113 = * CALL byref System.ReadOnlySpan`1[Byte][System.Byte].get_Item
/--* t113 byref
N007 ( 24, 16) [000115] DA-XG------- * STORE_LCL_VAR byref V20 tmp11
[000244] ------------ IL_OFFSET void IL offset: 0x71
N001 ( 3, 2) [000116] ------------ t116 = LCL_VAR byref V20 tmp11
/--* t116 byref
N002 ( 7, 5) [000117] *--XG------- t117 = * IND ubyte
/--* t117 ubyte
N004 ( 11, 8) [000119] DA-XG------- * STORE_LCL_VAR int V04 loc3
[000245] ------------ IL_OFFSET void IL offset: 0x73
N001 ( 3, 2) [000121] ------------ t121 = LCL_VAR int V02 loc1
N002 ( 1, 1) [000122] ------------ t122 = CNS_INT int 1
/--* t121 int
+--* t122 int
N003 ( 5, 4) [000123] ------------ t123 = * ADD int
N004 ( 3, 2) [000120] ------------ t120 = LCL_VAR byref V00 this
N005 ( 1, 1) [000201] ------------ t201 = CNS_INT long 24 field offset Fseq[_bufferPos]
/--* t120 byref
+--* t201 long
N006 ( 4, 3) [000202] -------N---- t202 = * ADD byref
/--* t202 byref
+--* t123 int
[000246] -A-XG------- * STOREIND int
[000247] ------------ IL_OFFSET void IL offset: 0x7c
N001 ( 3, 2) [000126] ------------ t126 = LCL_VAR int V04 loc3
/--* t126 int
N003 ( 7, 5) [000128] DA---------- * STORE_LCL_VAR int V06 loc5
[000248] ------------ IL_OFFSET void IL offset: 0x7f
N001 ( 0, 0) [000129] ------------ NOP void
------------ BB12 [081..09E) -> BB14 (cond), preds={BB08} succs={BB13,BB14}
[000249] ------------ IL_OFFSET void IL offset: 0x81
N004 ( 3, 2) [000204] ------------ t204 = LCL_VAR byref V00 this
/--* t204 byref
N005 ( 4, 3) [000205] ---X---N---- * NULLCHECK byte
N006 ( 3, 2) [000206] ------------ t206 = LCL_VAR byref V00 this
N007 ( 1, 1) [000207] ------------ t207 = CNS_INT long 64 field offset Fseq[_input]
/--* t206 byref
+--* t207 long
N008 ( 5, 4) [000208] ------------ t208 = * ADD byref
N010 ( 2, 10) [000046] H----------- t46 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t208 byref arg1 in rdx
+--* t46 long arg0 in rcx
N011 ( 25, 24) [000048] --CXG------- t48 = * CALL help ref HELPER.CORINFO_HELP_BOX
/--* t48 ref
N013 ( 29, 27) [000214] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp18
N014 ( 3, 2) [000215] ------------ t215 = LCL_VAR ref V27 tmp18
N015 ( 2, 10) [000049] H------N---- t49 = CNS_INT(h) long 0x7ff93b569758 class
/--* t215 ref arg1 in rdx
+--* t49 long arg0 in rcx
N016 ( 51, 46) [000050] --CXG------- t50 = * CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS
/--* t50 ref
N018 ( 55, 49) [000052] DA-XG------- * STORE_LCL_VAR ref V07 loc6
[000250] ------------ IL_OFFSET void IL offset: 0x93
N001 ( 3, 2) [000053] ------------ t53 = LCL_VAR ref V07 loc6
N002 ( 1, 1) [000054] ------------ t54 = CNS_INT ref null
/--* t53 ref
+--* t54 ref
N003 ( 8, 4) [000055] N----------- t55 = * NE int
/--* t55 int
N005 ( 12, 7) [000057] DA---------- * STORE_LCL_VAR int V08 loc7
[000251] ------------ IL_OFFSET void IL offset: 0x9a
N001 ( 3, 2) [000058] ------------ t58 = LCL_VAR int V08 loc7
N002 ( 1, 1) [000059] ------------ t59 = CNS_INT int 0
/--* t58 int
+--* t59 int
N003 ( 5, 4) [000060] J------N---- t60 = * EQ int
/--* t60 int
N004 ( 7, 6) [000061] ------------ * JTRUE void
------------ BB13 [09E..0AA) -> BB15 (always), preds={BB12} succs={BB15}
[000252] ------------ IL_OFFSET void IL offset: 0x9e
N001 ( 1, 1) [000072] ------------ NO_OP void
[000253] ------------ IL_OFFSET void IL offset: 0x9f
N002 ( 3, 2) [000073] ------------ t73 = LCL_VAR ref V07 loc6
/--* t73 ref this in rcx
N003 ( 23, 11) [000074] --CXG------- t74 = * CALLV ind int Hagar.Buffers.ReaderInput.ReadByte
/--* t74 int
N005 ( 27, 14) [000076] DA-XG------- * STORE_LCL_VAR int V17 tmp8
[000254] ------------ IL_OFFSET void IL offset: 0xa6
N001 ( 3, 2) [000077] ------------ t77 = LCL_VAR int V17 tmp8
/--* t77 int
N002 ( 4, 4) [000218] ------------ t218 = * CAST int <- ubyte <- int
/--* t218 int
N004 ( 8, 7) [000079] DA---------- * STORE_LCL_VAR int V06 loc5
[000255] ------------ IL_OFFSET void IL offset: 0xa8
N001 ( 0, 0) [000080] ------------ NOP void
------------ BB14 [0AA..0B4) -> BB15 (always), preds={BB12} succs={BB15}
[000256] ------------ IL_OFFSET void IL offset: 0xaa
N001 ( 1, 1) [000062] ------------ NO_OP void
[000257] ------------ IL_OFFSET void IL offset: 0xab
N001 ( 14, 5) [000063] --CXG------- t63 = CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].ThrowNotSupportedInput
/--* t63 int
N003 ( 18, 8) [000065] DA-XG------- * STORE_LCL_VAR int V16 tmp7
[000258] ------------ IL_OFFSET void IL offset: 0xb0
N001 ( 3, 2) [000066] ------------ t66 = LCL_VAR int V16 tmp7
/--* t66 int
N002 ( 4, 4) [000219] ------------ t219 = * CAST int <- ubyte <- int
/--* t219 int
N004 ( 8, 7) [000068] DA---------- * STORE_LCL_VAR int V06 loc5
[000259] ------------ IL_OFFSET void IL offset: 0xb2
N001 ( 0, 0) [000069] ------------ NOP void
------------ BB15 [0B4..0B7) (return), preds={BB10,BB11,BB13,BB14} succs={}
[000260] ------------ IL_OFFSET void IL offset: 0xb4
N001 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V06 loc5
/--* t70 int
N002 ( 4, 3) [000071] ------------ * RETURN int
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Lowering nodeinfo
lowering call (before):
N001 ( 14, 5) [000175] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
objp:
======
args:
======
late:
======
lowering call (after):
N001 ( 14, 5) [000175] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
lowering call (before):
N002 ( 2, 10) [000002] H----------- t2 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t2 long arg0 in rcx
N003 ( 16, 16) [000003] --C-G------- t3 = * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000179] ----------L- * ARGPLACE long
late:
======
lowering arg : N002 ( 2, 10) [000002] H----------- * CNS_INT(h) long 0x7ff93af7cd80 class
new node is : [000261] ------------ * PUTARG_REG long REG rcx
lowering call (after):
N002 ( 2, 10) [000002] H----------- t2 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t2 long
[000261] ------------ t261 = * PUTARG_REG long REG rcx
/--* t261 long arg0 in rcx
N003 ( 16, 16) [000003] --C-G------- t3 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
lowering store lcl var/field (before):
N002 ( 2, 10) [000002] H----------- t2 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t2 long
[000261] ------------ t261 = * PUTARG_REG long REG rcx
/--* t261 long arg0 in rcx
N003 ( 16, 16) [000003] --C-G------- t3 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t3 ref
N005 ( 20, 19) [000007] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
lowering store lcl var/field (after):
N002 ( 2, 10) [000002] H----------- t2 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t2 long
[000261] ------------ t261 = * PUTARG_REG long REG rcx
/--* t261 long arg0 in rcx
N003 ( 16, 16) [000003] --C-G------- t3 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t3 ref
N005 ( 20, 19) [000007] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
lowering call (before):
N002 ( 3, 4) [000008] ------------ t8 = LCL_FLD ref V10 tmp1 [+0]
/--* t8 ref arg0 in rcx
N003 ( 17, 10) [000004] --CXG------- t4 = * CALL ref System.Type.GetTypeFromHandle
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000180] ----------L- * ARGPLACE ref
late:
======
lowering arg : N002 ( 3, 4) [000008] ------------ * LCL_FLD ref V10 tmp1 [+0]
new node is : [000262] ------------ * PUTARG_REG ref REG rcx
lowering call (after):
N002 ( 3, 4) [000008] ------------ t8 = LCL_FLD ref V10 tmp1 [+0]
/--* t8 ref
[000262] ------------ t262 = * PUTARG_REG ref REG rcx
/--* t262 ref arg0 in rcx
N003 ( 17, 10) [000004] --CXG------- t4 = * CALL ref System.Type.GetTypeFromHandle
lowering store lcl var/field (before):
N002 ( 3, 4) [000008] ------------ t8 = LCL_FLD ref V10 tmp1 [+0]
/--* t8 ref
[000262] ------------ t262 = * PUTARG_REG ref REG rcx
/--* t262 ref arg0 in rcx
N003 ( 17, 10) [000004] --CXG------- t4 = * CALL ref System.Type.GetTypeFromHandle
/--* t4 ref
N005 ( 21, 13) [000012] DA-XG------- * STORE_LCL_VAR ref V11 tmp2
lowering store lcl var/field (after):
N002 ( 3, 4) [000008] ------------ t8 = LCL_FLD ref V10 tmp1 [+0]
/--* t8 ref
[000262] ------------ t262 = * PUTARG_REG ref REG rcx
/--* t262 ref arg0 in rcx
N003 ( 17, 10) [000004] --CXG------- t4 = * CALL ref System.Type.GetTypeFromHandle
/--* t4 ref
N005 ( 21, 13) [000012] DA-XG------- * STORE_LCL_VAR ref V11 tmp2
lowering call (before):
N002 ( 2, 10) [000014] H----------- t14 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t14 long arg0 in rcx
N003 ( 16, 16) [000015] --C-G------- t15 = * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000181] ----------L- * ARGPLACE long
late:
======
lowering arg : N002 ( 2, 10) [000014] H----------- * CNS_INT(h) long 0x7ff93af7cd80 class
new node is : [000263] ------------ * PUTARG_REG long REG rcx
lowering call (after):
N002 ( 2, 10) [000014] H----------- t14 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t14 long
[000263] ------------ t263 = * PUTARG_REG long REG rcx
/--* t263 long arg0 in rcx
N003 ( 16, 16) [000015] --C-G------- t15 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
lowering store lcl var/field (before):
N002 ( 2, 10) [000014] H----------- t14 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t14 long
[000263] ------------ t263 = * PUTARG_REG long REG rcx
/--* t263 long arg0 in rcx
N003 ( 16, 16) [000015] --C-G------- t15 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t15 ref
N005 ( 20, 19) [000019] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
lowering store lcl var/field (after):
N002 ( 2, 10) [000014] H----------- t14 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t14 long
[000263] ------------ t263 = * PUTARG_REG long REG rcx
/--* t263 long arg0 in rcx
N003 ( 16, 16) [000015] --C-G------- t15 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t15 ref
N005 ( 20, 19) [000019] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
lowering call (before):
N002 ( 3, 4) [000020] ------------ t20 = LCL_FLD ref V12 tmp3 [+0]
/--* t20 ref arg0 in rcx
N003 ( 17, 10) [000016] --CXG------- t16 = * CALL ref System.Type.GetTypeFromHandle
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000182] ----------L- * ARGPLACE ref
late:
======
lowering arg : N002 ( 3, 4) [000020] ------------ * LCL_FLD ref V12 tmp3 [+0]
new node is : [000264] ------------ * PUTARG_REG ref REG rcx
lowering call (after):
N002 ( 3, 4) [000020] ------------ t20 = LCL_FLD ref V12 tmp3 [+0]
/--* t20 ref
[000264] ------------ t264 = * PUTARG_REG ref REG rcx
/--* t264 ref arg0 in rcx
N003 ( 17, 10) [000016] --CXG------- t16 = * CALL ref System.Type.GetTypeFromHandle
lowering store lcl var/field (before):
N002 ( 3, 4) [000020] ------------ t20 = LCL_FLD ref V12 tmp3 [+0]
/--* t20 ref
[000264] ------------ t264 = * PUTARG_REG ref REG rcx
/--* t264 ref arg0 in rcx
N003 ( 17, 10) [000016] --CXG------- t16 = * CALL ref System.Type.GetTypeFromHandle
/--* t16 ref
N005 ( 21, 13) [000024] DA-XG------- * STORE_LCL_VAR ref V13 tmp4
lowering store lcl var/field (after):
N002 ( 3, 4) [000020] ------------ t20 = LCL_FLD ref V12 tmp3 [+0]
/--* t20 ref
[000264] ------------ t264 = * PUTARG_REG ref REG rcx
/--* t264 ref arg0 in rcx
N003 ( 17, 10) [000016] --CXG------- t16 = * CALL ref System.Type.GetTypeFromHandle
/--* t16 ref
N005 ( 21, 13) [000024] DA-XG------- * STORE_LCL_VAR ref V13 tmp4
lowering call (before):
N003 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V11 tmp2
N004 ( 3, 2) [000025] ------------ t25 = LCL_VAR ref V13 tmp4
/--* t13 ref arg0 in rcx
+--* t25 ref arg1 in rdx
N005 ( 20, 11) [000026] --CXG------- t26 = * CALL int System.Type.op_Equality
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000183] ----------L- * ARGPLACE ref
lowering arg : N002 ( 0, 0) [000184] ----------L- * ARGPLACE ref
late:
======
lowering arg : N003 ( 3, 2) [000013] ------------ * LCL_VAR ref V11 tmp2
new node is : [000265] ------------ * PUTARG_REG ref REG rcx
lowering arg : N004 ( 3, 2) [000025] ------------ * LCL_VAR ref V13 tmp4
new node is : [000266] ------------ * PUTARG_REG ref REG rdx
lowering call (after):
N003 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V11 tmp2
/--* t13 ref
[000265] ------------ t265 = * PUTARG_REG ref REG rcx
N004 ( 3, 2) [000025] ------------ t25 = LCL_VAR ref V13 tmp4
/--* t25 ref
[000266] ------------ t266 = * PUTARG_REG ref REG rdx
/--* t265 ref arg0 in rcx
+--* t266 ref arg1 in rdx
N005 ( 20, 11) [000026] --CXG------- t26 = * CALL int System.Type.op_Equality
lowering store lcl var/field (before):
N003 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V11 tmp2
/--* t13 ref
[000265] ------------ t265 = * PUTARG_REG ref REG rcx
N004 ( 3, 2) [000025] ------------ t25 = LCL_VAR ref V13 tmp4
/--* t25 ref
[000266] ------------ t266 = * PUTARG_REG ref REG rdx
/--* t265 ref arg0 in rcx
+--* t266 ref arg1 in rdx
N005 ( 20, 11) [000026] --CXG------- t26 = * CALL int System.Type.op_Equality
/--* t26 int
N007 ( 24, 14) [000028] DA-XG------- * STORE_LCL_VAR int V14 tmp5
lowering store lcl var/field (after):
N003 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V11 tmp2
/--* t13 ref
[000265] ------------ t265 = * PUTARG_REG ref REG rcx
N004 ( 3, 2) [000025] ------------ t25 = LCL_VAR ref V13 tmp4
/--* t25 ref
[000266] ------------ t266 = * PUTARG_REG ref REG rdx
/--* t265 ref arg0 in rcx
+--* t266 ref arg1 in rdx
N005 ( 20, 11) [000026] --CXG------- t26 = * CALL int System.Type.op_Equality
/--* t26 int
N007 ( 24, 14) [000028] DA-XG------- * STORE_LCL_VAR int V14 tmp5
lowering call (before):
N002 ( 2, 10) [000139] H----------- t139 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t139 long arg0 in rcx
N003 ( 16, 16) [000140] --C-G------- t140 = * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000185] ----------L- * ARGPLACE long
late:
======
lowering arg : N002 ( 2, 10) [000139] H----------- * CNS_INT(h) long 0x7ff93af7cd80 class
new node is : [000267] ------------ * PUTARG_REG long REG rcx
lowering call (after):
N002 ( 2, 10) [000139] H----------- t139 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t139 long
[000267] ------------ t267 = * PUTARG_REG long REG rcx
/--* t267 long arg0 in rcx
N003 ( 16, 16) [000140] --C-G------- t140 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
lowering store lcl var/field (before):
N002 ( 2, 10) [000139] H----------- t139 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t139 long
[000267] ------------ t267 = * PUTARG_REG long REG rcx
/--* t267 long arg0 in rcx
N003 ( 16, 16) [000140] --C-G------- t140 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t140 ref
N005 ( 20, 19) [000144] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
lowering store lcl var/field (after):
N002 ( 2, 10) [000139] H----------- t139 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t139 long
[000267] ------------ t267 = * PUTARG_REG long REG rcx
/--* t267 long arg0 in rcx
N003 ( 16, 16) [000140] --C-G------- t140 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t140 ref
N005 ( 20, 19) [000144] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
lowering call (before):
N002 ( 3, 4) [000145] ------------ t145 = LCL_FLD ref V22 tmp13 [+0]
/--* t145 ref arg0 in rcx
N003 ( 17, 10) [000141] --CXG------- t141 = * CALL ref System.Type.GetTypeFromHandle
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000186] ----------L- * ARGPLACE ref
late:
======
lowering arg : N002 ( 3, 4) [000145] ------------ * LCL_FLD ref V22 tmp13 [+0]
new node is : [000268] ------------ * PUTARG_REG ref REG rcx
lowering call (after):
N002 ( 3, 4) [000145] ------------ t145 = LCL_FLD ref V22 tmp13 [+0]
/--* t145 ref
[000268] ------------ t268 = * PUTARG_REG ref REG rcx
/--* t268 ref arg0 in rcx
N003 ( 17, 10) [000141] --CXG------- t141 = * CALL ref System.Type.GetTypeFromHandle
lowering store lcl var/field (before):
N002 ( 3, 4) [000145] ------------ t145 = LCL_FLD ref V22 tmp13 [+0]
/--* t145 ref
[000268] ------------ t268 = * PUTARG_REG ref REG rcx
/--* t268 ref arg0 in rcx
N003 ( 17, 10) [000141] --CXG------- t141 = * CALL ref System.Type.GetTypeFromHandle
/--* t141 ref
N005 ( 21, 13) [000149] DA-XG------- * STORE_LCL_VAR ref V23 tmp14
lowering store lcl var/field (after):
N002 ( 3, 4) [000145] ------------ t145 = LCL_FLD ref V22 tmp13 [+0]
/--* t145 ref
[000268] ------------ t268 = * PUTARG_REG ref REG rcx
/--* t268 ref arg0 in rcx
N003 ( 17, 10) [000141] --CXG------- t141 = * CALL ref System.Type.GetTypeFromHandle
/--* t141 ref
N005 ( 21, 13) [000149] DA-XG------- * STORE_LCL_VAR ref V23 tmp14
lowering call (before):
N002 ( 2, 10) [000151] H----------- t151 = CNS_INT(h) long 0x7ff93b56a7f8 class
/--* t151 long arg0 in rcx
N003 ( 16, 16) [000152] --C-G------- t152 = * CALL help struct HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000187] ----------L- * ARGPLACE long
late:
======
lowering arg : N002 ( 2, 10) [000151] H----------- * CNS_INT(h) long 0x7ff93b56a7f8 class
new node is : [000269] ------------ * PUTARG_REG long REG rcx
lowering call (after):
N002 ( 2, 10) [000151] H----------- t151 = CNS_INT(h) long 0x7ff93b56a7f8 class
/--* t151 long
[000269] ------------ t269 = * PUTARG_REG long REG rcx
/--* t269 long arg0 in rcx
N003 ( 16, 16) [000152] --C-G------- t152 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
lowering store lcl var/field (before):
N002 ( 2, 10) [000151] H----------- t151 = CNS_INT(h) long 0x7ff93b56a7f8 class
/--* t151 long
[000269] ------------ t269 = * PUTARG_REG long REG rcx
/--* t269 long arg0 in rcx
N003 ( 16, 16) [000152] --C-G------- t152 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t152 ref
N005 ( 20, 19) [000156] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
lowering store lcl var/field (after):
N002 ( 2, 10) [000151] H----------- t151 = CNS_INT(h) long 0x7ff93b56a7f8 class
/--* t151 long
[000269] ------------ t269 = * PUTARG_REG long REG rcx
/--* t269 long arg0 in rcx
N003 ( 16, 16) [000152] --C-G------- t152 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t152 ref
N005 ( 20, 19) [000156] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
lowering call (before):
N002 ( 3, 4) [000157] ------------ t157 = LCL_FLD ref V24 tmp15 [+0]
/--* t157 ref arg0 in rcx
N003 ( 17, 10) [000153] --CXG------- t153 = * CALL ref System.Type.GetTypeFromHandle
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000188] ----------L- * ARGPLACE ref
late:
======
lowering arg : N002 ( 3, 4) [000157] ------------ * LCL_FLD ref V24 tmp15 [+0]
new node is : [000270] ------------ * PUTARG_REG ref REG rcx
lowering call (after):
N002 ( 3, 4) [000157] ------------ t157 = LCL_FLD ref V24 tmp15 [+0]
/--* t157 ref
[000270] ------------ t270 = * PUTARG_REG ref REG rcx
/--* t270 ref arg0 in rcx
N003 ( 17, 10) [000153] --CXG------- t153 = * CALL ref System.Type.GetTypeFromHandle
lowering store lcl var/field (before):
N002 ( 3, 4) [000157] ------------ t157 = LCL_FLD ref V24 tmp15 [+0]
/--* t157 ref
[000270] ------------ t270 = * PUTARG_REG ref REG rcx
/--* t270 ref arg0 in rcx
N003 ( 17, 10) [000153] --CXG------- t153 = * CALL ref System.Type.GetTypeFromHandle
/--* t153 ref
N005 ( 21, 13) [000161] DA-XG------- * STORE_LCL_VAR ref V25 tmp16
lowering store lcl var/field (after):
N002 ( 3, 4) [000157] ------------ t157 = LCL_FLD ref V24 tmp15 [+0]
/--* t157 ref
[000270] ------------ t270 = * PUTARG_REG ref REG rcx
/--* t270 ref arg0 in rcx
N003 ( 17, 10) [000153] --CXG------- t153 = * CALL ref System.Type.GetTypeFromHandle
/--* t153 ref
N005 ( 21, 13) [000161] DA-XG------- * STORE_LCL_VAR ref V25 tmp16
lowering call (before):
N003 ( 3, 2) [000150] ------------ t150 = LCL_VAR ref V23 tmp14
N004 ( 3, 2) [000162] ------------ t162 = LCL_VAR ref V25 tmp16
/--* t150 ref arg0 in rcx
+--* t162 ref arg1 in rdx
N005 ( 20, 11) [000163] --CXG------- t163 = * CALL int System.Type.op_Equality
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000189] ----------L- * ARGPLACE ref
lowering arg : N002 ( 0, 0) [000190] ----------L- * ARGPLACE ref
late:
======
lowering arg : N003 ( 3, 2) [000150] ------------ * LCL_VAR ref V23 tmp14
new node is : [000271] ------------ * PUTARG_REG ref REG rcx
lowering arg : N004 ( 3, 2) [000162] ------------ * LCL_VAR ref V25 tmp16
new node is : [000272] ------------ * PUTARG_REG ref REG rdx
lowering call (after):
N003 ( 3, 2) [000150] ------------ t150 = LCL_VAR ref V23 tmp14
/--* t150 ref
[000271] ------------ t271 = * PUTARG_REG ref REG rcx
N004 ( 3, 2) [000162] ------------ t162 = LCL_VAR ref V25 tmp16
/--* t162 ref
[000272] ------------ t272 = * PUTARG_REG ref REG rdx
/--* t271 ref arg0 in rcx
+--* t272 ref arg1 in rdx
N005 ( 20, 11) [000163] --CXG------- t163 = * CALL int System.Type.op_Equality
lowering store lcl var/field (before):
N003 ( 3, 2) [000150] ------------ t150 = LCL_VAR ref V23 tmp14
/--* t150 ref
[000271] ------------ t271 = * PUTARG_REG ref REG rcx
N004 ( 3, 2) [000162] ------------ t162 = LCL_VAR ref V25 tmp16
/--* t162 ref
[000272] ------------ t272 = * PUTARG_REG ref REG rdx
/--* t271 ref arg0 in rcx
+--* t272 ref arg1 in rdx
N005 ( 20, 11) [000163] --CXG------- t163 = * CALL int System.Type.op_Equality
/--* t163 int
N007 ( 24, 14) [000165] DA-XG------- * STORE_LCL_VAR int V26 tmp17
lowering store lcl var/field (after):
N003 ( 3, 2) [000150] ------------ t150 = LCL_VAR ref V23 tmp14
/--* t150 ref
[000271] ------------ t271 = * PUTARG_REG ref REG rcx
N004 ( 3, 2) [000162] ------------ t162 = LCL_VAR ref V25 tmp16
/--* t162 ref
[000272] ------------ t272 = * PUTARG_REG ref REG rdx
/--* t271 ref arg0 in rcx
+--* t272 ref arg1 in rdx
N005 ( 20, 11) [000163] --CXG------- t163 = * CALL int System.Type.op_Equality
/--* t163 int
N007 ( 24, 14) [000165] DA-XG------- * STORE_LCL_VAR int V26 tmp17
lowering store lcl var/field (before):
N001 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V26 tmp17
/--* t166 int
N003 ( 7, 5) [000169] DA---------- * STORE_LCL_VAR int V15 tmp6
lowering store lcl var/field (after):
N001 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V26 tmp17
/--* t166 int
N003 ( 7, 5) [000169] DA---------- * STORE_LCL_VAR int V15 tmp6
lowering store lcl var/field (before):
N001 ( 1, 1) [000033] ------------ t33 = CNS_INT int 1
/--* t33 int
N003 ( 5, 4) [000035] DA---------- * STORE_LCL_VAR int V15 tmp6
lowering store lcl var/field (after):
N001 ( 1, 1) [000033] -c---------- t33 = CNS_INT int 1
/--* t33 int
N003 ( 5, 4) [000035] DA---------- * STORE_LCL_VAR int V15 tmp6
lowering store lcl var/field (before):
N001 ( 3, 2) [000037] ------------ t37 = LCL_VAR int V15 tmp6
/--* t37 int
N002 ( 4, 4) [000191] ------------ t191 = * CAST int <- bool <- int
/--* t191 int
N004 ( 8, 7) [000039] DA---------- * STORE_LCL_VAR int V01 loc0
lowering store lcl var/field (after):
N001 ( 3, 2) [000037] ------------ t37 = LCL_VAR int V15 tmp6
/--* t37 int
N002 ( 4, 4) [000191] ------------ t191 = * CAST int <- bool <- int
/--* t191 int
N004 ( 8, 7) [000039] DA---------- * STORE_LCL_VAR int V01 loc0
Addressing mode:
Base
N001 ( 3, 2) [000082] ------------ * LCL_VAR byref V00 this
+ 24
Removing unused node:
N002 ( 1, 1) [000192] -c---------- * CNS_INT long 24 field offset Fseq[_bufferPos]
New addressing mode node:
N003 ( 4, 3) [000193] ------------ * LEA(b+24) byref
lowering store lcl var/field (before):
N001 ( 3, 2) [000082] ------------ t82 = LCL_VAR byref V00 this
/--* t82 byref
N003 ( 4, 3) [000193] -c---------- t193 = * LEA(b+24) byref
/--* t193 byref
N004 ( 6, 5) [000083] *--XG------- t83 = * IND int
/--* t83 int
N006 ( 10, 8) [000085] DA-XG------- * STORE_LCL_VAR int V02 loc1
lowering store lcl var/field (after):
N001 ( 3, 2) [000082] ------------ t82 = LCL_VAR byref V00 this
/--* t82 byref
N003 ( 4, 3) [000193] -c---------- t193 = * LEA(b+24) byref
/--* t193 byref
N004 ( 6, 5) [000083] *--XG------- t83 = * IND int
/--* t83 int
N006 ( 10, 8) [000085] DA-XG------- * STORE_LCL_VAR int V02 loc1
lowering store lcl var/field (before):
N001 ( 3, 2) [000086] ------------ t86 = LCL_VAR byref V00 this
N002 ( 1, 1) [000194] -c---------- t194 = CNS_INT long 32 field offset Fseq[_currentSpan]
/--* t86 byref
+--* t194 long
N003 ( 5, 4) [000195] ------------ t195 = * ADD byref
/--* t195 byref
N004 ( 8, 6) [000087] *--XG------- t87 = * IND struct
/--* t87 struct
N006 ( 12, 9) [000090] DA-XG------- * STORE_LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16>(AX) V03 loc2
Addressing mode:
Base
N001 ( 3, 2) [000086] ------------ * LCL_VAR byref V00 this
+ 32
Removing unused node:
N002 ( 1, 1) [000194] -c---------- * CNS_INT long 32 field offset Fseq[_currentSpan]
New addressing mode node:
N003 ( 5, 4) [000195] ------------ * LEA(b+32) byref
lowering store lcl var/field (before):
N001 ( 3, 2) [000091] ------------ t91 = LCL_VAR int V02 loc1
/--* t91 int
N003 ( 7, 5) [000096] DA---------- * STORE_LCL_VAR int V18 tmp9
lowering store lcl var/field (after):
N001 ( 3, 2) [000091] ------------ t91 = LCL_VAR int V02 loc1
/--* t91 int
N003 ( 7, 5) [000096] DA---------- * STORE_LCL_VAR int V18 tmp9
lowering call (before):
N002 ( 3, 3) [000093] ------------ t93 = LCL_VAR_ADDR byref V03 loc2
/--* t93 byref this in rcx
N003 ( 17, 10) [000094] --CXG------- t94 = * CALL int System.ReadOnlySpan`1[Byte][System.Byte].get_Length
objp:
======
lowering arg : N001 ( 0, 0) [000196] ----------L- * ARGPLACE byref
args:
======
late:
======
lowering arg : N002 ( 3, 3) [000093] ------------ * LCL_VAR_ADDR byref V03 loc2
new node is : [000274] ------------ * PUTARG_REG byref REG rcx
lowering call (after):
N002 ( 3, 3) [000093] ------------ t93 = LCL_VAR_ADDR byref V03 loc2
/--* t93 byref
[000274] ------------ t274 = * PUTARG_REG byref REG rcx
/--* t274 byref this in rcx
N003 ( 17, 10) [000094] --CXG------- t94 = * CALL int System.ReadOnlySpan`1[Byte][System.Byte].get_Length
lowering store lcl var/field (before):
N002 ( 3, 3) [000093] ------------ t93 = LCL_VAR_ADDR byref V03 loc2
/--* t93 byref
[000274] ------------ t274 = * PUTARG_REG byref REG rcx
/--* t274 byref this in rcx
N003 ( 17, 10) [000094] --CXG------- t94 = * CALL int System.ReadOnlySpan`1[Byte][System.Byte].get_Length
/--* t94 int
N005 ( 21, 13) [000099] DA-XG------- * STORE_LCL_VAR int V19 tmp10
lowering store lcl var/field (after):
N002 ( 3, 3) [000093] ------------ t93 = LCL_VAR_ADDR byref V03 loc2
/--* t93 byref
[000274] ------------ t274 = * PUTARG_REG byref REG rcx
/--* t274 byref this in rcx
N003 ( 17, 10) [000094] --CXG------- t94 = * CALL int System.ReadOnlySpan`1[Byte][System.Byte].get_Length
/--* t94 int
N005 ( 21, 13) [000099] DA-XG------- * STORE_LCL_VAR int V19 tmp10
lowering store lcl var/field (before):
N001 ( 3, 2) [000097] ------------ t97 = LCL_VAR int V18 tmp9
N002 ( 3, 2) [000100] -c---------- t100 = LCL_VAR int V19 tmp10
/--* t97 int
+--* t100 int
N003 ( 10, 5) [000101] N--------U-- t101 = * GE int
/--* t101 int
N005 ( 14, 8) [000105] DA---------- * STORE_LCL_VAR int V05 loc4
lowering store lcl var/field (after):
N001 ( 3, 2) [000097] ------------ t97 = LCL_VAR int V18 tmp9
N002 ( 3, 2) [000100] -c---------- t100 = LCL_VAR int V19 tmp10
/--* t97 int
+--* t100 int
N003 ( 10, 5) [000101] N--------U-- t101 = * GE int
/--* t101 int
N005 ( 14, 8) [000105] DA---------- * STORE_LCL_VAR int V05 loc4
lowering call (before):
N002 ( 3, 2) [000131] ------------ t131 = LCL_VAR byref V00 this
/--* t131 byref arg0 in rcx
N003 ( 17, 8) [000132] --CXG------- t132 = * CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].<ReadByte>g__ReadByteSlow|18_0
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000197] ----------L- * ARGPLACE byref
late:
======
lowering arg : N002 ( 3, 2) [000131] ------------ * LCL_VAR byref V00 this
new node is : [000275] ------------ * PUTARG_REG byref REG rcx
lowering call (after):
N002 ( 3, 2) [000131] ------------ t131 = LCL_VAR byref V00 this
/--* t131 byref
[000275] ------------ t275 = * PUTARG_REG byref REG rcx
/--* t275 byref arg0 in rcx
N003 ( 17, 8) [000132] --CXG------- t132 = * CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].<ReadByte>g__ReadByteSlow|18_0
lowering store lcl var/field (before):
N002 ( 3, 2) [000131] ------------ t131 = LCL_VAR byref V00 this
/--* t131 byref
[000275] ------------ t275 = * PUTARG_REG byref REG rcx
/--* t275 byref arg0 in rcx
N003 ( 17, 8) [000132] --CXG------- t132 = * CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].<ReadByte>g__ReadByteSlow|18_0
/--* t132 int
N005 ( 21, 11) [000134] DA-XG------- * STORE_LCL_VAR int V21 tmp12
lowering store lcl var/field (after):
N002 ( 3, 2) [000131] ------------ t131 = LCL_VAR byref V00 this
/--* t131 byref
[000275] ------------ t275 = * PUTARG_REG byref REG rcx
/--* t275 byref arg0 in rcx
N003 ( 17, 8) [000132] --CXG------- t132 = * CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].<ReadByte>g__ReadByteSlow|18_0
/--* t132 int
N005 ( 21, 11) [000134] DA-XG------- * STORE_LCL_VAR int V21 tmp12
lowering store lcl var/field (before):
N001 ( 3, 2) [000135] ------------ t135 = LCL_VAR int V21 tmp12
/--* t135 int
N002 ( 4, 4) [000198] ------------ t198 = * CAST int <- ubyte <- int
/--* t198 int
N004 ( 8, 7) [000137] DA---------- * STORE_LCL_VAR int V06 loc5
lowering store lcl var/field (after):
N001 ( 3, 2) [000135] ------------ t135 = LCL_VAR int V21 tmp12
/--* t135 int
N002 ( 4, 4) [000198] ------------ t198 = * CAST int <- ubyte <- int
/--* t198 int
N004 ( 8, 7) [000137] DA---------- * STORE_LCL_VAR int V06 loc5
lowering call (before):
N003 ( 3, 3) [000111] ------------ t111 = LCL_VAR_ADDR byref V03 loc2
N004 ( 3, 2) [000112] ------------ t112 = LCL_VAR int V02 loc1
/--* t111 byref this in rcx
+--* t112 int arg1 in rdx
N005 ( 20, 13) [000113] --CXG------- t113 = * CALL byref System.ReadOnlySpan`1[Byte][System.Byte].get_Item
objp:
======
lowering arg : N001 ( 0, 0) [000199] ----------L- * ARGPLACE byref
args:
======
lowering arg : N002 ( 0, 0) [000200] ----------L- * ARGPLACE int
late:
======
lowering arg : N003 ( 3, 3) [000111] ------------ * LCL_VAR_ADDR byref V03 loc2
new node is : [000276] ------------ * PUTARG_REG byref REG rcx
lowering arg : N004 ( 3, 2) [000112] ------------ * LCL_VAR int V02 loc1
new node is : [000277] ------------ * PUTARG_REG int REG rdx
lowering call (after):
N003 ( 3, 3) [000111] ------------ t111 = LCL_VAR_ADDR byref V03 loc2
/--* t111 byref
[000276] ------------ t276 = * PUTARG_REG byref REG rcx
N004 ( 3, 2) [000112] ------------ t112 = LCL_VAR int V02 loc1
/--* t112 int
[000277] ------------ t277 = * PUTARG_REG int REG rdx
/--* t276 byref this in rcx
+--* t277 int arg1 in rdx
N005 ( 20, 13) [000113] --CXG------- t113 = * CALL byref System.ReadOnlySpan`1[Byte][System.Byte].get_Item
lowering store lcl var/field (before):
N003 ( 3, 3) [000111] ------------ t111 = LCL_VAR_ADDR byref V03 loc2
/--* t111 byref
[000276] ------------ t276 = * PUTARG_REG byref REG rcx
N004 ( 3, 2) [000112] ------------ t112 = LCL_VAR int V02 loc1
/--* t112 int
[000277] ------------ t277 = * PUTARG_REG int REG rdx
/--* t276 byref this in rcx
+--* t277 int arg1 in rdx
N005 ( 20, 13) [000113] --CXG------- t113 = * CALL byref System.ReadOnlySpan`1[Byte][System.Byte].get_Item
/--* t113 byref
N007 ( 24, 16) [000115] DA-XG------- * STORE_LCL_VAR byref V20 tmp11
lowering store lcl var/field (after):
N003 ( 3, 3) [000111] ------------ t111 = LCL_VAR_ADDR byref V03 loc2
/--* t111 byref
[000276] ------------ t276 = * PUTARG_REG byref REG rcx
N004 ( 3, 2) [000112] ------------ t112 = LCL_VAR int V02 loc1
/--* t112 int
[000277] ------------ t277 = * PUTARG_REG int REG rdx
/--* t276 byref this in rcx
+--* t277 int arg1 in rdx
N005 ( 20, 13) [000113] --CXG------- t113 = * CALL byref System.ReadOnlySpan`1[Byte][System.Byte].get_Item
/--* t113 byref
N007 ( 24, 16) [000115] DA-XG------- * STORE_LCL_VAR byref V20 tmp11
lowering store lcl var/field (before):
N001 ( 3, 2) [000116] ------------ t116 = LCL_VAR byref V20 tmp11
/--* t116 byref
N002 ( 7, 5) [000117] *--XG------- t117 = * IND ubyte
/--* t117 ubyte
N004 ( 11, 8) [000119] DA-XG------- * STORE_LCL_VAR int V04 loc3
lowering store lcl var/field (after):
N001 ( 3, 2) [000116] ------------ t116 = LCL_VAR byref V20 tmp11
/--* t116 byref
N002 ( 7, 5) [000117] *--XG------- t117 = * IND ubyte
/--* t117 ubyte
N004 ( 11, 8) [000119] DA-XG------- * STORE_LCL_VAR int V04 loc3
Addressing mode:
Base
N004 ( 3, 2) [000120] ------------ * LCL_VAR byref V00 this
+ 24
Removing unused node:
N005 ( 1, 1) [000201] -c---------- * CNS_INT long 24 field offset Fseq[_bufferPos]
New addressing mode node:
N006 ( 4, 3) [000202] ------------ * LEA(b+24) byref
Lower of StoreInd didn't mark the node as self contained for reason: 3
N001 ( 3, 2) [000121] ------------ t121 = LCL_VAR int V02 loc1
N002 ( 1, 1) [000122] -c---------- t122 = CNS_INT int 1
/--* t121 int
+--* t122 int
N003 ( 5, 4) [000123] ------------ t123 = * ADD int
N004 ( 3, 2) [000120] ------------ t120 = LCL_VAR byref V00 this
/--* t120 byref
N006 ( 4, 3) [000202] ------------ t202 = * LEA(b+24) byref
/--* t202 byref
+--* t123 int
[000246] -A-XG------- * STOREIND int
lowering store lcl var/field (before):
N001 ( 3, 2) [000126] ------------ t126 = LCL_VAR int V04 loc3
/--* t126 int
N003 ( 7, 5) [000128] DA---------- * STORE_LCL_VAR int V06 loc5
lowering store lcl var/field (after):
N001 ( 3, 2) [000126] ------------ t126 = LCL_VAR int V04 loc3
/--* t126 int
N003 ( 7, 5) [000128] DA---------- * STORE_LCL_VAR int V06 loc5
lowering call (before):
N006 ( 3, 2) [000206] ------------ t206 = LCL_VAR byref V00 this
N007 ( 1, 1) [000207] -c---------- t207 = CNS_INT long 64 field offset Fseq[_input]
/--* t206 byref
+--* t207 long
N008 ( 5, 4) [000208] ------------ t208 = * ADD byref
N010 ( 2, 10) [000046] H----------- t46 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t208 byref arg1 in rdx
+--* t46 long arg0 in rcx
N011 ( 25, 24) [000048] --CXG------- t48 = * CALL help ref HELPER.CORINFO_HELP_BOX
objp:
======
args:
======
lowering arg : N002 ( 0, 0) [000212] ----------L- * ARGPLACE long
lowering arg : N003 ( 0, 0) [000211] ----------L- * ARGPLACE byref
late:
======
lowering arg : N008 ( 5, 4) [000208] ------------ * ADD byref
new node is : [000278] ------------ * PUTARG_REG byref REG rdx
lowering arg : N010 ( 2, 10) [000046] H----------- * CNS_INT(h) long 0x7ff93af7cd80 class
new node is : [000279] ------------ * PUTARG_REG long REG rcx
lowering call (after):
N006 ( 3, 2) [000206] ------------ t206 = LCL_VAR byref V00 this
N007 ( 1, 1) [000207] -c---------- t207 = CNS_INT long 64 field offset Fseq[_input]
/--* t206 byref
+--* t207 long
N008 ( 5, 4) [000208] ------------ t208 = * ADD byref
/--* t208 byref
[000278] ------------ t278 = * PUTARG_REG byref REG rdx
N010 ( 2, 10) [000046] H----------- t46 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t46 long
[000279] ------------ t279 = * PUTARG_REG long REG rcx
/--* t278 byref arg1 in rdx
+--* t279 long arg0 in rcx
N011 ( 25, 24) [000048] --CXG------- t48 = * CALL help ref HELPER.CORINFO_HELP_BOX
lowering store lcl var/field (before):
N006 ( 3, 2) [000206] ------------ t206 = LCL_VAR byref V00 this
N007 ( 1, 1) [000207] -c---------- t207 = CNS_INT long 64 field offset Fseq[_input]
/--* t206 byref
+--* t207 long
N008 ( 5, 4) [000208] ------------ t208 = * ADD byref
/--* t208 byref
[000278] ------------ t278 = * PUTARG_REG byref REG rdx
N010 ( 2, 10) [000046] H----------- t46 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t46 long
[000279] ------------ t279 = * PUTARG_REG long REG rcx
/--* t278 byref arg1 in rdx
+--* t279 long arg0 in rcx
N011 ( 25, 24) [000048] --CXG------- t48 = * CALL help ref HELPER.CORINFO_HELP_BOX
/--* t48 ref
N013 ( 29, 27) [000214] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp18
lowering store lcl var/field (after):
N006 ( 3, 2) [000206] ------------ t206 = LCL_VAR byref V00 this
N007 ( 1, 1) [000207] -c---------- t207 = CNS_INT long 64 field offset Fseq[_input]
/--* t206 byref
+--* t207 long
N008 ( 5, 4) [000208] ------------ t208 = * ADD byref
/--* t208 byref
[000278] ------------ t278 = * PUTARG_REG byref REG rdx
N010 ( 2, 10) [000046] H----------- t46 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t46 long
[000279] ------------ t279 = * PUTARG_REG long REG rcx
/--* t278 byref arg1 in rdx
+--* t279 long arg0 in rcx
N011 ( 25, 24) [000048] --CXG------- t48 = * CALL help ref HELPER.CORINFO_HELP_BOX
/--* t48 ref
N013 ( 29, 27) [000214] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp18
lowering call (before):
N006 ( 3, 2) [000206] ------------ t206 = LCL_VAR byref V00 this
N007 ( 1, 1) [000207] -c---------- t207 = CNS_INT long 64 field offset Fseq[_input]
/--* t206 byref
+--* t207 long
N008 ( 5, 4) [000208] ------------ t208 = * ADD byref
/--* t208 byref
[000278] ------------ t278 = * PUTARG_REG byref REG rdx
N010 ( 2, 10) [000046] H----------- t46 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t46 long
[000279] ------------ t279 = * PUTARG_REG long REG rcx
/--* t278 byref arg1 in rdx
+--* t279 long arg0 in rcx
N011 ( 25, 24) [000048] --CXG------- t48 = * CALL help ref HELPER.CORINFO_HELP_BOX
/--* t48 ref
N013 ( 29, 27) [000214] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp18
N014 ( 3, 2) [000215] ------------ t215 = LCL_VAR ref V27 tmp18
N015 ( 2, 10) [000049] H------N---- t49 = CNS_INT(h) long 0x7ff93b569758 class
/--* t215 ref arg1 in rdx
+--* t49 long arg0 in rcx
N016 ( 51, 46) [000050] --CXG------- t50 = * CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000216] ----------L- * ARGPLACE long
lowering arg : N013 ( 29, 27) [000214] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp18
late:
======
lowering arg : N014 ( 3, 2) [000215] ------------ * LCL_VAR ref V27 tmp18
new node is : [000280] ------------ * PUTARG_REG ref REG rdx
lowering arg : N015 ( 2, 10) [000049] H------N---- * CNS_INT(h) long 0x7ff93b569758 class
new node is : [000281] ------------ * PUTARG_REG long REG rcx
lowering call (after):
N006 ( 3, 2) [000206] ------------ t206 = LCL_VAR byref V00 this
N007 ( 1, 1) [000207] -c---------- t207 = CNS_INT long 64 field offset Fseq[_input]
/--* t206 byref
+--* t207 long
N008 ( 5, 4) [000208] ------------ t208 = * ADD byref
/--* t208 byref
[000278] ------------ t278 = * PUTARG_REG byref REG rdx
N010 ( 2, 10) [000046] H----------- t46 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t46 long
[000279] ------------ t279 = * PUTARG_REG long REG rcx
/--* t278 byref arg1 in rdx
+--* t279 long arg0 in rcx
N011 ( 25, 24) [000048] --CXG------- t48 = * CALL help ref HELPER.CORINFO_HELP_BOX
/--* t48 ref
N013 ( 29, 27) [000214] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp18
N014 ( 3, 2) [000215] ------------ t215 = LCL_VAR ref V27 tmp18
/--* t215 ref
[000280] ------------ t280 = * PUTARG_REG ref REG rdx
N015 ( 2, 10) [000049] H------N---- t49 = CNS_INT(h) long 0x7ff93b569758 class
/--* t49 long
[000281] ------------ t281 = * PUTARG_REG long REG rcx
/--* t280 ref arg1 in rdx
+--* t281 long arg0 in rcx
N016 ( 51, 46) [000050] --CXG------- t50 = * CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS
lowering store lcl var/field (before):
N006 ( 3, 2) [000206] ------------ t206 = LCL_VAR byref V00 this
N007 ( 1, 1) [000207] -c---------- t207 = CNS_INT long 64 field offset Fseq[_input]
/--* t206 byref
+--* t207 long
N008 ( 5, 4) [000208] ------------ t208 = * ADD byref
/--* t208 byref
[000278] ------------ t278 = * PUTARG_REG byref REG rdx
N010 ( 2, 10) [000046] H----------- t46 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t46 long
[000279] ------------ t279 = * PUTARG_REG long REG rcx
/--* t278 byref arg1 in rdx
+--* t279 long arg0 in rcx
N011 ( 25, 24) [000048] --CXG------- t48 = * CALL help ref HELPER.CORINFO_HELP_BOX
/--* t48 ref
N013 ( 29, 27) [000214] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp18
N014 ( 3, 2) [000215] ------------ t215 = LCL_VAR ref V27 tmp18
/--* t215 ref
[000280] ------------ t280 = * PUTARG_REG ref REG rdx
N015 ( 2, 10) [000049] H------N---- t49 = CNS_INT(h) long 0x7ff93b569758 class
/--* t49 long
[000281] ------------ t281 = * PUTARG_REG long REG rcx
/--* t280 ref arg1 in rdx
+--* t281 long arg0 in rcx
N016 ( 51, 46) [000050] --CXG------- t50 = * CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS
/--* t50 ref
N018 ( 55, 49) [000052] DA-XG------- * STORE_LCL_VAR ref V07 loc6
lowering store lcl var/field (after):
N006 ( 3, 2) [000206] ------------ t206 = LCL_VAR byref V00 this
N007 ( 1, 1) [000207] -c---------- t207 = CNS_INT long 64 field offset Fseq[_input]
/--* t206 byref
+--* t207 long
N008 ( 5, 4) [000208] ------------ t208 = * ADD byref
/--* t208 byref
[000278] ------------ t278 = * PUTARG_REG byref REG rdx
N010 ( 2, 10) [000046] H----------- t46 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t46 long
[000279] ------------ t279 = * PUTARG_REG long REG rcx
/--* t278 byref arg1 in rdx
+--* t279 long arg0 in rcx
N011 ( 25, 24) [000048] --CXG------- t48 = * CALL help ref HELPER.CORINFO_HELP_BOX
/--* t48 ref
N013 ( 29, 27) [000214] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp18
N014 ( 3, 2) [000215] ------------ t215 = LCL_VAR ref V27 tmp18
/--* t215 ref
[000280] ------------ t280 = * PUTARG_REG ref REG rdx
N015 ( 2, 10) [000049] H------N---- t49 = CNS_INT(h) long 0x7ff93b569758 class
/--* t49 long
[000281] ------------ t281 = * PUTARG_REG long REG rcx
/--* t280 ref arg1 in rdx
+--* t281 long arg0 in rcx
N016 ( 51, 46) [000050] --CXG------- t50 = * CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS
/--* t50 ref
N018 ( 55, 49) [000052] DA-XG------- * STORE_LCL_VAR ref V07 loc6
lowering store lcl var/field (before):
N001 ( 3, 2) [000053] -c---------- t53 = LCL_VAR ref V07 loc6
N002 ( 1, 1) [000054] -c---------- t54 = CNS_INT ref null
/--* t53 ref
+--* t54 ref
N003 ( 8, 4) [000055] N----------- t55 = * NE int
/--* t55 int
N005 ( 12, 7) [000057] DA---------- * STORE_LCL_VAR int V08 loc7
lowering store lcl var/field (after):
N001 ( 3, 2) [000053] -c---------- t53 = LCL_VAR ref V07 loc6
N002 ( 1, 1) [000054] -c---------- t54 = CNS_INT ref null
/--* t53 ref
+--* t54 ref
N003 ( 8, 4) [000055] N----------- t55 = * NE int
/--* t55 int
N005 ( 12, 7) [000057] DA---------- * STORE_LCL_VAR int V08 loc7
lowering call (before):
N002 ( 3, 2) [000073] ------------ t73 = LCL_VAR ref V07 loc6
/--* t73 ref this in rcx
N003 ( 23, 11) [000074] --CXG------- t74 = * CALLV ind int Hagar.Buffers.ReaderInput.ReadByte
objp:
======
lowering arg : N001 ( 0, 0) [000217] ----------L- * ARGPLACE ref
args:
======
late:
======
lowering arg : N002 ( 3, 2) [000073] ------------ * LCL_VAR ref V07 loc6
new node is : [000282] ------------ * PUTARG_REG ref REG rcx
results of lowering call:
N001 ( 3, 2) [000283] ------------ t283 = LCL_VAR ref V07 loc6
/--* t283 ref
N002 ( 4, 3) [000284] ------------ t284 = * LEA(b+0) byref
/--* t284 byref
N003 ( 7, 5) [000285] ------------ t285 = * IND long
/--* t285 long
N004 ( 8, 6) [000286] ------------ t286 = * LEA(b+72) long
/--* t286 long
N005 ( 11, 8) [000287] ------------ t287 = * IND long
/--* t287 long
N006 ( 12, 9) [000288] ------------ t288 = * LEA(b+56) long
/--* t288 long
N007 ( 15, 11) [000289] ------------ t289 = * IND long
lowering call (after):
N002 ( 3, 2) [000073] ------------ t73 = LCL_VAR ref V07 loc6
/--* t73 ref
[000282] ------------ t282 = * PUTARG_REG ref REG rcx
N001 ( 3, 2) [000283] ------------ t283 = LCL_VAR ref V07 loc6
/--* t283 ref
N002 ( 4, 3) [000284] -c---------- t284 = * LEA(b+0) byref
/--* t284 byref
N003 ( 7, 5) [000285] ------------ t285 = * IND long
/--* t285 long
N004 ( 8, 6) [000286] -c---------- t286 = * LEA(b+72) long
/--* t286 long
N005 ( 11, 8) [000287] ------------ t287 = * IND long
/--* t287 long
N006 ( 12, 9) [000288] -c---------- t288 = * LEA(b+56) long
/--* t288 long
N007 ( 15, 11) [000289] -c---------- t289 = * IND long REG NA
/--* t282 ref this in rcx
+--* t289 long control expr
N003 ( 23, 11) [000074] --CXG------- t74 = * CALLV ind int Hagar.Buffers.ReaderInput.ReadByte
lowering store lcl var/field (before):
N002 ( 3, 2) [000073] ------------ t73 = LCL_VAR ref V07 loc6
/--* t73 ref
[000282] ------------ t282 = * PUTARG_REG ref REG rcx
N001 ( 3, 2) [000283] ------------ t283 = LCL_VAR ref V07 loc6
/--* t283 ref
N002 ( 4, 3) [000284] -c---------- t284 = * LEA(b+0) byref
/--* t284 byref
N003 ( 7, 5) [000285] ------------ t285 = * IND long
/--* t285 long
N004 ( 8, 6) [000286] -c---------- t286 = * LEA(b+72) long
/--* t286 long
N005 ( 11, 8) [000287] ------------ t287 = * IND long
/--* t287 long
N006 ( 12, 9) [000288] -c---------- t288 = * LEA(b+56) long
/--* t288 long
N007 ( 15, 11) [000289] -c---------- t289 = * IND long REG NA
/--* t282 ref this in rcx
+--* t289 long control expr
N003 ( 23, 11) [000074] --CXG------- t74 = * CALLV ind int Hagar.Buffers.ReaderInput.ReadByte
/--* t74 int
N005 ( 27, 14) [000076] DA-XG------- * STORE_LCL_VAR int V17 tmp8
lowering store lcl var/field (after):
N002 ( 3, 2) [000073] ------------ t73 = LCL_VAR ref V07 loc6
/--* t73 ref
[000282] ------------ t282 = * PUTARG_REG ref REG rcx
N001 ( 3, 2) [000283] ------------ t283 = LCL_VAR ref V07 loc6
/--* t283 ref
N002 ( 4, 3) [000284] -c---------- t284 = * LEA(b+0) byref
/--* t284 byref
N003 ( 7, 5) [000285] ------------ t285 = * IND long
/--* t285 long
N004 ( 8, 6) [000286] -c---------- t286 = * LEA(b+72) long
/--* t286 long
N005 ( 11, 8) [000287] ------------ t287 = * IND long
/--* t287 long
N006 ( 12, 9) [000288] -c---------- t288 = * LEA(b+56) long
/--* t288 long
N007 ( 15, 11) [000289] -c---------- t289 = * IND long REG NA
/--* t282 ref this in rcx
+--* t289 long control expr
N003 ( 23, 11) [000074] --CXG------- t74 = * CALLV ind int Hagar.Buffers.ReaderInput.ReadByte
/--* t74 int
N005 ( 27, 14) [000076] DA-XG------- * STORE_LCL_VAR int V17 tmp8
lowering store lcl var/field (before):
N001 ( 3, 2) [000077] ------------ t77 = LCL_VAR int V17 tmp8
/--* t77 int
N002 ( 4, 4) [000218] ------------ t218 = * CAST int <- ubyte <- int
/--* t218 int
N004 ( 8, 7) [000079] DA---------- * STORE_LCL_VAR int V06 loc5
lowering store lcl var/field (after):
N001 ( 3, 2) [000077] ------------ t77 = LCL_VAR int V17 tmp8
/--* t77 int
N002 ( 4, 4) [000218] ------------ t218 = * CAST int <- ubyte <- int
/--* t218 int
N004 ( 8, 7) [000079] DA---------- * STORE_LCL_VAR int V06 loc5
lowering call (before):
N001 ( 14, 5) [000063] --CXG------- t63 = CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].ThrowNotSupportedInput
objp:
======
args:
======
late:
======
lowering call (after):
N001 ( 14, 5) [000063] --CXG------- t63 = CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].ThrowNotSupportedInput
lowering store lcl var/field (before):
N001 ( 14, 5) [000063] --CXG------- t63 = CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].ThrowNotSupportedInput
/--* t63 int
N003 ( 18, 8) [000065] DA-XG------- * STORE_LCL_VAR int V16 tmp7
lowering store lcl var/field (after):
N001 ( 14, 5) [000063] --CXG------- t63 = CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].ThrowNotSupportedInput
/--* t63 int
N003 ( 18, 8) [000065] DA-XG------- * STORE_LCL_VAR int V16 tmp7
lowering store lcl var/field (before):
N001 ( 3, 2) [000066] ------------ t66 = LCL_VAR int V16 tmp7
/--* t66 int
N002 ( 4, 4) [000219] ------------ t219 = * CAST int <- ubyte <- int
/--* t219 int
N004 ( 8, 7) [000068] DA---------- * STORE_LCL_VAR int V06 loc5
lowering store lcl var/field (after):
N001 ( 3, 2) [000066] ------------ t66 = LCL_VAR int V16 tmp7
/--* t66 int
N002 ( 4, 4) [000219] ------------ t219 = * CAST int <- ubyte <- int
/--* t219 int
N004 ( 8, 7) [000068] DA---------- * STORE_LCL_VAR int V06 loc5
lowering GT_RETURN
N002 ( 4, 3) [000071] ------------ * RETURN int
============Lower has completed modifying nodes.
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target hascall LIR
BB02 [0013] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
BB03 [0014] 1 BB02 0.50 [???..???) internal LIR
BB04 [0012] 2 BB02,BB03 1 [???..???) i internal label target hascall LIR
BB05 [0001] 1 BB04 1 [000..01C)-> BB07 ( cond ) i hascall LIR
BB06 [0002] 1 BB05 1 [01C..037)-> BB08 (always) i hascall LIR
BB07 [0003] 1 BB05 1 [037..038) i label target LIR
BB08 [0004] 2 BB06,BB07 1 [038..03C)-> BB12 ( cond ) i label target LIR
BB09 [0005] 1 BB08 1 [03C..05E)-> BB11 ( cond ) i hascall LIR
BB10 [0006] 1 BB09 1 [05E..069)-> BB15 (always) i hascall gcsafe LIR
BB11 [0007] 1 BB09 1 [069..081)-> BB15 (always) i label target hascall LIR
BB12 [0008] 1 BB08 1 [081..09E)-> BB14 ( cond ) i label target hascall nullcheck LIR
BB13 [0009] 1 BB12 1 [09E..0AA)-> BB15 (always) i hascall gcsafe LIR
BB14 [0010] 1 BB12 1 [0AA..0B4)-> BB15 (always) i label target hascall gcsafe LIR
BB15 [0011] 4 BB10,BB11,BB13,BB14 1 [0B4..0B7) (return) i label target LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
N001 ( 0, 0) [000000] ------------ NOP void
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
N001 ( 2, 10) [000171] Hc---------- t171 = CNS_INT(h) long 0x7ff9392a5420 global ptr
/--* t171 long
N002 ( 4, 12) [000172] nc---------- t172 = * IND int
N003 ( 1, 1) [000173] -c---------- t173 = CNS_INT int 0
/--* t172 int
+--* t173 int
N004 ( 6, 14) [000174] J------N---- * EQ void
N005 ( 8, 16) [000221] ------------ * JTRUE void
------------ BB03 [???..???), preds={BB02} succs={BB04}
N001 ( 14, 5) [000175] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
------------ BB05 [000..01C) -> BB07 (cond), preds={BB04} succs={BB06,BB07}
[000222] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000001] ------------ NO_OP void
[000223] ------------ IL_OFFSET void IL offset: 0x1
N002 ( 2, 10) [000002] H----------- t2 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t2 long
[000261] ------------ t261 = * PUTARG_REG long REG rcx
/--* t261 long arg0 in rcx
N003 ( 16, 16) [000003] --C-G------- t3 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t3 ref
N005 ( 20, 19) [000007] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
N002 ( 3, 4) [000008] ------------ t8 = LCL_FLD ref V10 tmp1 [+0]
/--* t8 ref
[000262] ------------ t262 = * PUTARG_REG ref REG rcx
/--* t262 ref arg0 in rcx
N003 ( 17, 10) [000004] --CXG------- t4 = * CALL ref System.Type.GetTypeFromHandle
/--* t4 ref
N005 ( 21, 13) [000012] DA-XG------- * STORE_LCL_VAR ref V11 tmp2
[000224] ------------ IL_OFFSET void IL offset: 0xb
N002 ( 2, 10) [000014] H----------- t14 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t14 long
[000263] ------------ t263 = * PUTARG_REG long REG rcx
/--* t263 long arg0 in rcx
N003 ( 16, 16) [000015] --C-G------- t15 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t15 ref
N005 ( 20, 19) [000019] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
N002 ( 3, 4) [000020] ------------ t20 = LCL_FLD ref V12 tmp3 [+0]
/--* t20 ref
[000264] ------------ t264 = * PUTARG_REG ref REG rcx
/--* t264 ref arg0 in rcx
N003 ( 17, 10) [000016] --CXG------- t16 = * CALL ref System.Type.GetTypeFromHandle
/--* t16 ref
N005 ( 21, 13) [000024] DA-XG------- * STORE_LCL_VAR ref V13 tmp4
[000225] ------------ IL_OFFSET void IL offset: 0x15
N003 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V11 tmp2
/--* t13 ref
[000265] ------------ t265 = * PUTARG_REG ref REG rcx
N004 ( 3, 2) [000025] ------------ t25 = LCL_VAR ref V13 tmp4
/--* t25 ref
[000266] ------------ t266 = * PUTARG_REG ref REG rdx
/--* t265 ref arg0 in rcx
+--* t266 ref arg1 in rdx
N005 ( 20, 11) [000026] --CXG------- t26 = * CALL int System.Type.op_Equality
/--* t26 int
N007 ( 24, 14) [000028] DA-XG------- * STORE_LCL_VAR int V14 tmp5
[000226] ------------ IL_OFFSET void IL offset: 0x1a
N001 ( 3, 2) [000029] -c---------- t29 = LCL_VAR int V14 tmp5
N002 ( 1, 1) [000030] -c---------- t30 = CNS_INT int 0
/--* t29 int
+--* t30 int
N003 ( 5, 4) [000031] J------N---- * NE void
N004 ( 7, 6) [000032] ------------ * JTRUE void
------------ BB06 [01C..037) -> BB08 (always), preds={BB05} succs={BB08}
[000227] ------------ IL_OFFSET void IL offset: 0x1c
N002 ( 2, 10) [000139] H----------- t139 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t139 long
[000267] ------------ t267 = * PUTARG_REG long REG rcx
/--* t267 long arg0 in rcx
N003 ( 16, 16) [000140] --C-G------- t140 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t140 ref
N005 ( 20, 19) [000144] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
N002 ( 3, 4) [000145] ------------ t145 = LCL_FLD ref V22 tmp13 [+0]
/--* t145 ref
[000268] ------------ t268 = * PUTARG_REG ref REG rcx
/--* t268 ref arg0 in rcx
N003 ( 17, 10) [000141] --CXG------- t141 = * CALL ref System.Type.GetTypeFromHandle
/--* t141 ref
N005 ( 21, 13) [000149] DA-XG------- * STORE_LCL_VAR ref V23 tmp14
[000228] ------------ IL_OFFSET void IL offset: 0x26
N002 ( 2, 10) [000151] H----------- t151 = CNS_INT(h) long 0x7ff93b56a7f8 class
/--* t151 long
[000269] ------------ t269 = * PUTARG_REG long REG rcx
/--* t269 long arg0 in rcx
N003 ( 16, 16) [000152] --C-G------- t152 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t152 ref
N005 ( 20, 19) [000156] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
N002 ( 3, 4) [000157] ------------ t157 = LCL_FLD ref V24 tmp15 [+0]
/--* t157 ref
[000270] ------------ t270 = * PUTARG_REG ref REG rcx
/--* t270 ref arg0 in rcx
N003 ( 17, 10) [000153] --CXG------- t153 = * CALL ref System.Type.GetTypeFromHandle
/--* t153 ref
N005 ( 21, 13) [000161] DA-XG------- * STORE_LCL_VAR ref V25 tmp16
[000229] ------------ IL_OFFSET void IL offset: 0x30
N003 ( 3, 2) [000150] ------------ t150 = LCL_VAR ref V23 tmp14
/--* t150 ref
[000271] ------------ t271 = * PUTARG_REG ref REG rcx
N004 ( 3, 2) [000162] ------------ t162 = LCL_VAR ref V25 tmp16
/--* t162 ref
[000272] ------------ t272 = * PUTARG_REG ref REG rdx
/--* t271 ref arg0 in rcx
+--* t272 ref arg1 in rdx
N005 ( 20, 11) [000163] --CXG------- t163 = * CALL int System.Type.op_Equality
/--* t163 int
N007 ( 24, 14) [000165] DA-XG------- * STORE_LCL_VAR int V26 tmp17
[000230] ------------ IL_OFFSET void IL offset: 0x35
N001 ( 0, 0) [000167] ------------ NOP void
N001 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V26 tmp17
/--* t166 int
N003 ( 7, 5) [000169] DA---------- * STORE_LCL_VAR int V15 tmp6
------------ BB07 [037..038), preds={BB05} succs={BB08}
[000231] ------------ IL_OFFSET void IL offset: 0x37
N001 ( 1, 1) [000033] -c---------- t33 = CNS_INT int 1
/--* t33 int
N003 ( 5, 4) [000035] DA---------- * STORE_LCL_VAR int V15 tmp6
------------ BB08 [038..03C) -> BB12 (cond), preds={BB06,BB07} succs={BB09,BB12}
N001 ( 3, 2) [000037] ------------ t37 = LCL_VAR int V15 tmp6
/--* t37 int
N002 ( 4, 4) [000191] ------------ t191 = * CAST int <- bool <- int
/--* t191 int
N004 ( 8, 7) [000039] DA---------- * STORE_LCL_VAR int V01 loc0
[000232] ------------ IL_OFFSET void IL offset: 0x39
N001 ( 3, 2) [000040] -c---------- t40 = LCL_VAR int V01 loc0
N002 ( 1, 1) [000041] -c---------- t41 = CNS_INT int 0
/--* t40 int
+--* t41 int
N003 ( 5, 4) [000042] J------N---- * EQ void
N004 ( 7, 6) [000043] ------------ * JTRUE void
------------ BB09 [03C..05E) -> BB11 (cond), preds={BB08} succs={BB10,BB11}
[000233] ------------ IL_OFFSET void IL offset: 0x3c
N001 ( 1, 1) [000081] ------------ NO_OP void
[000234] ------------ IL_OFFSET void IL offset: 0x3d
N001 ( 3, 2) [000082] ------------ t82 = LCL_VAR byref V00 this
/--* t82 byref
N003 ( 4, 3) [000193] -c---------- t193 = * LEA(b+24) byref
/--* t193 byref
N004 ( 6, 5) [000083] *--XG------- t83 = * IND int
/--* t83 int
N006 ( 10, 8) [000085] DA-XG------- * STORE_LCL_VAR int V02 loc1
[000235] ------------ IL_OFFSET void IL offset: 0x44
N001 ( 3, 2) [000086] ------------ t86 = LCL_VAR byref V00 this
/--* t86 byref
N003 ( 5, 4) [000195] -c---------- t195 = * LEA(b+32) byref
/--* t195 byref
N004 ( 8, 6) [000087] *c-XG------- t87 = * IND struct
[000273] Dc-----N---- t273 = LCL_VAR_ADDR byref V03 loc2
/--* t273 byref
+--* t87 struct
N006 ( 12, 9) [000090] sA---------- * STORE_BLK struct<System.ReadOnlySpan`1[Byte], 16> (copy) (Unroll)
[000236] ------------ IL_OFFSET void IL offset: 0x4b
N001 ( 3, 2) [000091] ------------ t91 = LCL_VAR int V02 loc1
/--* t91 int
N003 ( 7, 5) [000096] DA---------- * STORE_LCL_VAR int V18 tmp9
N002 ( 3, 3) [000093] ------------ t93 = LCL_VAR_ADDR byref V03 loc2
/--* t93 byref
[000274] ------------ t274 = * PUTARG_REG byref REG rcx
/--* t274 byref this in rcx
N003 ( 17, 10) [000094] --CXG------- t94 = * CALL int System.ReadOnlySpan`1[Byte][System.Byte].get_Length
/--* t94 int
N005 ( 21, 13) [000099] DA-XG------- * STORE_LCL_VAR int V19 tmp10
[000237] ------------ IL_OFFSET void IL offset: 0x53
N001 ( 3, 2) [000097] ------------ t97 = LCL_VAR int V18 tmp9
N002 ( 3, 2) [000100] -c---------- t100 = LCL_VAR int V19 tmp10
/--* t97 int
+--* t100 int
N003 ( 10, 5) [000101] N--------U-- t101 = * GE int
/--* t101 int
N005 ( 14, 8) [000105] DA---------- * STORE_LCL_VAR int V05 loc4
[000238] ------------ IL_OFFSET void IL offset: 0x5a
N001 ( 3, 2) [000106] -c---------- t106 = LCL_VAR int V05 loc4
N002 ( 1, 1) [000107] -c---------- t107 = CNS_INT int 0
/--* t106 int
+--* t107 int
N003 ( 5, 4) [000108] J------N---- * EQ void
N004 ( 7, 6) [000109] ------------ * JTRUE void
------------ BB10 [05E..069) -> BB15 (always), preds={BB09} succs={BB15}
[000239] ------------ IL_OFFSET void IL offset: 0x5e
N001 ( 1, 1) [000130] ------------ NO_OP void
[000240] ------------ IL_OFFSET void IL offset: 0x5f
N002 ( 3, 2) [000131] ------------ t131 = LCL_VAR byref V00 this
/--* t131 byref
[000275] ------------ t275 = * PUTARG_REG byref REG rcx
/--* t275 byref arg0 in rcx
N003 ( 17, 8) [000132] --CXG------- t132 = * CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].<ReadByte>g__ReadByteSlow|18_0
/--* t132 int
N005 ( 21, 11) [000134] DA-XG------- * STORE_LCL_VAR int V21 tmp12
[000241] ------------ IL_OFFSET void IL offset: 0x65
N001 ( 3, 2) [000135] ------------ t135 = LCL_VAR int V21 tmp12
/--* t135 int
N002 ( 4, 4) [000198] ------------ t198 = * CAST int <- ubyte <- int
/--* t198 int
N004 ( 8, 7) [000137] DA---------- * STORE_LCL_VAR int V06 loc5
[000242] ------------ IL_OFFSET void IL offset: 0x67
N001 ( 0, 0) [000138] ------------ NOP void
------------ BB11 [069..081) -> BB15 (always), preds={BB09} succs={BB15}
[000243] ------------ IL_OFFSET void IL offset: 0x69
N003 ( 3, 3) [000111] ------------ t111 = LCL_VAR_ADDR byref V03 loc2
/--* t111 byref
[000276] ------------ t276 = * PUTARG_REG byref REG rcx
N004 ( 3, 2) [000112] ------------ t112 = LCL_VAR int V02 loc1
/--* t112 int
[000277] ------------ t277 = * PUTARG_REG int REG rdx
/--* t276 byref this in rcx
+--* t277 int arg1 in rdx
N005 ( 20, 13) [000113] --CXG------- t113 = * CALL byref System.ReadOnlySpan`1[Byte][System.Byte].get_Item
/--* t113 byref
N007 ( 24, 16) [000115] DA-XG------- * STORE_LCL_VAR byref V20 tmp11
[000244] ------------ IL_OFFSET void IL offset: 0x71
N001 ( 3, 2) [000116] ------------ t116 = LCL_VAR byref V20 tmp11
/--* t116 byref
N002 ( 7, 5) [000117] *--XG------- t117 = * IND ubyte
/--* t117 ubyte
N004 ( 11, 8) [000119] DA-XG------- * STORE_LCL_VAR int V04 loc3
[000245] ------------ IL_OFFSET void IL offset: 0x73
N001 ( 3, 2) [000121] ------------ t121 = LCL_VAR int V02 loc1
N002 ( 1, 1) [000122] -c---------- t122 = CNS_INT int 1
/--* t121 int
+--* t122 int
N003 ( 5, 4) [000123] ------------ t123 = * ADD int
N004 ( 3, 2) [000120] ------------ t120 = LCL_VAR byref V00 this
/--* t120 byref
N006 ( 4, 3) [000202] -c---------- t202 = * LEA(b+24) byref
/--* t202 byref
+--* t123 int
[000246] -A-XG------- * STOREIND int
[000247] ------------ IL_OFFSET void IL offset: 0x7c
N001 ( 3, 2) [000126] ------------ t126 = LCL_VAR int V04 loc3
/--* t126 int
N003 ( 7, 5) [000128] DA---------- * STORE_LCL_VAR int V06 loc5
[000248] ------------ IL_OFFSET void IL offset: 0x7f
N001 ( 0, 0) [000129] ------------ NOP void
------------ BB12 [081..09E) -> BB14 (cond), preds={BB08} succs={BB13,BB14}
[000249] ------------ IL_OFFSET void IL offset: 0x81
N004 ( 3, 2) [000204] ------------ t204 = LCL_VAR byref V00 this
/--* t204 byref
N005 ( 4, 3) [000205] ---X---N---- * NULLCHECK int
N006 ( 3, 2) [000206] ------------ t206 = LCL_VAR byref V00 this
N007 ( 1, 1) [000207] -c---------- t207 = CNS_INT long 64 field offset Fseq[_input]
/--* t206 byref
+--* t207 long
N008 ( 5, 4) [000208] ------------ t208 = * ADD byref
/--* t208 byref
[000278] ------------ t278 = * PUTARG_REG byref REG rdx
N010 ( 2, 10) [000046] H----------- t46 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t46 long
[000279] ------------ t279 = * PUTARG_REG long REG rcx
/--* t278 byref arg1 in rdx
+--* t279 long arg0 in rcx
N011 ( 25, 24) [000048] --CXG------- t48 = * CALL help ref HELPER.CORINFO_HELP_BOX
/--* t48 ref
N013 ( 29, 27) [000214] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp18
N014 ( 3, 2) [000215] ------------ t215 = LCL_VAR ref V27 tmp18
/--* t215 ref
[000280] ------------ t280 = * PUTARG_REG ref REG rdx
N015 ( 2, 10) [000049] H------N---- t49 = CNS_INT(h) long 0x7ff93b569758 class
/--* t49 long
[000281] ------------ t281 = * PUTARG_REG long REG rcx
/--* t280 ref arg1 in rdx
+--* t281 long arg0 in rcx
N016 ( 51, 46) [000050] --CXG------- t50 = * CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS
/--* t50 ref
N018 ( 55, 49) [000052] DA-XG------- * STORE_LCL_VAR ref V07 loc6
[000250] ------------ IL_OFFSET void IL offset: 0x93
N001 ( 3, 2) [000053] -c---------- t53 = LCL_VAR ref V07 loc6
N002 ( 1, 1) [000054] -c---------- t54 = CNS_INT ref null
/--* t53 ref
+--* t54 ref
N003 ( 8, 4) [000055] N----------- t55 = * NE int
/--* t55 int
N005 ( 12, 7) [000057] DA---------- * STORE_LCL_VAR int V08 loc7
[000251] ------------ IL_OFFSET void IL offset: 0x9a
N001 ( 3, 2) [000058] -c---------- t58 = LCL_VAR int V08 loc7
N002 ( 1, 1) [000059] -c---------- t59 = CNS_INT int 0
/--* t58 int
+--* t59 int
N003 ( 5, 4) [000060] J------N---- * EQ void
N004 ( 7, 6) [000061] ------------ * JTRUE void
------------ BB13 [09E..0AA) -> BB15 (always), preds={BB12} succs={BB15}
[000252] ------------ IL_OFFSET void IL offset: 0x9e
N001 ( 1, 1) [000072] ------------ NO_OP void
[000253] ------------ IL_OFFSET void IL offset: 0x9f
N002 ( 3, 2) [000073] ------------ t73 = LCL_VAR ref V07 loc6
/--* t73 ref
[000282] ------------ t282 = * PUTARG_REG ref REG rcx
N001 ( 3, 2) [000283] ------------ t283 = LCL_VAR ref V07 loc6
/--* t283 ref
N002 ( 4, 3) [000284] -c---------- t284 = * LEA(b+0) byref
/--* t284 byref
N003 ( 7, 5) [000285] ------------ t285 = * IND long
/--* t285 long
N004 ( 8, 6) [000286] -c---------- t286 = * LEA(b+72) long
/--* t286 long
N005 ( 11, 8) [000287] ------------ t287 = * IND long
/--* t287 long
N006 ( 12, 9) [000288] -c---------- t288 = * LEA(b+56) long
/--* t288 long
N007 ( 15, 11) [000289] -c---------- t289 = * IND long REG NA
/--* t282 ref this in rcx
+--* t289 long control expr
N003 ( 23, 11) [000074] --CXG------- t74 = * CALLV ind int Hagar.Buffers.ReaderInput.ReadByte
/--* t74 int
N005 ( 27, 14) [000076] DA-XG------- * STORE_LCL_VAR int V17 tmp8
[000254] ------------ IL_OFFSET void IL offset: 0xa6
N001 ( 3, 2) [000077] ------------ t77 = LCL_VAR int V17 tmp8
/--* t77 int
N002 ( 4, 4) [000218] ------------ t218 = * CAST int <- ubyte <- int
/--* t218 int
N004 ( 8, 7) [000079] DA---------- * STORE_LCL_VAR int V06 loc5
[000255] ------------ IL_OFFSET void IL offset: 0xa8
N001 ( 0, 0) [000080] ------------ NOP void
------------ BB14 [0AA..0B4) -> BB15 (always), preds={BB12} succs={BB15}
[000256] ------------ IL_OFFSET void IL offset: 0xaa
N001 ( 1, 1) [000062] ------------ NO_OP void
[000257] ------------ IL_OFFSET void IL offset: 0xab
N001 ( 14, 5) [000063] --CXG------- t63 = CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].ThrowNotSupportedInput
/--* t63 int
N003 ( 18, 8) [000065] DA-XG------- * STORE_LCL_VAR int V16 tmp7
[000258] ------------ IL_OFFSET void IL offset: 0xb0
N001 ( 3, 2) [000066] ------------ t66 = LCL_VAR int V16 tmp7
/--* t66 int
N002 ( 4, 4) [000219] ------------ t219 = * CAST int <- ubyte <- int
/--* t219 int
N004 ( 8, 7) [000068] DA---------- * STORE_LCL_VAR int V06 loc5
[000259] ------------ IL_OFFSET void IL offset: 0xb2
N001 ( 0, 0) [000069] ------------ NOP void
------------ BB15 [0B4..0B7) (return), preds={BB10,BB11,BB13,BB14} succs={}
[000260] ------------ IL_OFFSET void IL offset: 0xb4
N001 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V06 loc5
/--* t70 int
N002 ( 4, 3) [000071] ------------ * RETURN int
-------------------------------------------------------------------------------------------------------------------
*** lvaComputeRefCounts ***
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 this byref this
; V01 loc0 bool
; V02 loc1 int
; V03 loc2 struct <System.ReadOnlySpan`1[Byte], 16> do-not-enreg[XSB] addr-exposed ld-addr-op
; V04 loc3 ubyte
; V05 loc4 bool
; V06 loc5 ubyte
; V07 loc6 ref class-hnd
; V08 loc7 bool
; V09 OutArgs lclBlk <32> "OutgoingArgSpace"
; V10 tmp1 struct <System.RuntimeTypeHandle, 8> do-not-enreg[SB] "struct address for call/obj"
; V11 tmp2 ref class-hnd "impSpillStackEnsure"
; V12 tmp3 struct <System.RuntimeTypeHandle, 8> do-not-enreg[SB] "struct address for call/obj"
; V13 tmp4 ref class-hnd "impSpillStackEnsure"
; V14 tmp5 int "impSpillStackEnsure"
; V15 tmp6 int
; V16 tmp7 int "impSpillStackEnsure"
; V17 tmp8 int "impSpillStackEnsure"
; V18 tmp9 int "impSpillStackEnsure"
; V19 tmp10 int "impSpillStackEnsure"
; V20 tmp11 byref "impSpillStackEnsure"
; V21 tmp12 int "impSpillStackEnsure"
; V22 tmp13 struct <System.RuntimeTypeHandle, 8> do-not-enreg[SB] "struct address for call/obj"
; V23 tmp14 ref class-hnd "impSpillStackEnsure"
; V24 tmp15 struct <System.RuntimeTypeHandle, 8> do-not-enreg[SB] "struct address for call/obj"
; V25 tmp16 ref class-hnd "impSpillStackEnsure"
; V26 tmp17 int "impSpillStackEnsure"
; V27 tmp18 ref "argument with side effect"
In fgLocalVarLivenessInit
*************** In fgPerBlockLocalVarLiveness()
*************** In fgInterBlockLocalVarLiveness()
*************** In fgExtendDbgLifetimes()
Marking vars alive over their entire scope :
Local variable scopes = 9
VarNum LVNum Name Beg End
Sorted by enter scope:
0: 00h 00h V00 this 000h 0B7h <-- next enter scope
1: 07h 07h V07 loc6 000h 0B7h
2: 06h 06h V06 loc5 000h 0B7h
3: 05h 05h V05 loc4 000h 0B7h
4: 04h 04h V04 loc3 000h 0B7h
5: 03h 03h V03 loc2 000h 0B7h
6: 02h 02h V02 loc1 000h 0B7h
7: 01h 01h V01 loc0 000h 0B7h
8: 08h 08h V08 loc7 000h 0B7h
Sorted by exit scope:
0: 00h 00h V00 this 000h 0B7h <-- next exit scope
1: 07h 07h V07 loc6 000h 0B7h
2: 06h 06h V06 loc5 000h 0B7h
3: 05h 05h V05 loc4 000h 0B7h
4: 04h 04h V04 loc3 000h 0B7h
5: 03h 03h V03 loc2 000h 0B7h
6: 02h 02h V02 loc1 000h 0B7h
7: 01h 01h V01 loc0 000h 0B7h
8: 08h 08h V08 loc7 000h 0B7h
Scope info: block BB01 marking in scope: {}
Scope info: block BB02 marking in scope: {}
Scope info: block BB03 marking in scope: {}
Scope info: block BB04 marking in scope: {}
Scope info: block BB05 marking in scope: {}
Scope info: block BB06 marking in scope: {}
Scope info: block BB07 marking in scope: {}
Scope info: block BB08 marking in scope: {}
Scope info: block BB09 marking in scope: {}
Scope info: block BB10 marking in scope: {}
Scope info: block BB11 marking in scope: {}
Scope info: block BB12 marking in scope: {}
Scope info: block BB13 marking in scope: {}
Scope info: block BB14 marking in scope: {}
Scope info: block BB15 marking in scope: {}
Debug scopes:
BB01: {}
BB02: {}
BB03: {}
BB04: {}
BB05: {}
BB06: {}
BB07: {}
BB08: {}
BB09: {}
BB10: {}
BB11: {}
BB12: {}
BB13: {}
BB14: {}
BB15: {}
Scope info: block BB01 UNmarking in scope: {}
BB liveness after fgExtendDbgLifetimes():
BB01 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB02 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB03 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB04 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB05 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB06 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB07 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB08 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB09 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB10 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB11 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB12 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB13 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB14 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB15 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
*** lvaComputeRefCounts ***
*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target hascall LIR
BB02 [0013] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
BB03 [0014] 1 BB02 0.50 [???..???) internal LIR
BB04 [0012] 2 BB02,BB03 1 [???..???) i internal label target hascall LIR
BB05 [0001] 1 BB04 1 [000..01C)-> BB07 ( cond ) i hascall LIR
BB06 [0002] 1 BB05 1 [01C..037)-> BB08 (always) i hascall LIR
BB07 [0003] 1 BB05 1 [037..038) i label target LIR
BB08 [0004] 2 BB06,BB07 1 [038..03C)-> BB12 ( cond ) i label target LIR
BB09 [0005] 1 BB08 1 [03C..05E)-> BB11 ( cond ) i hascall LIR
BB10 [0006] 1 BB09 1 [05E..069)-> BB15 (always) i hascall gcsafe LIR
BB11 [0007] 1 BB09 1 [069..081)-> BB15 (always) i label target hascall LIR
BB12 [0008] 1 BB08 1 [081..09E)-> BB14 ( cond ) i label target hascall nullcheck LIR
BB13 [0009] 1 BB12 1 [09E..0AA)-> BB15 (always) i hascall gcsafe LIR
BB14 [0010] 1 BB12 1 [0AA..0B4)-> BB15 (always) i label target hascall gcsafe LIR
BB15 [0011] 4 BB10,BB11,BB13,BB14 1 [0B4..0B7) (return) i label target LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
N001 ( 0, 0) [000000] ------------ NOP void
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
N001 ( 2, 10) [000171] Hc---------- t171 = CNS_INT(h) long 0x7ff9392a5420 global ptr
/--* t171 long
N002 ( 4, 12) [000172] nc---------- t172 = * IND int
N003 ( 1, 1) [000173] -c---------- t173 = CNS_INT int 0
/--* t172 int
+--* t173 int
N004 ( 6, 14) [000174] J------N---- * EQ void
N005 ( 8, 16) [000221] ------------ * JTRUE void
------------ BB03 [???..???), preds={BB02} succs={BB04}
N001 ( 14, 5) [000175] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
------------ BB05 [000..01C) -> BB07 (cond), preds={BB04} succs={BB06,BB07}
[000222] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000001] ------------ NO_OP void
[000223] ------------ IL_OFFSET void IL offset: 0x1
N002 ( 2, 10) [000002] H----------- t2 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t2 long
[000261] ------------ t261 = * PUTARG_REG long REG rcx
/--* t261 long arg0 in rcx
N003 ( 16, 16) [000003] --C-G------- t3 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t3 ref
N005 ( 20, 19) [000007] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
N002 ( 3, 4) [000008] ------------ t8 = LCL_FLD ref V10 tmp1 [+0]
/--* t8 ref
[000262] ------------ t262 = * PUTARG_REG ref REG rcx
/--* t262 ref arg0 in rcx
N003 ( 17, 10) [000004] --CXG------- t4 = * CALL ref System.Type.GetTypeFromHandle
/--* t4 ref
N005 ( 21, 13) [000012] DA-XG------- * STORE_LCL_VAR ref V11 tmp2
[000224] ------------ IL_OFFSET void IL offset: 0xb
N002 ( 2, 10) [000014] H----------- t14 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t14 long
[000263] ------------ t263 = * PUTARG_REG long REG rcx
/--* t263 long arg0 in rcx
N003 ( 16, 16) [000015] --C-G------- t15 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t15 ref
N005 ( 20, 19) [000019] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
N002 ( 3, 4) [000020] ------------ t20 = LCL_FLD ref V12 tmp3 [+0]
/--* t20 ref
[000264] ------------ t264 = * PUTARG_REG ref REG rcx
/--* t264 ref arg0 in rcx
N003 ( 17, 10) [000016] --CXG------- t16 = * CALL ref System.Type.GetTypeFromHandle
/--* t16 ref
N005 ( 21, 13) [000024] DA-XG------- * STORE_LCL_VAR ref V13 tmp4
[000225] ------------ IL_OFFSET void IL offset: 0x15
N003 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V11 tmp2
/--* t13 ref
[000265] ------------ t265 = * PUTARG_REG ref REG rcx
N004 ( 3, 2) [000025] ------------ t25 = LCL_VAR ref V13 tmp4
/--* t25 ref
[000266] ------------ t266 = * PUTARG_REG ref REG rdx
/--* t265 ref arg0 in rcx
+--* t266 ref arg1 in rdx
N005 ( 20, 11) [000026] --CXG------- t26 = * CALL int System.Type.op_Equality
/--* t26 int
N007 ( 24, 14) [000028] DA-XG------- * STORE_LCL_VAR int V14 tmp5
[000226] ------------ IL_OFFSET void IL offset: 0x1a
N001 ( 3, 2) [000029] -c---------- t29 = LCL_VAR int V14 tmp5
N002 ( 1, 1) [000030] -c---------- t30 = CNS_INT int 0
/--* t29 int
+--* t30 int
N003 ( 5, 4) [000031] J------N---- * NE void
N004 ( 7, 6) [000032] ------------ * JTRUE void
------------ BB06 [01C..037) -> BB08 (always), preds={BB05} succs={BB08}
[000227] ------------ IL_OFFSET void IL offset: 0x1c
N002 ( 2, 10) [000139] H----------- t139 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t139 long
[000267] ------------ t267 = * PUTARG_REG long REG rcx
/--* t267 long arg0 in rcx
N003 ( 16, 16) [000140] --C-G------- t140 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t140 ref
N005 ( 20, 19) [000144] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
N002 ( 3, 4) [000145] ------------ t145 = LCL_FLD ref V22 tmp13 [+0]
/--* t145 ref
[000268] ------------ t268 = * PUTARG_REG ref REG rcx
/--* t268 ref arg0 in rcx
N003 ( 17, 10) [000141] --CXG------- t141 = * CALL ref System.Type.GetTypeFromHandle
/--* t141 ref
N005 ( 21, 13) [000149] DA-XG------- * STORE_LCL_VAR ref V23 tmp14
[000228] ------------ IL_OFFSET void IL offset: 0x26
N002 ( 2, 10) [000151] H----------- t151 = CNS_INT(h) long 0x7ff93b56a7f8 class
/--* t151 long
[000269] ------------ t269 = * PUTARG_REG long REG rcx
/--* t269 long arg0 in rcx
N003 ( 16, 16) [000152] --C-G------- t152 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t152 ref
N005 ( 20, 19) [000156] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
N002 ( 3, 4) [000157] ------------ t157 = LCL_FLD ref V24 tmp15 [+0]
/--* t157 ref
[000270] ------------ t270 = * PUTARG_REG ref REG rcx
/--* t270 ref arg0 in rcx
N003 ( 17, 10) [000153] --CXG------- t153 = * CALL ref System.Type.GetTypeFromHandle
/--* t153 ref
N005 ( 21, 13) [000161] DA-XG------- * STORE_LCL_VAR ref V25 tmp16
[000229] ------------ IL_OFFSET void IL offset: 0x30
N003 ( 3, 2) [000150] ------------ t150 = LCL_VAR ref V23 tmp14
/--* t150 ref
[000271] ------------ t271 = * PUTARG_REG ref REG rcx
N004 ( 3, 2) [000162] ------------ t162 = LCL_VAR ref V25 tmp16
/--* t162 ref
[000272] ------------ t272 = * PUTARG_REG ref REG rdx
/--* t271 ref arg0 in rcx
+--* t272 ref arg1 in rdx
N005 ( 20, 11) [000163] --CXG------- t163 = * CALL int System.Type.op_Equality
/--* t163 int
N007 ( 24, 14) [000165] DA-XG------- * STORE_LCL_VAR int V26 tmp17
[000230] ------------ IL_OFFSET void IL offset: 0x35
N001 ( 0, 0) [000167] ------------ NOP void
N001 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V26 tmp17
/--* t166 int
N003 ( 7, 5) [000169] DA---------- * STORE_LCL_VAR int V15 tmp6
------------ BB07 [037..038), preds={BB05} succs={BB08}
[000231] ------------ IL_OFFSET void IL offset: 0x37
N001 ( 1, 1) [000033] -c---------- t33 = CNS_INT int 1
/--* t33 int
N003 ( 5, 4) [000035] DA---------- * STORE_LCL_VAR int V15 tmp6
------------ BB08 [038..03C) -> BB12 (cond), preds={BB06,BB07} succs={BB09,BB12}
N001 ( 3, 2) [000037] ------------ t37 = LCL_VAR int V15 tmp6
/--* t37 int
N002 ( 4, 4) [000191] ------------ t191 = * CAST int <- bool <- int
/--* t191 int
N004 ( 8, 7) [000039] DA---------- * STORE_LCL_VAR int V01 loc0
[000232] ------------ IL_OFFSET void IL offset: 0x39
N001 ( 3, 2) [000040] -c---------- t40 = LCL_VAR int V01 loc0
N002 ( 1, 1) [000041] -c---------- t41 = CNS_INT int 0
/--* t40 int
+--* t41 int
N003 ( 5, 4) [000042] J------N---- * EQ void
N004 ( 7, 6) [000043] ------------ * JTRUE void
------------ BB09 [03C..05E) -> BB11 (cond), preds={BB08} succs={BB10,BB11}
[000233] ------------ IL_OFFSET void IL offset: 0x3c
N001 ( 1, 1) [000081] ------------ NO_OP void
[000234] ------------ IL_OFFSET void IL offset: 0x3d
N001 ( 3, 2) [000082] ------------ t82 = LCL_VAR byref V00 this
/--* t82 byref
N003 ( 4, 3) [000193] -c---------- t193 = * LEA(b+24) byref
/--* t193 byref
N004 ( 6, 5) [000083] *--XG------- t83 = * IND int
/--* t83 int
N006 ( 10, 8) [000085] DA-XG------- * STORE_LCL_VAR int V02 loc1
[000235] ------------ IL_OFFSET void IL offset: 0x44
N001 ( 3, 2) [000086] ------------ t86 = LCL_VAR byref V00 this
/--* t86 byref
N003 ( 5, 4) [000195] -c---------- t195 = * LEA(b+32) byref
/--* t195 byref
N004 ( 8, 6) [000087] *c-XG------- t87 = * IND struct
[000273] Dc-----N---- t273 = LCL_VAR_ADDR byref V03 loc2
/--* t273 byref
+--* t87 struct
N006 ( 12, 9) [000090] sA---------- * STORE_BLK struct<System.ReadOnlySpan`1[Byte], 16> (copy) (Unroll)
[000236] ------------ IL_OFFSET void IL offset: 0x4b
N001 ( 3, 2) [000091] ------------ t91 = LCL_VAR int V02 loc1
/--* t91 int
N003 ( 7, 5) [000096] DA---------- * STORE_LCL_VAR int V18 tmp9
N002 ( 3, 3) [000093] ------------ t93 = LCL_VAR_ADDR byref V03 loc2
/--* t93 byref
[000274] ------------ t274 = * PUTARG_REG byref REG rcx
/--* t274 byref this in rcx
N003 ( 17, 10) [000094] --CXG------- t94 = * CALL int System.ReadOnlySpan`1[Byte][System.Byte].get_Length
/--* t94 int
N005 ( 21, 13) [000099] DA-XG------- * STORE_LCL_VAR int V19 tmp10
[000237] ------------ IL_OFFSET void IL offset: 0x53
N001 ( 3, 2) [000097] ------------ t97 = LCL_VAR int V18 tmp9
N002 ( 3, 2) [000100] -c---------- t100 = LCL_VAR int V19 tmp10
/--* t97 int
+--* t100 int
N003 ( 10, 5) [000101] N--------U-- t101 = * GE int
/--* t101 int
N005 ( 14, 8) [000105] DA---------- * STORE_LCL_VAR int V05 loc4
[000238] ------------ IL_OFFSET void IL offset: 0x5a
N001 ( 3, 2) [000106] -c---------- t106 = LCL_VAR int V05 loc4
N002 ( 1, 1) [000107] -c---------- t107 = CNS_INT int 0
/--* t106 int
+--* t107 int
N003 ( 5, 4) [000108] J------N---- * EQ void
N004 ( 7, 6) [000109] ------------ * JTRUE void
------------ BB10 [05E..069) -> BB15 (always), preds={BB09} succs={BB15}
[000239] ------------ IL_OFFSET void IL offset: 0x5e
N001 ( 1, 1) [000130] ------------ NO_OP void
[000240] ------------ IL_OFFSET void IL offset: 0x5f
N002 ( 3, 2) [000131] ------------ t131 = LCL_VAR byref V00 this
/--* t131 byref
[000275] ------------ t275 = * PUTARG_REG byref REG rcx
/--* t275 byref arg0 in rcx
N003 ( 17, 8) [000132] --CXG------- t132 = * CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].<ReadByte>g__ReadByteSlow|18_0
/--* t132 int
N005 ( 21, 11) [000134] DA-XG------- * STORE_LCL_VAR int V21 tmp12
[000241] ------------ IL_OFFSET void IL offset: 0x65
N001 ( 3, 2) [000135] ------------ t135 = LCL_VAR int V21 tmp12
/--* t135 int
N002 ( 4, 4) [000198] ------------ t198 = * CAST int <- ubyte <- int
/--* t198 int
N004 ( 8, 7) [000137] DA---------- * STORE_LCL_VAR int V06 loc5
[000242] ------------ IL_OFFSET void IL offset: 0x67
N001 ( 0, 0) [000138] ------------ NOP void
------------ BB11 [069..081) -> BB15 (always), preds={BB09} succs={BB15}
[000243] ------------ IL_OFFSET void IL offset: 0x69
N003 ( 3, 3) [000111] ------------ t111 = LCL_VAR_ADDR byref V03 loc2
/--* t111 byref
[000276] ------------ t276 = * PUTARG_REG byref REG rcx
N004 ( 3, 2) [000112] ------------ t112 = LCL_VAR int V02 loc1
/--* t112 int
[000277] ------------ t277 = * PUTARG_REG int REG rdx
/--* t276 byref this in rcx
+--* t277 int arg1 in rdx
N005 ( 20, 13) [000113] --CXG------- t113 = * CALL byref System.ReadOnlySpan`1[Byte][System.Byte].get_Item
/--* t113 byref
N007 ( 24, 16) [000115] DA-XG------- * STORE_LCL_VAR byref V20 tmp11
[000244] ------------ IL_OFFSET void IL offset: 0x71
N001 ( 3, 2) [000116] ------------ t116 = LCL_VAR byref V20 tmp11
/--* t116 byref
N002 ( 7, 5) [000117] *--XG------- t117 = * IND ubyte
/--* t117 ubyte
N004 ( 11, 8) [000119] DA-XG------- * STORE_LCL_VAR int V04 loc3
[000245] ------------ IL_OFFSET void IL offset: 0x73
N001 ( 3, 2) [000121] ------------ t121 = LCL_VAR int V02 loc1
N002 ( 1, 1) [000122] -c---------- t122 = CNS_INT int 1
/--* t121 int
+--* t122 int
N003 ( 5, 4) [000123] ------------ t123 = * ADD int
N004 ( 3, 2) [000120] ------------ t120 = LCL_VAR byref V00 this
/--* t120 byref
N006 ( 4, 3) [000202] -c---------- t202 = * LEA(b+24) byref
/--* t202 byref
+--* t123 int
[000246] -A-XG------- * STOREIND int
[000247] ------------ IL_OFFSET void IL offset: 0x7c
N001 ( 3, 2) [000126] ------------ t126 = LCL_VAR int V04 loc3
/--* t126 int
N003 ( 7, 5) [000128] DA---------- * STORE_LCL_VAR int V06 loc5
[000248] ------------ IL_OFFSET void IL offset: 0x7f
N001 ( 0, 0) [000129] ------------ NOP void
------------ BB12 [081..09E) -> BB14 (cond), preds={BB08} succs={BB13,BB14}
[000249] ------------ IL_OFFSET void IL offset: 0x81
N004 ( 3, 2) [000204] ------------ t204 = LCL_VAR byref V00 this
/--* t204 byref
N005 ( 4, 3) [000205] ---X---N---- * NULLCHECK int
N006 ( 3, 2) [000206] ------------ t206 = LCL_VAR byref V00 this
N007 ( 1, 1) [000207] -c---------- t207 = CNS_INT long 64 field offset Fseq[_input]
/--* t206 byref
+--* t207 long
N008 ( 5, 4) [000208] ------------ t208 = * ADD byref
/--* t208 byref
[000278] ------------ t278 = * PUTARG_REG byref REG rdx
N010 ( 2, 10) [000046] H----------- t46 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t46 long
[000279] ------------ t279 = * PUTARG_REG long REG rcx
/--* t278 byref arg1 in rdx
+--* t279 long arg0 in rcx
N011 ( 25, 24) [000048] --CXG------- t48 = * CALL help ref HELPER.CORINFO_HELP_BOX
/--* t48 ref
N013 ( 29, 27) [000214] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp18
N014 ( 3, 2) [000215] ------------ t215 = LCL_VAR ref V27 tmp18
/--* t215 ref
[000280] ------------ t280 = * PUTARG_REG ref REG rdx
N015 ( 2, 10) [000049] H------N---- t49 = CNS_INT(h) long 0x7ff93b569758 class
/--* t49 long
[000281] ------------ t281 = * PUTARG_REG long REG rcx
/--* t280 ref arg1 in rdx
+--* t281 long arg0 in rcx
N016 ( 51, 46) [000050] --CXG------- t50 = * CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS
/--* t50 ref
N018 ( 55, 49) [000052] DA-XG------- * STORE_LCL_VAR ref V07 loc6
[000250] ------------ IL_OFFSET void IL offset: 0x93
N001 ( 3, 2) [000053] -c---------- t53 = LCL_VAR ref V07 loc6
N002 ( 1, 1) [000054] -c---------- t54 = CNS_INT ref null
/--* t53 ref
+--* t54 ref
N003 ( 8, 4) [000055] N----------- t55 = * NE int
/--* t55 int
N005 ( 12, 7) [000057] DA---------- * STORE_LCL_VAR int V08 loc7
[000251] ------------ IL_OFFSET void IL offset: 0x9a
N001 ( 3, 2) [000058] -c---------- t58 = LCL_VAR int V08 loc7
N002 ( 1, 1) [000059] -c---------- t59 = CNS_INT int 0
/--* t58 int
+--* t59 int
N003 ( 5, 4) [000060] J------N---- * EQ void
N004 ( 7, 6) [000061] ------------ * JTRUE void
------------ BB13 [09E..0AA) -> BB15 (always), preds={BB12} succs={BB15}
[000252] ------------ IL_OFFSET void IL offset: 0x9e
N001 ( 1, 1) [000072] ------------ NO_OP void
[000253] ------------ IL_OFFSET void IL offset: 0x9f
N002 ( 3, 2) [000073] ------------ t73 = LCL_VAR ref V07 loc6
/--* t73 ref
[000282] ------------ t282 = * PUTARG_REG ref REG rcx
N001 ( 3, 2) [000283] ------------ t283 = LCL_VAR ref V07 loc6
/--* t283 ref
N002 ( 4, 3) [000284] -c---------- t284 = * LEA(b+0) byref
/--* t284 byref
N003 ( 7, 5) [000285] ------------ t285 = * IND long
/--* t285 long
N004 ( 8, 6) [000286] -c---------- t286 = * LEA(b+72) long
/--* t286 long
N005 ( 11, 8) [000287] ------------ t287 = * IND long
/--* t287 long
N006 ( 12, 9) [000288] -c---------- t288 = * LEA(b+56) long
/--* t288 long
N007 ( 15, 11) [000289] -c---------- t289 = * IND long REG NA
/--* t282 ref this in rcx
+--* t289 long control expr
N003 ( 23, 11) [000074] --CXG------- t74 = * CALLV ind int Hagar.Buffers.ReaderInput.ReadByte
/--* t74 int
N005 ( 27, 14) [000076] DA-XG------- * STORE_LCL_VAR int V17 tmp8
[000254] ------------ IL_OFFSET void IL offset: 0xa6
N001 ( 3, 2) [000077] ------------ t77 = LCL_VAR int V17 tmp8
/--* t77 int
N002 ( 4, 4) [000218] ------------ t218 = * CAST int <- ubyte <- int
/--* t218 int
N004 ( 8, 7) [000079] DA---------- * STORE_LCL_VAR int V06 loc5
[000255] ------------ IL_OFFSET void IL offset: 0xa8
N001 ( 0, 0) [000080] ------------ NOP void
------------ BB14 [0AA..0B4) -> BB15 (always), preds={BB12} succs={BB15}
[000256] ------------ IL_OFFSET void IL offset: 0xaa
N001 ( 1, 1) [000062] ------------ NO_OP void
[000257] ------------ IL_OFFSET void IL offset: 0xab
N001 ( 14, 5) [000063] --CXG------- t63 = CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].ThrowNotSupportedInput
/--* t63 int
N003 ( 18, 8) [000065] DA-XG------- * STORE_LCL_VAR int V16 tmp7
[000258] ------------ IL_OFFSET void IL offset: 0xb0
N001 ( 3, 2) [000066] ------------ t66 = LCL_VAR int V16 tmp7
/--* t66 int
N002 ( 4, 4) [000219] ------------ t219 = * CAST int <- ubyte <- int
/--* t219 int
N004 ( 8, 7) [000068] DA---------- * STORE_LCL_VAR int V06 loc5
[000259] ------------ IL_OFFSET void IL offset: 0xb2
N001 ( 0, 0) [000069] ------------ NOP void
------------ BB15 [0B4..0B7) (return), preds={BB10,BB11,BB13,BB14} succs={}
[000260] ------------ IL_OFFSET void IL offset: 0xb4
N001 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V06 loc5
/--* t70 int
N002 ( 4, 3) [000071] ------------ * RETURN int
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Trees before Calculate stack level slots
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target hascall LIR
BB02 [0013] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
BB03 [0014] 1 BB02 0.50 [???..???) internal LIR
BB04 [0012] 2 BB02,BB03 1 [???..???) i internal label target hascall LIR
BB05 [0001] 1 BB04 1 [000..01C)-> BB07 ( cond ) i hascall LIR
BB06 [0002] 1 BB05 1 [01C..037)-> BB08 (always) i hascall LIR
BB07 [0003] 1 BB05 1 [037..038) i label target LIR
BB08 [0004] 2 BB06,BB07 1 [038..03C)-> BB12 ( cond ) i label target LIR
BB09 [0005] 1 BB08 1 [03C..05E)-> BB11 ( cond ) i hascall LIR
BB10 [0006] 1 BB09 1 [05E..069)-> BB15 (always) i hascall gcsafe LIR
BB11 [0007] 1 BB09 1 [069..081)-> BB15 (always) i label target hascall LIR
BB12 [0008] 1 BB08 1 [081..09E)-> BB14 ( cond ) i label target hascall nullcheck LIR
BB13 [0009] 1 BB12 1 [09E..0AA)-> BB15 (always) i hascall gcsafe LIR
BB14 [0010] 1 BB12 1 [0AA..0B4)-> BB15 (always) i label target hascall gcsafe LIR
BB15 [0011] 4 BB10,BB11,BB13,BB14 1 [0B4..0B7) (return) i label target LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
N001 ( 0, 0) [000000] ------------ NOP void
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
N001 ( 2, 10) [000171] Hc---------- t171 = CNS_INT(h) long 0x7ff9392a5420 global ptr
/--* t171 long
N002 ( 4, 12) [000172] nc---------- t172 = * IND int
N003 ( 1, 1) [000173] -c---------- t173 = CNS_INT int 0
/--* t172 int
+--* t173 int
N004 ( 6, 14) [000174] J------N---- * EQ void
N005 ( 8, 16) [000221] ------------ * JTRUE void
------------ BB03 [???..???), preds={BB02} succs={BB04}
N001 ( 14, 5) [000175] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
------------ BB05 [000..01C) -> BB07 (cond), preds={BB04} succs={BB06,BB07}
[000222] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000001] ------------ NO_OP void
[000223] ------------ IL_OFFSET void IL offset: 0x1
N002 ( 2, 10) [000002] H----------- t2 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t2 long
[000261] ------------ t261 = * PUTARG_REG long REG rcx
/--* t261 long arg0 in rcx
N003 ( 16, 16) [000003] --C-G------- t3 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t3 ref
N005 ( 20, 19) [000007] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1
N002 ( 3, 4) [000008] ------------ t8 = LCL_FLD ref V10 tmp1 [+0]
/--* t8 ref
[000262] ------------ t262 = * PUTARG_REG ref REG rcx
/--* t262 ref arg0 in rcx
N003 ( 17, 10) [000004] --CXG------- t4 = * CALL ref System.Type.GetTypeFromHandle
/--* t4 ref
N005 ( 21, 13) [000012] DA-XG------- * STORE_LCL_VAR ref V11 tmp2
[000224] ------------ IL_OFFSET void IL offset: 0xb
N002 ( 2, 10) [000014] H----------- t14 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t14 long
[000263] ------------ t263 = * PUTARG_REG long REG rcx
/--* t263 long arg0 in rcx
N003 ( 16, 16) [000015] --C-G------- t15 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t15 ref
N005 ( 20, 19) [000019] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3
N002 ( 3, 4) [000020] ------------ t20 = LCL_FLD ref V12 tmp3 [+0]
/--* t20 ref
[000264] ------------ t264 = * PUTARG_REG ref REG rcx
/--* t264 ref arg0 in rcx
N003 ( 17, 10) [000016] --CXG------- t16 = * CALL ref System.Type.GetTypeFromHandle
/--* t16 ref
N005 ( 21, 13) [000024] DA-XG------- * STORE_LCL_VAR ref V13 tmp4
[000225] ------------ IL_OFFSET void IL offset: 0x15
N003 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V11 tmp2
/--* t13 ref
[000265] ------------ t265 = * PUTARG_REG ref REG rcx
N004 ( 3, 2) [000025] ------------ t25 = LCL_VAR ref V13 tmp4
/--* t25 ref
[000266] ------------ t266 = * PUTARG_REG ref REG rdx
/--* t265 ref arg0 in rcx
+--* t266 ref arg1 in rdx
N005 ( 20, 11) [000026] --CXG------- t26 = * CALL int System.Type.op_Equality
/--* t26 int
N007 ( 24, 14) [000028] DA-XG------- * STORE_LCL_VAR int V14 tmp5
[000226] ------------ IL_OFFSET void IL offset: 0x1a
N001 ( 3, 2) [000029] -c---------- t29 = LCL_VAR int V14 tmp5
N002 ( 1, 1) [000030] -c---------- t30 = CNS_INT int 0
/--* t29 int
+--* t30 int
N003 ( 5, 4) [000031] J------N---- * NE void
N004 ( 7, 6) [000032] ------------ * JTRUE void
------------ BB06 [01C..037) -> BB08 (always), preds={BB05} succs={BB08}
[000227] ------------ IL_OFFSET void IL offset: 0x1c
N002 ( 2, 10) [000139] H----------- t139 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t139 long
[000267] ------------ t267 = * PUTARG_REG long REG rcx
/--* t267 long arg0 in rcx
N003 ( 16, 16) [000140] --C-G------- t140 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t140 ref
N005 ( 20, 19) [000144] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13
N002 ( 3, 4) [000145] ------------ t145 = LCL_FLD ref V22 tmp13 [+0]
/--* t145 ref
[000268] ------------ t268 = * PUTARG_REG ref REG rcx
/--* t268 ref arg0 in rcx
N003 ( 17, 10) [000141] --CXG------- t141 = * CALL ref System.Type.GetTypeFromHandle
/--* t141 ref
N005 ( 21, 13) [000149] DA-XG------- * STORE_LCL_VAR ref V23 tmp14
[000228] ------------ IL_OFFSET void IL offset: 0x26
N002 ( 2, 10) [000151] H----------- t151 = CNS_INT(h) long 0x7ff93b56a7f8 class
/--* t151 long
[000269] ------------ t269 = * PUTARG_REG long REG rcx
/--* t269 long arg0 in rcx
N003 ( 16, 16) [000152] --C-G------- t152 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
/--* t152 ref
N005 ( 20, 19) [000156] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15
N002 ( 3, 4) [000157] ------------ t157 = LCL_FLD ref V24 tmp15 [+0]
/--* t157 ref
[000270] ------------ t270 = * PUTARG_REG ref REG rcx
/--* t270 ref arg0 in rcx
N003 ( 17, 10) [000153] --CXG------- t153 = * CALL ref System.Type.GetTypeFromHandle
/--* t153 ref
N005 ( 21, 13) [000161] DA-XG------- * STORE_LCL_VAR ref V25 tmp16
[000229] ------------ IL_OFFSET void IL offset: 0x30
N003 ( 3, 2) [000150] ------------ t150 = LCL_VAR ref V23 tmp14
/--* t150 ref
[000271] ------------ t271 = * PUTARG_REG ref REG rcx
N004 ( 3, 2) [000162] ------------ t162 = LCL_VAR ref V25 tmp16
/--* t162 ref
[000272] ------------ t272 = * PUTARG_REG ref REG rdx
/--* t271 ref arg0 in rcx
+--* t272 ref arg1 in rdx
N005 ( 20, 11) [000163] --CXG------- t163 = * CALL int System.Type.op_Equality
/--* t163 int
N007 ( 24, 14) [000165] DA-XG------- * STORE_LCL_VAR int V26 tmp17
[000230] ------------ IL_OFFSET void IL offset: 0x35
N001 ( 0, 0) [000167] ------------ NOP void
N001 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V26 tmp17
/--* t166 int
N003 ( 7, 5) [000169] DA---------- * STORE_LCL_VAR int V15 tmp6
------------ BB07 [037..038), preds={BB05} succs={BB08}
[000231] ------------ IL_OFFSET void IL offset: 0x37
N001 ( 1, 1) [000033] -c---------- t33 = CNS_INT int 1
/--* t33 int
N003 ( 5, 4) [000035] DA---------- * STORE_LCL_VAR int V15 tmp6
------------ BB08 [038..03C) -> BB12 (cond), preds={BB06,BB07} succs={BB09,BB12}
N001 ( 3, 2) [000037] ------------ t37 = LCL_VAR int V15 tmp6
/--* t37 int
N002 ( 4, 4) [000191] ------------ t191 = * CAST int <- bool <- int
/--* t191 int
N004 ( 8, 7) [000039] DA---------- * STORE_LCL_VAR int V01 loc0
[000232] ------------ IL_OFFSET void IL offset: 0x39
N001 ( 3, 2) [000040] -c---------- t40 = LCL_VAR int V01 loc0
N002 ( 1, 1) [000041] -c---------- t41 = CNS_INT int 0
/--* t40 int
+--* t41 int
N003 ( 5, 4) [000042] J------N---- * EQ void
N004 ( 7, 6) [000043] ------------ * JTRUE void
------------ BB09 [03C..05E) -> BB11 (cond), preds={BB08} succs={BB10,BB11}
[000233] ------------ IL_OFFSET void IL offset: 0x3c
N001 ( 1, 1) [000081] ------------ NO_OP void
[000234] ------------ IL_OFFSET void IL offset: 0x3d
N001 ( 3, 2) [000082] ------------ t82 = LCL_VAR byref V00 this
/--* t82 byref
N003 ( 4, 3) [000193] -c---------- t193 = * LEA(b+24) byref
/--* t193 byref
N004 ( 6, 5) [000083] *--XG------- t83 = * IND int
/--* t83 int
N006 ( 10, 8) [000085] DA-XG------- * STORE_LCL_VAR int V02 loc1
[000235] ------------ IL_OFFSET void IL offset: 0x44
N001 ( 3, 2) [000086] ------------ t86 = LCL_VAR byref V00 this
/--* t86 byref
N003 ( 5, 4) [000195] -c---------- t195 = * LEA(b+32) byref
/--* t195 byref
N004 ( 8, 6) [000087] *c-XG------- t87 = * IND struct
[000273] Dc-----N---- t273 = LCL_VAR_ADDR byref V03 loc2
/--* t273 byref
+--* t87 struct
N006 ( 12, 9) [000090] sA---------- * STORE_BLK struct<System.ReadOnlySpan`1[Byte], 16> (copy) (Unroll)
[000236] ------------ IL_OFFSET void IL offset: 0x4b
N001 ( 3, 2) [000091] ------------ t91 = LCL_VAR int V02 loc1
/--* t91 int
N003 ( 7, 5) [000096] DA---------- * STORE_LCL_VAR int V18 tmp9
N002 ( 3, 3) [000093] ------------ t93 = LCL_VAR_ADDR byref V03 loc2
/--* t93 byref
[000274] ------------ t274 = * PUTARG_REG byref REG rcx
/--* t274 byref this in rcx
N003 ( 17, 10) [000094] --CXG------- t94 = * CALL int System.ReadOnlySpan`1[Byte][System.Byte].get_Length
/--* t94 int
N005 ( 21, 13) [000099] DA-XG------- * STORE_LCL_VAR int V19 tmp10
[000237] ------------ IL_OFFSET void IL offset: 0x53
N001 ( 3, 2) [000097] ------------ t97 = LCL_VAR int V18 tmp9
N002 ( 3, 2) [000100] -c---------- t100 = LCL_VAR int V19 tmp10
/--* t97 int
+--* t100 int
N003 ( 10, 5) [000101] N--------U-- t101 = * GE int
/--* t101 int
N005 ( 14, 8) [000105] DA---------- * STORE_LCL_VAR int V05 loc4
[000238] ------------ IL_OFFSET void IL offset: 0x5a
N001 ( 3, 2) [000106] -c---------- t106 = LCL_VAR int V05 loc4
N002 ( 1, 1) [000107] -c---------- t107 = CNS_INT int 0
/--* t106 int
+--* t107 int
N003 ( 5, 4) [000108] J------N---- * EQ void
N004 ( 7, 6) [000109] ------------ * JTRUE void
------------ BB10 [05E..069) -> BB15 (always), preds={BB09} succs={BB15}
[000239] ------------ IL_OFFSET void IL offset: 0x5e
N001 ( 1, 1) [000130] ------------ NO_OP void
[000240] ------------ IL_OFFSET void IL offset: 0x5f
N002 ( 3, 2) [000131] ------------ t131 = LCL_VAR byref V00 this
/--* t131 byref
[000275] ------------ t275 = * PUTARG_REG byref REG rcx
/--* t275 byref arg0 in rcx
N003 ( 17, 8) [000132] --CXG------- t132 = * CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].<ReadByte>g__ReadByteSlow|18_0
/--* t132 int
N005 ( 21, 11) [000134] DA-XG------- * STORE_LCL_VAR int V21 tmp12
[000241] ------------ IL_OFFSET void IL offset: 0x65
N001 ( 3, 2) [000135] ------------ t135 = LCL_VAR int V21 tmp12
/--* t135 int
N002 ( 4, 4) [000198] ------------ t198 = * CAST int <- ubyte <- int
/--* t198 int
N004 ( 8, 7) [000137] DA---------- * STORE_LCL_VAR int V06 loc5
[000242] ------------ IL_OFFSET void IL offset: 0x67
N001 ( 0, 0) [000138] ------------ NOP void
------------ BB11 [069..081) -> BB15 (always), preds={BB09} succs={BB15}
[000243] ------------ IL_OFFSET void IL offset: 0x69
N003 ( 3, 3) [000111] ------------ t111 = LCL_VAR_ADDR byref V03 loc2
/--* t111 byref
[000276] ------------ t276 = * PUTARG_REG byref REG rcx
N004 ( 3, 2) [000112] ------------ t112 = LCL_VAR int V02 loc1
/--* t112 int
[000277] ------------ t277 = * PUTARG_REG int REG rdx
/--* t276 byref this in rcx
+--* t277 int arg1 in rdx
N005 ( 20, 13) [000113] --CXG------- t113 = * CALL byref System.ReadOnlySpan`1[Byte][System.Byte].get_Item
/--* t113 byref
N007 ( 24, 16) [000115] DA-XG------- * STORE_LCL_VAR byref V20 tmp11
[000244] ------------ IL_OFFSET void IL offset: 0x71
N001 ( 3, 2) [000116] ------------ t116 = LCL_VAR byref V20 tmp11
/--* t116 byref
N002 ( 7, 5) [000117] *--XG------- t117 = * IND ubyte
/--* t117 ubyte
N004 ( 11, 8) [000119] DA-XG------- * STORE_LCL_VAR int V04 loc3
[000245] ------------ IL_OFFSET void IL offset: 0x73
N001 ( 3, 2) [000121] ------------ t121 = LCL_VAR int V02 loc1
N002 ( 1, 1) [000122] -c---------- t122 = CNS_INT int 1
/--* t121 int
+--* t122 int
N003 ( 5, 4) [000123] ------------ t123 = * ADD int
N004 ( 3, 2) [000120] ------------ t120 = LCL_VAR byref V00 this
/--* t120 byref
N006 ( 4, 3) [000202] -c---------- t202 = * LEA(b+24) byref
/--* t202 byref
+--* t123 int
[000246] -A-XG------- * STOREIND int
[000247] ------------ IL_OFFSET void IL offset: 0x7c
N001 ( 3, 2) [000126] ------------ t126 = LCL_VAR int V04 loc3
/--* t126 int
N003 ( 7, 5) [000128] DA---------- * STORE_LCL_VAR int V06 loc5
[000248] ------------ IL_OFFSET void IL offset: 0x7f
N001 ( 0, 0) [000129] ------------ NOP void
------------ BB12 [081..09E) -> BB14 (cond), preds={BB08} succs={BB13,BB14}
[000249] ------------ IL_OFFSET void IL offset: 0x81
N004 ( 3, 2) [000204] ------------ t204 = LCL_VAR byref V00 this
/--* t204 byref
N005 ( 4, 3) [000205] ---X---N---- * NULLCHECK int
N006 ( 3, 2) [000206] ------------ t206 = LCL_VAR byref V00 this
N007 ( 1, 1) [000207] -c---------- t207 = CNS_INT long 64 field offset Fseq[_input]
/--* t206 byref
+--* t207 long
N008 ( 5, 4) [000208] ------------ t208 = * ADD byref
/--* t208 byref
[000278] ------------ t278 = * PUTARG_REG byref REG rdx
N010 ( 2, 10) [000046] H----------- t46 = CNS_INT(h) long 0x7ff93af7cd80 class
/--* t46 long
[000279] ------------ t279 = * PUTARG_REG long REG rcx
/--* t278 byref arg1 in rdx
+--* t279 long arg0 in rcx
N011 ( 25, 24) [000048] --CXG------- t48 = * CALL help ref HELPER.CORINFO_HELP_BOX
/--* t48 ref
N013 ( 29, 27) [000214] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp18
N014 ( 3, 2) [000215] ------------ t215 = LCL_VAR ref V27 tmp18
/--* t215 ref
[000280] ------------ t280 = * PUTARG_REG ref REG rdx
N015 ( 2, 10) [000049] H------N---- t49 = CNS_INT(h) long 0x7ff93b569758 class
/--* t49 long
[000281] ------------ t281 = * PUTARG_REG long REG rcx
/--* t280 ref arg1 in rdx
+--* t281 long arg0 in rcx
N016 ( 51, 46) [000050] --CXG------- t50 = * CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS
/--* t50 ref
N018 ( 55, 49) [000052] DA-XG------- * STORE_LCL_VAR ref V07 loc6
[000250] ------------ IL_OFFSET void IL offset: 0x93
N001 ( 3, 2) [000053] -c---------- t53 = LCL_VAR ref V07 loc6
N002 ( 1, 1) [000054] -c---------- t54 = CNS_INT ref null
/--* t53 ref
+--* t54 ref
N003 ( 8, 4) [000055] N----------- t55 = * NE int
/--* t55 int
N005 ( 12, 7) [000057] DA---------- * STORE_LCL_VAR int V08 loc7
[000251] ------------ IL_OFFSET void IL offset: 0x9a
N001 ( 3, 2) [000058] -c---------- t58 = LCL_VAR int V08 loc7
N002 ( 1, 1) [000059] -c---------- t59 = CNS_INT int 0
/--* t58 int
+--* t59 int
N003 ( 5, 4) [000060] J------N---- * EQ void
N004 ( 7, 6) [000061] ------------ * JTRUE void
------------ BB13 [09E..0AA) -> BB15 (always), preds={BB12} succs={BB15}
[000252] ------------ IL_OFFSET void IL offset: 0x9e
N001 ( 1, 1) [000072] ------------ NO_OP void
[000253] ------------ IL_OFFSET void IL offset: 0x9f
N002 ( 3, 2) [000073] ------------ t73 = LCL_VAR ref V07 loc6
/--* t73 ref
[000282] ------------ t282 = * PUTARG_REG ref REG rcx
N001 ( 3, 2) [000283] ------------ t283 = LCL_VAR ref V07 loc6
/--* t283 ref
N002 ( 4, 3) [000284] -c---------- t284 = * LEA(b+0) byref
/--* t284 byref
N003 ( 7, 5) [000285] ------------ t285 = * IND long
/--* t285 long
N004 ( 8, 6) [000286] -c---------- t286 = * LEA(b+72) long
/--* t286 long
N005 ( 11, 8) [000287] ------------ t287 = * IND long
/--* t287 long
N006 ( 12, 9) [000288] -c---------- t288 = * LEA(b+56) long
/--* t288 long
N007 ( 15, 11) [000289] -c---------- t289 = * IND long REG NA
/--* t282 ref this in rcx
+--* t289 long control expr
N003 ( 23, 11) [000074] --CXG------- t74 = * CALLV ind int Hagar.Buffers.ReaderInput.ReadByte
/--* t74 int
N005 ( 27, 14) [000076] DA-XG------- * STORE_LCL_VAR int V17 tmp8
[000254] ------------ IL_OFFSET void IL offset: 0xa6
N001 ( 3, 2) [000077] ------------ t77 = LCL_VAR int V17 tmp8
/--* t77 int
N002 ( 4, 4) [000218] ------------ t218 = * CAST int <- ubyte <- int
/--* t218 int
N004 ( 8, 7) [000079] DA---------- * STORE_LCL_VAR int V06 loc5
[000255] ------------ IL_OFFSET void IL offset: 0xa8
N001 ( 0, 0) [000080] ------------ NOP void
------------ BB14 [0AA..0B4) -> BB15 (always), preds={BB12} succs={BB15}
[000256] ------------ IL_OFFSET void IL offset: 0xaa
N001 ( 1, 1) [000062] ------------ NO_OP void
[000257] ------------ IL_OFFSET void IL offset: 0xab
N001 ( 14, 5) [000063] --CXG------- t63 = CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].ThrowNotSupportedInput
/--* t63 int
N003 ( 18, 8) [000065] DA-XG------- * STORE_LCL_VAR int V16 tmp7
[000258] ------------ IL_OFFSET void IL offset: 0xb0
N001 ( 3, 2) [000066] ------------ t66 = LCL_VAR int V16 tmp7
/--* t66 int
N002 ( 4, 4) [000219] ------------ t219 = * CAST int <- ubyte <- int
/--* t219 int
N004 ( 8, 7) [000068] DA---------- * STORE_LCL_VAR int V06 loc5
[000259] ------------ IL_OFFSET void IL offset: 0xb2
N001 ( 0, 0) [000069] ------------ NOP void
------------ BB15 [0B4..0B7) (return), preds={BB10,BB11,BB13,BB14} succs={}
[000260] ------------ IL_OFFSET void IL offset: 0xb4
N001 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V06 loc5
/--* t70 int
N002 ( 4, 3) [000071] ------------ * RETURN int
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Calculate stack level slots
*************** Finishing PHASE Calculate stack level slots [no changes]
*************** Starting PHASE Linear scan register alloc
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01 use def in out
{}
{}
{}
{}
BB02 use def in out
{}
{}
{}
{}
BB03 use def in out
{}
{}
{}
{}
BB04 use def in out
{}
{}
{}
{}
BB05 use def in out
{}
{}
{}
{}
BB06 use def in out
{}
{}
{}
{}
BB07 use def in out
{}
{}
{}
{}
BB08 use def in out
{}
{}
{}
{}
BB09 use def in out
{}
{}
{}
{}
BB10 use def in out
{}
{}
{}
{}
BB11 use def in out
{}
{}
{}
{}
BB12 use def in out
{}
{}
{}
{}
BB13 use def in out
{}
{}
{}
{}
BB14 use def in out
{}
{}
{}
{}
BB15 use def in out
{}
{}
{}
{}
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = 0, singleExit = 1
TUPLE STYLE DUMP BEFORE LSRA
LSRA Block Sequence: BB01( 1 )
BB02( 1 )
BB03( 0.50)
BB04( 1 )
BB05( 1 )
BB06( 1 )
BB07( 1 )
BB08( 1 )
BB09( 1 )
BB10( 1 )
BB11( 1 )
BB12( 1 )
BB13( 1 )
BB14( 1 )
BB15( 1 )
BB01 [???..???), preds={} succs={BB02}
=====
N001. NOP
BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
=====
N001. CNS_INT(h) 0x7ff9392a5420 global ptr
N002. IND
N003. CNS_INT 0
N004. EQ
N005. JTRUE
BB03 [???..???), preds={BB02} succs={BB04}
=====
N001. CALL help
BB04 [???..???), preds={BB02,BB03} succs={BB05}
=====
BB05 [000..01C) -> BB07 (cond), preds={BB04} succs={BB06,BB07}
=====
N000. IL_OFFSET IL offset: 0x0
N001. NO_OP
N000. IL_OFFSET IL offset: 0x1
N002. t2 = CNS_INT(h) 0x7ff93af7cd80 class
N000. t261 = PUTARG_REG; t2
N003. t3 = CALL help; t261
N005. V10 MEM; t3
N002. t8 = V10 MEM
N000. t262 = PUTARG_REG; t8
N003. t4 = CALL ; t262
N005. V11 MEM; t4
N000. IL_OFFSET IL offset: 0xb
N002. t14 = CNS_INT(h) 0x7ff93af7cd80 class
N000. t263 = PUTARG_REG; t14
N003. t15 = CALL help; t263
N005. V12 MEM; t15
N002. t20 = V12 MEM
N000. t264 = PUTARG_REG; t20
N003. t16 = CALL ; t264
N005. V13 MEM; t16
N000. IL_OFFSET IL offset: 0x15
N003. t13 = V11 MEM
N000. t265 = PUTARG_REG; t13
N004. t25 = V13 MEM
N000. t266 = PUTARG_REG; t25
N005. t26 = CALL ; t265,t266
N007. V14 MEM; t26
N000. IL_OFFSET IL offset: 0x1a
N001. V14 MEM
N002. CNS_INT 0
N003. NE
N004. JTRUE
BB06 [01C..037) -> BB08 (always), preds={BB05} succs={BB08}
=====
N000. IL_OFFSET IL offset: 0x1c
N002. t139 = CNS_INT(h) 0x7ff93af7cd80 class
N000. t267 = PUTARG_REG; t139
N003. t140 = CALL help; t267
N005. V22 MEM; t140
N002. t145 = V22 MEM
N000. t268 = PUTARG_REG; t145
N003. t141 = CALL ; t268
N005. V23 MEM; t141
N000. IL_OFFSET IL offset: 0x26
N002. t151 = CNS_INT(h) 0x7ff93b56a7f8 class
N000. t269 = PUTARG_REG; t151
N003. t152 = CALL help; t269
N005. V24 MEM; t152
N002. t157 = V24 MEM
N000. t270 = PUTARG_REG; t157
N003. t153 = CALL ; t270
N005. V25 MEM; t153
N000. IL_OFFSET IL offset: 0x30
N003. t150 = V23 MEM
N000. t271 = PUTARG_REG; t150
N004. t162 = V25 MEM
N000. t272 = PUTARG_REG; t162
N005. t163 = CALL ; t271,t272
N007. V26 MEM; t163
N000. IL_OFFSET IL offset: 0x35
N001. NOP
N001. t166 = V26 MEM
N003. V15 MEM; t166
BB07 [037..038), preds={BB05} succs={BB08}
=====
N000. IL_OFFSET IL offset: 0x37
N001. CNS_INT 1
N003. V15 MEM
BB08 [038..03C) -> BB12 (cond), preds={BB06,BB07} succs={BB09,BB12}
=====
N001. t37 = V15 MEM
N002. t191 = CAST ; t37
N004. V01 MEM; t191
N000. IL_OFFSET IL offset: 0x39
N001. V01 MEM
N002. CNS_INT 0
N003. EQ
N004. JTRUE
BB09 [03C..05E) -> BB11 (cond), preds={BB08} succs={BB10,BB11}
=====
N000. IL_OFFSET IL offset: 0x3c
N001. NO_OP
N000. IL_OFFSET IL offset: 0x3d
N001. t82 = V00 MEM
N003. t193 = LEA(b+24); t82
N004. t83 = IND ; t193
N006. V02 MEM; t83
N000. IL_OFFSET IL offset: 0x44
N001. t86 = V00 MEM
N003. t195 = LEA(b+32); t86
N004. t87 = IND ; t195
N000. LCL_VAR_ADDR V03 loc2
N006. STORE_BLK; t87
N000. IL_OFFSET IL offset: 0x4b
N001. t91 = V02 MEM
N003. V18 MEM; t91
N002. t93 = LCL_VAR_ADDR V03 loc2
N000. t274 = PUTARG_REG; t93
N003. t94 = CALL ; t274
N005. V19 MEM; t94
N000. IL_OFFSET IL offset: 0x53
N001. t97 = V18 MEM
N002. V19 MEM
N003. t101 = GE ; t97
N005. V05 MEM; t101
N000. IL_OFFSET IL offset: 0x5a
N001. V05 MEM
N002. CNS_INT 0
N003. EQ
N004. JTRUE
BB10 [05E..069) -> BB15 (always), preds={BB09} succs={BB15}
=====
N000. IL_OFFSET IL offset: 0x5e
N001. NO_OP
N000. IL_OFFSET IL offset: 0x5f
N002. t131 = V00 MEM
N000. t275 = PUTARG_REG; t131
N003. t132 = CALL ; t275
N005. V21 MEM; t132
N000. IL_OFFSET IL offset: 0x65
N001. t135 = V21 MEM
N002. t198 = CAST ; t135
N004. V06 MEM; t198
N000. IL_OFFSET IL offset: 0x67
N001. NOP
BB11 [069..081) -> BB15 (always), preds={BB09} succs={BB15}
=====
N000. IL_OFFSET IL offset: 0x69
N003. t111 = LCL_VAR_ADDR V03 loc2
N000. t276 = PUTARG_REG; t111
N004. t112 = V02 MEM
N000. t277 = PUTARG_REG; t112
N005. t113 = CALL ; t276,t277
N007. V20 MEM; t113
N000. IL_OFFSET IL offset: 0x71
N001. t116 = V20 MEM
N002. t117 = IND ; t116
N004. V04 MEM; t117
N000. IL_OFFSET IL offset: 0x73
N001. t121 = V02 MEM
N002. CNS_INT 1
N003. t123 = ADD ; t121
N004. t120 = V00 MEM
N006. t202 = LEA(b+24); t120
N000. STOREIND ; t202,t123
N000. IL_OFFSET IL offset: 0x7c
N001. t126 = V04 MEM
N003. V06 MEM; t126
N000. IL_OFFSET IL offset: 0x7f
N001. NOP
BB12 [081..09E) -> BB14 (cond), preds={BB08} succs={BB13,BB14}
=====
N000. IL_OFFSET IL offset: 0x81
N004. t204 = V00 MEM
N005. NULLCHECK; t204
N006. t206 = V00 MEM
N007. CNS_INT 64 field offset Fseq[_input]
N008. t208 = ADD ; t206
N000. t278 = PUTARG_REG; t208
N010. t46 = CNS_INT(h) 0x7ff93af7cd80 class
N000. t279 = PUTARG_REG; t46
N011. t48 = CALL help; t278,t279
N013. V27 MEM; t48
N014. t215 = V27 MEM
N000. t280 = PUTARG_REG; t215
N015. t49 = CNS_INT(h) 0x7ff93b569758 class
N000. t281 = PUTARG_REG; t49
N016. t50 = CALL help; t280,t281
N018. V07 MEM; t50
N000. IL_OFFSET IL offset: 0x93
N001. V07 MEM
N002. CNS_INT null
N003. t55 = NE
N005. V08 MEM; t55
N000. IL_OFFSET IL offset: 0x9a
N001. V08 MEM
N002. CNS_INT 0
N003. EQ
N004. JTRUE
BB13 [09E..0AA) -> BB15 (always), preds={BB12} succs={BB15}
=====
N000. IL_OFFSET IL offset: 0x9e
N001. NO_OP
N000. IL_OFFSET IL offset: 0x9f
N002. t73 = V07 MEM
N000. t282 = PUTARG_REG; t73
N001. t283 = V07 MEM
N002. t284 = LEA(b+0) ; t283
N003. t285 = IND ; t284
N004. t286 = LEA(b+72); t285
N005. t287 = IND ; t286
N006. t288 = LEA(b+56); t287
N007. t289 = IND ; t288
N003. t74 = CALLV ind; t282,t289
N005. V17 MEM; t74
N000. IL_OFFSET IL offset: 0xa6
N001. t77 = V17 MEM
N002. t218 = CAST ; t77
N004. V06 MEM; t218
N000. IL_OFFSET IL offset: 0xa8
N001. NOP
BB14 [0AA..0B4) -> BB15 (always), preds={BB12} succs={BB15}
=====
N000. IL_OFFSET IL offset: 0xaa
N001. NO_OP
N000. IL_OFFSET IL offset: 0xab
N001. t63 = CALL
N003. V16 MEM; t63
N000. IL_OFFSET IL offset: 0xb0
N001. t66 = V16 MEM
N002. t219 = CAST ; t66
N004. V06 MEM; t219
N000. IL_OFFSET IL offset: 0xb2
N001. NOP
BB15 [0B4..0B7) (return), preds={BB10,BB11,BB13,BB14} succs={}
=====
N000. IL_OFFSET IL offset: 0xb4
N001. t70 = V06 MEM
N002. RETURN ; t70
buildIntervals second part ========
Int arg V00 in reg rcx
NEW BLOCK BB01
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
DefList: { }
N002 ( 0, 0) [000000] ------------ * NOP void REG NA
NEW BLOCK BB02
Setting BB01 as the predecessor for determining incoming variable registers of BB02
<RefPosition #1 @4 RefTypeBB BB02 regmask=[] minReg=1>
DefList: { }
N006 ( 2, 10) [000171] Hc---------- * CNS_INT(h) long 0x7ff9392a5420 global ptr REG NA
Contained
DefList: { }
N008 ( 4, 12) [000172] nc---------- * IND int REG NA
Contained
DefList: { }
N010 ( 1, 1) [000173] -c---------- * CNS_INT int 0 REG NA
Contained
DefList: { }
N012 ( 6, 14) [000174] J------N---- * EQ void REG NA
DefList: { }
N014 ( 8, 16) [000221] ------------ * JTRUE void REG NA
NEW BLOCK BB03
Setting BB02 as the predecessor for determining incoming variable registers of BB03
<RefPosition #2 @16 RefTypeBB BB03 regmask=[] minReg=1>
DefList: { }
N018 ( 14, 5) [000175] --C-G-?----- * CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE REG NA
<RefPosition #3 @19 RefTypeKill <Reg:rax> BB03 regmask=[rax] minReg=1>
<RefPosition #4 @19 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] minReg=1>
<RefPosition #5 @19 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] minReg=1>
<RefPosition #6 @19 RefTypeKill <Reg:r8 > BB03 regmask=[r8] minReg=1>
<RefPosition #7 @19 RefTypeKill <Reg:r9 > BB03 regmask=[r9] minReg=1>
<RefPosition #8 @19 RefTypeKill <Reg:r10> BB03 regmask=[r10] minReg=1>
<RefPosition #9 @19 RefTypeKill <Reg:r11> BB03 regmask=[r11] minReg=1>
NEW BLOCK BB04
Setting BB02 as the predecessor for determining incoming variable registers of BB04
<RefPosition #10 @20 RefTypeBB BB04 regmask=[] minReg=1>
NEW BLOCK BB05
Setting BB04 as the predecessor for determining incoming variable registers of BB05
<RefPosition #11 @22 RefTypeBB BB05 regmask=[] minReg=1>
DefList: { }
N024 (???,???) [000222] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
DefList: { }
N026 ( 1, 1) [000001] ------------ * NO_OP void REG NA
DefList: { }
N028 (???,???) [000223] ------------ * IL_OFFSET void IL offset: 0x1 REG NA
DefList: { }
N030 ( 2, 10) [000002] H----------- * CNS_INT(h) long 0x7ff93af7cd80 class REG NA
Interval 0: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #12 @31 RefTypeDef <Ivl:0> CNS_INT BB05 regmask=[allIntButFP] minReg=1>
DefList: { N030.t2. CNS_INT }
N032 (???,???) [000261] ------------ * PUTARG_REG long REG rcx
<RefPosition #13 @32 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #14 @32 RefTypeUse <Ivl:0> BB05 regmask=[rcx] minReg=1 last fixed>
Interval 1: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #15 @33 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #16 @33 RefTypeDef <Ivl:1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
DefList: { N032.t261. PUTARG_REG }
N034 ( 16, 16) [000003] --C-G------- * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE REG NA
<RefPosition #17 @34 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #18 @34 RefTypeUse <Ivl:1> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #19 @35 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #20 @35 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #21 @35 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #22 @35 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1>
<RefPosition #23 @35 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1>
<RefPosition #24 @35 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1>
<RefPosition #25 @35 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1>
Interval 2: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #26 @35 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #27 @35 RefTypeDef <Ivl:2> CALL BB05 regmask=[rax] minReg=1 fixed>
DefList: { N034.t3. CALL }
N036 ( 20, 19) [000007] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1 NA REG NA
<RefPosition #28 @36 RefTypeUse <Ivl:2> BB05 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N038 ( 3, 4) [000008] ------------ * LCL_FLD ref V10 tmp1 [+0] NA REG NA
Interval 3: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #29 @39 RefTypeDef <Ivl:3> LCL_FLD BB05 regmask=[allIntButFP] minReg=1>
DefList: { N038.t8. LCL_FLD }
N040 (???,???) [000262] ------------ * PUTARG_REG ref REG rcx
<RefPosition #30 @40 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #31 @40 RefTypeUse <Ivl:3> BB05 regmask=[rcx] minReg=1 last fixed>
Interval 4: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #32 @41 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #33 @41 RefTypeDef <Ivl:4> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
DefList: { N040.t262. PUTARG_REG }
N042 ( 17, 10) [000004] --CXG------- * CALL ref System.Type.GetTypeFromHandle REG NA
<RefPosition #34 @42 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #35 @42 RefTypeUse <Ivl:4> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #36 @43 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #37 @43 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #38 @43 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #39 @43 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1>
<RefPosition #40 @43 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1>
<RefPosition #41 @43 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1>
<RefPosition #42 @43 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1>
Interval 5: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #43 @43 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #44 @43 RefTypeDef <Ivl:5> CALL BB05 regmask=[rax] minReg=1 fixed>
DefList: { N042.t4. CALL }
N044 ( 21, 13) [000012] DA-XG------- * STORE_LCL_VAR ref V11 tmp2 NA REG NA
<RefPosition #45 @44 RefTypeUse <Ivl:5> BB05 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N046 (???,???) [000224] ------------ * IL_OFFSET void IL offset: 0xb REG NA
DefList: { }
N048 ( 2, 10) [000014] H----------- * CNS_INT(h) long 0x7ff93af7cd80 class REG NA
Interval 6: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #46 @49 RefTypeDef <Ivl:6> CNS_INT BB05 regmask=[allIntButFP] minReg=1>
DefList: { N048.t14. CNS_INT }
N050 (???,???) [000263] ------------ * PUTARG_REG long REG rcx
<RefPosition #47 @50 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #48 @50 RefTypeUse <Ivl:6> BB05 regmask=[rcx] minReg=1 last fixed>
Interval 7: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #49 @51 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #50 @51 RefTypeDef <Ivl:7> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
DefList: { N050.t263. PUTARG_REG }
N052 ( 16, 16) [000015] --C-G------- * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE REG NA
<RefPosition #51 @52 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #52 @52 RefTypeUse <Ivl:7> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #53 @53 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #54 @53 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #55 @53 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #56 @53 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1>
<RefPosition #57 @53 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1>
<RefPosition #58 @53 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1>
<RefPosition #59 @53 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1>
Interval 8: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #60 @53 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #61 @53 RefTypeDef <Ivl:8> CALL BB05 regmask=[rax] minReg=1 fixed>
DefList: { N052.t15. CALL }
N054 ( 20, 19) [000019] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3 NA REG NA
<RefPosition #62 @54 RefTypeUse <Ivl:8> BB05 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N056 ( 3, 4) [000020] ------------ * LCL_FLD ref V12 tmp3 [+0] NA REG NA
Interval 9: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #63 @57 RefTypeDef <Ivl:9> LCL_FLD BB05 regmask=[allIntButFP] minReg=1>
DefList: { N056.t20. LCL_FLD }
N058 (???,???) [000264] ------------ * PUTARG_REG ref REG rcx
<RefPosition #64 @58 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #65 @58 RefTypeUse <Ivl:9> BB05 regmask=[rcx] minReg=1 last fixed>
Interval 10: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #66 @59 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #67 @59 RefTypeDef <Ivl:10> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
DefList: { N058.t264. PUTARG_REG }
N060 ( 17, 10) [000016] --CXG------- * CALL ref System.Type.GetTypeFromHandle REG NA
<RefPosition #68 @60 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #69 @60 RefTypeUse <Ivl:10> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #70 @61 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #71 @61 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #72 @61 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #73 @61 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1>
<RefPosition #74 @61 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1>
<RefPosition #75 @61 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1>
<RefPosition #76 @61 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1>
Interval 11: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #77 @61 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #78 @61 RefTypeDef <Ivl:11> CALL BB05 regmask=[rax] minReg=1 fixed>
DefList: { N060.t16. CALL }
N062 ( 21, 13) [000024] DA-XG------- * STORE_LCL_VAR ref V13 tmp4 NA REG NA
<RefPosition #79 @62 RefTypeUse <Ivl:11> BB05 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N064 (???,???) [000225] ------------ * IL_OFFSET void IL offset: 0x15 REG NA
DefList: { }
N066 ( 3, 2) [000013] ------------ * LCL_VAR ref V11 tmp2 NA REG NA
Interval 12: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #80 @67 RefTypeDef <Ivl:12> LCL_VAR BB05 regmask=[allIntButFP] minReg=1>
DefList: { N066.t13. LCL_VAR }
N068 (???,???) [000265] ------------ * PUTARG_REG ref REG rcx
<RefPosition #81 @68 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #82 @68 RefTypeUse <Ivl:12> BB05 regmask=[rcx] minReg=1 last fixed>
Interval 13: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #83 @69 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #84 @69 RefTypeDef <Ivl:13> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
DefList: { N068.t265. PUTARG_REG }
N070 ( 3, 2) [000025] ------------ * LCL_VAR ref V13 tmp4 NA REG NA
Interval 14: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #85 @71 RefTypeDef <Ivl:14> LCL_VAR BB05 regmask=[allIntButFP] minReg=1>
DefList: { N068.t265. PUTARG_REG; N070.t25. LCL_VAR }
N072 (???,???) [000266] ------------ * PUTARG_REG ref REG rdx
<RefPosition #86 @72 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #87 @72 RefTypeUse <Ivl:14> BB05 regmask=[rdx] minReg=1 last fixed>
Interval 15: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #88 @73 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #89 @73 RefTypeDef <Ivl:15> PUTARG_REG BB05 regmask=[rdx] minReg=1 fixed>
DefList: { N068.t265. PUTARG_REG; N072.t266. PUTARG_REG }
N074 ( 20, 11) [000026] --CXG------- * CALL int System.Type.op_Equality REG NA
<RefPosition #90 @74 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #91 @74 RefTypeUse <Ivl:13> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #92 @74 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #93 @74 RefTypeUse <Ivl:15> BB05 regmask=[rdx] minReg=1 last fixed>
<RefPosition #94 @75 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #95 @75 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #96 @75 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #97 @75 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1>
<RefPosition #98 @75 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1>
<RefPosition #99 @75 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1>
<RefPosition #100 @75 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1>
Interval 16: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #101 @75 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #102 @75 RefTypeDef <Ivl:16> CALL BB05 regmask=[rax] minReg=1 fixed>
DefList: { N074.t26. CALL }
N076 ( 24, 14) [000028] DA-XG------- * STORE_LCL_VAR int V14 tmp5 NA REG NA
<RefPosition #103 @76 RefTypeUse <Ivl:16> BB05 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N078 (???,???) [000226] ------------ * IL_OFFSET void IL offset: 0x1a REG NA
DefList: { }
N080 ( 3, 2) [000029] -c---------- * LCL_VAR int V14 tmp5 NA REG NA
Contained
DefList: { }
N082 ( 1, 1) [000030] -c---------- * CNS_INT int 0 REG NA
Contained
DefList: { }
N084 ( 5, 4) [000031] J------N---- * NE void REG NA
DefList: { }
N086 ( 7, 6) [000032] ------------ * JTRUE void REG NA
NEW BLOCK BB06
Setting BB05 as the predecessor for determining incoming variable registers of BB06
<RefPosition #104 @88 RefTypeBB BB06 regmask=[] minReg=1>
DefList: { }
N090 (???,???) [000227] ------------ * IL_OFFSET void IL offset: 0x1c REG NA
DefList: { }
N092 ( 2, 10) [000139] H----------- * CNS_INT(h) long 0x7ff93af7cd80 class REG NA
Interval 17: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #105 @93 RefTypeDef <Ivl:17> CNS_INT BB06 regmask=[allIntButFP] minReg=1>
DefList: { N092.t139. CNS_INT }
N094 (???,???) [000267] ------------ * PUTARG_REG long REG rcx
<RefPosition #106 @94 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #107 @94 RefTypeUse <Ivl:17> BB06 regmask=[rcx] minReg=1 last fixed>
Interval 18: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #108 @95 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #109 @95 RefTypeDef <Ivl:18> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
DefList: { N094.t267. PUTARG_REG }
N096 ( 16, 16) [000140] --C-G------- * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE REG NA
<RefPosition #110 @96 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #111 @96 RefTypeUse <Ivl:18> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #112 @97 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #113 @97 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #114 @97 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1>
<RefPosition #115 @97 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1>
<RefPosition #116 @97 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1>
<RefPosition #117 @97 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1>
<RefPosition #118 @97 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1>
Interval 19: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #119 @97 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #120 @97 RefTypeDef <Ivl:19> CALL BB06 regmask=[rax] minReg=1 fixed>
DefList: { N096.t140. CALL }
N098 ( 20, 19) [000144] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13 NA REG NA
<RefPosition #121 @98 RefTypeUse <Ivl:19> BB06 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N100 ( 3, 4) [000145] ------------ * LCL_FLD ref V22 tmp13 [+0] NA REG NA
Interval 20: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #122 @101 RefTypeDef <Ivl:20> LCL_FLD BB06 regmask=[allIntButFP] minReg=1>
DefList: { N100.t145. LCL_FLD }
N102 (???,???) [000268] ------------ * PUTARG_REG ref REG rcx
<RefPosition #123 @102 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #124 @102 RefTypeUse <Ivl:20> BB06 regmask=[rcx] minReg=1 last fixed>
Interval 21: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #125 @103 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #126 @103 RefTypeDef <Ivl:21> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
DefList: { N102.t268. PUTARG_REG }
N104 ( 17, 10) [000141] --CXG------- * CALL ref System.Type.GetTypeFromHandle REG NA
<RefPosition #127 @104 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #128 @104 RefTypeUse <Ivl:21> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #129 @105 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #130 @105 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #131 @105 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1>
<RefPosition #132 @105 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1>
<RefPosition #133 @105 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1>
<RefPosition #134 @105 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1>
<RefPosition #135 @105 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1>
Interval 22: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #136 @105 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #137 @105 RefTypeDef <Ivl:22> CALL BB06 regmask=[rax] minReg=1 fixed>
DefList: { N104.t141. CALL }
N106 ( 21, 13) [000149] DA-XG------- * STORE_LCL_VAR ref V23 tmp14 NA REG NA
<RefPosition #138 @106 RefTypeUse <Ivl:22> BB06 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N108 (???,???) [000228] ------------ * IL_OFFSET void IL offset: 0x26 REG NA
DefList: { }
N110 ( 2, 10) [000151] H----------- * CNS_INT(h) long 0x7ff93b56a7f8 class REG NA
Interval 23: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #139 @111 RefTypeDef <Ivl:23> CNS_INT BB06 regmask=[allIntButFP] minReg=1>
DefList: { N110.t151. CNS_INT }
N112 (???,???) [000269] ------------ * PUTARG_REG long REG rcx
<RefPosition #140 @112 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #141 @112 RefTypeUse <Ivl:23> BB06 regmask=[rcx] minReg=1 last fixed>
Interval 24: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #142 @113 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #143 @113 RefTypeDef <Ivl:24> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
DefList: { N112.t269. PUTARG_REG }
N114 ( 16, 16) [000152] --C-G------- * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE REG NA
<RefPosition #144 @114 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #145 @114 RefTypeUse <Ivl:24> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #146 @115 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #147 @115 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #148 @115 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1>
<RefPosition #149 @115 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1>
<RefPosition #150 @115 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1>
<RefPosition #151 @115 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1>
<RefPosition #152 @115 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1>
Interval 25: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #153 @115 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #154 @115 RefTypeDef <Ivl:25> CALL BB06 regmask=[rax] minReg=1 fixed>
DefList: { N114.t152. CALL }
N116 ( 20, 19) [000156] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15 NA REG NA
<RefPosition #155 @116 RefTypeUse <Ivl:25> BB06 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N118 ( 3, 4) [000157] ------------ * LCL_FLD ref V24 tmp15 [+0] NA REG NA
Interval 26: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #156 @119 RefTypeDef <Ivl:26> LCL_FLD BB06 regmask=[allIntButFP] minReg=1>
DefList: { N118.t157. LCL_FLD }
N120 (???,???) [000270] ------------ * PUTARG_REG ref REG rcx
<RefPosition #157 @120 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #158 @120 RefTypeUse <Ivl:26> BB06 regmask=[rcx] minReg=1 last fixed>
Interval 27: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #159 @121 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #160 @121 RefTypeDef <Ivl:27> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
DefList: { N120.t270. PUTARG_REG }
N122 ( 17, 10) [000153] --CXG------- * CALL ref System.Type.GetTypeFromHandle REG NA
<RefPosition #161 @122 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #162 @122 RefTypeUse <Ivl:27> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #163 @123 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #164 @123 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #165 @123 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1>
<RefPosition #166 @123 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1>
<RefPosition #167 @123 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1>
<RefPosition #168 @123 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1>
<RefPosition #169 @123 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1>
Interval 28: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #170 @123 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #171 @123 RefTypeDef <Ivl:28> CALL BB06 regmask=[rax] minReg=1 fixed>
DefList: { N122.t153. CALL }
N124 ( 21, 13) [000161] DA-XG------- * STORE_LCL_VAR ref V25 tmp16 NA REG NA
<RefPosition #172 @124 RefTypeUse <Ivl:28> BB06 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N126 (???,???) [000229] ------------ * IL_OFFSET void IL offset: 0x30 REG NA
DefList: { }
N128 ( 3, 2) [000150] ------------ * LCL_VAR ref V23 tmp14 NA REG NA
Interval 29: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #173 @129 RefTypeDef <Ivl:29> LCL_VAR BB06 regmask=[allIntButFP] minReg=1>
DefList: { N128.t150. LCL_VAR }
N130 (???,???) [000271] ------------ * PUTARG_REG ref REG rcx
<RefPosition #174 @130 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #175 @130 RefTypeUse <Ivl:29> BB06 regmask=[rcx] minReg=1 last fixed>
Interval 30: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #176 @131 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #177 @131 RefTypeDef <Ivl:30> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
DefList: { N130.t271. PUTARG_REG }
N132 ( 3, 2) [000162] ------------ * LCL_VAR ref V25 tmp16 NA REG NA
Interval 31: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #178 @133 RefTypeDef <Ivl:31> LCL_VAR BB06 regmask=[allIntButFP] minReg=1>
DefList: { N130.t271. PUTARG_REG; N132.t162. LCL_VAR }
N134 (???,???) [000272] ------------ * PUTARG_REG ref REG rdx
<RefPosition #179 @134 RefTypeFixedReg <Reg:rdx> BB06 regmask=[rdx] minReg=1>
<RefPosition #180 @134 RefTypeUse <Ivl:31> BB06 regmask=[rdx] minReg=1 last fixed>
Interval 32: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #181 @135 RefTypeFixedReg <Reg:rdx> BB06 regmask=[rdx] minReg=1>
<RefPosition #182 @135 RefTypeDef <Ivl:32> PUTARG_REG BB06 regmask=[rdx] minReg=1 fixed>
DefList: { N130.t271. PUTARG_REG; N134.t272. PUTARG_REG }
N136 ( 20, 11) [000163] --CXG------- * CALL int System.Type.op_Equality REG NA
<RefPosition #183 @136 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #184 @136 RefTypeUse <Ivl:30> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #185 @136 RefTypeFixedReg <Reg:rdx> BB06 regmask=[rdx] minReg=1>
<RefPosition #186 @136 RefTypeUse <Ivl:32> BB06 regmask=[rdx] minReg=1 last fixed>
<RefPosition #187 @137 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #188 @137 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #189 @137 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1>
<RefPosition #190 @137 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1>
<RefPosition #191 @137 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1>
<RefPosition #192 @137 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1>
<RefPosition #193 @137 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1>
Interval 33: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #194 @137 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #195 @137 RefTypeDef <Ivl:33> CALL BB06 regmask=[rax] minReg=1 fixed>
DefList: { N136.t163. CALL }
N138 ( 24, 14) [000165] DA-XG------- * STORE_LCL_VAR int V26 tmp17 NA REG NA
<RefPosition #196 @138 RefTypeUse <Ivl:33> BB06 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N140 (???,???) [000230] ------------ * IL_OFFSET void IL offset: 0x35 REG NA
DefList: { }
N142 ( 0, 0) [000167] ------------ * NOP void REG NA
DefList: { }
N144 ( 3, 2) [000166] ------------ * LCL_VAR int V26 tmp17 NA REG NA
Interval 34: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #197 @145 RefTypeDef <Ivl:34> LCL_VAR BB06 regmask=[allIntButFP] minReg=1>
DefList: { N144.t166. LCL_VAR }
N146 ( 7, 5) [000169] DA---------- * STORE_LCL_VAR int V15 tmp6 NA REG NA
<RefPosition #198 @146 RefTypeUse <Ivl:34> BB06 regmask=[allIntButFP] minReg=1 last>
NEW BLOCK BB07
Setting BB05 as the predecessor for determining incoming variable registers of BB07
<RefPosition #199 @148 RefTypeBB BB07 regmask=[] minReg=1>
DefList: { }
N150 (???,???) [000231] ------------ * IL_OFFSET void IL offset: 0x37 REG NA
DefList: { }
N152 ( 1, 1) [000033] -c---------- * CNS_INT int 1 REG NA
Contained
DefList: { }
N154 ( 5, 4) [000035] DA---------- * STORE_LCL_VAR int V15 tmp6 NA REG NA
NEW BLOCK BB08
Setting BB06 as the predecessor for determining incoming variable registers of BB08
<RefPosition #200 @156 RefTypeBB BB08 regmask=[] minReg=1>
DefList: { }
N158 ( 3, 2) [000037] ------------ * LCL_VAR int V15 tmp6 NA REG NA
Interval 35: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #201 @159 RefTypeDef <Ivl:35> LCL_VAR BB08 regmask=[allIntButFP] minReg=1>
DefList: { N158.t37. LCL_VAR }
N160 ( 4, 4) [000191] ------------ * CAST int <- bool <- int REG NA
<RefPosition #202 @160 RefTypeUse <Ivl:35> BB08 regmask=[allIntButFP] minReg=1 last>
Interval 36: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #203 @161 RefTypeDef <Ivl:36> CAST BB08 regmask=[allIntButFP] minReg=1>
DefList: { N160.t191. CAST }
N162 ( 8, 7) [000039] DA---------- * STORE_LCL_VAR int V01 loc0 NA REG NA
<RefPosition #204 @162 RefTypeUse <Ivl:36> BB08 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N164 (???,???) [000232] ------------ * IL_OFFSET void IL offset: 0x39 REG NA
DefList: { }
N166 ( 3, 2) [000040] -c---------- * LCL_VAR int V01 loc0 NA REG NA
Contained
DefList: { }
N168 ( 1, 1) [000041] -c---------- * CNS_INT int 0 REG NA
Contained
DefList: { }
N170 ( 5, 4) [000042] J------N---- * EQ void REG NA
DefList: { }
N172 ( 7, 6) [000043] ------------ * JTRUE void REG NA
NEW BLOCK BB09
Setting BB08 as the predecessor for determining incoming variable registers of BB09
<RefPosition #205 @174 RefTypeBB BB09 regmask=[] minReg=1>
DefList: { }
N176 (???,???) [000233] ------------ * IL_OFFSET void IL offset: 0x3c REG NA
DefList: { }
N178 ( 1, 1) [000081] ------------ * NO_OP void REG NA
DefList: { }
N180 (???,???) [000234] ------------ * IL_OFFSET void IL offset: 0x3d REG NA
DefList: { }
N182 ( 3, 2) [000082] ------------ * LCL_VAR byref V00 this NA REG NA
Interval 37: byref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #206 @183 RefTypeDef <Ivl:37> LCL_VAR BB09 regmask=[allIntButFP] minReg=1>
DefList: { N182.t82. LCL_VAR }
N184 ( 4, 3) [000193] -c---------- * LEA(b+24) byref REG NA
Contained
DefList: { N182.t82. LCL_VAR }
N186 ( 6, 5) [000083] *--XG------- * IND int REG NA
<RefPosition #207 @186 RefTypeUse <Ivl:37> BB09 regmask=[allIntButFP] minReg=1 last>
Interval 38: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #208 @187 RefTypeDef <Ivl:38> IND BB09 regmask=[allIntButFP] minReg=1>
DefList: { N186.t83. IND }
N188 ( 10, 8) [000085] DA-XG------- * STORE_LCL_VAR int V02 loc1 NA REG NA
<RefPosition #209 @188 RefTypeUse <Ivl:38> BB09 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N190 (???,???) [000235] ------------ * IL_OFFSET void IL offset: 0x44 REG NA
DefList: { }
N192 ( 3, 2) [000086] ------------ * LCL_VAR byref V00 this NA REG NA
Interval 39: byref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #210 @193 RefTypeDef <Ivl:39> LCL_VAR BB09 regmask=[allIntButFP] minReg=1>
DefList: { N192.t86. LCL_VAR }
N194 ( 5, 4) [000195] -c---------- * LEA(b+32) byref REG NA
Contained
DefList: { N192.t86. LCL_VAR }
N196 ( 8, 6) [000087] *c-XG------- * IND struct REG NA
Contained
DefList: { N192.t86. LCL_VAR }
N198 (???,???) [000273] Dc-----N---- * LCL_VAR_ADDR byref V03 loc2 NA REG NA
Contained
DefList: { N192.t86. LCL_VAR }
N200 ( 12, 9) [000090] sA---------- * STORE_BLK struct<System.ReadOnlySpan`1[Byte], 16> (copy) (Unroll) REG NA
Interval 40: float RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #211 @200 RefTypeDef <Ivl:40 internal> STORE_BLK BB09 regmask=[mm0-mm5] minReg=1>
<RefPosition #212 @200 RefTypeUse <Ivl:39> BB09 regmask=[allIntButFP] minReg=1 last>
<RefPosition #213 @200 RefTypeUse <Ivl:40 internal> STORE_BLK BB09 regmask=[mm0-mm5] minReg=1 last>
DefList: { }
N202 (???,???) [000236] ------------ * IL_OFFSET void IL offset: 0x4b REG NA
DefList: { }
N204 ( 3, 2) [000091] ------------ * LCL_VAR int V02 loc1 NA REG NA
Interval 41: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #214 @205 RefTypeDef <Ivl:41> LCL_VAR BB09 regmask=[allIntButFP] minReg=1>
DefList: { N204.t91. LCL_VAR }
N206 ( 7, 5) [000096] DA---------- * STORE_LCL_VAR int V18 tmp9 NA REG NA
<RefPosition #215 @206 RefTypeUse <Ivl:41> BB09 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N208 ( 3, 3) [000093] ------------ * LCL_VAR_ADDR byref V03 loc2 NA REG NA
Interval 42: byref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #216 @209 RefTypeDef <Ivl:42> LCL_VAR_ADDR BB09 regmask=[allIntButFP] minReg=1>
DefList: { N208.t93. LCL_VAR_ADDR }
N210 (???,???) [000274] ------------ * PUTARG_REG byref REG rcx
<RefPosition #217 @210 RefTypeFixedReg <Reg:rcx> BB09 regmask=[rcx] minReg=1>
<RefPosition #218 @210 RefTypeUse <Ivl:42> BB09 regmask=[rcx] minReg=1 last fixed>
Interval 43: byref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #219 @211 RefTypeFixedReg <Reg:rcx> BB09 regmask=[rcx] minReg=1>
<RefPosition #220 @211 RefTypeDef <Ivl:43> PUTARG_REG BB09 regmask=[rcx] minReg=1 fixed>
DefList: { N210.t274. PUTARG_REG }
N212 ( 17, 10) [000094] --CXG------- * CALL int System.ReadOnlySpan`1[Byte][System.Byte].get_Length REG NA
<RefPosition #221 @212 RefTypeFixedReg <Reg:rcx> BB09 regmask=[rcx] minReg=1>
<RefPosition #222 @212 RefTypeUse <Ivl:43> BB09 regmask=[rcx] minReg=1 last fixed>
<RefPosition #223 @213 RefTypeKill <Reg:rax> BB09 regmask=[rax] minReg=1>
<RefPosition #224 @213 RefTypeKill <Reg:rcx> BB09 regmask=[rcx] minReg=1>
<RefPosition #225 @213 RefTypeKill <Reg:rdx> BB09 regmask=[rdx] minReg=1>
<RefPosition #226 @213 RefTypeKill <Reg:r8 > BB09 regmask=[r8] minReg=1>
<RefPosition #227 @213 RefTypeKill <Reg:r9 > BB09 regmask=[r9] minReg=1>
<RefPosition #228 @213 RefTypeKill <Reg:r10> BB09 regmask=[r10] minReg=1>
<RefPosition #229 @213 RefTypeKill <Reg:r11> BB09 regmask=[r11] minReg=1>
Interval 44: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #230 @213 RefTypeFixedReg <Reg:rax> BB09 regmask=[rax] minReg=1>
<RefPosition #231 @213 RefTypeDef <Ivl:44> CALL BB09 regmask=[rax] minReg=1 fixed>
DefList: { N212.t94. CALL }
N214 ( 21, 13) [000099] DA-XG------- * STORE_LCL_VAR int V19 tmp10 NA REG NA
<RefPosition #232 @214 RefTypeUse <Ivl:44> BB09 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N216 (???,???) [000237] ------------ * IL_OFFSET void IL offset: 0x53 REG NA
DefList: { }
N218 ( 3, 2) [000097] ------------ * LCL_VAR int V18 tmp9 NA REG NA
Interval 45: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #233 @219 RefTypeDef <Ivl:45> LCL_VAR BB09 regmask=[allIntButFP] minReg=1>
DefList: { N218.t97. LCL_VAR }
N220 ( 3, 2) [000100] -c---------- * LCL_VAR int V19 tmp10 NA REG NA
Contained
DefList: { N218.t97. LCL_VAR }
N222 ( 10, 5) [000101] N--------U-- * GE int REG NA
<RefPosition #234 @222 RefTypeUse <Ivl:45> BB09 regmask=[allIntButFP] minReg=1 last>
Interval 46: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #235 @223 RefTypeDef <Ivl:46> GE BB09 regmask=[allIntButFP] minReg=1>
DefList: { N222.t101. GE }
N224 ( 14, 8) [000105] DA---------- * STORE_LCL_VAR int V05 loc4 NA REG NA
<RefPosition #236 @224 RefTypeUse <Ivl:46> BB09 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N226 (???,???) [000238] ------------ * IL_OFFSET void IL offset: 0x5a REG NA
DefList: { }
N228 ( 3, 2) [000106] -c---------- * LCL_VAR int V05 loc4 NA REG NA
Contained
DefList: { }
N230 ( 1, 1) [000107] -c---------- * CNS_INT int 0 REG NA
Contained
DefList: { }
N232 ( 5, 4) [000108] J------N---- * EQ void REG NA
DefList: { }
N234 ( 7, 6) [000109] ------------ * JTRUE void REG NA
NEW BLOCK BB10
Setting BB09 as the predecessor for determining incoming variable registers of BB10
<RefPosition #237 @236 RefTypeBB BB10 regmask=[] minReg=1>
DefList: { }
N238 (???,???) [000239] ------------ * IL_OFFSET void IL offset: 0x5e REG NA
DefList: { }
N240 ( 1, 1) [000130] ------------ * NO_OP void REG NA
DefList: { }
N242 (???,???) [000240] ------------ * IL_OFFSET void IL offset: 0x5f REG NA
DefList: { }
N244 ( 3, 2) [000131] ------------ * LCL_VAR byref V00 this NA REG NA
Interval 47: byref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #238 @245 RefTypeDef <Ivl:47> LCL_VAR BB10 regmask=[allIntButFP] minReg=1>
DefList: { N244.t131. LCL_VAR }
N246 (???,???) [000275] ------------ * PUTARG_REG byref REG rcx
<RefPosition #239 @246 RefTypeFixedReg <Reg:rcx> BB10 regmask=[rcx] minReg=1>
<RefPosition #240 @246 RefTypeUse <Ivl:47> BB10 regmask=[rcx] minReg=1 last fixed>
Interval 48: byref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #241 @247 RefTypeFixedReg <Reg:rcx> BB10 regmask=[rcx] minReg=1>
<RefPosition #242 @247 RefTypeDef <Ivl:48> PUTARG_REG BB10 regmask=[rcx] minReg=1 fixed>
DefList: { N246.t275. PUTARG_REG }
N248 ( 17, 8) [000132] --CXG------- * CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].<ReadByte>g__ReadByteSlow|18_0 REG NA
<RefPosition #243 @248 RefTypeFixedReg <Reg:rcx> BB10 regmask=[rcx] minReg=1>
<RefPosition #244 @248 RefTypeUse <Ivl:48> BB10 regmask=[rcx] minReg=1 last fixed>
<RefPosition #245 @249 RefTypeKill <Reg:rax> BB10 regmask=[rax] minReg=1>
<RefPosition #246 @249 RefTypeKill <Reg:rcx> BB10 regmask=[rcx] minReg=1>
<RefPosition #247 @249 RefTypeKill <Reg:rdx> BB10 regmask=[rdx] minReg=1>
<RefPosition #248 @249 RefTypeKill <Reg:r8 > BB10 regmask=[r8] minReg=1>
<RefPosition #249 @249 RefTypeKill <Reg:r9 > BB10 regmask=[r9] minReg=1>
<RefPosition #250 @249 RefTypeKill <Reg:r10> BB10 regmask=[r10] minReg=1>
<RefPosition #251 @249 RefTypeKill <Reg:r11> BB10 regmask=[r11] minReg=1>
Interval 49: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #252 @249 RefTypeFixedReg <Reg:rax> BB10 regmask=[rax] minReg=1>
<RefPosition #253 @249 RefTypeDef <Ivl:49> CALL BB10 regmask=[rax] minReg=1 fixed>
DefList: { N248.t132. CALL }
N250 ( 21, 11) [000134] DA-XG------- * STORE_LCL_VAR int V21 tmp12 NA REG NA
<RefPosition #254 @250 RefTypeUse <Ivl:49> BB10 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N252 (???,???) [000241] ------------ * IL_OFFSET void IL offset: 0x65 REG NA
DefList: { }
N254 ( 3, 2) [000135] ------------ * LCL_VAR int V21 tmp12 NA REG NA
Interval 50: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #255 @255 RefTypeDef <Ivl:50> LCL_VAR BB10 regmask=[allIntButFP] minReg=1>
DefList: { N254.t135. LCL_VAR }
N256 ( 4, 4) [000198] ------------ * CAST int <- ubyte <- int REG NA
<RefPosition #256 @256 RefTypeUse <Ivl:50> BB10 regmask=[allIntButFP] minReg=1 last>
Interval 51: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #257 @257 RefTypeDef <Ivl:51> CAST BB10 regmask=[allIntButFP] minReg=1>
DefList: { N256.t198. CAST }
N258 ( 8, 7) [000137] DA---------- * STORE_LCL_VAR int V06 loc5 NA REG NA
<RefPosition #258 @258 RefTypeUse <Ivl:51> BB10 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N260 (???,???) [000242] ------------ * IL_OFFSET void IL offset: 0x67 REG NA
DefList: { }
N262 ( 0, 0) [000138] ------------ * NOP void REG NA
NEW BLOCK BB11
Setting BB09 as the predecessor for determining incoming variable registers of BB11
<RefPosition #259 @264 RefTypeBB BB11 regmask=[] minReg=1>
DefList: { }
N266 (???,???) [000243] ------------ * IL_OFFSET void IL offset: 0x69 REG NA
DefList: { }
N268 ( 3, 3) [000111] ------------ * LCL_VAR_ADDR byref V03 loc2 NA REG NA
Interval 52: byref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #260 @269 RefTypeDef <Ivl:52> LCL_VAR_ADDR BB11 regmask=[allIntButFP] minReg=1>
DefList: { N268.t111. LCL_VAR_ADDR }
N270 (???,???) [000276] ------------ * PUTARG_REG byref REG rcx
<RefPosition #261 @270 RefTypeFixedReg <Reg:rcx> BB11 regmask=[rcx] minReg=1>
<RefPosition #262 @270 RefTypeUse <Ivl:52> BB11 regmask=[rcx] minReg=1 last fixed>
Interval 53: byref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #263 @271 RefTypeFixedReg <Reg:rcx> BB11 regmask=[rcx] minReg=1>
<RefPosition #264 @271 RefTypeDef <Ivl:53> PUTARG_REG BB11 regmask=[rcx] minReg=1 fixed>
DefList: { N270.t276. PUTARG_REG }
N272 ( 3, 2) [000112] ------------ * LCL_VAR int V02 loc1 NA REG NA
Interval 54: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #265 @273 RefTypeDef <Ivl:54> LCL_VAR BB11 regmask=[allIntButFP] minReg=1>
DefList: { N270.t276. PUTARG_REG; N272.t112. LCL_VAR }
N274 (???,???) [000277] ------------ * PUTARG_REG int REG rdx
<RefPosition #266 @274 RefTypeFixedReg <Reg:rdx> BB11 regmask=[rdx] minReg=1>
<RefPosition #267 @274 RefTypeUse <Ivl:54> BB11 regmask=[rdx] minReg=1 last fixed>
Interval 55: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #268 @275 RefTypeFixedReg <Reg:rdx> BB11 regmask=[rdx] minReg=1>
<RefPosition #269 @275 RefTypeDef <Ivl:55> PUTARG_REG BB11 regmask=[rdx] minReg=1 fixed>
DefList: { N270.t276. PUTARG_REG; N274.t277. PUTARG_REG }
N276 ( 20, 13) [000113] --CXG------- * CALL byref System.ReadOnlySpan`1[Byte][System.Byte].get_Item REG NA
<RefPosition #270 @276 RefTypeFixedReg <Reg:rcx> BB11 regmask=[rcx] minReg=1>
<RefPosition #271 @276 RefTypeUse <Ivl:53> BB11 regmask=[rcx] minReg=1 last fixed>
<RefPosition #272 @276 RefTypeFixedReg <Reg:rdx> BB11 regmask=[rdx] minReg=1>
<RefPosition #273 @276 RefTypeUse <Ivl:55> BB11 regmask=[rdx] minReg=1 last fixed>
<RefPosition #274 @277 RefTypeKill <Reg:rax> BB11 regmask=[rax] minReg=1>
<RefPosition #275 @277 RefTypeKill <Reg:rcx> BB11 regmask=[rcx] minReg=1>
<RefPosition #276 @277 RefTypeKill <Reg:rdx> BB11 regmask=[rdx] minReg=1>
<RefPosition #277 @277 RefTypeKill <Reg:r8 > BB11 regmask=[r8] minReg=1>
<RefPosition #278 @277 RefTypeKill <Reg:r9 > BB11 regmask=[r9] minReg=1>
<RefPosition #279 @277 RefTypeKill <Reg:r10> BB11 regmask=[r10] minReg=1>
<RefPosition #280 @277 RefTypeKill <Reg:r11> BB11 regmask=[r11] minReg=1>
Interval 56: byref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #281 @277 RefTypeFixedReg <Reg:rax> BB11 regmask=[rax] minReg=1>
<RefPosition #282 @277 RefTypeDef <Ivl:56> CALL BB11 regmask=[rax] minReg=1 fixed>
DefList: { N276.t113. CALL }
N278 ( 24, 16) [000115] DA-XG------- * STORE_LCL_VAR byref V20 tmp11 NA REG NA
<RefPosition #283 @278 RefTypeUse <Ivl:56> BB11 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N280 (???,???) [000244] ------------ * IL_OFFSET void IL offset: 0x71 REG NA
DefList: { }
N282 ( 3, 2) [000116] ------------ * LCL_VAR byref V20 tmp11 NA REG NA
Interval 57: byref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #284 @283 RefTypeDef <Ivl:57> LCL_VAR BB11 regmask=[allIntButFP] minReg=1>
DefList: { N282.t116. LCL_VAR }
N284 ( 7, 5) [000117] *--XG------- * IND ubyte REG NA
<RefPosition #285 @284 RefTypeUse <Ivl:57> BB11 regmask=[allIntButFP] minReg=1 last>
Interval 58: ubyte RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #286 @285 RefTypeDef <Ivl:58> IND BB11 regmask=[allIntButFP] minReg=1>
DefList: { N284.t117. IND }
N286 ( 11, 8) [000119] DA-XG------- * STORE_LCL_VAR int V04 loc3 NA REG NA
<RefPosition #287 @286 RefTypeUse <Ivl:58> BB11 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N288 (???,???) [000245] ------------ * IL_OFFSET void IL offset: 0x73 REG NA
DefList: { }
N290 ( 3, 2) [000121] ------------ * LCL_VAR int V02 loc1 NA REG NA
Interval 59: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #288 @291 RefTypeDef <Ivl:59> LCL_VAR BB11 regmask=[allIntButFP] minReg=1>
DefList: { N290.t121. LCL_VAR }
N292 ( 1, 1) [000122] -c---------- * CNS_INT int 1 REG NA
Contained
DefList: { N290.t121. LCL_VAR }
N294 ( 5, 4) [000123] ------------ * ADD int REG NA
<RefPosition #289 @294 RefTypeUse <Ivl:59> BB11 regmask=[allIntButFP] minReg=1 last>
Interval 60: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #290 @295 RefTypeDef <Ivl:60> ADD BB11 regmask=[allIntButFP] minReg=1>
Assigning related <I60> to <I59>
DefList: { N294.t123. ADD }
N296 ( 3, 2) [000120] ------------ * LCL_VAR byref V00 this NA REG NA
Interval 61: byref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #291 @297 RefTypeDef <Ivl:61> LCL_VAR BB11 regmask=[allIntButFP] minReg=1>
DefList: { N294.t123. ADD; N296.t120. LCL_VAR }
N298 ( 4, 3) [000202] -c---------- * LEA(b+24) byref REG NA
Contained
DefList: { N294.t123. ADD; N296.t120. LCL_VAR }
N300 (???,???) [000246] -A-XG------- * STOREIND int REG NA
<RefPosition #292 @300 RefTypeUse <Ivl:61> BB11 regmask=[allIntButFP] minReg=1 last>
<RefPosition #293 @300 RefTypeUse <Ivl:60> BB11 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N302 (???,???) [000247] ------------ * IL_OFFSET void IL offset: 0x7c REG NA
DefList: { }
N304 ( 3, 2) [000126] ------------ * LCL_VAR int V04 loc3 NA REG NA
Interval 62: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #294 @305 RefTypeDef <Ivl:62> LCL_VAR BB11 regmask=[allIntButFP] minReg=1>
DefList: { N304.t126. LCL_VAR }
N306 ( 7, 5) [000128] DA---------- * STORE_LCL_VAR int V06 loc5 NA REG NA
<RefPosition #295 @306 RefTypeUse <Ivl:62> BB11 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N308 (???,???) [000248] ------------ * IL_OFFSET void IL offset: 0x7f REG NA
DefList: { }
N310 ( 0, 0) [000129] ------------ * NOP void REG NA
NEW BLOCK BB12
Setting BB08 as the predecessor for determining incoming variable registers of BB12
<RefPosition #296 @312 RefTypeBB BB12 regmask=[] minReg=1>
DefList: { }
N314 (???,???) [000249] ------------ * IL_OFFSET void IL offset: 0x81 REG NA
DefList: { }
N316 ( 3, 2) [000204] ------------ * LCL_VAR byref V00 this NA REG NA
Interval 63: byref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #297 @317 RefTypeDef <Ivl:63> LCL_VAR BB12 regmask=[allIntButFP] minReg=1>
DefList: { N316.t204. LCL_VAR }
N318 ( 4, 3) [000205] ---X---N---- * NULLCHECK int REG NA
<RefPosition #298 @318 RefTypeUse <Ivl:63> BB12 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N320 ( 3, 2) [000206] ------------ * LCL_VAR byref V00 this NA REG NA
Interval 64: byref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #299 @321 RefTypeDef <Ivl:64> LCL_VAR BB12 regmask=[allIntButFP] minReg=1>
DefList: { N320.t206. LCL_VAR }
N322 ( 1, 1) [000207] -c---------- * CNS_INT long 64 field offset Fseq[_input] REG NA
Contained
DefList: { N320.t206. LCL_VAR }
N324 ( 5, 4) [000208] ------------ * ADD byref REG NA
<RefPosition #300 @324 RefTypeUse <Ivl:64> BB12 regmask=[allIntButFP] minReg=1 last>
Interval 65: byref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #301 @325 RefTypeDef <Ivl:65> ADD BB12 regmask=[allIntButFP] minReg=1>
Assigning related <I65> to <I64>
DefList: { N324.t208. ADD }
N326 (???,???) [000278] ------------ * PUTARG_REG byref REG rdx
<RefPosition #302 @326 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #303 @326 RefTypeUse <Ivl:65> BB12 regmask=[rdx] minReg=1 last fixed>
Interval 66: byref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #304 @327 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #305 @327 RefTypeDef <Ivl:66> PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed>
DefList: { N326.t278. PUTARG_REG }
N328 ( 2, 10) [000046] H----------- * CNS_INT(h) long 0x7ff93af7cd80 class REG NA
Interval 67: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #306 @329 RefTypeDef <Ivl:67> CNS_INT BB12 regmask=[allIntButFP] minReg=1>
DefList: { N326.t278. PUTARG_REG; N328.t46. CNS_INT }
N330 (???,???) [000279] ------------ * PUTARG_REG long REG rcx
<RefPosition #307 @330 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #308 @330 RefTypeUse <Ivl:67> BB12 regmask=[rcx] minReg=1 last fixed>
Interval 68: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #309 @331 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #310 @331 RefTypeDef <Ivl:68> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed>
DefList: { N326.t278. PUTARG_REG; N330.t279. PUTARG_REG }
N332 ( 25, 24) [000048] --CXG------- * CALL help ref HELPER.CORINFO_HELP_BOX REG NA
<RefPosition #311 @332 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #312 @332 RefTypeUse <Ivl:66> BB12 regmask=[rdx] minReg=1 last fixed>
<RefPosition #313 @332 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #314 @332 RefTypeUse <Ivl:68> BB12 regmask=[rcx] minReg=1 last fixed>
<RefPosition #315 @333 RefTypeKill <Reg:rax> BB12 regmask=[rax] minReg=1>
<RefPosition #316 @333 RefTypeKill <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #317 @333 RefTypeKill <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #318 @333 RefTypeKill <Reg:r8 > BB12 regmask=[r8] minReg=1>
<RefPosition #319 @333 RefTypeKill <Reg:r9 > BB12 regmask=[r9] minReg=1>
<RefPosition #320 @333 RefTypeKill <Reg:r10> BB12 regmask=[r10] minReg=1>
<RefPosition #321 @333 RefTypeKill <Reg:r11> BB12 regmask=[r11] minReg=1>
Interval 69: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #322 @333 RefTypeFixedReg <Reg:rax> BB12 regmask=[rax] minReg=1>
<RefPosition #323 @333 RefTypeDef <Ivl:69> CALL BB12 regmask=[rax] minReg=1 fixed>
DefList: { N332.t48. CALL }
N334 ( 29, 27) [000214] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp18 NA REG NA
<RefPosition #324 @334 RefTypeUse <Ivl:69> BB12 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N336 ( 3, 2) [000215] ------------ * LCL_VAR ref V27 tmp18 NA REG NA
Interval 70: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #325 @337 RefTypeDef <Ivl:70> LCL_VAR BB12 regmask=[allIntButFP] minReg=1>
DefList: { N336.t215. LCL_VAR }
N338 (???,???) [000280] ------------ * PUTARG_REG ref REG rdx
<RefPosition #326 @338 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #327 @338 RefTypeUse <Ivl:70> BB12 regmask=[rdx] minReg=1 last fixed>
Interval 71: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #328 @339 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #329 @339 RefTypeDef <Ivl:71> PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed>
DefList: { N338.t280. PUTARG_REG }
N340 ( 2, 10) [000049] H------N---- * CNS_INT(h) long 0x7ff93b569758 class REG NA
Interval 72: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #330 @341 RefTypeDef <Ivl:72> CNS_INT BB12 regmask=[allIntButFP] minReg=1>
DefList: { N338.t280. PUTARG_REG; N340.t49. CNS_INT }
N342 (???,???) [000281] ------------ * PUTARG_REG long REG rcx
<RefPosition #331 @342 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #332 @342 RefTypeUse <Ivl:72> BB12 regmask=[rcx] minReg=1 last fixed>
Interval 73: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #333 @343 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #334 @343 RefTypeDef <Ivl:73> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed>
DefList: { N338.t280. PUTARG_REG; N342.t281. PUTARG_REG }
N344 ( 51, 46) [000050] --CXG------- * CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS REG NA
<RefPosition #335 @344 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #336 @344 RefTypeUse <Ivl:71> BB12 regmask=[rdx] minReg=1 last fixed>
<RefPosition #337 @344 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #338 @344 RefTypeUse <Ivl:73> BB12 regmask=[rcx] minReg=1 last fixed>
<RefPosition #339 @345 RefTypeKill <Reg:rax> BB12 regmask=[rax] minReg=1>
<RefPosition #340 @345 RefTypeKill <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #341 @345 RefTypeKill <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #342 @345 RefTypeKill <Reg:r8 > BB12 regmask=[r8] minReg=1>
<RefPosition #343 @345 RefTypeKill <Reg:r9 > BB12 regmask=[r9] minReg=1>
<RefPosition #344 @345 RefTypeKill <Reg:r10> BB12 regmask=[r10] minReg=1>
<RefPosition #345 @345 RefTypeKill <Reg:r11> BB12 regmask=[r11] minReg=1>
Interval 74: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #346 @345 RefTypeFixedReg <Reg:rax> BB12 regmask=[rax] minReg=1>
<RefPosition #347 @345 RefTypeDef <Ivl:74> CALL BB12 regmask=[rax] minReg=1 fixed>
DefList: { N344.t50. CALL }
N346 ( 55, 49) [000052] DA-XG------- * STORE_LCL_VAR ref V07 loc6 NA REG NA
<RefPosition #348 @346 RefTypeUse <Ivl:74> BB12 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N348 (???,???) [000250] ------------ * IL_OFFSET void IL offset: 0x93 REG NA
DefList: { }
N350 ( 3, 2) [000053] -c---------- * LCL_VAR ref V07 loc6 NA REG NA
Contained
DefList: { }
N352 ( 1, 1) [000054] -c---------- * CNS_INT ref null REG NA
Contained
DefList: { }
N354 ( 8, 4) [000055] N----------- * NE int REG NA
Interval 75: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #349 @355 RefTypeDef <Ivl:75> NE BB12 regmask=[allIntButFP] minReg=1>
DefList: { N354.t55. NE }
N356 ( 12, 7) [000057] DA---------- * STORE_LCL_VAR int V08 loc7 NA REG NA
<RefPosition #350 @356 RefTypeUse <Ivl:75> BB12 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N358 (???,???) [000251] ------------ * IL_OFFSET void IL offset: 0x9a REG NA
DefList: { }
N360 ( 3, 2) [000058] -c---------- * LCL_VAR int V08 loc7 NA REG NA
Contained
DefList: { }
N362 ( 1, 1) [000059] -c---------- * CNS_INT int 0 REG NA
Contained
DefList: { }
N364 ( 5, 4) [000060] J------N---- * EQ void REG NA
DefList: { }
N366 ( 7, 6) [000061] ------------ * JTRUE void REG NA
NEW BLOCK BB13
Setting BB12 as the predecessor for determining incoming variable registers of BB13
<RefPosition #351 @368 RefTypeBB BB13 regmask=[] minReg=1>
DefList: { }
N370 (???,???) [000252] ------------ * IL_OFFSET void IL offset: 0x9e REG NA
DefList: { }
N372 ( 1, 1) [000072] ------------ * NO_OP void REG NA
DefList: { }
N374 (???,???) [000253] ------------ * IL_OFFSET void IL offset: 0x9f REG NA
DefList: { }
N376 ( 3, 2) [000073] ------------ * LCL_VAR ref V07 loc6 NA REG NA
Interval 76: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #352 @377 RefTypeDef <Ivl:76> LCL_VAR BB13 regmask=[allIntButFP] minReg=1>
DefList: { N376.t73. LCL_VAR }
N378 (???,???) [000282] ------------ * PUTARG_REG ref REG rcx
<RefPosition #353 @378 RefTypeFixedReg <Reg:rcx> BB13 regmask=[rcx] minReg=1>
<RefPosition #354 @378 RefTypeUse <Ivl:76> BB13 regmask=[rcx] minReg=1 last fixed>
Interval 77: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #355 @379 RefTypeFixedReg <Reg:rcx> BB13 regmask=[rcx] minReg=1>
<RefPosition #356 @379 RefTypeDef <Ivl:77> PUTARG_REG BB13 regmask=[rcx] minReg=1 fixed>
DefList: { N378.t282. PUTARG_REG }
N380 ( 3, 2) [000283] ------------ * LCL_VAR ref V07 loc6 NA REG NA
Interval 78: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #357 @381 RefTypeDef <Ivl:78> LCL_VAR BB13 regmask=[allIntButFP] minReg=1>
DefList: { N378.t282. PUTARG_REG; N380.t283. LCL_VAR }
N382 ( 4, 3) [000284] -c---------- * LEA(b+0) byref REG NA
Contained
DefList: { N378.t282. PUTARG_REG; N380.t283. LCL_VAR }
N384 ( 7, 5) [000285] ------------ * IND long REG NA
<RefPosition #358 @384 RefTypeUse <Ivl:78> BB13 regmask=[allIntButFP] minReg=1 last>
Interval 79: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #359 @385 RefTypeDef <Ivl:79> IND BB13 regmask=[allIntButFP] minReg=1>
DefList: { N378.t282. PUTARG_REG; N384.t285. IND }
N386 ( 8, 6) [000286] -c---------- * LEA(b+72) long REG NA
Contained
DefList: { N378.t282. PUTARG_REG; N384.t285. IND }
N388 ( 11, 8) [000287] ------------ * IND long REG NA
<RefPosition #360 @388 RefTypeUse <Ivl:79> BB13 regmask=[allIntButFP] minReg=1 last>
Interval 80: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #361 @389 RefTypeDef <Ivl:80> IND BB13 regmask=[allIntButFP] minReg=1>
DefList: { N378.t282. PUTARG_REG; N388.t287. IND }
N390 ( 12, 9) [000288] -c---------- * LEA(b+56) long REG NA
Contained
DefList: { N378.t282. PUTARG_REG; N388.t287. IND }
N392 ( 15, 11) [000289] -c---------- * IND long REG NA
Contained
DefList: { N378.t282. PUTARG_REG; N388.t287. IND }
N394 ( 23, 11) [000074] --CXG------- * CALLV ind int Hagar.Buffers.ReaderInput.ReadByte REG NA
<RefPosition #362 @394 RefTypeFixedReg <Reg:rcx> BB13 regmask=[rcx] minReg=1>
<RefPosition #363 @394 RefTypeUse <Ivl:77> BB13 regmask=[rcx] minReg=1 last fixed>
<RefPosition #364 @394 RefTypeUse <Ivl:80> BB13 regmask=[allIntButFP] minReg=1 last>
<RefPosition #365 @395 RefTypeKill <Reg:rax> BB13 regmask=[rax] minReg=1>
<RefPosition #366 @395 RefTypeKill <Reg:rcx> BB13 regmask=[rcx] minReg=1>
<RefPosition #367 @395 RefTypeKill <Reg:rdx> BB13 regmask=[rdx] minReg=1>
<RefPosition #368 @395 RefTypeKill <Reg:r8 > BB13 regmask=[r8] minReg=1>
<RefPosition #369 @395 RefTypeKill <Reg:r9 > BB13 regmask=[r9] minReg=1>
<RefPosition #370 @395 RefTypeKill <Reg:r10> BB13 regmask=[r10] minReg=1>
<RefPosition #371 @395 RefTypeKill <Reg:r11> BB13 regmask=[r11] minReg=1>
Interval 81: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #372 @395 RefTypeFixedReg <Reg:rax> BB13 regmask=[rax] minReg=1>
<RefPosition #373 @395 RefTypeDef <Ivl:81> CALL BB13 regmask=[rax] minReg=1 fixed>
DefList: { N394.t74. CALL }
N396 ( 27, 14) [000076] DA-XG------- * STORE_LCL_VAR int V17 tmp8 NA REG NA
<RefPosition #374 @396 RefTypeUse <Ivl:81> BB13 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N398 (???,???) [000254] ------------ * IL_OFFSET void IL offset: 0xa6 REG NA
DefList: { }
N400 ( 3, 2) [000077] ------------ * LCL_VAR int V17 tmp8 NA REG NA
Interval 82: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #375 @401 RefTypeDef <Ivl:82> LCL_VAR BB13 regmask=[allIntButFP] minReg=1>
DefList: { N400.t77. LCL_VAR }
N402 ( 4, 4) [000218] ------------ * CAST int <- ubyte <- int REG NA
<RefPosition #376 @402 RefTypeUse <Ivl:82> BB13 regmask=[allIntButFP] minReg=1 last>
Interval 83: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #377 @403 RefTypeDef <Ivl:83> CAST BB13 regmask=[allIntButFP] minReg=1>
DefList: { N402.t218. CAST }
N404 ( 8, 7) [000079] DA---------- * STORE_LCL_VAR int V06 loc5 NA REG NA
<RefPosition #378 @404 RefTypeUse <Ivl:83> BB13 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N406 (???,???) [000255] ------------ * IL_OFFSET void IL offset: 0xa8 REG NA
DefList: { }
N408 ( 0, 0) [000080] ------------ * NOP void REG NA
NEW BLOCK BB14
Setting BB12 as the predecessor for determining incoming variable registers of BB14
<RefPosition #379 @410 RefTypeBB BB14 regmask=[] minReg=1>
DefList: { }
N412 (???,???) [000256] ------------ * IL_OFFSET void IL offset: 0xaa REG NA
DefList: { }
N414 ( 1, 1) [000062] ------------ * NO_OP void REG NA
DefList: { }
N416 (???,???) [000257] ------------ * IL_OFFSET void IL offset: 0xab REG NA
DefList: { }
N418 ( 14, 5) [000063] --CXG------- * CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].ThrowNotSupportedInput REG NA
<RefPosition #380 @419 RefTypeKill <Reg:rax> BB14 regmask=[rax] minReg=1>
<RefPosition #381 @419 RefTypeKill <Reg:rcx> BB14 regmask=[rcx] minReg=1>
<RefPosition #382 @419 RefTypeKill <Reg:rdx> BB14 regmask=[rdx] minReg=1>
<RefPosition #383 @419 RefTypeKill <Reg:r8 > BB14 regmask=[r8] minReg=1>
<RefPosition #384 @419 RefTypeKill <Reg:r9 > BB14 regmask=[r9] minReg=1>
<RefPosition #385 @419 RefTypeKill <Reg:r10> BB14 regmask=[r10] minReg=1>
<RefPosition #386 @419 RefTypeKill <Reg:r11> BB14 regmask=[r11] minReg=1>
Interval 84: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #387 @419 RefTypeFixedReg <Reg:rax> BB14 regmask=[rax] minReg=1>
<RefPosition #388 @419 RefTypeDef <Ivl:84> CALL BB14 regmask=[rax] minReg=1 fixed>
DefList: { N418.t63. CALL }
N420 ( 18, 8) [000065] DA-XG------- * STORE_LCL_VAR int V16 tmp7 NA REG NA
<RefPosition #389 @420 RefTypeUse <Ivl:84> BB14 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N422 (???,???) [000258] ------------ * IL_OFFSET void IL offset: 0xb0 REG NA
DefList: { }
N424 ( 3, 2) [000066] ------------ * LCL_VAR int V16 tmp7 NA REG NA
Interval 85: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #390 @425 RefTypeDef <Ivl:85> LCL_VAR BB14 regmask=[allIntButFP] minReg=1>
DefList: { N424.t66. LCL_VAR }
N426 ( 4, 4) [000219] ------------ * CAST int <- ubyte <- int REG NA
<RefPosition #391 @426 RefTypeUse <Ivl:85> BB14 regmask=[allIntButFP] minReg=1 last>
Interval 86: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #392 @427 RefTypeDef <Ivl:86> CAST BB14 regmask=[allIntButFP] minReg=1>
DefList: { N426.t219. CAST }
N428 ( 8, 7) [000068] DA---------- * STORE_LCL_VAR int V06 loc5 NA REG NA
<RefPosition #393 @428 RefTypeUse <Ivl:86> BB14 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N430 (???,???) [000259] ------------ * IL_OFFSET void IL offset: 0xb2 REG NA
DefList: { }
N432 ( 0, 0) [000069] ------------ * NOP void REG NA
NEW BLOCK BB15
Setting BB10 as the predecessor for determining incoming variable registers of BB15
<RefPosition #394 @434 RefTypeBB BB15 regmask=[] minReg=1>
DefList: { }
N436 (???,???) [000260] ------------ * IL_OFFSET void IL offset: 0xb4 REG NA
DefList: { }
N438 ( 3, 2) [000070] ------------ * LCL_VAR int V06 loc5 NA REG NA
Interval 87: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #395 @439 RefTypeDef <Ivl:87> LCL_VAR BB15 regmask=[allIntButFP] minReg=1>
DefList: { N438.t70. LCL_VAR }
N440 ( 4, 3) [000071] ------------ * RETURN int REG NA
<RefPosition #396 @440 RefTypeFixedReg <Reg:rax> BB15 regmask=[rax] minReg=1>
<RefPosition #397 @440 RefTypeUse <Ivl:87> BB15 regmask=[rax] minReg=1 last fixed>
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: long (constant) RefPositions {#12@31 #14@32} physReg:NA Preferences=[rcx]
Interval 1: long RefPositions {#16@33 #18@34} physReg:NA Preferences=[rcx]
Interval 2: ref RefPositions {#27@35 #28@36} physReg:NA Preferences=[rax]
Interval 3: ref RefPositions {#29@39 #31@40} physReg:NA Preferences=[rcx]
Interval 4: ref RefPositions {#33@41 #35@42} physReg:NA Preferences=[rcx]
Interval 5: ref RefPositions {#44@43 #45@44} physReg:NA Preferences=[rax]
Interval 6: long (constant) RefPositions {#46@49 #48@50} physReg:NA Preferences=[rcx]
Interval 7: long RefPositions {#50@51 #52@52} physReg:NA Preferences=[rcx]
Interval 8: ref RefPositions {#61@53 #62@54} physReg:NA Preferences=[rax]
Interval 9: ref RefPositions {#63@57 #65@58} physReg:NA Preferences=[rcx]
Interval 10: ref RefPositions {#67@59 #69@60} physReg:NA Preferences=[rcx]
Interval 11: ref RefPositions {#78@61 #79@62} physReg:NA Preferences=[rax]
Interval 12: ref RefPositions {#80@67 #82@68} physReg:NA Preferences=[rcx]
Interval 13: ref RefPositions {#84@69 #91@74} physReg:NA Preferences=[rcx]
Interval 14: ref RefPositions {#85@71 #87@72} physReg:NA Preferences=[rdx]
Interval 15: ref RefPositions {#89@73 #93@74} physReg:NA Preferences=[rdx]
Interval 16: int RefPositions {#102@75 #103@76} physReg:NA Preferences=[rax]
Interval 17: long (constant) RefPositions {#105@93 #107@94} physReg:NA Preferences=[rcx]
Interval 18: long RefPositions {#109@95 #111@96} physReg:NA Preferences=[rcx]
Interval 19: ref RefPositions {#120@97 #121@98} physReg:NA Preferences=[rax]
Interval 20: ref RefPositions {#122@101 #124@102} physReg:NA Preferences=[rcx]
Interval 21: ref RefPositions {#126@103 #128@104} physReg:NA Preferences=[rcx]
Interval 22: ref RefPositions {#137@105 #138@106} physReg:NA Preferences=[rax]
Interval 23: long (constant) RefPositions {#139@111 #141@112} physReg:NA Preferences=[rcx]
Interval 24: long RefPositions {#143@113 #145@114} physReg:NA Preferences=[rcx]
Interval 25: ref RefPositions {#154@115 #155@116} physReg:NA Preferences=[rax]
Interval 26: ref RefPositions {#156@119 #158@120} physReg:NA Preferences=[rcx]
Interval 27: ref RefPositions {#160@121 #162@122} physReg:NA Preferences=[rcx]
Interval 28: ref RefPositions {#171@123 #172@124} physReg:NA Preferences=[rax]
Interval 29: ref RefPositions {#173@129 #175@130} physReg:NA Preferences=[rcx]
Interval 30: ref RefPositions {#177@131 #184@136} physReg:NA Preferences=[rcx]
Interval 31: ref RefPositions {#178@133 #180@134} physReg:NA Preferences=[rdx]
Interval 32: ref RefPositions {#182@135 #186@136} physReg:NA Preferences=[rdx]
Interval 33: int RefPositions {#195@137 #196@138} physReg:NA Preferences=[rax]
Interval 34: int RefPositions {#197@145 #198@146} physReg:NA Preferences=[allIntButFP]
Interval 35: int RefPositions {#201@159 #202@160} physReg:NA Preferences=[allIntButFP]
Interval 36: int RefPositions {#203@161 #204@162} physReg:NA Preferences=[allIntButFP]
Interval 37: byref RefPositions {#206@183 #207@186} physReg:NA Preferences=[allIntButFP]
Interval 38: int RefPositions {#208@187 #209@188} physReg:NA Preferences=[allIntButFP]
Interval 39: byref RefPositions {#210@193 #212@200} physReg:NA Preferences=[allIntButFP]
Interval 40: float (INTERNAL) RefPositions {#211@200 #213@200} physReg:NA Preferences=[mm0-mm5]
Interval 41: int RefPositions {#214@205 #215@206} physReg:NA Preferences=[allIntButFP]
Interval 42: byref RefPositions {#216@209 #218@210} physReg:NA Preferences=[rcx]
Interval 43: byref RefPositions {#220@211 #222@212} physReg:NA Preferences=[rcx]
Interval 44: int RefPositions {#231@213 #232@214} physReg:NA Preferences=[rax]
Interval 45: int RefPositions {#233@219 #234@222} physReg:NA Preferences=[allIntButFP]
Interval 46: int RefPositions {#235@223 #236@224} physReg:NA Preferences=[allIntButFP]
Interval 47: byref RefPositions {#238@245 #240@246} physReg:NA Preferences=[rcx]
Interval 48: byref RefPositions {#242@247 #244@248} physReg:NA Preferences=[rcx]
Interval 49: int RefPositions {#253@249 #254@250} physReg:NA Preferences=[rax]
Interval 50: int RefPositions {#255@255 #256@256} physReg:NA Preferences=[allIntButFP]
Interval 51: int RefPositions {#257@257 #258@258} physReg:NA Preferences=[allIntButFP]
Interval 52: byref RefPositions {#260@269 #262@270} physReg:NA Preferences=[rcx]
Interval 53: byref RefPositions {#264@271 #271@276} physReg:NA Preferences=[rcx]
Interval 54: int RefPositions {#265@273 #267@274} physReg:NA Preferences=[rdx]
Interval 55: int RefPositions {#269@275 #273@276} physReg:NA Preferences=[rdx]
Interval 56: byref RefPositions {#282@277 #283@278} physReg:NA Preferences=[rax]
Interval 57: byref RefPositions {#284@283 #285@284} physReg:NA Preferences=[allIntButFP]
Interval 58: ubyte RefPositions {#286@285 #287@286} physReg:NA Preferences=[allIntButFP]
Interval 59: int RefPositions {#288@291 #289@294} physReg:NA Preferences=[allIntButFP] RelatedInterval <I60>
Interval 60: int RefPositions {#290@295 #293@300} physReg:NA Preferences=[allIntButFP]
Interval 61: byref RefPositions {#291@297 #292@300} physReg:NA Preferences=[allIntButFP]
Interval 62: int RefPositions {#294@305 #295@306} physReg:NA Preferences=[allIntButFP]
Interval 63: byref RefPositions {#297@317 #298@318} physReg:NA Preferences=[allIntButFP]
Interval 64: byref RefPositions {#299@321 #300@324} physReg:NA Preferences=[allIntButFP] RelatedInterval <I65>
Interval 65: byref RefPositions {#301@325 #303@326} physReg:NA Preferences=[rdx]
Interval 66: byref RefPositions {#305@327 #312@332} physReg:NA Preferences=[rdx]
Interval 67: long (constant) RefPositions {#306@329 #308@330} physReg:NA Preferences=[rcx]
Interval 68: long RefPositions {#310@331 #314@332} physReg:NA Preferences=[rcx]
Interval 69: ref RefPositions {#323@333 #324@334} physReg:NA Preferences=[rax]
Interval 70: ref RefPositions {#325@337 #327@338} physReg:NA Preferences=[rdx]
Interval 71: ref RefPositions {#329@339 #336@344} physReg:NA Preferences=[rdx]
Interval 72: long (constant) RefPositions {#330@341 #332@342} physReg:NA Preferences=[rcx]
Interval 73: long RefPositions {#334@343 #338@344} physReg:NA Preferences=[rcx]
Interval 74: ref RefPositions {#347@345 #348@346} physReg:NA Preferences=[rax]
Interval 75: int RefPositions {#349@355 #350@356} physReg:NA Preferences=[allIntButFP]
Interval 76: ref RefPositions {#352@377 #354@378} physReg:NA Preferences=[rcx]
Interval 77: ref RefPositions {#356@379 #363@394} physReg:NA Preferences=[rcx]
Interval 78: ref RefPositions {#357@381 #358@384} physReg:NA Preferences=[allIntButFP]
Interval 79: long RefPositions {#359@385 #360@388} physReg:NA Preferences=[allIntButFP]
Interval 80: long RefPositions {#361@389 #364@394} physReg:NA Preferences=[allIntButFP]
Interval 81: int RefPositions {#373@395 #374@396} physReg:NA Preferences=[rax]
Interval 82: int RefPositions {#375@401 #376@402} physReg:NA Preferences=[allIntButFP]
Interval 83: int RefPositions {#377@403 #378@404} physReg:NA Preferences=[allIntButFP]
Interval 84: int RefPositions {#388@419 #389@420} physReg:NA Preferences=[rax]
Interval 85: int RefPositions {#390@425 #391@426} physReg:NA Preferences=[allIntButFP]
Interval 86: int RefPositions {#392@427 #393@428} physReg:NA Preferences=[allIntButFP]
Interval 87: int RefPositions {#395@439 #397@440} physReg:NA Preferences=[rax]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @4 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #2 @16 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #3 @19 RefTypeKill <Reg:rax> BB03 regmask=[rax] minReg=1 last>
<RefPosition #4 @19 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] minReg=1 last>
<RefPosition #5 @19 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] minReg=1 last>
<RefPosition #6 @19 RefTypeKill <Reg:r8 > BB03 regmask=[r8] minReg=1 last>
<RefPosition #7 @19 RefTypeKill <Reg:r9 > BB03 regmask=[r9] minReg=1 last>
<RefPosition #8 @19 RefTypeKill <Reg:r10> BB03 regmask=[r10] minReg=1 last>
<RefPosition #9 @19 RefTypeKill <Reg:r11> BB03 regmask=[r11] minReg=1 last>
<RefPosition #10 @20 RefTypeBB BB04 regmask=[] minReg=1>
<RefPosition #11 @22 RefTypeBB BB05 regmask=[] minReg=1>
<RefPosition #12 @31 RefTypeDef <Ivl:0> CNS_INT BB05 regmask=[rcx] minReg=1>
<RefPosition #13 @32 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #14 @32 RefTypeUse <Ivl:0> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #15 @33 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #16 @33 RefTypeDef <Ivl:1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
<RefPosition #17 @34 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #18 @34 RefTypeUse <Ivl:1> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #19 @35 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
<RefPosition #20 @35 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #21 @35 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
<RefPosition #22 @35 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
<RefPosition #23 @35 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
<RefPosition #24 @35 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
<RefPosition #25 @35 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
<RefPosition #26 @35 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #27 @35 RefTypeDef <Ivl:2> CALL BB05 regmask=[rax] minReg=1 fixed>
<RefPosition #28 @36 RefTypeUse <Ivl:2> BB05 regmask=[allIntButFP] minReg=1 last>
<RefPosition #29 @39 RefTypeDef <Ivl:3> LCL_FLD BB05 regmask=[rcx] minReg=1>
<RefPosition #30 @40 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #31 @40 RefTypeUse <Ivl:3> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #32 @41 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #33 @41 RefTypeDef <Ivl:4> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
<RefPosition #34 @42 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #35 @42 RefTypeUse <Ivl:4> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #36 @43 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
<RefPosition #37 @43 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #38 @43 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
<RefPosition #39 @43 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
<RefPosition #40 @43 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
<RefPosition #41 @43 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
<RefPosition #42 @43 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
<RefPosition #43 @43 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #44 @43 RefTypeDef <Ivl:5> CALL BB05 regmask=[rax] minReg=1 fixed>
<RefPosition #45 @44 RefTypeUse <Ivl:5> BB05 regmask=[allIntButFP] minReg=1 last>
<RefPosition #46 @49 RefTypeDef <Ivl:6> CNS_INT BB05 regmask=[rcx] minReg=1>
<RefPosition #47 @50 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #48 @50 RefTypeUse <Ivl:6> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #49 @51 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #50 @51 RefTypeDef <Ivl:7> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
<RefPosition #51 @52 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #52 @52 RefTypeUse <Ivl:7> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #53 @53 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
<RefPosition #54 @53 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #55 @53 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
<RefPosition #56 @53 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
<RefPosition #57 @53 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
<RefPosition #58 @53 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
<RefPosition #59 @53 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
<RefPosition #60 @53 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #61 @53 RefTypeDef <Ivl:8> CALL BB05 regmask=[rax] minReg=1 fixed>
<RefPosition #62 @54 RefTypeUse <Ivl:8> BB05 regmask=[allIntButFP] minReg=1 last>
<RefPosition #63 @57 RefTypeDef <Ivl:9> LCL_FLD BB05 regmask=[rcx] minReg=1>
<RefPosition #64 @58 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #65 @58 RefTypeUse <Ivl:9> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #66 @59 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #67 @59 RefTypeDef <Ivl:10> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
<RefPosition #68 @60 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #69 @60 RefTypeUse <Ivl:10> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #70 @61 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
<RefPosition #71 @61 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #72 @61 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
<RefPosition #73 @61 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
<RefPosition #74 @61 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
<RefPosition #75 @61 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
<RefPosition #76 @61 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
<RefPosition #77 @61 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #78 @61 RefTypeDef <Ivl:11> CALL BB05 regmask=[rax] minReg=1 fixed>
<RefPosition #79 @62 RefTypeUse <Ivl:11> BB05 regmask=[allIntButFP] minReg=1 last>
<RefPosition #80 @67 RefTypeDef <Ivl:12> LCL_VAR BB05 regmask=[rcx] minReg=1>
<RefPosition #81 @68 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #82 @68 RefTypeUse <Ivl:12> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #83 @69 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #84 @69 RefTypeDef <Ivl:13> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
<RefPosition #85 @71 RefTypeDef <Ivl:14> LCL_VAR BB05 regmask=[rdx] minReg=1>
<RefPosition #86 @72 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #87 @72 RefTypeUse <Ivl:14> BB05 regmask=[rdx] minReg=1 last fixed>
<RefPosition #88 @73 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #89 @73 RefTypeDef <Ivl:15> PUTARG_REG BB05 regmask=[rdx] minReg=1 fixed>
<RefPosition #90 @74 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #91 @74 RefTypeUse <Ivl:13> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #92 @74 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #93 @74 RefTypeUse <Ivl:15> BB05 regmask=[rdx] minReg=1 last fixed>
<RefPosition #94 @75 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
<RefPosition #95 @75 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #96 @75 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
<RefPosition #97 @75 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
<RefPosition #98 @75 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
<RefPosition #99 @75 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
<RefPosition #100 @75 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
<RefPosition #101 @75 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #102 @75 RefTypeDef <Ivl:16> CALL BB05 regmask=[rax] minReg=1 fixed>
<RefPosition #103 @76 RefTypeUse <Ivl:16> BB05 regmask=[allIntButFP] minReg=1 last>
<RefPosition #104 @88 RefTypeBB BB06 regmask=[] minReg=1>
<RefPosition #105 @93 RefTypeDef <Ivl:17> CNS_INT BB06 regmask=[rcx] minReg=1>
<RefPosition #106 @94 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #107 @94 RefTypeUse <Ivl:17> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #108 @95 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #109 @95 RefTypeDef <Ivl:18> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
<RefPosition #110 @96 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #111 @96 RefTypeUse <Ivl:18> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #112 @97 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1 last>
<RefPosition #113 @97 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #114 @97 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1 last>
<RefPosition #115 @97 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1 last>
<RefPosition #116 @97 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1 last>
<RefPosition #117 @97 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1 last>
<RefPosition #118 @97 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1 last>
<RefPosition #119 @97 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #120 @97 RefTypeDef <Ivl:19> CALL BB06 regmask=[rax] minReg=1 fixed>
<RefPosition #121 @98 RefTypeUse <Ivl:19> BB06 regmask=[allIntButFP] minReg=1 last>
<RefPosition #122 @101 RefTypeDef <Ivl:20> LCL_FLD BB06 regmask=[rcx] minReg=1>
<RefPosition #123 @102 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #124 @102 RefTypeUse <Ivl:20> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #125 @103 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #126 @103 RefTypeDef <Ivl:21> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
<RefPosition #127 @104 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #128 @104 RefTypeUse <Ivl:21> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #129 @105 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1 last>
<RefPosition #130 @105 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #131 @105 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1 last>
<RefPosition #132 @105 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1 last>
<RefPosition #133 @105 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1 last>
<RefPosition #134 @105 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1 last>
<RefPosition #135 @105 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1 last>
<RefPosition #136 @105 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #137 @105 RefTypeDef <Ivl:22> CALL BB06 regmask=[rax] minReg=1 fixed>
<RefPosition #138 @106 RefTypeUse <Ivl:22> BB06 regmask=[allIntButFP] minReg=1 last>
<RefPosition #139 @111 RefTypeDef <Ivl:23> CNS_INT BB06 regmask=[rcx] minReg=1>
<RefPosition #140 @112 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #141 @112 RefTypeUse <Ivl:23> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #142 @113 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #143 @113 RefTypeDef <Ivl:24> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
<RefPosition #144 @114 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #145 @114 RefTypeUse <Ivl:24> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #146 @115 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1 last>
<RefPosition #147 @115 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #148 @115 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1 last>
<RefPosition #149 @115 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1 last>
<RefPosition #150 @115 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1 last>
<RefPosition #151 @115 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1 last>
<RefPosition #152 @115 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1 last>
<RefPosition #153 @115 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #154 @115 RefTypeDef <Ivl:25> CALL BB06 regmask=[rax] minReg=1 fixed>
<RefPosition #155 @116 RefTypeUse <Ivl:25> BB06 regmask=[allIntButFP] minReg=1 last>
<RefPosition #156 @119 RefTypeDef <Ivl:26> LCL_FLD BB06 regmask=[rcx] minReg=1>
<RefPosition #157 @120 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #158 @120 RefTypeUse <Ivl:26> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #159 @121 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #160 @121 RefTypeDef <Ivl:27> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
<RefPosition #161 @122 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #162 @122 RefTypeUse <Ivl:27> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #163 @123 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1 last>
<RefPosition #164 @123 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #165 @123 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1 last>
<RefPosition #166 @123 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1 last>
<RefPosition #167 @123 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1 last>
<RefPosition #168 @123 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1 last>
<RefPosition #169 @123 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1 last>
<RefPosition #170 @123 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #171 @123 RefTypeDef <Ivl:28> CALL BB06 regmask=[rax] minReg=1 fixed>
<RefPosition #172 @124 RefTypeUse <Ivl:28> BB06 regmask=[allIntButFP] minReg=1 last>
<RefPosition #173 @129 RefTypeDef <Ivl:29> LCL_VAR BB06 regmask=[rcx] minReg=1>
<RefPosition #174 @130 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #175 @130 RefTypeUse <Ivl:29> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #176 @131 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #177 @131 RefTypeDef <Ivl:30> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
<RefPosition #178 @133 RefTypeDef <Ivl:31> LCL_VAR BB06 regmask=[rdx] minReg=1>
<RefPosition #179 @134 RefTypeFixedReg <Reg:rdx> BB06 regmask=[rdx] minReg=1>
<RefPosition #180 @134 RefTypeUse <Ivl:31> BB06 regmask=[rdx] minReg=1 last fixed>
<RefPosition #181 @135 RefTypeFixedReg <Reg:rdx> BB06 regmask=[rdx] minReg=1>
<RefPosition #182 @135 RefTypeDef <Ivl:32> PUTARG_REG BB06 regmask=[rdx] minReg=1 fixed>
<RefPosition #183 @136 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #184 @136 RefTypeUse <Ivl:30> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #185 @136 RefTypeFixedReg <Reg:rdx> BB06 regmask=[rdx] minReg=1>
<RefPosition #186 @136 RefTypeUse <Ivl:32> BB06 regmask=[rdx] minReg=1 last fixed>
<RefPosition #187 @137 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1 last>
<RefPosition #188 @137 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #189 @137 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1 last>
<RefPosition #190 @137 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1 last>
<RefPosition #191 @137 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1 last>
<RefPosition #192 @137 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1 last>
<RefPosition #193 @137 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1 last>
<RefPosition #194 @137 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #195 @137 RefTypeDef <Ivl:33> CALL BB06 regmask=[rax] minReg=1 fixed>
<RefPosition #196 @138 RefTypeUse <Ivl:33> BB06 regmask=[allIntButFP] minReg=1 last>
<RefPosition #197 @145 RefTypeDef <Ivl:34> LCL_VAR BB06 regmask=[allIntButFP] minReg=1>
<RefPosition #198 @146 RefTypeUse <Ivl:34> BB06 regmask=[allIntButFP] minReg=1 last>
<RefPosition #199 @148 RefTypeBB BB07 regmask=[] minReg=1>
<RefPosition #200 @156 RefTypeBB BB08 regmask=[] minReg=1>
<RefPosition #201 @159 RefTypeDef <Ivl:35> LCL_VAR BB08 regmask=[allIntButFP] minReg=1>
<RefPosition #202 @160 RefTypeUse <Ivl:35> BB08 regmask=[allIntButFP] minReg=1 last>
<RefPosition #203 @161 RefTypeDef <Ivl:36> CAST BB08 regmask=[allIntButFP] minReg=1>
<RefPosition #204 @162 RefTypeUse <Ivl:36> BB08 regmask=[allIntButFP] minReg=1 last>
<RefPosition #205 @174 RefTypeBB BB09 regmask=[] minReg=1>
<RefPosition #206 @183 RefTypeDef <Ivl:37> LCL_VAR BB09 regmask=[allIntButFP] minReg=1>
<RefPosition #207 @186 RefTypeUse <Ivl:37> BB09 regmask=[allIntButFP] minReg=1 last>
<RefPosition #208 @187 RefTypeDef <Ivl:38> IND BB09 regmask=[allIntButFP] minReg=1>
<RefPosition #209 @188 RefTypeUse <Ivl:38> BB09 regmask=[allIntButFP] minReg=1 last>
<RefPosition #210 @193 RefTypeDef <Ivl:39> LCL_VAR BB09 regmask=[allIntButFP] minReg=1>
<RefPosition #211 @200 RefTypeDef <Ivl:40 internal> STORE_BLK BB09 regmask=[mm0-mm5] minReg=1>
<RefPosition #212 @200 RefTypeUse <Ivl:39> BB09 regmask=[allIntButFP] minReg=1 last>
<RefPosition #213 @200 RefTypeUse <Ivl:40 internal> STORE_BLK BB09 regmask=[mm0-mm5] minReg=1 last>
<RefPosition #214 @205 RefTypeDef <Ivl:41> LCL_VAR BB09 regmask=[allIntButFP] minReg=1>
<RefPosition #215 @206 RefTypeUse <Ivl:41> BB09 regmask=[allIntButFP] minReg=1 last>
<RefPosition #216 @209 RefTypeDef <Ivl:42> LCL_VAR_ADDR BB09 regmask=[rcx] minReg=1>
<RefPosition #217 @210 RefTypeFixedReg <Reg:rcx> BB09 regmask=[rcx] minReg=1>
<RefPosition #218 @210 RefTypeUse <Ivl:42> BB09 regmask=[rcx] minReg=1 last fixed>
<RefPosition #219 @211 RefTypeFixedReg <Reg:rcx> BB09 regmask=[rcx] minReg=1>
<RefPosition #220 @211 RefTypeDef <Ivl:43> PUTARG_REG BB09 regmask=[rcx] minReg=1 fixed>
<RefPosition #221 @212 RefTypeFixedReg <Reg:rcx> BB09 regmask=[rcx] minReg=1>
<RefPosition #222 @212 RefTypeUse <Ivl:43> BB09 regmask=[rcx] minReg=1 last fixed>
<RefPosition #223 @213 RefTypeKill <Reg:rax> BB09 regmask=[rax] minReg=1 last>
<RefPosition #224 @213 RefTypeKill <Reg:rcx> BB09 regmask=[rcx] minReg=1 last>
<RefPosition #225 @213 RefTypeKill <Reg:rdx> BB09 regmask=[rdx] minReg=1 last>
<RefPosition #226 @213 RefTypeKill <Reg:r8 > BB09 regmask=[r8] minReg=1 last>
<RefPosition #227 @213 RefTypeKill <Reg:r9 > BB09 regmask=[r9] minReg=1 last>
<RefPosition #228 @213 RefTypeKill <Reg:r10> BB09 regmask=[r10] minReg=1 last>
<RefPosition #229 @213 RefTypeKill <Reg:r11> BB09 regmask=[r11] minReg=1 last>
<RefPosition #230 @213 RefTypeFixedReg <Reg:rax> BB09 regmask=[rax] minReg=1>
<RefPosition #231 @213 RefTypeDef <Ivl:44> CALL BB09 regmask=[rax] minReg=1 fixed>
<RefPosition #232 @214 RefTypeUse <Ivl:44> BB09 regmask=[allIntButFP] minReg=1 last>
<RefPosition #233 @219 RefTypeDef <Ivl:45> LCL_VAR BB09 regmask=[allIntButFP] minReg=1>
<RefPosition #234 @222 RefTypeUse <Ivl:45> BB09 regmask=[allIntButFP] minReg=1 last>
<RefPosition #235 @223 RefTypeDef <Ivl:46> GE BB09 regmask=[allIntButFP] minReg=1>
<RefPosition #236 @224 RefTypeUse <Ivl:46> BB09 regmask=[allIntButFP] minReg=1 last>
<RefPosition #237 @236 RefTypeBB BB10 regmask=[] minReg=1>
<RefPosition #238 @245 RefTypeDef <Ivl:47> LCL_VAR BB10 regmask=[rcx] minReg=1>
<RefPosition #239 @246 RefTypeFixedReg <Reg:rcx> BB10 regmask=[rcx] minReg=1>
<RefPosition #240 @246 RefTypeUse <Ivl:47> BB10 regmask=[rcx] minReg=1 last fixed>
<RefPosition #241 @247 RefTypeFixedReg <Reg:rcx> BB10 regmask=[rcx] minReg=1>
<RefPosition #242 @247 RefTypeDef <Ivl:48> PUTARG_REG BB10 regmask=[rcx] minReg=1 fixed>
<RefPosition #243 @248 RefTypeFixedReg <Reg:rcx> BB10 regmask=[rcx] minReg=1>
<RefPosition #244 @248 RefTypeUse <Ivl:48> BB10 regmask=[rcx] minReg=1 last fixed>
<RefPosition #245 @249 RefTypeKill <Reg:rax> BB10 regmask=[rax] minReg=1 last>
<RefPosition #246 @249 RefTypeKill <Reg:rcx> BB10 regmask=[rcx] minReg=1 last>
<RefPosition #247 @249 RefTypeKill <Reg:rdx> BB10 regmask=[rdx] minReg=1 last>
<RefPosition #248 @249 RefTypeKill <Reg:r8 > BB10 regmask=[r8] minReg=1 last>
<RefPosition #249 @249 RefTypeKill <Reg:r9 > BB10 regmask=[r9] minReg=1 last>
<RefPosition #250 @249 RefTypeKill <Reg:r10> BB10 regmask=[r10] minReg=1 last>
<RefPosition #251 @249 RefTypeKill <Reg:r11> BB10 regmask=[r11] minReg=1 last>
<RefPosition #252 @249 RefTypeFixedReg <Reg:rax> BB10 regmask=[rax] minReg=1>
<RefPosition #253 @249 RefTypeDef <Ivl:49> CALL BB10 regmask=[rax] minReg=1 fixed>
<RefPosition #254 @250 RefTypeUse <Ivl:49> BB10 regmask=[allIntButFP] minReg=1 last>
<RefPosition #255 @255 RefTypeDef <Ivl:50> LCL_VAR BB10 regmask=[allIntButFP] minReg=1>
<RefPosition #256 @256 RefTypeUse <Ivl:50> BB10 regmask=[allIntButFP] minReg=1 last>
<RefPosition #257 @257 RefTypeDef <Ivl:51> CAST BB10 regmask=[allIntButFP] minReg=1>
<RefPosition #258 @258 RefTypeUse <Ivl:51> BB10 regmask=[allIntButFP] minReg=1 last>
<RefPosition #259 @264 RefTypeBB BB11 regmask=[] minReg=1>
<RefPosition #260 @269 RefTypeDef <Ivl:52> LCL_VAR_ADDR BB11 regmask=[rcx] minReg=1>
<RefPosition #261 @270 RefTypeFixedReg <Reg:rcx> BB11 regmask=[rcx] minReg=1>
<RefPosition #262 @270 RefTypeUse <Ivl:52> BB11 regmask=[rcx] minReg=1 last fixed>
<RefPosition #263 @271 RefTypeFixedReg <Reg:rcx> BB11 regmask=[rcx] minReg=1>
<RefPosition #264 @271 RefTypeDef <Ivl:53> PUTARG_REG BB11 regmask=[rcx] minReg=1 fixed>
<RefPosition #265 @273 RefTypeDef <Ivl:54> LCL_VAR BB11 regmask=[rdx] minReg=1>
<RefPosition #266 @274 RefTypeFixedReg <Reg:rdx> BB11 regmask=[rdx] minReg=1>
<RefPosition #267 @274 RefTypeUse <Ivl:54> BB11 regmask=[rdx] minReg=1 last fixed>
<RefPosition #268 @275 RefTypeFixedReg <Reg:rdx> BB11 regmask=[rdx] minReg=1>
<RefPosition #269 @275 RefTypeDef <Ivl:55> PUTARG_REG BB11 regmask=[rdx] minReg=1 fixed>
<RefPosition #270 @276 RefTypeFixedReg <Reg:rcx> BB11 regmask=[rcx] minReg=1>
<RefPosition #271 @276 RefTypeUse <Ivl:53> BB11 regmask=[rcx] minReg=1 last fixed>
<RefPosition #272 @276 RefTypeFixedReg <Reg:rdx> BB11 regmask=[rdx] minReg=1>
<RefPosition #273 @276 RefTypeUse <Ivl:55> BB11 regmask=[rdx] minReg=1 last fixed>
<RefPosition #274 @277 RefTypeKill <Reg:rax> BB11 regmask=[rax] minReg=1 last>
<RefPosition #275 @277 RefTypeKill <Reg:rcx> BB11 regmask=[rcx] minReg=1 last>
<RefPosition #276 @277 RefTypeKill <Reg:rdx> BB11 regmask=[rdx] minReg=1 last>
<RefPosition #277 @277 RefTypeKill <Reg:r8 > BB11 regmask=[r8] minReg=1 last>
<RefPosition #278 @277 RefTypeKill <Reg:r9 > BB11 regmask=[r9] minReg=1 last>
<RefPosition #279 @277 RefTypeKill <Reg:r10> BB11 regmask=[r10] minReg=1 last>
<RefPosition #280 @277 RefTypeKill <Reg:r11> BB11 regmask=[r11] minReg=1 last>
<RefPosition #281 @277 RefTypeFixedReg <Reg:rax> BB11 regmask=[rax] minReg=1>
<RefPosition #282 @277 RefTypeDef <Ivl:56> CALL BB11 regmask=[rax] minReg=1 fixed>
<RefPosition #283 @278 RefTypeUse <Ivl:56> BB11 regmask=[allIntButFP] minReg=1 last>
<RefPosition #284 @283 RefTypeDef <Ivl:57> LCL_VAR BB11 regmask=[allIntButFP] minReg=1>
<RefPosition #285 @284 RefTypeUse <Ivl:57> BB11 regmask=[allIntButFP] minReg=1 last>
<RefPosition #286 @285 RefTypeDef <Ivl:58> IND BB11 regmask=[allIntButFP] minReg=1>
<RefPosition #287 @286 RefTypeUse <Ivl:58> BB11 regmask=[allIntButFP] minReg=1 last>
<RefPosition #288 @291 RefTypeDef <Ivl:59> LCL_VAR BB11 regmask=[allIntButFP] minReg=1>
<RefPosition #289 @294 RefTypeUse <Ivl:59> BB11 regmask=[allIntButFP] minReg=1 last>
<RefPosition #290 @295 RefTypeDef <Ivl:60> ADD BB11 regmask=[allIntButFP] minReg=1>
<RefPosition #291 @297 RefTypeDef <Ivl:61> LCL_VAR BB11 regmask=[allIntButFP] minReg=1>
<RefPosition #292 @300 RefTypeUse <Ivl:61> BB11 regmask=[allIntButFP] minReg=1 last>
<RefPosition #293 @300 RefTypeUse <Ivl:60> BB11 regmask=[allIntButFP] minReg=1 last>
<RefPosition #294 @305 RefTypeDef <Ivl:62> LCL_VAR BB11 regmask=[allIntButFP] minReg=1>
<RefPosition #295 @306 RefTypeUse <Ivl:62> BB11 regmask=[allIntButFP] minReg=1 last>
<RefPosition #296 @312 RefTypeBB BB12 regmask=[] minReg=1>
<RefPosition #297 @317 RefTypeDef <Ivl:63> LCL_VAR BB12 regmask=[allIntButFP] minReg=1>
<RefPosition #298 @318 RefTypeUse <Ivl:63> BB12 regmask=[allIntButFP] minReg=1 last>
<RefPosition #299 @321 RefTypeDef <Ivl:64> LCL_VAR BB12 regmask=[allIntButFP] minReg=1>
<RefPosition #300 @324 RefTypeUse <Ivl:64> BB12 regmask=[allIntButFP] minReg=1 last>
<RefPosition #301 @325 RefTypeDef <Ivl:65> ADD BB12 regmask=[rdx] minReg=1>
<RefPosition #302 @326 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #303 @326 RefTypeUse <Ivl:65> BB12 regmask=[rdx] minReg=1 last fixed>
<RefPosition #304 @327 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #305 @327 RefTypeDef <Ivl:66> PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed>
<RefPosition #306 @329 RefTypeDef <Ivl:67> CNS_INT BB12 regmask=[rcx] minReg=1>
<RefPosition #307 @330 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #308 @330 RefTypeUse <Ivl:67> BB12 regmask=[rcx] minReg=1 last fixed>
<RefPosition #309 @331 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #310 @331 RefTypeDef <Ivl:68> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed>
<RefPosition #311 @332 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #312 @332 RefTypeUse <Ivl:66> BB12 regmask=[rdx] minReg=1 last fixed>
<RefPosition #313 @332 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #314 @332 RefTypeUse <Ivl:68> BB12 regmask=[rcx] minReg=1 last fixed>
<RefPosition #315 @333 RefTypeKill <Reg:rax> BB12 regmask=[rax] minReg=1 last>
<RefPosition #316 @333 RefTypeKill <Reg:rcx> BB12 regmask=[rcx] minReg=1 last>
<RefPosition #317 @333 RefTypeKill <Reg:rdx> BB12 regmask=[rdx] minReg=1 last>
<RefPosition #318 @333 RefTypeKill <Reg:r8 > BB12 regmask=[r8] minReg=1 last>
<RefPosition #319 @333 RefTypeKill <Reg:r9 > BB12 regmask=[r9] minReg=1 last>
<RefPosition #320 @333 RefTypeKill <Reg:r10> BB12 regmask=[r10] minReg=1 last>
<RefPosition #321 @333 RefTypeKill <Reg:r11> BB12 regmask=[r11] minReg=1 last>
<RefPosition #322 @333 RefTypeFixedReg <Reg:rax> BB12 regmask=[rax] minReg=1>
<RefPosition #323 @333 RefTypeDef <Ivl:69> CALL BB12 regmask=[rax] minReg=1 fixed>
<RefPosition #324 @334 RefTypeUse <Ivl:69> BB12 regmask=[allIntButFP] minReg=1 last>
<RefPosition #325 @337 RefTypeDef <Ivl:70> LCL_VAR BB12 regmask=[rdx] minReg=1>
<RefPosition #326 @338 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #327 @338 RefTypeUse <Ivl:70> BB12 regmask=[rdx] minReg=1 last fixed>
<RefPosition #328 @339 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #329 @339 RefTypeDef <Ivl:71> PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed>
<RefPosition #330 @341 RefTypeDef <Ivl:72> CNS_INT BB12 regmask=[rcx] minReg=1>
<RefPosition #331 @342 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #332 @342 RefTypeUse <Ivl:72> BB12 regmask=[rcx] minReg=1 last fixed>
<RefPosition #333 @343 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #334 @343 RefTypeDef <Ivl:73> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed>
<RefPosition #335 @344 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #336 @344 RefTypeUse <Ivl:71> BB12 regmask=[rdx] minReg=1 last fixed>
<RefPosition #337 @344 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #338 @344 RefTypeUse <Ivl:73> BB12 regmask=[rcx] minReg=1 last fixed>
<RefPosition #339 @345 RefTypeKill <Reg:rax> BB12 regmask=[rax] minReg=1 last>
<RefPosition #340 @345 RefTypeKill <Reg:rcx> BB12 regmask=[rcx] minReg=1 last>
<RefPosition #341 @345 RefTypeKill <Reg:rdx> BB12 regmask=[rdx] minReg=1 last>
<RefPosition #342 @345 RefTypeKill <Reg:r8 > BB12 regmask=[r8] minReg=1 last>
<RefPosition #343 @345 RefTypeKill <Reg:r9 > BB12 regmask=[r9] minReg=1 last>
<RefPosition #344 @345 RefTypeKill <Reg:r10> BB12 regmask=[r10] minReg=1 last>
<RefPosition #345 @345 RefTypeKill <Reg:r11> BB12 regmask=[r11] minReg=1 last>
<RefPosition #346 @345 RefTypeFixedReg <Reg:rax> BB12 regmask=[rax] minReg=1>
<RefPosition #347 @345 RefTypeDef <Ivl:74> CALL BB12 regmask=[rax] minReg=1 fixed>
<RefPosition #348 @346 RefTypeUse <Ivl:74> BB12 regmask=[allIntButFP] minReg=1 last>
<RefPosition #349 @355 RefTypeDef <Ivl:75> NE BB12 regmask=[allIntButFP] minReg=1>
<RefPosition #350 @356 RefTypeUse <Ivl:75> BB12 regmask=[allIntButFP] minReg=1 last>
<RefPosition #351 @368 RefTypeBB BB13 regmask=[] minReg=1>
<RefPosition #352 @377 RefTypeDef <Ivl:76> LCL_VAR BB13 regmask=[rcx] minReg=1>
<RefPosition #353 @378 RefTypeFixedReg <Reg:rcx> BB13 regmask=[rcx] minReg=1>
<RefPosition #354 @378 RefTypeUse <Ivl:76> BB13 regmask=[rcx] minReg=1 last fixed>
<RefPosition #355 @379 RefTypeFixedReg <Reg:rcx> BB13 regmask=[rcx] minReg=1>
<RefPosition #356 @379 RefTypeDef <Ivl:77> PUTARG_REG BB13 regmask=[rcx] minReg=1 fixed>
<RefPosition #357 @381 RefTypeDef <Ivl:78> LCL_VAR BB13 regmask=[allIntButFP] minReg=1>
<RefPosition #358 @384 RefTypeUse <Ivl:78> BB13 regmask=[allIntButFP] minReg=1 last>
<RefPosition #359 @385 RefTypeDef <Ivl:79> IND BB13 regmask=[allIntButFP] minReg=1>
<RefPosition #360 @388 RefTypeUse <Ivl:79> BB13 regmask=[allIntButFP] minReg=1 last>
<RefPosition #361 @389 RefTypeDef <Ivl:80> IND BB13 regmask=[allIntButFP] minReg=1>
<RefPosition #362 @394 RefTypeFixedReg <Reg:rcx> BB13 regmask=[rcx] minReg=1>
<RefPosition #363 @394 RefTypeUse <Ivl:77> BB13 regmask=[rcx] minReg=1 last fixed>
<RefPosition #364 @394 RefTypeUse <Ivl:80> BB13 regmask=[allIntButFP] minReg=1 last>
<RefPosition #365 @395 RefTypeKill <Reg:rax> BB13 regmask=[rax] minReg=1 last>
<RefPosition #366 @395 RefTypeKill <Reg:rcx> BB13 regmask=[rcx] minReg=1 last>
<RefPosition #367 @395 RefTypeKill <Reg:rdx> BB13 regmask=[rdx] minReg=1 last>
<RefPosition #368 @395 RefTypeKill <Reg:r8 > BB13 regmask=[r8] minReg=1 last>
<RefPosition #369 @395 RefTypeKill <Reg:r9 > BB13 regmask=[r9] minReg=1 last>
<RefPosition #370 @395 RefTypeKill <Reg:r10> BB13 regmask=[r10] minReg=1 last>
<RefPosition #371 @395 RefTypeKill <Reg:r11> BB13 regmask=[r11] minReg=1 last>
<RefPosition #372 @395 RefTypeFixedReg <Reg:rax> BB13 regmask=[rax] minReg=1>
<RefPosition #373 @395 RefTypeDef <Ivl:81> CALL BB13 regmask=[rax] minReg=1 fixed>
<RefPosition #374 @396 RefTypeUse <Ivl:81> BB13 regmask=[allIntButFP] minReg=1 last>
<RefPosition #375 @401 RefTypeDef <Ivl:82> LCL_VAR BB13 regmask=[allIntButFP] minReg=1>
<RefPosition #376 @402 RefTypeUse <Ivl:82> BB13 regmask=[allIntButFP] minReg=1 last>
<RefPosition #377 @403 RefTypeDef <Ivl:83> CAST BB13 regmask=[allIntButFP] minReg=1>
<RefPosition #378 @404 RefTypeUse <Ivl:83> BB13 regmask=[allIntButFP] minReg=1 last>
<RefPosition #379 @410 RefTypeBB BB14 regmask=[] minReg=1>
<RefPosition #380 @419 RefTypeKill <Reg:rax> BB14 regmask=[rax] minReg=1 last>
<RefPosition #381 @419 RefTypeKill <Reg:rcx> BB14 regmask=[rcx] minReg=1 last>
<RefPosition #382 @419 RefTypeKill <Reg:rdx> BB14 regmask=[rdx] minReg=1 last>
<RefPosition #383 @419 RefTypeKill <Reg:r8 > BB14 regmask=[r8] minReg=1 last>
<RefPosition #384 @419 RefTypeKill <Reg:r9 > BB14 regmask=[r9] minReg=1 last>
<RefPosition #385 @419 RefTypeKill <Reg:r10> BB14 regmask=[r10] minReg=1 last>
<RefPosition #386 @419 RefTypeKill <Reg:r11> BB14 regmask=[r11] minReg=1 last>
<RefPosition #387 @419 RefTypeFixedReg <Reg:rax> BB14 regmask=[rax] minReg=1>
<RefPosition #388 @419 RefTypeDef <Ivl:84> CALL BB14 regmask=[rax] minReg=1 fixed>
<RefPosition #389 @420 RefTypeUse <Ivl:84> BB14 regmask=[allIntButFP] minReg=1 last>
<RefPosition #390 @425 RefTypeDef <Ivl:85> LCL_VAR BB14 regmask=[allIntButFP] minReg=1>
<RefPosition #391 @426 RefTypeUse <Ivl:85> BB14 regmask=[allIntButFP] minReg=1 last>
<RefPosition #392 @427 RefTypeDef <Ivl:86> CAST BB14 regmask=[allIntButFP] minReg=1>
<RefPosition #393 @428 RefTypeUse <Ivl:86> BB14 regmask=[allIntButFP] minReg=1 last>
<RefPosition #394 @434 RefTypeBB BB15 regmask=[] minReg=1>
<RefPosition #395 @439 RefTypeDef <Ivl:87> LCL_VAR BB15 regmask=[rax] minReg=1>
<RefPosition #396 @440 RefTypeFixedReg <Reg:rax> BB15 regmask=[rax] minReg=1>
<RefPosition #397 @440 RefTypeUse <Ivl:87> BB15 regmask=[rax] minReg=1 last fixed>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters:
BB01 [???..???), preds={} succs={BB02}
=====
N002. NOP
BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
=====
N006. CNS_INT(h) 0x7ff9392a5420 global ptr
N008. IND
N010. CNS_INT 0
N012. EQ
N014. JTRUE
BB03 [???..???), preds={BB02} succs={BB04}
=====
N018. CALL help
Kill: rax rcx rdx r8 r9 r10 r11
BB04 [???..???), preds={BB02,BB03} succs={BB05}
=====
BB05 [000..01C) -> BB07 (cond), preds={BB04} succs={BB06,BB07}
=====
N024. IL_OFFSET IL offset: 0x0
N026. NO_OP
N028. IL_OFFSET IL offset: 0x1
N030. CNS_INT(h) 0x7ff93af7cd80 class
Def:<I0>(#12)
N032. PUTARG_REG
Use:<I0>(#14) Fixed:rcx(#13) *
Def:<I1>(#16) rcx
N034. CALL help
Use:<I1>(#18) Fixed:rcx(#17) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I2>(#27) rax
N036. V10 MEM
Use:<I2>(#28) *
N038. V10 MEM
Def:<I3>(#29)
N040. PUTARG_REG
Use:<I3>(#31) Fixed:rcx(#30) *
Def:<I4>(#33) rcx
N042. CALL
Use:<I4>(#35) Fixed:rcx(#34) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I5>(#44) rax
N044. V11 MEM
Use:<I5>(#45) *
N046. IL_OFFSET IL offset: 0xb
N048. CNS_INT(h) 0x7ff93af7cd80 class
Def:<I6>(#46)
N050. PUTARG_REG
Use:<I6>(#48) Fixed:rcx(#47) *
Def:<I7>(#50) rcx
N052. CALL help
Use:<I7>(#52) Fixed:rcx(#51) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I8>(#61) rax
N054. V12 MEM
Use:<I8>(#62) *
N056. V12 MEM
Def:<I9>(#63)
N058. PUTARG_REG
Use:<I9>(#65) Fixed:rcx(#64) *
Def:<I10>(#67) rcx
N060. CALL
Use:<I10>(#69) Fixed:rcx(#68) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I11>(#78) rax
N062. V13 MEM
Use:<I11>(#79) *
N064. IL_OFFSET IL offset: 0x15
N066. V11 MEM
Def:<I12>(#80)
N068. PUTARG_REG
Use:<I12>(#82) Fixed:rcx(#81) *
Def:<I13>(#84) rcx
N070. V13 MEM
Def:<I14>(#85)
N072. PUTARG_REG
Use:<I14>(#87) Fixed:rdx(#86) *
Def:<I15>(#89) rdx
N074. CALL
Use:<I13>(#91) Fixed:rcx(#90) *
Use:<I15>(#93) Fixed:rdx(#92) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I16>(#102) rax
N076. V14 MEM
Use:<I16>(#103) *
N078. IL_OFFSET IL offset: 0x1a
N080. V14 MEM
N082. CNS_INT 0
N084. NE
N086. JTRUE
BB06 [01C..037) -> BB08 (always), preds={BB05} succs={BB08}
=====
N090. IL_OFFSET IL offset: 0x1c
N092. CNS_INT(h) 0x7ff93af7cd80 class
Def:<I17>(#105)
N094. PUTARG_REG
Use:<I17>(#107) Fixed:rcx(#106) *
Def:<I18>(#109) rcx
N096. CALL help
Use:<I18>(#111) Fixed:rcx(#110) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I19>(#120) rax
N098. V22 MEM
Use:<I19>(#121) *
N100. V22 MEM
Def:<I20>(#122)
N102. PUTARG_REG
Use:<I20>(#124) Fixed:rcx(#123) *
Def:<I21>(#126) rcx
N104. CALL
Use:<I21>(#128) Fixed:rcx(#127) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I22>(#137) rax
N106. V23 MEM
Use:<I22>(#138) *
N108. IL_OFFSET IL offset: 0x26
N110. CNS_INT(h) 0x7ff93b56a7f8 class
Def:<I23>(#139)
N112. PUTARG_REG
Use:<I23>(#141) Fixed:rcx(#140) *
Def:<I24>(#143) rcx
N114. CALL help
Use:<I24>(#145) Fixed:rcx(#144) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I25>(#154) rax
N116. V24 MEM
Use:<I25>(#155) *
N118. V24 MEM
Def:<I26>(#156)
N120. PUTARG_REG
Use:<I26>(#158) Fixed:rcx(#157) *
Def:<I27>(#160) rcx
N122. CALL
Use:<I27>(#162) Fixed:rcx(#161) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I28>(#171) rax
N124. V25 MEM
Use:<I28>(#172) *
N126. IL_OFFSET IL offset: 0x30
N128. V23 MEM
Def:<I29>(#173)
N130. PUTARG_REG
Use:<I29>(#175) Fixed:rcx(#174) *
Def:<I30>(#177) rcx
N132. V25 MEM
Def:<I31>(#178)
N134. PUTARG_REG
Use:<I31>(#180) Fixed:rdx(#179) *
Def:<I32>(#182) rdx
N136. CALL
Use:<I30>(#184) Fixed:rcx(#183) *
Use:<I32>(#186) Fixed:rdx(#185) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I33>(#195) rax
N138. V26 MEM
Use:<I33>(#196) *
N140. IL_OFFSET IL offset: 0x35
N142. NOP
N144. V26 MEM
Def:<I34>(#197)
N146. V15 MEM
Use:<I34>(#198) *
BB07 [037..038), preds={BB05} succs={BB08}
=====
N150. IL_OFFSET IL offset: 0x37
N152. CNS_INT 1
N154. V15 MEM
BB08 [038..03C) -> BB12 (cond), preds={BB06,BB07} succs={BB09,BB12}
=====
N158. V15 MEM
Def:<I35>(#201)
N160. CAST
Use:<I35>(#202) *
Def:<I36>(#203)
N162. V01 MEM
Use:<I36>(#204) *
N164. IL_OFFSET IL offset: 0x39
N166. V01 MEM
N168. CNS_INT 0
N170. EQ
N172. JTRUE
BB09 [03C..05E) -> BB11 (cond), preds={BB08} succs={BB10,BB11}
=====
N176. IL_OFFSET IL offset: 0x3c
N178. NO_OP
N180. IL_OFFSET IL offset: 0x3d
N182. V00 MEM
Def:<I37>(#206)
N184. LEA(b+24)
N186. IND
Use:<I37>(#207) *
Def:<I38>(#208)
N188. V02 MEM
Use:<I38>(#209) *
N190. IL_OFFSET IL offset: 0x44
N192. V00 MEM
Def:<I39>(#210)
N194. LEA(b+32)
N196. IND
N198. LCL_VAR_ADDR V03 loc2 NA
N200. STORE_BLK
Def:<T40>(#211)
Use:<I39>(#212) *
Use:<T40>(#213) *
N202. IL_OFFSET IL offset: 0x4b
N204. V02 MEM
Def:<I41>(#214)
N206. V18 MEM
Use:<I41>(#215) *
N208. LCL_VAR_ADDR V03 loc2 NA
Def:<I42>(#216)
N210. PUTARG_REG
Use:<I42>(#218) Fixed:rcx(#217) *
Def:<I43>(#220) rcx
N212. CALL
Use:<I43>(#222) Fixed:rcx(#221) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I44>(#231) rax
N214. V19 MEM
Use:<I44>(#232) *
N216. IL_OFFSET IL offset: 0x53
N218. V18 MEM
Def:<I45>(#233)
N220. V19 MEM
N222. GE
Use:<I45>(#234) *
Def:<I46>(#235)
N224. V05 MEM
Use:<I46>(#236) *
N226. IL_OFFSET IL offset: 0x5a
N228. V05 MEM
N230. CNS_INT 0
N232. EQ
N234. JTRUE
BB10 [05E..069) -> BB15 (always), preds={BB09} succs={BB15}
=====
N238. IL_OFFSET IL offset: 0x5e
N240. NO_OP
N242. IL_OFFSET IL offset: 0x5f
N244. V00 MEM
Def:<I47>(#238)
N246. PUTARG_REG
Use:<I47>(#240) Fixed:rcx(#239) *
Def:<I48>(#242) rcx
N248. CALL
Use:<I48>(#244) Fixed:rcx(#243) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I49>(#253) rax
N250. V21 MEM
Use:<I49>(#254) *
N252. IL_OFFSET IL offset: 0x65
N254. V21 MEM
Def:<I50>(#255)
N256. CAST
Use:<I50>(#256) *
Def:<I51>(#257)
N258. V06 MEM
Use:<I51>(#258) *
N260. IL_OFFSET IL offset: 0x67
N262. NOP
BB11 [069..081) -> BB15 (always), preds={BB09} succs={BB15}
=====
N266. IL_OFFSET IL offset: 0x69
N268. LCL_VAR_ADDR V03 loc2 NA
Def:<I52>(#260)
N270. PUTARG_REG
Use:<I52>(#262) Fixed:rcx(#261) *
Def:<I53>(#264) rcx
N272. V02 MEM
Def:<I54>(#265)
N274. PUTARG_REG
Use:<I54>(#267) Fixed:rdx(#266) *
Def:<I55>(#269) rdx
N276. CALL
Use:<I53>(#271) Fixed:rcx(#270) *
Use:<I55>(#273) Fixed:rdx(#272) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I56>(#282) rax
N278. V20 MEM
Use:<I56>(#283) *
N280. IL_OFFSET IL offset: 0x71
N282. V20 MEM
Def:<I57>(#284)
N284. IND
Use:<I57>(#285) *
Def:<I58>(#286)
N286. V04 MEM
Use:<I58>(#287) *
N288. IL_OFFSET IL offset: 0x73
N290. V02 MEM
Def:<I59>(#288) Pref:<I60>
N292. CNS_INT 1
N294. ADD
Use:<I59>(#289) *
Def:<I60>(#290)
N296. V00 MEM
Def:<I61>(#291)
N298. LEA(b+24)
N300. STOREIND
Use:<I61>(#292) *
Use:<I60>(#293) *
N302. IL_OFFSET IL offset: 0x7c
N304. V04 MEM
Def:<I62>(#294)
N306. V06 MEM
Use:<I62>(#295) *
N308. IL_OFFSET IL offset: 0x7f
N310. NOP
BB12 [081..09E) -> BB14 (cond), preds={BB08} succs={BB13,BB14}
=====
N314. IL_OFFSET IL offset: 0x81
N316. V00 MEM
Def:<I63>(#297)
N318. NULLCHECK
Use:<I63>(#298) *
N320. V00 MEM
Def:<I64>(#299) Pref:<I65>
N322. CNS_INT 64 field offset Fseq[_input]
N324. ADD
Use:<I64>(#300) *
Def:<I65>(#301)
N326. PUTARG_REG
Use:<I65>(#303) Fixed:rdx(#302) *
Def:<I66>(#305) rdx
N328. CNS_INT(h) 0x7ff93af7cd80 class
Def:<I67>(#306)
N330. PUTARG_REG
Use:<I67>(#308) Fixed:rcx(#307) *
Def:<I68>(#310) rcx
N332. CALL help
Use:<I66>(#312) Fixed:rdx(#311) *
Use:<I68>(#314) Fixed:rcx(#313) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I69>(#323) rax
N334. V27 MEM
Use:<I69>(#324) *
N336. V27 MEM
Def:<I70>(#325)
N338. PUTARG_REG
Use:<I70>(#327) Fixed:rdx(#326) *
Def:<I71>(#329) rdx
N340. CNS_INT(h) 0x7ff93b569758 class
Def:<I72>(#330)
N342. PUTARG_REG
Use:<I72>(#332) Fixed:rcx(#331) *
Def:<I73>(#334) rcx
N344. CALL help
Use:<I71>(#336) Fixed:rdx(#335) *
Use:<I73>(#338) Fixed:rcx(#337) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I74>(#347) rax
N346. V07 MEM
Use:<I74>(#348) *
N348. IL_OFFSET IL offset: 0x93
N350. V07 MEM
N352. CNS_INT null
N354. NE
Def:<I75>(#349)
N356. V08 MEM
Use:<I75>(#350) *
N358. IL_OFFSET IL offset: 0x9a
N360. V08 MEM
N362. CNS_INT 0
N364. EQ
N366. JTRUE
BB13 [09E..0AA) -> BB15 (always), preds={BB12} succs={BB15}
=====
N370. IL_OFFSET IL offset: 0x9e
N372. NO_OP
N374. IL_OFFSET IL offset: 0x9f
N376. V07 MEM
Def:<I76>(#352)
N378. PUTARG_REG
Use:<I76>(#354) Fixed:rcx(#353) *
Def:<I77>(#356) rcx
N380. V07 MEM
Def:<I78>(#357)
N382. LEA(b+0)
N384. IND
Use:<I78>(#358) *
Def:<I79>(#359)
N386. LEA(b+72)
N388. IND
Use:<I79>(#360) *
Def:<I80>(#361)
N390. LEA(b+56)
N392. IND
N394. CALLV ind
Use:<I77>(#363) Fixed:rcx(#362) *
Use:<I80>(#364) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I81>(#373) rax
N396. V17 MEM
Use:<I81>(#374) *
N398. IL_OFFSET IL offset: 0xa6
N400. V17 MEM
Def:<I82>(#375)
N402. CAST
Use:<I82>(#376) *
Def:<I83>(#377)
N404. V06 MEM
Use:<I83>(#378) *
N406. IL_OFFSET IL offset: 0xa8
N408. NOP
BB14 [0AA..0B4) -> BB15 (always), preds={BB12} succs={BB15}
=====
N412. IL_OFFSET IL offset: 0xaa
N414. NO_OP
N416. IL_OFFSET IL offset: 0xab
N418. CALL
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I84>(#388) rax
N420. V16 MEM
Use:<I84>(#389) *
N422. IL_OFFSET IL offset: 0xb0
N424. V16 MEM
Def:<I85>(#390)
N426. CAST
Use:<I85>(#391) *
Def:<I86>(#392)
N428. V06 MEM
Use:<I86>(#393) *
N430. IL_OFFSET IL offset: 0xb2
N432. NOP
BB15 [0B4..0B7) (return), preds={BB10,BB11,BB13,BB14} succs={}
=====
N436. IL_OFFSET IL offset: 0xb4
N438. V06 MEM
Def:<I87>(#395)
N440. RETURN
Use:<I87>(#397) Fixed:rax(#396) *
Linear scan intervals after buildIntervals:
Interval 0: long (constant) RefPositions {#12@31 #14@32} physReg:NA Preferences=[rcx]
Interval 1: long RefPositions {#16@33 #18@34} physReg:NA Preferences=[rcx]
Interval 2: ref RefPositions {#27@35 #28@36} physReg:NA Preferences=[rax]
Interval 3: ref RefPositions {#29@39 #31@40} physReg:NA Preferences=[rcx]
Interval 4: ref RefPositions {#33@41 #35@42} physReg:NA Preferences=[rcx]
Interval 5: ref RefPositions {#44@43 #45@44} physReg:NA Preferences=[rax]
Interval 6: long (constant) RefPositions {#46@49 #48@50} physReg:NA Preferences=[rcx]
Interval 7: long RefPositions {#50@51 #52@52} physReg:NA Preferences=[rcx]
Interval 8: ref RefPositions {#61@53 #62@54} physReg:NA Preferences=[rax]
Interval 9: ref RefPositions {#63@57 #65@58} physReg:NA Preferences=[rcx]
Interval 10: ref RefPositions {#67@59 #69@60} physReg:NA Preferences=[rcx]
Interval 11: ref RefPositions {#78@61 #79@62} physReg:NA Preferences=[rax]
Interval 12: ref RefPositions {#80@67 #82@68} physReg:NA Preferences=[rcx]
Interval 13: ref RefPositions {#84@69 #91@74} physReg:NA Preferences=[rcx]
Interval 14: ref RefPositions {#85@71 #87@72} physReg:NA Preferences=[rdx]
Interval 15: ref RefPositions {#89@73 #93@74} physReg:NA Preferences=[rdx]
Interval 16: int RefPositions {#102@75 #103@76} physReg:NA Preferences=[rax]
Interval 17: long (constant) RefPositions {#105@93 #107@94} physReg:NA Preferences=[rcx]
Interval 18: long RefPositions {#109@95 #111@96} physReg:NA Preferences=[rcx]
Interval 19: ref RefPositions {#120@97 #121@98} physReg:NA Preferences=[rax]
Interval 20: ref RefPositions {#122@101 #124@102} physReg:NA Preferences=[rcx]
Interval 21: ref RefPositions {#126@103 #128@104} physReg:NA Preferences=[rcx]
Interval 22: ref RefPositions {#137@105 #138@106} physReg:NA Preferences=[rax]
Interval 23: long (constant) RefPositions {#139@111 #141@112} physReg:NA Preferences=[rcx]
Interval 24: long RefPositions {#143@113 #145@114} physReg:NA Preferences=[rcx]
Interval 25: ref RefPositions {#154@115 #155@116} physReg:NA Preferences=[rax]
Interval 26: ref RefPositions {#156@119 #158@120} physReg:NA Preferences=[rcx]
Interval 27: ref RefPositions {#160@121 #162@122} physReg:NA Preferences=[rcx]
Interval 28: ref RefPositions {#171@123 #172@124} physReg:NA Preferences=[rax]
Interval 29: ref RefPositions {#173@129 #175@130} physReg:NA Preferences=[rcx]
Interval 30: ref RefPositions {#177@131 #184@136} physReg:NA Preferences=[rcx]
Interval 31: ref RefPositions {#178@133 #180@134} physReg:NA Preferences=[rdx]
Interval 32: ref RefPositions {#182@135 #186@136} physReg:NA Preferences=[rdx]
Interval 33: int RefPositions {#195@137 #196@138} physReg:NA Preferences=[rax]
Interval 34: int RefPositions {#197@145 #198@146} physReg:NA Preferences=[allIntButFP]
Interval 35: int RefPositions {#201@159 #202@160} physReg:NA Preferences=[allIntButFP]
Interval 36: int RefPositions {#203@161 #204@162} physReg:NA Preferences=[allIntButFP]
Interval 37: byref RefPositions {#206@183 #207@186} physReg:NA Preferences=[allIntButFP]
Interval 38: int RefPositions {#208@187 #209@188} physReg:NA Preferences=[allIntButFP]
Interval 39: byref RefPositions {#210@193 #212@200} physReg:NA Preferences=[allIntButFP]
Interval 40: float (INTERNAL) RefPositions {#211@200 #213@200} physReg:NA Preferences=[mm0-mm5]
Interval 41: int RefPositions {#214@205 #215@206} physReg:NA Preferences=[allIntButFP]
Interval 42: byref RefPositions {#216@209 #218@210} physReg:NA Preferences=[rcx]
Interval 43: byref RefPositions {#220@211 #222@212} physReg:NA Preferences=[rcx]
Interval 44: int RefPositions {#231@213 #232@214} physReg:NA Preferences=[rax]
Interval 45: int RefPositions {#233@219 #234@222} physReg:NA Preferences=[allIntButFP]
Interval 46: int RefPositions {#235@223 #236@224} physReg:NA Preferences=[allIntButFP]
Interval 47: byref RefPositions {#238@245 #240@246} physReg:NA Preferences=[rcx]
Interval 48: byref RefPositions {#242@247 #244@248} physReg:NA Preferences=[rcx]
Interval 49: int RefPositions {#253@249 #254@250} physReg:NA Preferences=[rax]
Interval 50: int RefPositions {#255@255 #256@256} physReg:NA Preferences=[allIntButFP]
Interval 51: int RefPositions {#257@257 #258@258} physReg:NA Preferences=[allIntButFP]
Interval 52: byref RefPositions {#260@269 #262@270} physReg:NA Preferences=[rcx]
Interval 53: byref RefPositions {#264@271 #271@276} physReg:NA Preferences=[rcx]
Interval 54: int RefPositions {#265@273 #267@274} physReg:NA Preferences=[rdx]
Interval 55: int RefPositions {#269@275 #273@276} physReg:NA Preferences=[rdx]
Interval 56: byref RefPositions {#282@277 #283@278} physReg:NA Preferences=[rax]
Interval 57: byref RefPositions {#284@283 #285@284} physReg:NA Preferences=[allIntButFP]
Interval 58: ubyte RefPositions {#286@285 #287@286} physReg:NA Preferences=[allIntButFP]
Interval 59: int RefPositions {#288@291 #289@294} physReg:NA Preferences=[allIntButFP] RelatedInterval <I60>
Interval 60: int RefPositions {#290@295 #293@300} physReg:NA Preferences=[allIntButFP]
Interval 61: byref RefPositions {#291@297 #292@300} physReg:NA Preferences=[allIntButFP]
Interval 62: int RefPositions {#294@305 #295@306} physReg:NA Preferences=[allIntButFP]
Interval 63: byref RefPositions {#297@317 #298@318} physReg:NA Preferences=[allIntButFP]
Interval 64: byref RefPositions {#299@321 #300@324} physReg:NA Preferences=[allIntButFP] RelatedInterval <I65>
Interval 65: byref RefPositions {#301@325 #303@326} physReg:NA Preferences=[rdx]
Interval 66: byref RefPositions {#305@327 #312@332} physReg:NA Preferences=[rdx]
Interval 67: long (constant) RefPositions {#306@329 #308@330} physReg:NA Preferences=[rcx]
Interval 68: long RefPositions {#310@331 #314@332} physReg:NA Preferences=[rcx]
Interval 69: ref RefPositions {#323@333 #324@334} physReg:NA Preferences=[rax]
Interval 70: ref RefPositions {#325@337 #327@338} physReg:NA Preferences=[rdx]
Interval 71: ref RefPositions {#329@339 #336@344} physReg:NA Preferences=[rdx]
Interval 72: long (constant) RefPositions {#330@341 #332@342} physReg:NA Preferences=[rcx]
Interval 73: long RefPositions {#334@343 #338@344} physReg:NA Preferences=[rcx]
Interval 74: ref RefPositions {#347@345 #348@346} physReg:NA Preferences=[rax]
Interval 75: int RefPositions {#349@355 #350@356} physReg:NA Preferences=[allIntButFP]
Interval 76: ref RefPositions {#352@377 #354@378} physReg:NA Preferences=[rcx]
Interval 77: ref RefPositions {#356@379 #363@394} physReg:NA Preferences=[rcx]
Interval 78: ref RefPositions {#357@381 #358@384} physReg:NA Preferences=[allIntButFP]
Interval 79: long RefPositions {#359@385 #360@388} physReg:NA Preferences=[allIntButFP]
Interval 80: long RefPositions {#361@389 #364@394} physReg:NA Preferences=[allIntButFP]
Interval 81: int RefPositions {#373@395 #374@396} physReg:NA Preferences=[rax]
Interval 82: int RefPositions {#375@401 #376@402} physReg:NA Preferences=[allIntButFP]
Interval 83: int RefPositions {#377@403 #378@404} physReg:NA Preferences=[allIntButFP]
Interval 84: int RefPositions {#388@419 #389@420} physReg:NA Preferences=[rax]
Interval 85: int RefPositions {#390@425 #391@426} physReg:NA Preferences=[allIntButFP]
Interval 86: int RefPositions {#392@427 #393@428} physReg:NA Preferences=[allIntButFP]
Interval 87: int RefPositions {#395@439 #397@440} physReg:NA Preferences=[rax]
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: long (constant) RefPositions {#12@31 #14@32} physReg:NA Preferences=[rcx]
Interval 1: long RefPositions {#16@33 #18@34} physReg:NA Preferences=[rcx]
Interval 2: ref RefPositions {#27@35 #28@36} physReg:NA Preferences=[rax]
Interval 3: ref RefPositions {#29@39 #31@40} physReg:NA Preferences=[rcx]
Interval 4: ref RefPositions {#33@41 #35@42} physReg:NA Preferences=[rcx]
Interval 5: ref RefPositions {#44@43 #45@44} physReg:NA Preferences=[rax]
Interval 6: long (constant) RefPositions {#46@49 #48@50} physReg:NA Preferences=[rcx]
Interval 7: long RefPositions {#50@51 #52@52} physReg:NA Preferences=[rcx]
Interval 8: ref RefPositions {#61@53 #62@54} physReg:NA Preferences=[rax]
Interval 9: ref RefPositions {#63@57 #65@58} physReg:NA Preferences=[rcx]
Interval 10: ref RefPositions {#67@59 #69@60} physReg:NA Preferences=[rcx]
Interval 11: ref RefPositions {#78@61 #79@62} physReg:NA Preferences=[rax]
Interval 12: ref RefPositions {#80@67 #82@68} physReg:NA Preferences=[rcx]
Interval 13: ref RefPositions {#84@69 #91@74} physReg:NA Preferences=[rcx]
Interval 14: ref RefPositions {#85@71 #87@72} physReg:NA Preferences=[rdx]
Interval 15: ref RefPositions {#89@73 #93@74} physReg:NA Preferences=[rdx]
Interval 16: int RefPositions {#102@75 #103@76} physReg:NA Preferences=[rax]
Interval 17: long (constant) RefPositions {#105@93 #107@94} physReg:NA Preferences=[rcx]
Interval 18: long RefPositions {#109@95 #111@96} physReg:NA Preferences=[rcx]
Interval 19: ref RefPositions {#120@97 #121@98} physReg:NA Preferences=[rax]
Interval 20: ref RefPositions {#122@101 #124@102} physReg:NA Preferences=[rcx]
Interval 21: ref RefPositions {#126@103 #128@104} physReg:NA Preferences=[rcx]
Interval 22: ref RefPositions {#137@105 #138@106} physReg:NA Preferences=[rax]
Interval 23: long (constant) RefPositions {#139@111 #141@112} physReg:NA Preferences=[rcx]
Interval 24: long RefPositions {#143@113 #145@114} physReg:NA Preferences=[rcx]
Interval 25: ref RefPositions {#154@115 #155@116} physReg:NA Preferences=[rax]
Interval 26: ref RefPositions {#156@119 #158@120} physReg:NA Preferences=[rcx]
Interval 27: ref RefPositions {#160@121 #162@122} physReg:NA Preferences=[rcx]
Interval 28: ref RefPositions {#171@123 #172@124} physReg:NA Preferences=[rax]
Interval 29: ref RefPositions {#173@129 #175@130} physReg:NA Preferences=[rcx]
Interval 30: ref RefPositions {#177@131 #184@136} physReg:NA Preferences=[rcx]
Interval 31: ref RefPositions {#178@133 #180@134} physReg:NA Preferences=[rdx]
Interval 32: ref RefPositions {#182@135 #186@136} physReg:NA Preferences=[rdx]
Interval 33: int RefPositions {#195@137 #196@138} physReg:NA Preferences=[rax]
Interval 34: int RefPositions {#197@145 #198@146} physReg:NA Preferences=[allIntButFP]
Interval 35: int RefPositions {#201@159 #202@160} physReg:NA Preferences=[allIntButFP]
Interval 36: int RefPositions {#203@161 #204@162} physReg:NA Preferences=[allIntButFP]
Interval 37: byref RefPositions {#206@183 #207@186} physReg:NA Preferences=[allIntButFP]
Interval 38: int RefPositions {#208@187 #209@188} physReg:NA Preferences=[allIntButFP]
Interval 39: byref RefPositions {#210@193 #212@200} physReg:NA Preferences=[allIntButFP]
Interval 40: float (INTERNAL) RefPositions {#211@200 #213@200} physReg:NA Preferences=[mm0-mm5]
Interval 41: int RefPositions {#214@205 #215@206} physReg:NA Preferences=[allIntButFP]
Interval 42: byref RefPositions {#216@209 #218@210} physReg:NA Preferences=[rcx]
Interval 43: byref RefPositions {#220@211 #222@212} physReg:NA Preferences=[rcx]
Interval 44: int RefPositions {#231@213 #232@214} physReg:NA Preferences=[rax]
Interval 45: int RefPositions {#233@219 #234@222} physReg:NA Preferences=[allIntButFP]
Interval 46: int RefPositions {#235@223 #236@224} physReg:NA Preferences=[allIntButFP]
Interval 47: byref RefPositions {#238@245 #240@246} physReg:NA Preferences=[rcx]
Interval 48: byref RefPositions {#242@247 #244@248} physReg:NA Preferences=[rcx]
Interval 49: int RefPositions {#253@249 #254@250} physReg:NA Preferences=[rax]
Interval 50: int RefPositions {#255@255 #256@256} physReg:NA Preferences=[allIntButFP]
Interval 51: int RefPositions {#257@257 #258@258} physReg:NA Preferences=[allIntButFP]
Interval 52: byref RefPositions {#260@269 #262@270} physReg:NA Preferences=[rcx]
Interval 53: byref RefPositions {#264@271 #271@276} physReg:NA Preferences=[rcx]
Interval 54: int RefPositions {#265@273 #267@274} physReg:NA Preferences=[rdx]
Interval 55: int RefPositions {#269@275 #273@276} physReg:NA Preferences=[rdx]
Interval 56: byref RefPositions {#282@277 #283@278} physReg:NA Preferences=[rax]
Interval 57: byref RefPositions {#284@283 #285@284} physReg:NA Preferences=[allIntButFP]
Interval 58: ubyte RefPositions {#286@285 #287@286} physReg:NA Preferences=[allIntButFP]
Interval 59: int RefPositions {#288@291 #289@294} physReg:NA Preferences=[allIntButFP] RelatedInterval <I60>
Interval 60: int RefPositions {#290@295 #293@300} physReg:NA Preferences=[allIntButFP]
Interval 61: byref RefPositions {#291@297 #292@300} physReg:NA Preferences=[allIntButFP]
Interval 62: int RefPositions {#294@305 #295@306} physReg:NA Preferences=[allIntButFP]
Interval 63: byref RefPositions {#297@317 #298@318} physReg:NA Preferences=[allIntButFP]
Interval 64: byref RefPositions {#299@321 #300@324} physReg:NA Preferences=[allIntButFP] RelatedInterval <I65>
Interval 65: byref RefPositions {#301@325 #303@326} physReg:NA Preferences=[rdx]
Interval 66: byref RefPositions {#305@327 #312@332} physReg:NA Preferences=[rdx]
Interval 67: long (constant) RefPositions {#306@329 #308@330} physReg:NA Preferences=[rcx]
Interval 68: long RefPositions {#310@331 #314@332} physReg:NA Preferences=[rcx]
Interval 69: ref RefPositions {#323@333 #324@334} physReg:NA Preferences=[rax]
Interval 70: ref RefPositions {#325@337 #327@338} physReg:NA Preferences=[rdx]
Interval 71: ref RefPositions {#329@339 #336@344} physReg:NA Preferences=[rdx]
Interval 72: long (constant) RefPositions {#330@341 #332@342} physReg:NA Preferences=[rcx]
Interval 73: long RefPositions {#334@343 #338@344} physReg:NA Preferences=[rcx]
Interval 74: ref RefPositions {#347@345 #348@346} physReg:NA Preferences=[rax]
Interval 75: int RefPositions {#349@355 #350@356} physReg:NA Preferences=[allIntButFP]
Interval 76: ref RefPositions {#352@377 #354@378} physReg:NA Preferences=[rcx]
Interval 77: ref RefPositions {#356@379 #363@394} physReg:NA Preferences=[rcx]
Interval 78: ref RefPositions {#357@381 #358@384} physReg:NA Preferences=[allIntButFP]
Interval 79: long RefPositions {#359@385 #360@388} physReg:NA Preferences=[allIntButFP]
Interval 80: long RefPositions {#361@389 #364@394} physReg:NA Preferences=[allIntButFP]
Interval 81: int RefPositions {#373@395 #374@396} physReg:NA Preferences=[rax]
Interval 82: int RefPositions {#375@401 #376@402} physReg:NA Preferences=[allIntButFP]
Interval 83: int RefPositions {#377@403 #378@404} physReg:NA Preferences=[allIntButFP]
Interval 84: int RefPositions {#388@419 #389@420} physReg:NA Preferences=[rax]
Interval 85: int RefPositions {#390@425 #391@426} physReg:NA Preferences=[allIntButFP]
Interval 86: int RefPositions {#392@427 #393@428} physReg:NA Preferences=[allIntButFP]
Interval 87: int RefPositions {#395@439 #397@440} physReg:NA Preferences=[rax]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @4 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #2 @16 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #3 @19 RefTypeKill <Reg:rax> BB03 regmask=[rax] minReg=1 last>
<RefPosition #4 @19 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] minReg=1 last>
<RefPosition #5 @19 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] minReg=1 last>
<RefPosition #6 @19 RefTypeKill <Reg:r8 > BB03 regmask=[r8] minReg=1 last>
<RefPosition #7 @19 RefTypeKill <Reg:r9 > BB03 regmask=[r9] minReg=1 last>
<RefPosition #8 @19 RefTypeKill <Reg:r10> BB03 regmask=[r10] minReg=1 last>
<RefPosition #9 @19 RefTypeKill <Reg:r11> BB03 regmask=[r11] minReg=1 last>
<RefPosition #10 @20 RefTypeBB BB04 regmask=[] minReg=1>
<RefPosition #11 @22 RefTypeBB BB05 regmask=[] minReg=1>
<RefPosition #12 @31 RefTypeDef <Ivl:0> CNS_INT BB05 regmask=[rcx] minReg=1>
<RefPosition #13 @32 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #14 @32 RefTypeUse <Ivl:0> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #15 @33 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #16 @33 RefTypeDef <Ivl:1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
<RefPosition #17 @34 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #18 @34 RefTypeUse <Ivl:1> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #19 @35 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
<RefPosition #20 @35 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #21 @35 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
<RefPosition #22 @35 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
<RefPosition #23 @35 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
<RefPosition #24 @35 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
<RefPosition #25 @35 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
<RefPosition #26 @35 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #27 @35 RefTypeDef <Ivl:2> CALL BB05 regmask=[rax] minReg=1 fixed>
<RefPosition #28 @36 RefTypeUse <Ivl:2> BB05 regmask=[allIntButFP] minReg=1 last>
<RefPosition #29 @39 RefTypeDef <Ivl:3> LCL_FLD BB05 regmask=[rcx] minReg=1>
<RefPosition #30 @40 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #31 @40 RefTypeUse <Ivl:3> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #32 @41 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #33 @41 RefTypeDef <Ivl:4> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
<RefPosition #34 @42 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #35 @42 RefTypeUse <Ivl:4> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #36 @43 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
<RefPosition #37 @43 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #38 @43 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
<RefPosition #39 @43 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
<RefPosition #40 @43 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
<RefPosition #41 @43 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
<RefPosition #42 @43 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
<RefPosition #43 @43 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #44 @43 RefTypeDef <Ivl:5> CALL BB05 regmask=[rax] minReg=1 fixed>
<RefPosition #45 @44 RefTypeUse <Ivl:5> BB05 regmask=[allIntButFP] minReg=1 last>
<RefPosition #46 @49 RefTypeDef <Ivl:6> CNS_INT BB05 regmask=[rcx] minReg=1>
<RefPosition #47 @50 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #48 @50 RefTypeUse <Ivl:6> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #49 @51 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #50 @51 RefTypeDef <Ivl:7> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
<RefPosition #51 @52 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #52 @52 RefTypeUse <Ivl:7> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #53 @53 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
<RefPosition #54 @53 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #55 @53 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
<RefPosition #56 @53 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
<RefPosition #57 @53 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
<RefPosition #58 @53 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
<RefPosition #59 @53 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
<RefPosition #60 @53 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #61 @53 RefTypeDef <Ivl:8> CALL BB05 regmask=[rax] minReg=1 fixed>
<RefPosition #62 @54 RefTypeUse <Ivl:8> BB05 regmask=[allIntButFP] minReg=1 last>
<RefPosition #63 @57 RefTypeDef <Ivl:9> LCL_FLD BB05 regmask=[rcx] minReg=1>
<RefPosition #64 @58 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #65 @58 RefTypeUse <Ivl:9> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #66 @59 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #67 @59 RefTypeDef <Ivl:10> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
<RefPosition #68 @60 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #69 @60 RefTypeUse <Ivl:10> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #70 @61 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
<RefPosition #71 @61 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #72 @61 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
<RefPosition #73 @61 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
<RefPosition #74 @61 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
<RefPosition #75 @61 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
<RefPosition #76 @61 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
<RefPosition #77 @61 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #78 @61 RefTypeDef <Ivl:11> CALL BB05 regmask=[rax] minReg=1 fixed>
<RefPosition #79 @62 RefTypeUse <Ivl:11> BB05 regmask=[allIntButFP] minReg=1 last>
<RefPosition #80 @67 RefTypeDef <Ivl:12> LCL_VAR BB05 regmask=[rcx] minReg=1>
<RefPosition #81 @68 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #82 @68 RefTypeUse <Ivl:12> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #83 @69 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #84 @69 RefTypeDef <Ivl:13> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
<RefPosition #85 @71 RefTypeDef <Ivl:14> LCL_VAR BB05 regmask=[rdx] minReg=1>
<RefPosition #86 @72 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #87 @72 RefTypeUse <Ivl:14> BB05 regmask=[rdx] minReg=1 last fixed>
<RefPosition #88 @73 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #89 @73 RefTypeDef <Ivl:15> PUTARG_REG BB05 regmask=[rdx] minReg=1 fixed>
<RefPosition #90 @74 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #91 @74 RefTypeUse <Ivl:13> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #92 @74 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #93 @74 RefTypeUse <Ivl:15> BB05 regmask=[rdx] minReg=1 last fixed>
<RefPosition #94 @75 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
<RefPosition #95 @75 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #96 @75 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
<RefPosition #97 @75 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
<RefPosition #98 @75 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
<RefPosition #99 @75 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
<RefPosition #100 @75 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
<RefPosition #101 @75 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #102 @75 RefTypeDef <Ivl:16> CALL BB05 regmask=[rax] minReg=1 fixed>
<RefPosition #103 @76 RefTypeUse <Ivl:16> BB05 regmask=[allIntButFP] minReg=1 last>
<RefPosition #104 @88 RefTypeBB BB06 regmask=[] minReg=1>
<RefPosition #105 @93 RefTypeDef <Ivl:17> CNS_INT BB06 regmask=[rcx] minReg=1>
<RefPosition #106 @94 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #107 @94 RefTypeUse <Ivl:17> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #108 @95 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #109 @95 RefTypeDef <Ivl:18> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
<RefPosition #110 @96 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #111 @96 RefTypeUse <Ivl:18> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #112 @97 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1 last>
<RefPosition #113 @97 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #114 @97 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1 last>
<RefPosition #115 @97 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1 last>
<RefPosition #116 @97 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1 last>
<RefPosition #117 @97 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1 last>
<RefPosition #118 @97 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1 last>
<RefPosition #119 @97 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #120 @97 RefTypeDef <Ivl:19> CALL BB06 regmask=[rax] minReg=1 fixed>
<RefPosition #121 @98 RefTypeUse <Ivl:19> BB06 regmask=[allIntButFP] minReg=1 last>
<RefPosition #122 @101 RefTypeDef <Ivl:20> LCL_FLD BB06 regmask=[rcx] minReg=1>
<RefPosition #123 @102 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #124 @102 RefTypeUse <Ivl:20> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #125 @103 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #126 @103 RefTypeDef <Ivl:21> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
<RefPosition #127 @104 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #128 @104 RefTypeUse <Ivl:21> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #129 @105 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1 last>
<RefPosition #130 @105 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #131 @105 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1 last>
<RefPosition #132 @105 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1 last>
<RefPosition #133 @105 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1 last>
<RefPosition #134 @105 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1 last>
<RefPosition #135 @105 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1 last>
<RefPosition #136 @105 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #137 @105 RefTypeDef <Ivl:22> CALL BB06 regmask=[rax] minReg=1 fixed>
<RefPosition #138 @106 RefTypeUse <Ivl:22> BB06 regmask=[allIntButFP] minReg=1 last>
<RefPosition #139 @111 RefTypeDef <Ivl:23> CNS_INT BB06 regmask=[rcx] minReg=1>
<RefPosition #140 @112 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #141 @112 RefTypeUse <Ivl:23> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #142 @113 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #143 @113 RefTypeDef <Ivl:24> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
<RefPosition #144 @114 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #145 @114 RefTypeUse <Ivl:24> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #146 @115 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1 last>
<RefPosition #147 @115 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #148 @115 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1 last>
<RefPosition #149 @115 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1 last>
<RefPosition #150 @115 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1 last>
<RefPosition #151 @115 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1 last>
<RefPosition #152 @115 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1 last>
<RefPosition #153 @115 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #154 @115 RefTypeDef <Ivl:25> CALL BB06 regmask=[rax] minReg=1 fixed>
<RefPosition #155 @116 RefTypeUse <Ivl:25> BB06 regmask=[allIntButFP] minReg=1 last>
<RefPosition #156 @119 RefTypeDef <Ivl:26> LCL_FLD BB06 regmask=[rcx] minReg=1>
<RefPosition #157 @120 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #158 @120 RefTypeUse <Ivl:26> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #159 @121 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #160 @121 RefTypeDef <Ivl:27> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
<RefPosition #161 @122 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #162 @122 RefTypeUse <Ivl:27> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #163 @123 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1 last>
<RefPosition #164 @123 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #165 @123 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1 last>
<RefPosition #166 @123 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1 last>
<RefPosition #167 @123 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1 last>
<RefPosition #168 @123 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1 last>
<RefPosition #169 @123 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1 last>
<RefPosition #170 @123 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #171 @123 RefTypeDef <Ivl:28> CALL BB06 regmask=[rax] minReg=1 fixed>
<RefPosition #172 @124 RefTypeUse <Ivl:28> BB06 regmask=[allIntButFP] minReg=1 last>
<RefPosition #173 @129 RefTypeDef <Ivl:29> LCL_VAR BB06 regmask=[rcx] minReg=1>
<RefPosition #174 @130 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #175 @130 RefTypeUse <Ivl:29> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #176 @131 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #177 @131 RefTypeDef <Ivl:30> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
<RefPosition #178 @133 RefTypeDef <Ivl:31> LCL_VAR BB06 regmask=[rdx] minReg=1>
<RefPosition #179 @134 RefTypeFixedReg <Reg:rdx> BB06 regmask=[rdx] minReg=1>
<RefPosition #180 @134 RefTypeUse <Ivl:31> BB06 regmask=[rdx] minReg=1 last fixed>
<RefPosition #181 @135 RefTypeFixedReg <Reg:rdx> BB06 regmask=[rdx] minReg=1>
<RefPosition #182 @135 RefTypeDef <Ivl:32> PUTARG_REG BB06 regmask=[rdx] minReg=1 fixed>
<RefPosition #183 @136 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #184 @136 RefTypeUse <Ivl:30> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #185 @136 RefTypeFixedReg <Reg:rdx> BB06 regmask=[rdx] minReg=1>
<RefPosition #186 @136 RefTypeUse <Ivl:32> BB06 regmask=[rdx] minReg=1 last fixed>
<RefPosition #187 @137 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1 last>
<RefPosition #188 @137 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #189 @137 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1 last>
<RefPosition #190 @137 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1 last>
<RefPosition #191 @137 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1 last>
<RefPosition #192 @137 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1 last>
<RefPosition #193 @137 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1 last>
<RefPosition #194 @137 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #195 @137 RefTypeDef <Ivl:33> CALL BB06 regmask=[rax] minReg=1 fixed>
<RefPosition #196 @138 RefTypeUse <Ivl:33> BB06 regmask=[allIntButFP] minReg=1 last>
<RefPosition #197 @145 RefTypeDef <Ivl:34> LCL_VAR BB06 regmask=[allIntButFP] minReg=1>
<RefPosition #198 @146 RefTypeUse <Ivl:34> BB06 regmask=[allIntButFP] minReg=1 last>
<RefPosition #199 @148 RefTypeBB BB07 regmask=[] minReg=1>
<RefPosition #200 @156 RefTypeBB BB08 regmask=[] minReg=1>
<RefPosition #201 @159 RefTypeDef <Ivl:35> LCL_VAR BB08 regmask=[allIntButFP] minReg=1>
<RefPosition #202 @160 RefTypeUse <Ivl:35> BB08 regmask=[allIntButFP] minReg=1 last>
<RefPosition #203 @161 RefTypeDef <Ivl:36> CAST BB08 regmask=[allIntButFP] minReg=1>
<RefPosition #204 @162 RefTypeUse <Ivl:36> BB08 regmask=[allIntButFP] minReg=1 last>
<RefPosition #205 @174 RefTypeBB BB09 regmask=[] minReg=1>
<RefPosition #206 @183 RefTypeDef <Ivl:37> LCL_VAR BB09 regmask=[allIntButFP] minReg=1>
<RefPosition #207 @186 RefTypeUse <Ivl:37> BB09 regmask=[allIntButFP] minReg=1 last>
<RefPosition #208 @187 RefTypeDef <Ivl:38> IND BB09 regmask=[allIntButFP] minReg=1>
<RefPosition #209 @188 RefTypeUse <Ivl:38> BB09 regmask=[allIntButFP] minReg=1 last>
<RefPosition #210 @193 RefTypeDef <Ivl:39> LCL_VAR BB09 regmask=[allIntButFP] minReg=1>
<RefPosition #211 @200 RefTypeDef <Ivl:40 internal> STORE_BLK BB09 regmask=[mm0-mm5] minReg=1>
<RefPosition #212 @200 RefTypeUse <Ivl:39> BB09 regmask=[allIntButFP] minReg=1 last>
<RefPosition #213 @200 RefTypeUse <Ivl:40 internal> STORE_BLK BB09 regmask=[mm0-mm5] minReg=1 last>
<RefPosition #214 @205 RefTypeDef <Ivl:41> LCL_VAR BB09 regmask=[allIntButFP] minReg=1>
<RefPosition #215 @206 RefTypeUse <Ivl:41> BB09 regmask=[allIntButFP] minReg=1 last>
<RefPosition #216 @209 RefTypeDef <Ivl:42> LCL_VAR_ADDR BB09 regmask=[rcx] minReg=1>
<RefPosition #217 @210 RefTypeFixedReg <Reg:rcx> BB09 regmask=[rcx] minReg=1>
<RefPosition #218 @210 RefTypeUse <Ivl:42> BB09 regmask=[rcx] minReg=1 last fixed>
<RefPosition #219 @211 RefTypeFixedReg <Reg:rcx> BB09 regmask=[rcx] minReg=1>
<RefPosition #220 @211 RefTypeDef <Ivl:43> PUTARG_REG BB09 regmask=[rcx] minReg=1 fixed>
<RefPosition #221 @212 RefTypeFixedReg <Reg:rcx> BB09 regmask=[rcx] minReg=1>
<RefPosition #222 @212 RefTypeUse <Ivl:43> BB09 regmask=[rcx] minReg=1 last fixed>
<RefPosition #223 @213 RefTypeKill <Reg:rax> BB09 regmask=[rax] minReg=1 last>
<RefPosition #224 @213 RefTypeKill <Reg:rcx> BB09 regmask=[rcx] minReg=1 last>
<RefPosition #225 @213 RefTypeKill <Reg:rdx> BB09 regmask=[rdx] minReg=1 last>
<RefPosition #226 @213 RefTypeKill <Reg:r8 > BB09 regmask=[r8] minReg=1 last>
<RefPosition #227 @213 RefTypeKill <Reg:r9 > BB09 regmask=[r9] minReg=1 last>
<RefPosition #228 @213 RefTypeKill <Reg:r10> BB09 regmask=[r10] minReg=1 last>
<RefPosition #229 @213 RefTypeKill <Reg:r11> BB09 regmask=[r11] minReg=1 last>
<RefPosition #230 @213 RefTypeFixedReg <Reg:rax> BB09 regmask=[rax] minReg=1>
<RefPosition #231 @213 RefTypeDef <Ivl:44> CALL BB09 regmask=[rax] minReg=1 fixed>
<RefPosition #232 @214 RefTypeUse <Ivl:44> BB09 regmask=[allIntButFP] minReg=1 last>
<RefPosition #233 @219 RefTypeDef <Ivl:45> LCL_VAR BB09 regmask=[allIntButFP] minReg=1>
<RefPosition #234 @222 RefTypeUse <Ivl:45> BB09 regmask=[allIntButFP] minReg=1 last>
<RefPosition #235 @223 RefTypeDef <Ivl:46> GE BB09 regmask=[allIntButFP] minReg=1>
<RefPosition #236 @224 RefTypeUse <Ivl:46> BB09 regmask=[allIntButFP] minReg=1 last>
<RefPosition #237 @236 RefTypeBB BB10 regmask=[] minReg=1>
<RefPosition #238 @245 RefTypeDef <Ivl:47> LCL_VAR BB10 regmask=[rcx] minReg=1>
<RefPosition #239 @246 RefTypeFixedReg <Reg:rcx> BB10 regmask=[rcx] minReg=1>
<RefPosition #240 @246 RefTypeUse <Ivl:47> BB10 regmask=[rcx] minReg=1 last fixed>
<RefPosition #241 @247 RefTypeFixedReg <Reg:rcx> BB10 regmask=[rcx] minReg=1>
<RefPosition #242 @247 RefTypeDef <Ivl:48> PUTARG_REG BB10 regmask=[rcx] minReg=1 fixed>
<RefPosition #243 @248 RefTypeFixedReg <Reg:rcx> BB10 regmask=[rcx] minReg=1>
<RefPosition #244 @248 RefTypeUse <Ivl:48> BB10 regmask=[rcx] minReg=1 last fixed>
<RefPosition #245 @249 RefTypeKill <Reg:rax> BB10 regmask=[rax] minReg=1 last>
<RefPosition #246 @249 RefTypeKill <Reg:rcx> BB10 regmask=[rcx] minReg=1 last>
<RefPosition #247 @249 RefTypeKill <Reg:rdx> BB10 regmask=[rdx] minReg=1 last>
<RefPosition #248 @249 RefTypeKill <Reg:r8 > BB10 regmask=[r8] minReg=1 last>
<RefPosition #249 @249 RefTypeKill <Reg:r9 > BB10 regmask=[r9] minReg=1 last>
<RefPosition #250 @249 RefTypeKill <Reg:r10> BB10 regmask=[r10] minReg=1 last>
<RefPosition #251 @249 RefTypeKill <Reg:r11> BB10 regmask=[r11] minReg=1 last>
<RefPosition #252 @249 RefTypeFixedReg <Reg:rax> BB10 regmask=[rax] minReg=1>
<RefPosition #253 @249 RefTypeDef <Ivl:49> CALL BB10 regmask=[rax] minReg=1 fixed>
<RefPosition #254 @250 RefTypeUse <Ivl:49> BB10 regmask=[allIntButFP] minReg=1 last>
<RefPosition #255 @255 RefTypeDef <Ivl:50> LCL_VAR BB10 regmask=[allIntButFP] minReg=1>
<RefPosition #256 @256 RefTypeUse <Ivl:50> BB10 regmask=[allIntButFP] minReg=1 last>
<RefPosition #257 @257 RefTypeDef <Ivl:51> CAST BB10 regmask=[allIntButFP] minReg=1>
<RefPosition #258 @258 RefTypeUse <Ivl:51> BB10 regmask=[allIntButFP] minReg=1 last>
<RefPosition #259 @264 RefTypeBB BB11 regmask=[] minReg=1>
<RefPosition #260 @269 RefTypeDef <Ivl:52> LCL_VAR_ADDR BB11 regmask=[rcx] minReg=1>
<RefPosition #261 @270 RefTypeFixedReg <Reg:rcx> BB11 regmask=[rcx] minReg=1>
<RefPosition #262 @270 RefTypeUse <Ivl:52> BB11 regmask=[rcx] minReg=1 last fixed>
<RefPosition #263 @271 RefTypeFixedReg <Reg:rcx> BB11 regmask=[rcx] minReg=1>
<RefPosition #264 @271 RefTypeDef <Ivl:53> PUTARG_REG BB11 regmask=[rcx] minReg=1 fixed>
<RefPosition #265 @273 RefTypeDef <Ivl:54> LCL_VAR BB11 regmask=[rdx] minReg=1>
<RefPosition #266 @274 RefTypeFixedReg <Reg:rdx> BB11 regmask=[rdx] minReg=1>
<RefPosition #267 @274 RefTypeUse <Ivl:54> BB11 regmask=[rdx] minReg=1 last fixed>
<RefPosition #268 @275 RefTypeFixedReg <Reg:rdx> BB11 regmask=[rdx] minReg=1>
<RefPosition #269 @275 RefTypeDef <Ivl:55> PUTARG_REG BB11 regmask=[rdx] minReg=1 fixed>
<RefPosition #270 @276 RefTypeFixedReg <Reg:rcx> BB11 regmask=[rcx] minReg=1>
<RefPosition #271 @276 RefTypeUse <Ivl:53> BB11 regmask=[rcx] minReg=1 last fixed>
<RefPosition #272 @276 RefTypeFixedReg <Reg:rdx> BB11 regmask=[rdx] minReg=1>
<RefPosition #273 @276 RefTypeUse <Ivl:55> BB11 regmask=[rdx] minReg=1 last fixed>
<RefPosition #274 @277 RefTypeKill <Reg:rax> BB11 regmask=[rax] minReg=1 last>
<RefPosition #275 @277 RefTypeKill <Reg:rcx> BB11 regmask=[rcx] minReg=1 last>
<RefPosition #276 @277 RefTypeKill <Reg:rdx> BB11 regmask=[rdx] minReg=1 last>
<RefPosition #277 @277 RefTypeKill <Reg:r8 > BB11 regmask=[r8] minReg=1 last>
<RefPosition #278 @277 RefTypeKill <Reg:r9 > BB11 regmask=[r9] minReg=1 last>
<RefPosition #279 @277 RefTypeKill <Reg:r10> BB11 regmask=[r10] minReg=1 last>
<RefPosition #280 @277 RefTypeKill <Reg:r11> BB11 regmask=[r11] minReg=1 last>
<RefPosition #281 @277 RefTypeFixedReg <Reg:rax> BB11 regmask=[rax] minReg=1>
<RefPosition #282 @277 RefTypeDef <Ivl:56> CALL BB11 regmask=[rax] minReg=1 fixed>
<RefPosition #283 @278 RefTypeUse <Ivl:56> BB11 regmask=[allIntButFP] minReg=1 last>
<RefPosition #284 @283 RefTypeDef <Ivl:57> LCL_VAR BB11 regmask=[allIntButFP] minReg=1>
<RefPosition #285 @284 RefTypeUse <Ivl:57> BB11 regmask=[allIntButFP] minReg=1 last>
<RefPosition #286 @285 RefTypeDef <Ivl:58> IND BB11 regmask=[allIntButFP] minReg=1>
<RefPosition #287 @286 RefTypeUse <Ivl:58> BB11 regmask=[allIntButFP] minReg=1 last>
<RefPosition #288 @291 RefTypeDef <Ivl:59> LCL_VAR BB11 regmask=[allIntButFP] minReg=1>
<RefPosition #289 @294 RefTypeUse <Ivl:59> BB11 regmask=[allIntButFP] minReg=1 last>
<RefPosition #290 @295 RefTypeDef <Ivl:60> ADD BB11 regmask=[allIntButFP] minReg=1>
<RefPosition #291 @297 RefTypeDef <Ivl:61> LCL_VAR BB11 regmask=[allIntButFP] minReg=1>
<RefPosition #292 @300 RefTypeUse <Ivl:61> BB11 regmask=[allIntButFP] minReg=1 last>
<RefPosition #293 @300 RefTypeUse <Ivl:60> BB11 regmask=[allIntButFP] minReg=1 last>
<RefPosition #294 @305 RefTypeDef <Ivl:62> LCL_VAR BB11 regmask=[allIntButFP] minReg=1>
<RefPosition #295 @306 RefTypeUse <Ivl:62> BB11 regmask=[allIntButFP] minReg=1 last>
<RefPosition #296 @312 RefTypeBB BB12 regmask=[] minReg=1>
<RefPosition #297 @317 RefTypeDef <Ivl:63> LCL_VAR BB12 regmask=[allIntButFP] minReg=1>
<RefPosition #298 @318 RefTypeUse <Ivl:63> BB12 regmask=[allIntButFP] minReg=1 last>
<RefPosition #299 @321 RefTypeDef <Ivl:64> LCL_VAR BB12 regmask=[allIntButFP] minReg=1>
<RefPosition #300 @324 RefTypeUse <Ivl:64> BB12 regmask=[allIntButFP] minReg=1 last>
<RefPosition #301 @325 RefTypeDef <Ivl:65> ADD BB12 regmask=[rdx] minReg=1>
<RefPosition #302 @326 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #303 @326 RefTypeUse <Ivl:65> BB12 regmask=[rdx] minReg=1 last fixed>
<RefPosition #304 @327 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #305 @327 RefTypeDef <Ivl:66> PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed>
<RefPosition #306 @329 RefTypeDef <Ivl:67> CNS_INT BB12 regmask=[rcx] minReg=1>
<RefPosition #307 @330 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #308 @330 RefTypeUse <Ivl:67> BB12 regmask=[rcx] minReg=1 last fixed>
<RefPosition #309 @331 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #310 @331 RefTypeDef <Ivl:68> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed>
<RefPosition #311 @332 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #312 @332 RefTypeUse <Ivl:66> BB12 regmask=[rdx] minReg=1 last fixed>
<RefPosition #313 @332 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #314 @332 RefTypeUse <Ivl:68> BB12 regmask=[rcx] minReg=1 last fixed>
<RefPosition #315 @333 RefTypeKill <Reg:rax> BB12 regmask=[rax] minReg=1 last>
<RefPosition #316 @333 RefTypeKill <Reg:rcx> BB12 regmask=[rcx] minReg=1 last>
<RefPosition #317 @333 RefTypeKill <Reg:rdx> BB12 regmask=[rdx] minReg=1 last>
<RefPosition #318 @333 RefTypeKill <Reg:r8 > BB12 regmask=[r8] minReg=1 last>
<RefPosition #319 @333 RefTypeKill <Reg:r9 > BB12 regmask=[r9] minReg=1 last>
<RefPosition #320 @333 RefTypeKill <Reg:r10> BB12 regmask=[r10] minReg=1 last>
<RefPosition #321 @333 RefTypeKill <Reg:r11> BB12 regmask=[r11] minReg=1 last>
<RefPosition #322 @333 RefTypeFixedReg <Reg:rax> BB12 regmask=[rax] minReg=1>
<RefPosition #323 @333 RefTypeDef <Ivl:69> CALL BB12 regmask=[rax] minReg=1 fixed>
<RefPosition #324 @334 RefTypeUse <Ivl:69> BB12 regmask=[allIntButFP] minReg=1 last>
<RefPosition #325 @337 RefTypeDef <Ivl:70> LCL_VAR BB12 regmask=[rdx] minReg=1>
<RefPosition #326 @338 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #327 @338 RefTypeUse <Ivl:70> BB12 regmask=[rdx] minReg=1 last fixed>
<RefPosition #328 @339 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #329 @339 RefTypeDef <Ivl:71> PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed>
<RefPosition #330 @341 RefTypeDef <Ivl:72> CNS_INT BB12 regmask=[rcx] minReg=1>
<RefPosition #331 @342 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #332 @342 RefTypeUse <Ivl:72> BB12 regmask=[rcx] minReg=1 last fixed>
<RefPosition #333 @343 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #334 @343 RefTypeDef <Ivl:73> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed>
<RefPosition #335 @344 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #336 @344 RefTypeUse <Ivl:71> BB12 regmask=[rdx] minReg=1 last fixed>
<RefPosition #337 @344 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #338 @344 RefTypeUse <Ivl:73> BB12 regmask=[rcx] minReg=1 last fixed>
<RefPosition #339 @345 RefTypeKill <Reg:rax> BB12 regmask=[rax] minReg=1 last>
<RefPosition #340 @345 RefTypeKill <Reg:rcx> BB12 regmask=[rcx] minReg=1 last>
<RefPosition #341 @345 RefTypeKill <Reg:rdx> BB12 regmask=[rdx] minReg=1 last>
<RefPosition #342 @345 RefTypeKill <Reg:r8 > BB12 regmask=[r8] minReg=1 last>
<RefPosition #343 @345 RefTypeKill <Reg:r9 > BB12 regmask=[r9] minReg=1 last>
<RefPosition #344 @345 RefTypeKill <Reg:r10> BB12 regmask=[r10] minReg=1 last>
<RefPosition #345 @345 RefTypeKill <Reg:r11> BB12 regmask=[r11] minReg=1 last>
<RefPosition #346 @345 RefTypeFixedReg <Reg:rax> BB12 regmask=[rax] minReg=1>
<RefPosition #347 @345 RefTypeDef <Ivl:74> CALL BB12 regmask=[rax] minReg=1 fixed>
<RefPosition #348 @346 RefTypeUse <Ivl:74> BB12 regmask=[allIntButFP] minReg=1 last>
<RefPosition #349 @355 RefTypeDef <Ivl:75> NE BB12 regmask=[allIntButFP] minReg=1>
<RefPosition #350 @356 RefTypeUse <Ivl:75> BB12 regmask=[allIntButFP] minReg=1 last>
<RefPosition #351 @368 RefTypeBB BB13 regmask=[] minReg=1>
<RefPosition #352 @377 RefTypeDef <Ivl:76> LCL_VAR BB13 regmask=[rcx] minReg=1>
<RefPosition #353 @378 RefTypeFixedReg <Reg:rcx> BB13 regmask=[rcx] minReg=1>
<RefPosition #354 @378 RefTypeUse <Ivl:76> BB13 regmask=[rcx] minReg=1 last fixed>
<RefPosition #355 @379 RefTypeFixedReg <Reg:rcx> BB13 regmask=[rcx] minReg=1>
<RefPosition #356 @379 RefTypeDef <Ivl:77> PUTARG_REG BB13 regmask=[rcx] minReg=1 fixed>
<RefPosition #357 @381 RefTypeDef <Ivl:78> LCL_VAR BB13 regmask=[allIntButFP] minReg=1>
<RefPosition #358 @384 RefTypeUse <Ivl:78> BB13 regmask=[allIntButFP] minReg=1 last>
<RefPosition #359 @385 RefTypeDef <Ivl:79> IND BB13 regmask=[allIntButFP] minReg=1>
<RefPosition #360 @388 RefTypeUse <Ivl:79> BB13 regmask=[allIntButFP] minReg=1 last>
<RefPosition #361 @389 RefTypeDef <Ivl:80> IND BB13 regmask=[allIntButFP] minReg=1>
<RefPosition #362 @394 RefTypeFixedReg <Reg:rcx> BB13 regmask=[rcx] minReg=1>
<RefPosition #363 @394 RefTypeUse <Ivl:77> BB13 regmask=[rcx] minReg=1 last fixed>
<RefPosition #364 @394 RefTypeUse <Ivl:80> BB13 regmask=[allIntButFP] minReg=1 last>
<RefPosition #365 @395 RefTypeKill <Reg:rax> BB13 regmask=[rax] minReg=1 last>
<RefPosition #366 @395 RefTypeKill <Reg:rcx> BB13 regmask=[rcx] minReg=1 last>
<RefPosition #367 @395 RefTypeKill <Reg:rdx> BB13 regmask=[rdx] minReg=1 last>
<RefPosition #368 @395 RefTypeKill <Reg:r8 > BB13 regmask=[r8] minReg=1 last>
<RefPosition #369 @395 RefTypeKill <Reg:r9 > BB13 regmask=[r9] minReg=1 last>
<RefPosition #370 @395 RefTypeKill <Reg:r10> BB13 regmask=[r10] minReg=1 last>
<RefPosition #371 @395 RefTypeKill <Reg:r11> BB13 regmask=[r11] minReg=1 last>
<RefPosition #372 @395 RefTypeFixedReg <Reg:rax> BB13 regmask=[rax] minReg=1>
<RefPosition #373 @395 RefTypeDef <Ivl:81> CALL BB13 regmask=[rax] minReg=1 fixed>
<RefPosition #374 @396 RefTypeUse <Ivl:81> BB13 regmask=[allIntButFP] minReg=1 last>
<RefPosition #375 @401 RefTypeDef <Ivl:82> LCL_VAR BB13 regmask=[allIntButFP] minReg=1>
<RefPosition #376 @402 RefTypeUse <Ivl:82> BB13 regmask=[allIntButFP] minReg=1 last>
<RefPosition #377 @403 RefTypeDef <Ivl:83> CAST BB13 regmask=[allIntButFP] minReg=1>
<RefPosition #378 @404 RefTypeUse <Ivl:83> BB13 regmask=[allIntButFP] minReg=1 last>
<RefPosition #379 @410 RefTypeBB BB14 regmask=[] minReg=1>
<RefPosition #380 @419 RefTypeKill <Reg:rax> BB14 regmask=[rax] minReg=1 last>
<RefPosition #381 @419 RefTypeKill <Reg:rcx> BB14 regmask=[rcx] minReg=1 last>
<RefPosition #382 @419 RefTypeKill <Reg:rdx> BB14 regmask=[rdx] minReg=1 last>
<RefPosition #383 @419 RefTypeKill <Reg:r8 > BB14 regmask=[r8] minReg=1 last>
<RefPosition #384 @419 RefTypeKill <Reg:r9 > BB14 regmask=[r9] minReg=1 last>
<RefPosition #385 @419 RefTypeKill <Reg:r10> BB14 regmask=[r10] minReg=1 last>
<RefPosition #386 @419 RefTypeKill <Reg:r11> BB14 regmask=[r11] minReg=1 last>
<RefPosition #387 @419 RefTypeFixedReg <Reg:rax> BB14 regmask=[rax] minReg=1>
<RefPosition #388 @419 RefTypeDef <Ivl:84> CALL BB14 regmask=[rax] minReg=1 fixed>
<RefPosition #389 @420 RefTypeUse <Ivl:84> BB14 regmask=[allIntButFP] minReg=1 last>
<RefPosition #390 @425 RefTypeDef <Ivl:85> LCL_VAR BB14 regmask=[allIntButFP] minReg=1>
<RefPosition #391 @426 RefTypeUse <Ivl:85> BB14 regmask=[allIntButFP] minReg=1 last>
<RefPosition #392 @427 RefTypeDef <Ivl:86> CAST BB14 regmask=[allIntButFP] minReg=1>
<RefPosition #393 @428 RefTypeUse <Ivl:86> BB14 regmask=[allIntButFP] minReg=1 last>
<RefPosition #394 @434 RefTypeBB BB15 regmask=[] minReg=1>
<RefPosition #395 @439 RefTypeDef <Ivl:87> LCL_VAR BB15 regmask=[rax] minReg=1>
<RefPosition #396 @440 RefTypeFixedReg <Reg:rax> BB15 regmask=[rax] minReg=1>
<RefPosition #397 @440 RefTypeUse <Ivl:87> BB15 regmask=[rax] minReg=1 last fixed>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The first column provides the basic information about the RefPosition, with its type (e.g. Def,
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive.
Columns are only printed up to the last modifed register, which may increase during allocation,
in which case additional columns will appear.
Registers which are not marked modified have ---- in their column.
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
| | | | | | | | | |
0.#0 BB1 PredBB0 | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
4.#1 BB2 PredBB1 | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
16.#2 BB3 PredBB2 | | | | | | | | | |
19.#3 rax Kill Keep rax | | | | | | | | | |
19.#4 rcx Kill Keep rcx | | | | | | | | | |
19.#5 rdx Kill Keep rdx | | | | | | | | | |
19.#6 r8 Kill Keep r8 | | | | | | | | | |
19.#7 r9 Kill Keep r9 | | | | | | | | | |
19.#8 r10 Kill Keep r10 | | | | | | | | | |
19.#9 r11 Kill Keep r11 | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
20.#10 BB4 PredBB2 | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
22.#11 BB5 PredBB4 | | | | | | | | | |
31.#12 C0 Def Alloc rcx | |C0 a| | | | | | | |
32.#13 rcx Fixd Keep rcx | |C0 a| | | | | | | |
32.#14 C0 Use * Keep rcx | |C0 a| | | | | | | |
33.#15 rcx Fixd Keep rcx | | | | | | | | | |
33.#16 I1 Def Alloc rcx | |I1 a| | | | | | | |
34.#17 rcx Fixd Keep rcx | |I1 a| | | | | | | |
34.#18 I1 Use * Keep rcx | |I1 a| | | | | | | |
35.#19 rax Kill Keep rax | | | | | | | | | |
35.#20 rcx Kill Keep rcx | | | | | | | | | |
35.#21 rdx Kill Keep rdx | | | | | | | | | |
35.#22 r8 Kill Keep r8 | | | | | | | | | |
35.#23 r9 Kill Keep r9 | | | | | | | | | |
35.#24 r10 Kill Keep r10 | | | | | | | | | |
35.#25 r11 Kill Keep r11 | | | | | | | | | |
35.#26 rax Fixd Keep rax | | | | | | | | | |
35.#27 I2 Def Alloc rax |I2 a| | | | | | | | |
36.#28 I2 Use * Keep rax |I2 a| | | | | | | | |
39.#29 I3 Def Alloc rcx | |I3 a| | | | | | | |
40.#30 rcx Fixd Keep rcx | |I3 a| | | | | | | |
40.#31 I3 Use * Keep rcx | |I3 a| | | | | | | |
41.#32 rcx Fixd Keep rcx | | | | | | | | | |
41.#33 I4 Def Alloc rcx | |I4 a| | | | | | | |
42.#34 rcx Fixd Keep rcx | |I4 a| | | | | | | |
42.#35 I4 Use * Keep rcx | |I4 a| | | | | | | |
43.#36 rax Kill Keep rax | | | | | | | | | |
43.#37 rcx Kill Keep rcx | | | | | | | | | |
43.#38 rdx Kill Keep rdx | | | | | | | | | |
43.#39 r8 Kill Keep r8 | | | | | | | | | |
43.#40 r9 Kill Keep r9 | | | | | | | | | |
43.#41 r10 Kill Keep r10 | | | | | | | | | |
43.#42 r11 Kill Keep r11 | | | | | | | | | |
43.#43 rax Fixd Keep rax | | | | | | | | | |
43.#44 I5 Def Alloc rax |I5 a| | | | | | | | |
44.#45 I5 Use * Keep rax |I5 a| | | | | | | | |
49.#46 C6 Def Alloc rcx | |C6 a| | | | | | | |
50.#47 rcx Fixd Keep rcx | |C6 a| | | | | | | |
50.#48 C6 Use * Keep rcx | |C6 a| | | | | | | |
51.#49 rcx Fixd Keep rcx | | | | | | | | | |
51.#50 I7 Def Alloc rcx | |I7 a| | | | | | | |
52.#51 rcx Fixd Keep rcx | |I7 a| | | | | | | |
52.#52 I7 Use * Keep rcx | |I7 a| | | | | | | |
53.#53 rax Kill Keep rax | | | | | | | | | |
53.#54 rcx Kill Keep rcx | | | | | | | | | |
53.#55 rdx Kill Keep rdx | | | | | | | | | |
53.#56 r8 Kill Keep r8 | | | | | | | | | |
53.#57 r9 Kill Keep r9 | | | | | | | | | |
53.#58 r10 Kill Keep r10 | | | | | | | | | |
53.#59 r11 Kill Keep r11 | | | | | | | | | |
53.#60 rax Fixd Keep rax | | | | | | | | | |
53.#61 I8 Def Alloc rax |I8 a| | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
54.#62 I8 Use * Keep rax |I8 a| | | | | | | | |
57.#63 I9 Def Alloc rcx | |I9 a| | | | | | | |
58.#64 rcx Fixd Keep rcx | |I9 a| | | | | | | |
58.#65 I9 Use * Keep rcx | |I9 a| | | | | | | |
59.#66 rcx Fixd Keep rcx | | | | | | | | | |
59.#67 I10 Def Alloc rcx | |I10a| | | | | | | |
60.#68 rcx Fixd Keep rcx | |I10a| | | | | | | |
60.#69 I10 Use * Keep rcx | |I10a| | | | | | | |
61.#70 rax Kill Keep rax | | | | | | | | | |
61.#71 rcx Kill Keep rcx | | | | | | | | | |
61.#72 rdx Kill Keep rdx | | | | | | | | | |
61.#73 r8 Kill Keep r8 | | | | | | | | | |
61.#74 r9 Kill Keep r9 | | | | | | | | | |
61.#75 r10 Kill Keep r10 | | | | | | | | | |
61.#76 r11 Kill Keep r11 | | | | | | | | | |
61.#77 rax Fixd Keep rax | | | | | | | | | |
61.#78 I11 Def Alloc rax |I11a| | | | | | | | |
62.#79 I11 Use * Keep rax |I11a| | | | | | | | |
67.#80 I12 Def Alloc rcx | |I12a| | | | | | | |
68.#81 rcx Fixd Keep rcx | |I12a| | | | | | | |
68.#82 I12 Use * Keep rcx | |I12a| | | | | | | |
69.#83 rcx Fixd Keep rcx | | | | | | | | | |
69.#84 I13 Def Alloc rcx | |I13a| | | | | | | |
71.#85 I14 Def Alloc rdx | |I13a|I14a| | | | | | |
72.#86 rdx Fixd Keep rdx | |I13a|I14a| | | | | | |
72.#87 I14 Use * Keep rdx | |I13a|I14a| | | | | | |
73.#88 rdx Fixd Keep rdx | |I13a| | | | | | | |
73.#89 I15 Def Alloc rdx | |I13a|I15a| | | | | | |
74.#90 rcx Fixd Keep rcx | |I13a|I15a| | | | | | |
74.#91 I13 Use * Keep rcx | |I13a|I15a| | | | | | |
74.#92 rdx Fixd Keep rdx | |I13a|I15a| | | | | | |
74.#93 I15 Use * Keep rdx | |I13a|I15a| | | | | | |
75.#94 rax Kill Keep rax | | | | | | | | | |
75.#95 rcx Kill Keep rcx | | | | | | | | | |
75.#96 rdx Kill Keep rdx | | | | | | | | | |
75.#97 r8 Kill Keep r8 | | | | | | | | | |
75.#98 r9 Kill Keep r9 | | | | | | | | | |
75.#99 r10 Kill Keep r10 | | | | | | | | | |
75.#100 r11 Kill Keep r11 | | | | | | | | | |
75.#101 rax Fixd Keep rax | | | | | | | | | |
75.#102 I16 Def Alloc rax |I16a| | | | | | | | |
76.#103 I16 Use * Keep rax |I16a| | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
88.#104 BB6 PredBB5 | | | | | | | | | |
93.#105 C17 Def Alloc rcx | |C17a| | | | | | | |
94.#106 rcx Fixd Keep rcx | |C17a| | | | | | | |
94.#107 C17 Use * Keep rcx | |C17a| | | | | | | |
95.#108 rcx Fixd Keep rcx | | | | | | | | | |
95.#109 I18 Def Alloc rcx | |I18a| | | | | | | |
96.#110 rcx Fixd Keep rcx | |I18a| | | | | | | |
96.#111 I18 Use * Keep rcx | |I18a| | | | | | | |
97.#112 rax Kill Keep rax | | | | | | | | | |
97.#113 rcx Kill Keep rcx | | | | | | | | | |
97.#114 rdx Kill Keep rdx | | | | | | | | | |
97.#115 r8 Kill Keep r8 | | | | | | | | | |
97.#116 r9 Kill Keep r9 | | | | | | | | | |
97.#117 r10 Kill Keep r10 | | | | | | | | | |
97.#118 r11 Kill Keep r11 | | | | | | | | | |
97.#119 rax Fixd Keep rax | | | | | | | | | |
97.#120 I19 Def Alloc rax |I19a| | | | | | | | |
98.#121 I19 Use * Keep rax |I19a| | | | | | | | |
101.#122 I20 Def Alloc rcx | |I20a| | | | | | | |
102.#123 rcx Fixd Keep rcx | |I20a| | | | | | | |
102.#124 I20 Use * Keep rcx | |I20a| | | | | | | |
103.#125 rcx Fixd Keep rcx | | | | | | | | | |
103.#126 I21 Def Alloc rcx | |I21a| | | | | | | |
104.#127 rcx Fixd Keep rcx | |I21a| | | | | | | |
104.#128 I21 Use * Keep rcx | |I21a| | | | | | | |
105.#129 rax Kill Keep rax | | | | | | | | | |
105.#130 rcx Kill Keep rcx | | | | | | | | | |
105.#131 rdx Kill Keep rdx | | | | | | | | | |
105.#132 r8 Kill Keep r8 | | | | | | | | | |
105.#133 r9 Kill Keep r9 | | | | | | | | | |
105.#134 r10 Kill Keep r10 | | | | | | | | | |
105.#135 r11 Kill Keep r11 | | | | | | | | | |
105.#136 rax Fixd Keep rax | | | | | | | | | |
105.#137 I22 Def Alloc rax |I22a| | | | | | | | |
106.#138 I22 Use * Keep rax |I22a| | | | | | | | |
111.#139 C23 Def Alloc rcx | |C23a| | | | | | | |
112.#140 rcx Fixd Keep rcx | |C23a| | | | | | | |
112.#141 C23 Use * Keep rcx | |C23a| | | | | | | |
113.#142 rcx Fixd Keep rcx | | | | | | | | | |
113.#143 I24 Def Alloc rcx | |I24a| | | | | | | |
114.#144 rcx Fixd Keep rcx | |I24a| | | | | | | |
114.#145 I24 Use * Keep rcx | |I24a| | | | | | | |
115.#146 rax Kill Keep rax | | | | | | | | | |
115.#147 rcx Kill Keep rcx | | | | | | | | | |
115.#148 rdx Kill Keep rdx | | | | | | | | | |
115.#149 r8 Kill Keep r8 | | | | | | | | | |
115.#150 r9 Kill Keep r9 | | | | | | | | | |
115.#151 r10 Kill Keep r10 | | | | | | | | | |
115.#152 r11 Kill Keep r11 | | | | | | | | | |
115.#153 rax Fixd Keep rax | | | | | | | | | |
115.#154 I25 Def Alloc rax |I25a| | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
116.#155 I25 Use * Keep rax |I25a| | | | | | | | |
119.#156 I26 Def Alloc rcx | |I26a| | | | | | | |
120.#157 rcx Fixd Keep rcx | |I26a| | | | | | | |
120.#158 I26 Use * Keep rcx | |I26a| | | | | | | |
121.#159 rcx Fixd Keep rcx | | | | | | | | | |
121.#160 I27 Def Alloc rcx | |I27a| | | | | | | |
122.#161 rcx Fixd Keep rcx | |I27a| | | | | | | |
122.#162 I27 Use * Keep rcx | |I27a| | | | | | | |
123.#163 rax Kill Keep rax | | | | | | | | | |
123.#164 rcx Kill Keep rcx | | | | | | | | | |
123.#165 rdx Kill Keep rdx | | | | | | | | | |
123.#166 r8 Kill Keep r8 | | | | | | | | | |
123.#167 r9 Kill Keep r9 | | | | | | | | | |
123.#168 r10 Kill Keep r10 | | | | | | | | | |
123.#169 r11 Kill Keep r11 | | | | | | | | | |
123.#170 rax Fixd Keep rax | | | | | | | | | |
123.#171 I28 Def Alloc rax |I28a| | | | | | | | |
124.#172 I28 Use * Keep rax |I28a| | | | | | | | |
129.#173 I29 Def Alloc rcx | |I29a| | | | | | | |
130.#174 rcx Fixd Keep rcx | |I29a| | | | | | | |
130.#175 I29 Use * Keep rcx | |I29a| | | | | | | |
131.#176 rcx Fixd Keep rcx | | | | | | | | | |
131.#177 I30 Def Alloc rcx | |I30a| | | | | | | |
133.#178 I31 Def Alloc rdx | |I30a|I31a| | | | | | |
134.#179 rdx Fixd Keep rdx | |I30a|I31a| | | | | | |
134.#180 I31 Use * Keep rdx | |I30a|I31a| | | | | | |
135.#181 rdx Fixd Keep rdx | |I30a| | | | | | | |
135.#182 I32 Def Alloc rdx | |I30a|I32a| | | | | | |
136.#183 rcx Fixd Keep rcx | |I30a|I32a| | | | | | |
136.#184 I30 Use * Keep rcx | |I30a|I32a| | | | | | |
136.#185 rdx Fixd Keep rdx | |I30a|I32a| | | | | | |
136.#186 I32 Use * Keep rdx | |I30a|I32a| | | | | | |
137.#187 rax Kill Keep rax | | | | | | | | | |
137.#188 rcx Kill Keep rcx | | | | | | | | | |
137.#189 rdx Kill Keep rdx | | | | | | | | | |
137.#190 r8 Kill Keep r8 | | | | | | | | | |
137.#191 r9 Kill Keep r9 | | | | | | | | | |
137.#192 r10 Kill Keep r10 | | | | | | | | | |
137.#193 r11 Kill Keep r11 | | | | | | | | | |
137.#194 rax Fixd Keep rax | | | | | | | | | |
137.#195 I33 Def Alloc rax |I33a| | | | | | | | |
138.#196 I33 Use * Keep rax |I33a| | | | | | | | |
145.#197 I34 Def Alloc rcx | |I34a| | | | | | | |
146.#198 I34 Use * Keep rcx | |I34a| | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
148.#199 BB7 PredBB5 | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
156.#200 BB8 PredBB6 | | | | | | | | | |
159.#201 I35 Def Alloc rcx | |I35a| | | | | | | |
160.#202 I35 Use * Keep rcx | |I35a| | | | | | | |
161.#203 I36 Def Alloc rcx | |I36a| | | | | | | |
162.#204 I36 Use * Keep rcx | |I36a| | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
174.#205 BB9 PredBB8 | | | | | | | | | |
183.#206 I37 Def Alloc rcx | |I37a| | | | | | | |
186.#207 I37 Use * Keep rcx | |I37a| | | | | | | |
187.#208 I38 Def Alloc rcx | |I38a| | | | | | | |
188.#209 I38 Use * Keep rcx | |I38a| | | | | | | |
193.#210 I39 Def Alloc rcx | |I39a| | | | | | | |
200.#211 I40 Def Alloc mm0 | |I39a| | | | | | | |
200.#212 I39 Use * Keep rcx | |I39a| | | | | | | |
200.#213 I40 Use * Keep mm0 | |I39a| | | | | | | |
205.#214 I41 Def Alloc rcx | |I41a| | | | | | | |
206.#215 I41 Use * Keep rcx | |I41a| | | | | | | |
209.#216 I42 Def Alloc rcx | |I42a| | | | | | | |
210.#217 rcx Fixd Keep rcx | |I42a| | | | | | | |
210.#218 I42 Use * Keep rcx | |I42a| | | | | | | |
211.#219 rcx Fixd Keep rcx | | | | | | | | | |
211.#220 I43 Def Alloc rcx | |I43a| | | | | | | |
212.#221 rcx Fixd Keep rcx | |I43a| | | | | | | |
212.#222 I43 Use * Keep rcx | |I43a| | | | | | | |
213.#223 rax Kill Keep rax | | | | | | | | | |
213.#224 rcx Kill Keep rcx | | | | | | | | | |
213.#225 rdx Kill Keep rdx | | | | | | | | | |
213.#226 r8 Kill Keep r8 | | | | | | | | | |
213.#227 r9 Kill Keep r9 | | | | | | | | | |
213.#228 r10 Kill Keep r10 | | | | | | | | | |
213.#229 r11 Kill Keep r11 | | | | | | | | | |
213.#230 rax Fixd Keep rax | | | | | | | | | |
213.#231 I44 Def Alloc rax |I44a| | | | | | | | |
214.#232 I44 Use * Keep rax |I44a| | | | | | | | |
219.#233 I45 Def Alloc rcx | |I45a| | | | | | | |
222.#234 I45 Use * Keep rcx | |I45a| | | | | | | |
223.#235 I46 Def Alloc rcx | |I46a| | | | | | | |
224.#236 I46 Use * Keep rcx | |I46a| | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
236.#237 BB10 PredBB9 | | | | | | | | | |
245.#238 I47 Def Alloc rcx | |I47a| | | | | | | |
246.#239 rcx Fixd Keep rcx | |I47a| | | | | | | |
246.#240 I47 Use * Keep rcx | |I47a| | | | | | | |
247.#241 rcx Fixd Keep rcx | | | | | | | | | |
247.#242 I48 Def Alloc rcx | |I48a| | | | | | | |
248.#243 rcx Fixd Keep rcx | |I48a| | | | | | | |
248.#244 I48 Use * Keep rcx | |I48a| | | | | | | |
249.#245 rax Kill Keep rax | | | | | | | | | |
249.#246 rcx Kill Keep rcx | | | | | | | | | |
249.#247 rdx Kill Keep rdx | | | | | | | | | |
249.#248 r8 Kill Keep r8 | | | | | | | | | |
249.#249 r9 Kill Keep r9 | | | | | | | | | |
249.#250 r10 Kill Keep r10 | | | | | | | | | |
249.#251 r11 Kill Keep r11 | | | | | | | | | |
249.#252 rax Fixd Keep rax | | | | | | | | | |
249.#253 I49 Def Alloc rax |I49a| | | | | | | | |
250.#254 I49 Use * Keep rax |I49a| | | | | | | | |
255.#255 I50 Def Alloc rcx | |I50a| | | | | | | |
256.#256 I50 Use * Keep rcx | |I50a| | | | | | | |
257.#257 I51 Def Alloc rcx | |I51a| | | | | | | |
258.#258 I51 Use * Keep rcx | |I51a| | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
264.#259 BB11 PredBB9 | | | | | | | | | |
269.#260 I52 Def Alloc rcx | |I52a| | | | | | | |
270.#261 rcx Fixd Keep rcx | |I52a| | | | | | | |
270.#262 I52 Use * Keep rcx | |I52a| | | | | | | |
271.#263 rcx Fixd Keep rcx | | | | | | | | | |
271.#264 I53 Def Alloc rcx | |I53a| | | | | | | |
273.#265 I54 Def Alloc rdx | |I53a|I54a| | | | | | |
274.#266 rdx Fixd Keep rdx | |I53a|I54a| | | | | | |
274.#267 I54 Use * Keep rdx | |I53a|I54a| | | | | | |
275.#268 rdx Fixd Keep rdx | |I53a| | | | | | | |
275.#269 I55 Def Alloc rdx | |I53a|I55a| | | | | | |
276.#270 rcx Fixd Keep rcx | |I53a|I55a| | | | | | |
276.#271 I53 Use * Keep rcx | |I53a|I55a| | | | | | |
276.#272 rdx Fixd Keep rdx | |I53a|I55a| | | | | | |
276.#273 I55 Use * Keep rdx | |I53a|I55a| | | | | | |
277.#274 rax Kill Keep rax | | | | | | | | | |
277.#275 rcx Kill Keep rcx | | | | | | | | | |
277.#276 rdx Kill Keep rdx | | | | | | | | | |
277.#277 r8 Kill Keep r8 | | | | | | | | | |
277.#278 r9 Kill Keep r9 | | | | | | | | | |
277.#279 r10 Kill Keep r10 | | | | | | | | | |
277.#280 r11 Kill Keep r11 | | | | | | | | | |
277.#281 rax Fixd Keep rax | | | | | | | | | |
277.#282 I56 Def Alloc rax |I56a| | | | | | | | |
278.#283 I56 Use * Keep rax |I56a| | | | | | | | |
283.#284 I57 Def Alloc rdx | | |I57a| | | | | | |
284.#285 I57 Use * Keep rdx | | |I57a| | | | | | |
285.#286 I58 Def Alloc rdx | | |I58a| | | | | | |
286.#287 I58 Use * Keep rdx | | |I58a| | | | | | |
291.#288 I59 Def Alloc rdx | | |I59a| | | | | | |
294.#289 I59 Use * Keep rdx | | |I59a| | | | | | |
295.#290 I60 Def Alloc rdx | | |I60a| | | | | | |
297.#291 I61 Def Alloc rcx | |I61a|I60a| | | | | | |
300.#292 I61 Use * Keep rcx | |I61a|I60a| | | | | | |
300.#293 I60 Use * Keep rdx | |I61a|I60a| | | | | | |
305.#294 I62 Def Alloc rdx | | |I62a| | | | | | |
306.#295 I62 Use * Keep rdx | | |I62a| | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
312.#296 BB12 PredBB8 | | | | | | | | | |
317.#297 I63 Def Alloc rdx | | |I63a| | | | | | |
318.#298 I63 Use * Keep rdx | | |I63a| | | | | | |
321.#299 I64 Def Alloc rdx | | |I64a| | | | | | |
324.#300 I64 Use * Keep rdx | | |I64a| | | | | | |
325.#301 I65 Def Alloc rdx | | |I65a| | | | | | |
326.#302 rdx Fixd Keep rdx | | |I65a| | | | | | |
326.#303 I65 Use * Keep rdx | | |I65a| | | | | | |
327.#304 rdx Fixd Keep rdx | | | | | | | | | |
327.#305 I66 Def Alloc rdx | | |I66a| | | | | | |
329.#306 C67 Def Alloc rcx | |C67a|I66a| | | | | | |
330.#307 rcx Fixd Keep rcx | |C67a|I66a| | | | | | |
330.#308 C67 Use * Keep rcx | |C67a|I66a| | | | | | |
331.#309 rcx Fixd Keep rcx | | |I66a| | | | | | |
331.#310 I68 Def Alloc rcx | |I68a|I66a| | | | | | |
332.#311 rdx Fixd Keep rdx | |I68a|I66a| | | | | | |
332.#312 I66 Use * Keep rdx | |I68a|I66a| | | | | | |
332.#313 rcx Fixd Keep rcx | |I68a|I66a| | | | | | |
332.#314 I68 Use * Keep rcx | |I68a|I66a| | | | | | |
333.#315 rax Kill Keep rax | | | | | | | | | |
333.#316 rcx Kill Keep rcx | | | | | | | | | |
333.#317 rdx Kill Keep rdx | | | | | | | | | |
333.#318 r8 Kill Keep r8 | | | | | | | | | |
333.#319 r9 Kill Keep r9 | | | | | | | | | |
333.#320 r10 Kill Keep r10 | | | | | | | | | |
333.#321 r11 Kill Keep r11 | | | | | | | | | |
333.#322 rax Fixd Keep rax | | | | | | | | | |
333.#323 I69 Def Alloc rax |I69a| | | | | | | | |
334.#324 I69 Use * Keep rax |I69a| | | | | | | | |
337.#325 I70 Def Alloc rdx | | |I70a| | | | | | |
338.#326 rdx Fixd Keep rdx | | |I70a| | | | | | |
338.#327 I70 Use * Keep rdx | | |I70a| | | | | | |
339.#328 rdx Fixd Keep rdx | | | | | | | | | |
339.#329 I71 Def Alloc rdx | | |I71a| | | | | | |
341.#330 C72 Def Alloc rcx | |C72a|I71a| | | | | | |
342.#331 rcx Fixd Keep rcx | |C72a|I71a| | | | | | |
342.#332 C72 Use * Keep rcx | |C72a|I71a| | | | | | |
343.#333 rcx Fixd Keep rcx | | |I71a| | | | | | |
343.#334 I73 Def Alloc rcx | |I73a|I71a| | | | | | |
344.#335 rdx Fixd Keep rdx | |I73a|I71a| | | | | | |
344.#336 I71 Use * Keep rdx | |I73a|I71a| | | | | | |
344.#337 rcx Fixd Keep rcx | |I73a|I71a| | | | | | |
344.#338 I73 Use * Keep rcx | |I73a|I71a| | | | | | |
345.#339 rax Kill Keep rax | | | | | | | | | |
345.#340 rcx Kill Keep rcx | | | | | | | | | |
345.#341 rdx Kill Keep rdx | | | | | | | | | |
345.#342 r8 Kill Keep r8 | | | | | | | | | |
345.#343 r9 Kill Keep r9 | | | | | | | | | |
345.#344 r10 Kill Keep r10 | | | | | | | | | |
345.#345 r11 Kill Keep r11 | | | | | | | | | |
345.#346 rax Fixd Keep rax | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
345.#347 I74 Def Alloc rax |I74a| | | | | | | | |
346.#348 I74 Use * Keep rax |I74a| | | | | | | | |
355.#349 I75 Def Alloc rcx | |I75a| | | | | | | |
356.#350 I75 Use * Keep rcx | |I75a| | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
368.#351 BB13 PredBB12 | | | | | | | | | |
377.#352 I76 Def Alloc rcx | |I76a| | | | | | | |
378.#353 rcx Fixd Keep rcx | |I76a| | | | | | | |
378.#354 I76 Use * Keep rcx | |I76a| | | | | | | |
379.#355 rcx Fixd Keep rcx | | | | | | | | | |
379.#356 I77 Def Alloc rcx | |I77a| | | | | | | |
381.#357 I78 Def Alloc rax |I78a|I77a| | | | | | | |
384.#358 I78 Use * Keep rax |I78a|I77a| | | | | | | |
385.#359 I79 Def Alloc rax |I79a|I77a| | | | | | | |
388.#360 I79 Use * Keep rax |I79a|I77a| | | | | | | |
389.#361 I80 Def Alloc rax |I80a|I77a| | | | | | | |
394.#362 rcx Fixd Keep rcx |I80a|I77a| | | | | | | |
394.#363 I77 Use * Keep rcx |I80a|I77a| | | | | | | |
394.#364 I80 Use * Keep rax |I80a|I77a| | | | | | | |
395.#365 rax Kill Keep rax | | | | | | | | | |
395.#366 rcx Kill Keep rcx | | | | | | | | | |
395.#367 rdx Kill Keep rdx | | | | | | | | | |
395.#368 r8 Kill Keep r8 | | | | | | | | | |
395.#369 r9 Kill Keep r9 | | | | | | | | | |
395.#370 r10 Kill Keep r10 | | | | | | | | | |
395.#371 r11 Kill Keep r11 | | | | | | | | | |
395.#372 rax Fixd Keep rax | | | | | | | | | |
395.#373 I81 Def Alloc rax |I81a| | | | | | | | |
396.#374 I81 Use * Keep rax |I81a| | | | | | | | |
401.#375 I82 Def Alloc rax |I82a| | | | | | | | |
402.#376 I82 Use * Keep rax |I82a| | | | | | | | |
403.#377 I83 Def Alloc rax |I83a| | | | | | | | |
404.#378 I83 Use * Keep rax |I83a| | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
410.#379 BB14 PredBB12 | | | | | | | | | |
419.#380 rax Kill Keep rax | | | | | | | | | |
419.#381 rcx Kill Keep rcx | | | | | | | | | |
419.#382 rdx Kill Keep rdx | | | | | | | | | |
419.#383 r8 Kill Keep r8 | | | | | | | | | |
419.#384 r9 Kill Keep r9 | | | | | | | | | |
419.#385 r10 Kill Keep r10 | | | | | | | | | |
419.#386 r11 Kill Keep r11 | | | | | | | | | |
419.#387 rax Fixd Keep rax | | | | | | | | | |
419.#388 I84 Def Alloc rax |I84a| | | | | | | | |
420.#389 I84 Use * Keep rax |I84a| | | | | | | | |
425.#390 I85 Def Alloc rax |I85a| | | | | | | | |
426.#391 I85 Use * Keep rax |I85a| | | | | | | | |
427.#392 I86 Def Alloc rax |I86a| | | | | | | | |
428.#393 I86 Use * Keep rax |I86a| | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
434.#394 BB15 PredBB10 | | | | | | | | | |
439.#395 I87 Def Alloc rax |I87a| | | | | | | | |
440.#396 rax Fixd Keep rax |I87a| | | | | | | | |
440.#397 I87 Use * Keep rax | | | | | | | | | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @4 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #2 @16 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #3 @19 RefTypeKill <Reg:rax> BB03 regmask=[rax] minReg=1 last>
<RefPosition #4 @19 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] minReg=1 last>
<RefPosition #5 @19 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] minReg=1 last>
<RefPosition #6 @19 RefTypeKill <Reg:r8 > BB03 regmask=[r8] minReg=1 last>
<RefPosition #7 @19 RefTypeKill <Reg:r9 > BB03 regmask=[r9] minReg=1 last>
<RefPosition #8 @19 RefTypeKill <Reg:r10> BB03 regmask=[r10] minReg=1 last>
<RefPosition #9 @19 RefTypeKill <Reg:r11> BB03 regmask=[r11] minReg=1 last>
<RefPosition #10 @20 RefTypeBB BB04 regmask=[] minReg=1>
<RefPosition #11 @22 RefTypeBB BB05 regmask=[] minReg=1>
<RefPosition #12 @31 RefTypeDef <Ivl:0> CNS_INT BB05 regmask=[rcx] minReg=1>
<RefPosition #13 @32 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #14 @32 RefTypeUse <Ivl:0> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #15 @33 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #16 @33 RefTypeDef <Ivl:1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
<RefPosition #17 @34 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #18 @34 RefTypeUse <Ivl:1> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #19 @35 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
<RefPosition #20 @35 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #21 @35 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
<RefPosition #22 @35 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
<RefPosition #23 @35 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
<RefPosition #24 @35 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
<RefPosition #25 @35 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
<RefPosition #26 @35 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #27 @35 RefTypeDef <Ivl:2> CALL BB05 regmask=[rax] minReg=1 fixed>
<RefPosition #28 @36 RefTypeUse <Ivl:2> BB05 regmask=[rax] minReg=1 last>
<RefPosition #29 @39 RefTypeDef <Ivl:3> LCL_FLD BB05 regmask=[rcx] minReg=1>
<RefPosition #30 @40 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #31 @40 RefTypeUse <Ivl:3> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #32 @41 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #33 @41 RefTypeDef <Ivl:4> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
<RefPosition #34 @42 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #35 @42 RefTypeUse <Ivl:4> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #36 @43 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
<RefPosition #37 @43 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #38 @43 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
<RefPosition #39 @43 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
<RefPosition #40 @43 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
<RefPosition #41 @43 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
<RefPosition #42 @43 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
<RefPosition #43 @43 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #44 @43 RefTypeDef <Ivl:5> CALL BB05 regmask=[rax] minReg=1 fixed>
<RefPosition #45 @44 RefTypeUse <Ivl:5> BB05 regmask=[rax] minReg=1 last>
<RefPosition #46 @49 RefTypeDef <Ivl:6> CNS_INT BB05 regmask=[rcx] minReg=1>
<RefPosition #47 @50 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #48 @50 RefTypeUse <Ivl:6> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #49 @51 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #50 @51 RefTypeDef <Ivl:7> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
<RefPosition #51 @52 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #52 @52 RefTypeUse <Ivl:7> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #53 @53 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
<RefPosition #54 @53 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #55 @53 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
<RefPosition #56 @53 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
<RefPosition #57 @53 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
<RefPosition #58 @53 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
<RefPosition #59 @53 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
<RefPosition #60 @53 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #61 @53 RefTypeDef <Ivl:8> CALL BB05 regmask=[rax] minReg=1 fixed>
<RefPosition #62 @54 RefTypeUse <Ivl:8> BB05 regmask=[rax] minReg=1 last>
<RefPosition #63 @57 RefTypeDef <Ivl:9> LCL_FLD BB05 regmask=[rcx] minReg=1>
<RefPosition #64 @58 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #65 @58 RefTypeUse <Ivl:9> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #66 @59 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #67 @59 RefTypeDef <Ivl:10> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
<RefPosition #68 @60 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #69 @60 RefTypeUse <Ivl:10> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #70 @61 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
<RefPosition #71 @61 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #72 @61 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
<RefPosition #73 @61 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
<RefPosition #74 @61 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
<RefPosition #75 @61 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
<RefPosition #76 @61 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
<RefPosition #77 @61 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #78 @61 RefTypeDef <Ivl:11> CALL BB05 regmask=[rax] minReg=1 fixed>
<RefPosition #79 @62 RefTypeUse <Ivl:11> BB05 regmask=[rax] minReg=1 last>
<RefPosition #80 @67 RefTypeDef <Ivl:12> LCL_VAR BB05 regmask=[rcx] minReg=1>
<RefPosition #81 @68 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #82 @68 RefTypeUse <Ivl:12> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #83 @69 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #84 @69 RefTypeDef <Ivl:13> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
<RefPosition #85 @71 RefTypeDef <Ivl:14> LCL_VAR BB05 regmask=[rdx] minReg=1>
<RefPosition #86 @72 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #87 @72 RefTypeUse <Ivl:14> BB05 regmask=[rdx] minReg=1 last fixed>
<RefPosition #88 @73 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #89 @73 RefTypeDef <Ivl:15> PUTARG_REG BB05 regmask=[rdx] minReg=1 fixed>
<RefPosition #90 @74 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #91 @74 RefTypeUse <Ivl:13> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #92 @74 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #93 @74 RefTypeUse <Ivl:15> BB05 regmask=[rdx] minReg=1 last fixed>
<RefPosition #94 @75 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
<RefPosition #95 @75 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #96 @75 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
<RefPosition #97 @75 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
<RefPosition #98 @75 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
<RefPosition #99 @75 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
<RefPosition #100 @75 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
<RefPosition #101 @75 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #102 @75 RefTypeDef <Ivl:16> CALL BB05 regmask=[rax] minReg=1 fixed>
<RefPosition #103 @76 RefTypeUse <Ivl:16> BB05 regmask=[rax] minReg=1 last>
<RefPosition #104 @88 RefTypeBB BB06 regmask=[] minReg=1>
<RefPosition #105 @93 RefTypeDef <Ivl:17> CNS_INT BB06 regmask=[rcx] minReg=1>
<RefPosition #106 @94 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #107 @94 RefTypeUse <Ivl:17> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #108 @95 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #109 @95 RefTypeDef <Ivl:18> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
<RefPosition #110 @96 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #111 @96 RefTypeUse <Ivl:18> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #112 @97 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1 last>
<RefPosition #113 @97 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #114 @97 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1 last>
<RefPosition #115 @97 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1 last>
<RefPosition #116 @97 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1 last>
<RefPosition #117 @97 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1 last>
<RefPosition #118 @97 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1 last>
<RefPosition #119 @97 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #120 @97 RefTypeDef <Ivl:19> CALL BB06 regmask=[rax] minReg=1 fixed>
<RefPosition #121 @98 RefTypeUse <Ivl:19> BB06 regmask=[rax] minReg=1 last>
<RefPosition #122 @101 RefTypeDef <Ivl:20> LCL_FLD BB06 regmask=[rcx] minReg=1>
<RefPosition #123 @102 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #124 @102 RefTypeUse <Ivl:20> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #125 @103 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #126 @103 RefTypeDef <Ivl:21> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
<RefPosition #127 @104 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #128 @104 RefTypeUse <Ivl:21> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #129 @105 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1 last>
<RefPosition #130 @105 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #131 @105 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1 last>
<RefPosition #132 @105 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1 last>
<RefPosition #133 @105 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1 last>
<RefPosition #134 @105 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1 last>
<RefPosition #135 @105 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1 last>
<RefPosition #136 @105 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #137 @105 RefTypeDef <Ivl:22> CALL BB06 regmask=[rax] minReg=1 fixed>
<RefPosition #138 @106 RefTypeUse <Ivl:22> BB06 regmask=[rax] minReg=1 last>
<RefPosition #139 @111 RefTypeDef <Ivl:23> CNS_INT BB06 regmask=[rcx] minReg=1>
<RefPosition #140 @112 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #141 @112 RefTypeUse <Ivl:23> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #142 @113 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #143 @113 RefTypeDef <Ivl:24> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
<RefPosition #144 @114 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #145 @114 RefTypeUse <Ivl:24> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #146 @115 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1 last>
<RefPosition #147 @115 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #148 @115 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1 last>
<RefPosition #149 @115 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1 last>
<RefPosition #150 @115 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1 last>
<RefPosition #151 @115 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1 last>
<RefPosition #152 @115 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1 last>
<RefPosition #153 @115 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #154 @115 RefTypeDef <Ivl:25> CALL BB06 regmask=[rax] minReg=1 fixed>
<RefPosition #155 @116 RefTypeUse <Ivl:25> BB06 regmask=[rax] minReg=1 last>
<RefPosition #156 @119 RefTypeDef <Ivl:26> LCL_FLD BB06 regmask=[rcx] minReg=1>
<RefPosition #157 @120 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #158 @120 RefTypeUse <Ivl:26> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #159 @121 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #160 @121 RefTypeDef <Ivl:27> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
<RefPosition #161 @122 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #162 @122 RefTypeUse <Ivl:27> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #163 @123 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1 last>
<RefPosition #164 @123 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #165 @123 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1 last>
<RefPosition #166 @123 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1 last>
<RefPosition #167 @123 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1 last>
<RefPosition #168 @123 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1 last>
<RefPosition #169 @123 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1 last>
<RefPosition #170 @123 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #171 @123 RefTypeDef <Ivl:28> CALL BB06 regmask=[rax] minReg=1 fixed>
<RefPosition #172 @124 RefTypeUse <Ivl:28> BB06 regmask=[rax] minReg=1 last>
<RefPosition #173 @129 RefTypeDef <Ivl:29> LCL_VAR BB06 regmask=[rcx] minReg=1>
<RefPosition #174 @130 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #175 @130 RefTypeUse <Ivl:29> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #176 @131 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #177 @131 RefTypeDef <Ivl:30> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
<RefPosition #178 @133 RefTypeDef <Ivl:31> LCL_VAR BB06 regmask=[rdx] minReg=1>
<RefPosition #179 @134 RefTypeFixedReg <Reg:rdx> BB06 regmask=[rdx] minReg=1>
<RefPosition #180 @134 RefTypeUse <Ivl:31> BB06 regmask=[rdx] minReg=1 last fixed>
<RefPosition #181 @135 RefTypeFixedReg <Reg:rdx> BB06 regmask=[rdx] minReg=1>
<RefPosition #182 @135 RefTypeDef <Ivl:32> PUTARG_REG BB06 regmask=[rdx] minReg=1 fixed>
<RefPosition #183 @136 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #184 @136 RefTypeUse <Ivl:30> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #185 @136 RefTypeFixedReg <Reg:rdx> BB06 regmask=[rdx] minReg=1>
<RefPosition #186 @136 RefTypeUse <Ivl:32> BB06 regmask=[rdx] minReg=1 last fixed>
<RefPosition #187 @137 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1 last>
<RefPosition #188 @137 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #189 @137 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1 last>
<RefPosition #190 @137 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1 last>
<RefPosition #191 @137 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1 last>
<RefPosition #192 @137 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1 last>
<RefPosition #193 @137 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1 last>
<RefPosition #194 @137 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #195 @137 RefTypeDef <Ivl:33> CALL BB06 regmask=[rax] minReg=1 fixed>
<RefPosition #196 @138 RefTypeUse <Ivl:33> BB06 regmask=[rax] minReg=1 last>
<RefPosition #197 @145 RefTypeDef <Ivl:34> LCL_VAR BB06 regmask=[rcx] minReg=1>
<RefPosition #198 @146 RefTypeUse <Ivl:34> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #199 @148 RefTypeBB BB07 regmask=[] minReg=1>
<RefPosition #200 @156 RefTypeBB BB08 regmask=[] minReg=1>
<RefPosition #201 @159 RefTypeDef <Ivl:35> LCL_VAR BB08 regmask=[rcx] minReg=1>
<RefPosition #202 @160 RefTypeUse <Ivl:35> BB08 regmask=[rcx] minReg=1 last>
<RefPosition #203 @161 RefTypeDef <Ivl:36> CAST BB08 regmask=[rcx] minReg=1>
<RefPosition #204 @162 RefTypeUse <Ivl:36> BB08 regmask=[rcx] minReg=1 last>
<RefPosition #205 @174 RefTypeBB BB09 regmask=[] minReg=1>
<RefPosition #206 @183 RefTypeDef <Ivl:37> LCL_VAR BB09 regmask=[rcx] minReg=1>
<RefPosition #207 @186 RefTypeUse <Ivl:37> BB09 regmask=[rcx] minReg=1 last>
<RefPosition #208 @187 RefTypeDef <Ivl:38> IND BB09 regmask=[rcx] minReg=1>
<RefPosition #209 @188 RefTypeUse <Ivl:38> BB09 regmask=[rcx] minReg=1 last>
<RefPosition #210 @193 RefTypeDef <Ivl:39> LCL_VAR BB09 regmask=[rcx] minReg=1>
<RefPosition #211 @200 RefTypeDef <Ivl:40 internal> STORE_BLK BB09 regmask=[mm0] minReg=1>
<RefPosition #212 @200 RefTypeUse <Ivl:39> BB09 regmask=[rcx] minReg=1 last>
<RefPosition #213 @200 RefTypeUse <Ivl:40 internal> STORE_BLK BB09 regmask=[mm0] minReg=1 last>
<RefPosition #214 @205 RefTypeDef <Ivl:41> LCL_VAR BB09 regmask=[rcx] minReg=1>
<RefPosition #215 @206 RefTypeUse <Ivl:41> BB09 regmask=[rcx] minReg=1 last>
<RefPosition #216 @209 RefTypeDef <Ivl:42> LCL_VAR_ADDR BB09 regmask=[rcx] minReg=1>
<RefPosition #217 @210 RefTypeFixedReg <Reg:rcx> BB09 regmask=[rcx] minReg=1>
<RefPosition #218 @210 RefTypeUse <Ivl:42> BB09 regmask=[rcx] minReg=1 last fixed>
<RefPosition #219 @211 RefTypeFixedReg <Reg:rcx> BB09 regmask=[rcx] minReg=1>
<RefPosition #220 @211 RefTypeDef <Ivl:43> PUTARG_REG BB09 regmask=[rcx] minReg=1 fixed>
<RefPosition #221 @212 RefTypeFixedReg <Reg:rcx> BB09 regmask=[rcx] minReg=1>
<RefPosition #222 @212 RefTypeUse <Ivl:43> BB09 regmask=[rcx] minReg=1 last fixed>
<RefPosition #223 @213 RefTypeKill <Reg:rax> BB09 regmask=[rax] minReg=1 last>
<RefPosition #224 @213 RefTypeKill <Reg:rcx> BB09 regmask=[rcx] minReg=1 last>
<RefPosition #225 @213 RefTypeKill <Reg:rdx> BB09 regmask=[rdx] minReg=1 last>
<RefPosition #226 @213 RefTypeKill <Reg:r8 > BB09 regmask=[r8] minReg=1 last>
<RefPosition #227 @213 RefTypeKill <Reg:r9 > BB09 regmask=[r9] minReg=1 last>
<RefPosition #228 @213 RefTypeKill <Reg:r10> BB09 regmask=[r10] minReg=1 last>
<RefPosition #229 @213 RefTypeKill <Reg:r11> BB09 regmask=[r11] minReg=1 last>
<RefPosition #230 @213 RefTypeFixedReg <Reg:rax> BB09 regmask=[rax] minReg=1>
<RefPosition #231 @213 RefTypeDef <Ivl:44> CALL BB09 regmask=[rax] minReg=1 fixed>
<RefPosition #232 @214 RefTypeUse <Ivl:44> BB09 regmask=[rax] minReg=1 last>
<RefPosition #233 @219 RefTypeDef <Ivl:45> LCL_VAR BB09 regmask=[rcx] minReg=1>
<RefPosition #234 @222 RefTypeUse <Ivl:45> BB09 regmask=[rcx] minReg=1 last>
<RefPosition #235 @223 RefTypeDef <Ivl:46> GE BB09 regmask=[rcx] minReg=1>
<RefPosition #236 @224 RefTypeUse <Ivl:46> BB09 regmask=[rcx] minReg=1 last>
<RefPosition #237 @236 RefTypeBB BB10 regmask=[] minReg=1>
<RefPosition #238 @245 RefTypeDef <Ivl:47> LCL_VAR BB10 regmask=[rcx] minReg=1>
<RefPosition #239 @246 RefTypeFixedReg <Reg:rcx> BB10 regmask=[rcx] minReg=1>
<RefPosition #240 @246 RefTypeUse <Ivl:47> BB10 regmask=[rcx] minReg=1 last fixed>
<RefPosition #241 @247 RefTypeFixedReg <Reg:rcx> BB10 regmask=[rcx] minReg=1>
<RefPosition #242 @247 RefTypeDef <Ivl:48> PUTARG_REG BB10 regmask=[rcx] minReg=1 fixed>
<RefPosition #243 @248 RefTypeFixedReg <Reg:rcx> BB10 regmask=[rcx] minReg=1>
<RefPosition #244 @248 RefTypeUse <Ivl:48> BB10 regmask=[rcx] minReg=1 last fixed>
<RefPosition #245 @249 RefTypeKill <Reg:rax> BB10 regmask=[rax] minReg=1 last>
<RefPosition #246 @249 RefTypeKill <Reg:rcx> BB10 regmask=[rcx] minReg=1 last>
<RefPosition #247 @249 RefTypeKill <Reg:rdx> BB10 regmask=[rdx] minReg=1 last>
<RefPosition #248 @249 RefTypeKill <Reg:r8 > BB10 regmask=[r8] minReg=1 last>
<RefPosition #249 @249 RefTypeKill <Reg:r9 > BB10 regmask=[r9] minReg=1 last>
<RefPosition #250 @249 RefTypeKill <Reg:r10> BB10 regmask=[r10] minReg=1 last>
<RefPosition #251 @249 RefTypeKill <Reg:r11> BB10 regmask=[r11] minReg=1 last>
<RefPosition #252 @249 RefTypeFixedReg <Reg:rax> BB10 regmask=[rax] minReg=1>
<RefPosition #253 @249 RefTypeDef <Ivl:49> CALL BB10 regmask=[rax] minReg=1 fixed>
<RefPosition #254 @250 RefTypeUse <Ivl:49> BB10 regmask=[rax] minReg=1 last>
<RefPosition #255 @255 RefTypeDef <Ivl:50> LCL_VAR BB10 regmask=[rcx] minReg=1>
<RefPosition #256 @256 RefTypeUse <Ivl:50> BB10 regmask=[rcx] minReg=1 last>
<RefPosition #257 @257 RefTypeDef <Ivl:51> CAST BB10 regmask=[rcx] minReg=1>
<RefPosition #258 @258 RefTypeUse <Ivl:51> BB10 regmask=[rcx] minReg=1 last>
<RefPosition #259 @264 RefTypeBB BB11 regmask=[] minReg=1>
<RefPosition #260 @269 RefTypeDef <Ivl:52> LCL_VAR_ADDR BB11 regmask=[rcx] minReg=1>
<RefPosition #261 @270 RefTypeFixedReg <Reg:rcx> BB11 regmask=[rcx] minReg=1>
<RefPosition #262 @270 RefTypeUse <Ivl:52> BB11 regmask=[rcx] minReg=1 last fixed>
<RefPosition #263 @271 RefTypeFixedReg <Reg:rcx> BB11 regmask=[rcx] minReg=1>
<RefPosition #264 @271 RefTypeDef <Ivl:53> PUTARG_REG BB11 regmask=[rcx] minReg=1 fixed>
<RefPosition #265 @273 RefTypeDef <Ivl:54> LCL_VAR BB11 regmask=[rdx] minReg=1>
<RefPosition #266 @274 RefTypeFixedReg <Reg:rdx> BB11 regmask=[rdx] minReg=1>
<RefPosition #267 @274 RefTypeUse <Ivl:54> BB11 regmask=[rdx] minReg=1 last fixed>
<RefPosition #268 @275 RefTypeFixedReg <Reg:rdx> BB11 regmask=[rdx] minReg=1>
<RefPosition #269 @275 RefTypeDef <Ivl:55> PUTARG_REG BB11 regmask=[rdx] minReg=1 fixed>
<RefPosition #270 @276 RefTypeFixedReg <Reg:rcx> BB11 regmask=[rcx] minReg=1>
<RefPosition #271 @276 RefTypeUse <Ivl:53> BB11 regmask=[rcx] minReg=1 last fixed>
<RefPosition #272 @276 RefTypeFixedReg <Reg:rdx> BB11 regmask=[rdx] minReg=1>
<RefPosition #273 @276 RefTypeUse <Ivl:55> BB11 regmask=[rdx] minReg=1 last fixed>
<RefPosition #274 @277 RefTypeKill <Reg:rax> BB11 regmask=[rax] minReg=1 last>
<RefPosition #275 @277 RefTypeKill <Reg:rcx> BB11 regmask=[rcx] minReg=1 last>
<RefPosition #276 @277 RefTypeKill <Reg:rdx> BB11 regmask=[rdx] minReg=1 last>
<RefPosition #277 @277 RefTypeKill <Reg:r8 > BB11 regmask=[r8] minReg=1 last>
<RefPosition #278 @277 RefTypeKill <Reg:r9 > BB11 regmask=[r9] minReg=1 last>
<RefPosition #279 @277 RefTypeKill <Reg:r10> BB11 regmask=[r10] minReg=1 last>
<RefPosition #280 @277 RefTypeKill <Reg:r11> BB11 regmask=[r11] minReg=1 last>
<RefPosition #281 @277 RefTypeFixedReg <Reg:rax> BB11 regmask=[rax] minReg=1>
<RefPosition #282 @277 RefTypeDef <Ivl:56> CALL BB11 regmask=[rax] minReg=1 fixed>
<RefPosition #283 @278 RefTypeUse <Ivl:56> BB11 regmask=[rax] minReg=1 last>
<RefPosition #284 @283 RefTypeDef <Ivl:57> LCL_VAR BB11 regmask=[rdx] minReg=1>
<RefPosition #285 @284 RefTypeUse <Ivl:57> BB11 regmask=[rdx] minReg=1 last>
<RefPosition #286 @285 RefTypeDef <Ivl:58> IND BB11 regmask=[rdx] minReg=1>
<RefPosition #287 @286 RefTypeUse <Ivl:58> BB11 regmask=[rdx] minReg=1 last>
<RefPosition #288 @291 RefTypeDef <Ivl:59> LCL_VAR BB11 regmask=[rdx] minReg=1>
<RefPosition #289 @294 RefTypeUse <Ivl:59> BB11 regmask=[rdx] minReg=1 last>
<RefPosition #290 @295 RefTypeDef <Ivl:60> ADD BB11 regmask=[rdx] minReg=1>
<RefPosition #291 @297 RefTypeDef <Ivl:61> LCL_VAR BB11 regmask=[rcx] minReg=1>
<RefPosition #292 @300 RefTypeUse <Ivl:61> BB11 regmask=[rcx] minReg=1 last>
<RefPosition #293 @300 RefTypeUse <Ivl:60> BB11 regmask=[rdx] minReg=1 last>
<RefPosition #294 @305 RefTypeDef <Ivl:62> LCL_VAR BB11 regmask=[rdx] minReg=1>
<RefPosition #295 @306 RefTypeUse <Ivl:62> BB11 regmask=[rdx] minReg=1 last>
<RefPosition #296 @312 RefTypeBB BB12 regmask=[] minReg=1>
<RefPosition #297 @317 RefTypeDef <Ivl:63> LCL_VAR BB12 regmask=[rdx] minReg=1>
<RefPosition #298 @318 RefTypeUse <Ivl:63> BB12 regmask=[rdx] minReg=1 last>
<RefPosition #299 @321 RefTypeDef <Ivl:64> LCL_VAR BB12 regmask=[rdx] minReg=1>
<RefPosition #300 @324 RefTypeUse <Ivl:64> BB12 regmask=[rdx] minReg=1 last>
<RefPosition #301 @325 RefTypeDef <Ivl:65> ADD BB12 regmask=[rdx] minReg=1>
<RefPosition #302 @326 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #303 @326 RefTypeUse <Ivl:65> BB12 regmask=[rdx] minReg=1 last fixed>
<RefPosition #304 @327 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #305 @327 RefTypeDef <Ivl:66> PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed>
<RefPosition #306 @329 RefTypeDef <Ivl:67> CNS_INT BB12 regmask=[rcx] minReg=1>
<RefPosition #307 @330 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #308 @330 RefTypeUse <Ivl:67> BB12 regmask=[rcx] minReg=1 last fixed>
<RefPosition #309 @331 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #310 @331 RefTypeDef <Ivl:68> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed>
<RefPosition #311 @332 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #312 @332 RefTypeUse <Ivl:66> BB12 regmask=[rdx] minReg=1 last fixed>
<RefPosition #313 @332 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #314 @332 RefTypeUse <Ivl:68> BB12 regmask=[rcx] minReg=1 last fixed>
<RefPosition #315 @333 RefTypeKill <Reg:rax> BB12 regmask=[rax] minReg=1 last>
<RefPosition #316 @333 RefTypeKill <Reg:rcx> BB12 regmask=[rcx] minReg=1 last>
<RefPosition #317 @333 RefTypeKill <Reg:rdx> BB12 regmask=[rdx] minReg=1 last>
<RefPosition #318 @333 RefTypeKill <Reg:r8 > BB12 regmask=[r8] minReg=1 last>
<RefPosition #319 @333 RefTypeKill <Reg:r9 > BB12 regmask=[r9] minReg=1 last>
<RefPosition #320 @333 RefTypeKill <Reg:r10> BB12 regmask=[r10] minReg=1 last>
<RefPosition #321 @333 RefTypeKill <Reg:r11> BB12 regmask=[r11] minReg=1 last>
<RefPosition #322 @333 RefTypeFixedReg <Reg:rax> BB12 regmask=[rax] minReg=1>
<RefPosition #323 @333 RefTypeDef <Ivl:69> CALL BB12 regmask=[rax] minReg=1 fixed>
<RefPosition #324 @334 RefTypeUse <Ivl:69> BB12 regmask=[rax] minReg=1 last>
<RefPosition #325 @337 RefTypeDef <Ivl:70> LCL_VAR BB12 regmask=[rdx] minReg=1>
<RefPosition #326 @338 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #327 @338 RefTypeUse <Ivl:70> BB12 regmask=[rdx] minReg=1 last fixed>
<RefPosition #328 @339 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #329 @339 RefTypeDef <Ivl:71> PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed>
<RefPosition #330 @341 RefTypeDef <Ivl:72> CNS_INT BB12 regmask=[rcx] minReg=1>
<RefPosition #331 @342 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #332 @342 RefTypeUse <Ivl:72> BB12 regmask=[rcx] minReg=1 last fixed>
<RefPosition #333 @343 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #334 @343 RefTypeDef <Ivl:73> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed>
<RefPosition #335 @344 RefTypeFixedReg <Reg:rdx> BB12 regmask=[rdx] minReg=1>
<RefPosition #336 @344 RefTypeUse <Ivl:71> BB12 regmask=[rdx] minReg=1 last fixed>
<RefPosition #337 @344 RefTypeFixedReg <Reg:rcx> BB12 regmask=[rcx] minReg=1>
<RefPosition #338 @344 RefTypeUse <Ivl:73> BB12 regmask=[rcx] minReg=1 last fixed>
<RefPosition #339 @345 RefTypeKill <Reg:rax> BB12 regmask=[rax] minReg=1 last>
<RefPosition #340 @345 RefTypeKill <Reg:rcx> BB12 regmask=[rcx] minReg=1 last>
<RefPosition #341 @345 RefTypeKill <Reg:rdx> BB12 regmask=[rdx] minReg=1 last>
<RefPosition #342 @345 RefTypeKill <Reg:r8 > BB12 regmask=[r8] minReg=1 last>
<RefPosition #343 @345 RefTypeKill <Reg:r9 > BB12 regmask=[r9] minReg=1 last>
<RefPosition #344 @345 RefTypeKill <Reg:r10> BB12 regmask=[r10] minReg=1 last>
<RefPosition #345 @345 RefTypeKill <Reg:r11> BB12 regmask=[r11] minReg=1 last>
<RefPosition #346 @345 RefTypeFixedReg <Reg:rax> BB12 regmask=[rax] minReg=1>
<RefPosition #347 @345 RefTypeDef <Ivl:74> CALL BB12 regmask=[rax] minReg=1 fixed>
<RefPosition #348 @346 RefTypeUse <Ivl:74> BB12 regmask=[rax] minReg=1 last>
<RefPosition #349 @355 RefTypeDef <Ivl:75> NE BB12 regmask=[rcx] minReg=1>
<RefPosition #350 @356 RefTypeUse <Ivl:75> BB12 regmask=[rcx] minReg=1 last>
<RefPosition #351 @368 RefTypeBB BB13 regmask=[] minReg=1>
<RefPosition #352 @377 RefTypeDef <Ivl:76> LCL_VAR BB13 regmask=[rcx] minReg=1>
<RefPosition #353 @378 RefTypeFixedReg <Reg:rcx> BB13 regmask=[rcx] minReg=1>
<RefPosition #354 @378 RefTypeUse <Ivl:76> BB13 regmask=[rcx] minReg=1 last fixed>
<RefPosition #355 @379 RefTypeFixedReg <Reg:rcx> BB13 regmask=[rcx] minReg=1>
<RefPosition #356 @379 RefTypeDef <Ivl:77> PUTARG_REG BB13 regmask=[rcx] minReg=1 fixed>
<RefPosition #357 @381 RefTypeDef <Ivl:78> LCL_VAR BB13 regmask=[rax] minReg=1>
<RefPosition #358 @384 RefTypeUse <Ivl:78> BB13 regmask=[rax] minReg=1 last>
<RefPosition #359 @385 RefTypeDef <Ivl:79> IND BB13 regmask=[rax] minReg=1>
<RefPosition #360 @388 RefTypeUse <Ivl:79> BB13 regmask=[rax] minReg=1 last>
<RefPosition #361 @389 RefTypeDef <Ivl:80> IND BB13 regmask=[rax] minReg=1>
<RefPosition #362 @394 RefTypeFixedReg <Reg:rcx> BB13 regmask=[rcx] minReg=1>
<RefPosition #363 @394 RefTypeUse <Ivl:77> BB13 regmask=[rcx] minReg=1 last fixed>
<RefPosition #364 @394 RefTypeUse <Ivl:80> BB13 regmask=[rax] minReg=1 last>
<RefPosition #365 @395 RefTypeKill <Reg:rax> BB13 regmask=[rax] minReg=1 last>
<RefPosition #366 @395 RefTypeKill <Reg:rcx> BB13 regmask=[rcx] minReg=1 last>
<RefPosition #367 @395 RefTypeKill <Reg:rdx> BB13 regmask=[rdx] minReg=1 last>
<RefPosition #368 @395 RefTypeKill <Reg:r8 > BB13 regmask=[r8] minReg=1 last>
<RefPosition #369 @395 RefTypeKill <Reg:r9 > BB13 regmask=[r9] minReg=1 last>
<RefPosition #370 @395 RefTypeKill <Reg:r10> BB13 regmask=[r10] minReg=1 last>
<RefPosition #371 @395 RefTypeKill <Reg:r11> BB13 regmask=[r11] minReg=1 last>
<RefPosition #372 @395 RefTypeFixedReg <Reg:rax> BB13 regmask=[rax] minReg=1>
<RefPosition #373 @395 RefTypeDef <Ivl:81> CALL BB13 regmask=[rax] minReg=1 fixed>
<RefPosition #374 @396 RefTypeUse <Ivl:81> BB13 regmask=[rax] minReg=1 last>
<RefPosition #375 @401 RefTypeDef <Ivl:82> LCL_VAR BB13 regmask=[rax] minReg=1>
<RefPosition #376 @402 RefTypeUse <Ivl:82> BB13 regmask=[rax] minReg=1 last>
<RefPosition #377 @403 RefTypeDef <Ivl:83> CAST BB13 regmask=[rax] minReg=1>
<RefPosition #378 @404 RefTypeUse <Ivl:83> BB13 regmask=[rax] minReg=1 last>
<RefPosition #379 @410 RefTypeBB BB14 regmask=[] minReg=1>
<RefPosition #380 @419 RefTypeKill <Reg:rax> BB14 regmask=[rax] minReg=1 last>
<RefPosition #381 @419 RefTypeKill <Reg:rcx> BB14 regmask=[rcx] minReg=1 last>
<RefPosition #382 @419 RefTypeKill <Reg:rdx> BB14 regmask=[rdx] minReg=1 last>
<RefPosition #383 @419 RefTypeKill <Reg:r8 > BB14 regmask=[r8] minReg=1 last>
<RefPosition #384 @419 RefTypeKill <Reg:r9 > BB14 regmask=[r9] minReg=1 last>
<RefPosition #385 @419 RefTypeKill <Reg:r10> BB14 regmask=[r10] minReg=1 last>
<RefPosition #386 @419 RefTypeKill <Reg:r11> BB14 regmask=[r11] minReg=1 last>
<RefPosition #387 @419 RefTypeFixedReg <Reg:rax> BB14 regmask=[rax] minReg=1>
<RefPosition #388 @419 RefTypeDef <Ivl:84> CALL BB14 regmask=[rax] minReg=1 fixed>
<RefPosition #389 @420 RefTypeUse <Ivl:84> BB14 regmask=[rax] minReg=1 last>
<RefPosition #390 @425 RefTypeDef <Ivl:85> LCL_VAR BB14 regmask=[rax] minReg=1>
<RefPosition #391 @426 RefTypeUse <Ivl:85> BB14 regmask=[rax] minReg=1 last>
<RefPosition #392 @427 RefTypeDef <Ivl:86> CAST BB14 regmask=[rax] minReg=1>
<RefPosition #393 @428 RefTypeUse <Ivl:86> BB14 regmask=[rax] minReg=1 last>
<RefPosition #394 @434 RefTypeBB BB15 regmask=[] minReg=1>
<RefPosition #395 @439 RefTypeDef <Ivl:87> LCL_VAR BB15 regmask=[rax] minReg=1>
<RefPosition #396 @440 RefTypeFixedReg <Reg:rax> BB15 regmask=[rax] minReg=1>
<RefPosition #397 @440 RefTypeUse <Ivl:87> BB15 regmask=[rax] minReg=1 last fixed>
Active intervals at end of allocation:
Trees after linear scan register allocator (LSRA)
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target hascall LIR
BB02 [0013] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
BB03 [0014] 1 BB02 0.50 [???..???) internal LIR
BB04 [0012] 2 BB02,BB03 1 [???..???) i internal label target hascall LIR
BB05 [0001] 1 BB04 1 [000..01C)-> BB07 ( cond ) i hascall LIR
BB06 [0002] 1 BB05 1 [01C..037)-> BB08 (always) i hascall LIR
BB07 [0003] 1 BB05 1 [037..038) i label target LIR
BB08 [0004] 2 BB06,BB07 1 [038..03C)-> BB12 ( cond ) i label target LIR
BB09 [0005] 1 BB08 1 [03C..05E)-> BB11 ( cond ) i hascall LIR
BB10 [0006] 1 BB09 1 [05E..069)-> BB15 (always) i hascall gcsafe LIR
BB11 [0007] 1 BB09 1 [069..081)-> BB15 (always) i label target hascall LIR
BB12 [0008] 1 BB08 1 [081..09E)-> BB14 ( cond ) i label target hascall nullcheck LIR
BB13 [0009] 1 BB12 1 [09E..0AA)-> BB15 (always) i hascall gcsafe LIR
BB14 [0010] 1 BB12 1 [0AA..0B4)-> BB15 (always) i label target hascall gcsafe LIR
BB15 [0011] 4 BB10,BB11,BB13,BB14 1 [0B4..0B7) (return) i label target LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
N002 ( 0, 0) [000000] ------------ NOP void REG NA
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
N006 ( 2, 10) [000171] Hc---------- t171 = CNS_INT(h) long 0x7ff9392a5420 global ptr REG NA
/--* t171 long
N008 ( 4, 12) [000172] nc---------- t172 = * IND int REG NA
N010 ( 1, 1) [000173] -c---------- t173 = CNS_INT int 0 REG NA
/--* t172 int
+--* t173 int
N012 ( 6, 14) [000174] J------N---- * EQ void REG NA
N014 ( 8, 16) [000221] ------------ * JTRUE void REG NA
------------ BB03 [???..???), preds={BB02} succs={BB04}
N018 ( 14, 5) [000175] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE REG NA
------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
------------ BB05 [000..01C) -> BB07 (cond), preds={BB04} succs={BB06,BB07}
N024 (???,???) [000222] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N026 ( 1, 1) [000001] ------------ NO_OP void REG NA
N028 (???,???) [000223] ------------ IL_OFFSET void IL offset: 0x1 REG NA
N030 ( 2, 10) [000002] H----------- t2 = CNS_INT(h) long 0x7ff93af7cd80 class REG rcx
/--* t2 long
N032 (???,???) [000261] ------------ t261 = * PUTARG_REG long REG rcx
/--* t261 long arg0 in rcx
N034 ( 16, 16) [000003] --C-G------- t3 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE REG rax
/--* t3 ref
N036 ( 20, 19) [000007] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1 NA REG NA
N038 ( 3, 4) [000008] ------------ t8 = LCL_FLD ref V10 tmp1 [+0] rcx REG rcx
/--* t8 ref
N040 (???,???) [000262] ------------ t262 = * PUTARG_REG ref REG rcx
/--* t262 ref arg0 in rcx
N042 ( 17, 10) [000004] --CXG------- t4 = * CALL ref System.Type.GetTypeFromHandle REG rax
/--* t4 ref
N044 ( 21, 13) [000012] DA-XG------- * STORE_LCL_VAR ref V11 tmp2 NA REG NA
N046 (???,???) [000224] ------------ IL_OFFSET void IL offset: 0xb REG NA
N048 ( 2, 10) [000014] H----------- t14 = CNS_INT(h) long 0x7ff93af7cd80 class REG rcx
/--* t14 long
N050 (???,???) [000263] ------------ t263 = * PUTARG_REG long REG rcx
/--* t263 long arg0 in rcx
N052 ( 16, 16) [000015] --C-G------- t15 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE REG rax
/--* t15 ref
N054 ( 20, 19) [000019] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3 NA REG NA
N056 ( 3, 4) [000020] ------------ t20 = LCL_FLD ref V12 tmp3 [+0] rcx REG rcx
/--* t20 ref
N058 (???,???) [000264] ------------ t264 = * PUTARG_REG ref REG rcx
/--* t264 ref arg0 in rcx
N060 ( 17, 10) [000016] --CXG------- t16 = * CALL ref System.Type.GetTypeFromHandle REG rax
/--* t16 ref
N062 ( 21, 13) [000024] DA-XG------- * STORE_LCL_VAR ref V13 tmp4 NA REG NA
N064 (???,???) [000225] ------------ IL_OFFSET void IL offset: 0x15 REG NA
N066 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V11 tmp2 rcx REG rcx
/--* t13 ref
N068 (???,???) [000265] ------------ t265 = * PUTARG_REG ref REG rcx
N070 ( 3, 2) [000025] ------------ t25 = LCL_VAR ref V13 tmp4 rdx REG rdx
/--* t25 ref
N072 (???,???) [000266] ------------ t266 = * PUTARG_REG ref REG rdx
/--* t265 ref arg0 in rcx
+--* t266 ref arg1 in rdx
N074 ( 20, 11) [000026] --CXG------- t26 = * CALL int System.Type.op_Equality REG rax
/--* t26 int
N076 ( 24, 14) [000028] DA-XG------- * STORE_LCL_VAR int V14 tmp5 NA REG NA
N078 (???,???) [000226] ------------ IL_OFFSET void IL offset: 0x1a REG NA
N080 ( 3, 2) [000029] -c---------- t29 = LCL_VAR int V14 tmp5 NA REG NA
N082 ( 1, 1) [000030] -c---------- t30 = CNS_INT int 0 REG NA
/--* t29 int
+--* t30 int
N084 ( 5, 4) [000031] J------N---- * NE void REG NA
N086 ( 7, 6) [000032] ------------ * JTRUE void REG NA
------------ BB06 [01C..037) -> BB08 (always), preds={BB05} succs={BB08}
N090 (???,???) [000227] ------------ IL_OFFSET void IL offset: 0x1c REG NA
N092 ( 2, 10) [000139] H----------- t139 = CNS_INT(h) long 0x7ff93af7cd80 class REG rcx
/--* t139 long
N094 (???,???) [000267] ------------ t267 = * PUTARG_REG long REG rcx
/--* t267 long arg0 in rcx
N096 ( 16, 16) [000140] --C-G------- t140 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE REG rax
/--* t140 ref
N098 ( 20, 19) [000144] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13 NA REG NA
N100 ( 3, 4) [000145] ------------ t145 = LCL_FLD ref V22 tmp13 [+0] rcx REG rcx
/--* t145 ref
N102 (???,???) [000268] ------------ t268 = * PUTARG_REG ref REG rcx
/--* t268 ref arg0 in rcx
N104 ( 17, 10) [000141] --CXG------- t141 = * CALL ref System.Type.GetTypeFromHandle REG rax
/--* t141 ref
N106 ( 21, 13) [000149] DA-XG------- * STORE_LCL_VAR ref V23 tmp14 NA REG NA
N108 (???,???) [000228] ------------ IL_OFFSET void IL offset: 0x26 REG NA
N110 ( 2, 10) [000151] H----------- t151 = CNS_INT(h) long 0x7ff93b56a7f8 class REG rcx
/--* t151 long
N112 (???,???) [000269] ------------ t269 = * PUTARG_REG long REG rcx
/--* t269 long arg0 in rcx
N114 ( 16, 16) [000152] --C-G------- t152 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE REG rax
/--* t152 ref
N116 ( 20, 19) [000156] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15 NA REG NA
N118 ( 3, 4) [000157] ------------ t157 = LCL_FLD ref V24 tmp15 [+0] rcx REG rcx
/--* t157 ref
N120 (???,???) [000270] ------------ t270 = * PUTARG_REG ref REG rcx
/--* t270 ref arg0 in rcx
N122 ( 17, 10) [000153] --CXG------- t153 = * CALL ref System.Type.GetTypeFromHandle REG rax
/--* t153 ref
N124 ( 21, 13) [000161] DA-XG------- * STORE_LCL_VAR ref V25 tmp16 NA REG NA
N126 (???,???) [000229] ------------ IL_OFFSET void IL offset: 0x30 REG NA
N128 ( 3, 2) [000150] ------------ t150 = LCL_VAR ref V23 tmp14 rcx REG rcx
/--* t150 ref
N130 (???,???) [000271] ------------ t271 = * PUTARG_REG ref REG rcx
N132 ( 3, 2) [000162] ------------ t162 = LCL_VAR ref V25 tmp16 rdx REG rdx
/--* t162 ref
N134 (???,???) [000272] ------------ t272 = * PUTARG_REG ref REG rdx
/--* t271 ref arg0 in rcx
+--* t272 ref arg1 in rdx
N136 ( 20, 11) [000163] --CXG------- t163 = * CALL int System.Type.op_Equality REG rax
/--* t163 int
N138 ( 24, 14) [000165] DA-XG------- * STORE_LCL_VAR int V26 tmp17 NA REG NA
N140 (???,???) [000230] ------------ IL_OFFSET void IL offset: 0x35 REG NA
N142 ( 0, 0) [000167] ------------ NOP void REG NA
N144 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V26 tmp17 rcx REG rcx
/--* t166 int
N146 ( 7, 5) [000169] DA---------- * STORE_LCL_VAR int V15 tmp6 NA REG NA
------------ BB07 [037..038), preds={BB05} succs={BB08}
N150 (???,???) [000231] ------------ IL_OFFSET void IL offset: 0x37 REG NA
N152 ( 1, 1) [000033] -c---------- t33 = CNS_INT int 1 REG NA
/--* t33 int
N154 ( 5, 4) [000035] DA---------- * STORE_LCL_VAR int V15 tmp6 NA REG NA
------------ BB08 [038..03C) -> BB12 (cond), preds={BB06,BB07} succs={BB09,BB12}
N158 ( 3, 2) [000037] ------------ t37 = LCL_VAR int V15 tmp6 rcx REG rcx
/--* t37 int
N160 ( 4, 4) [000191] ------------ t191 = * CAST int <- bool <- int REG rcx
/--* t191 int
N162 ( 8, 7) [000039] DA---------- * STORE_LCL_VAR int V01 loc0 NA REG NA
N164 (???,???) [000232] ------------ IL_OFFSET void IL offset: 0x39 REG NA
N166 ( 3, 2) [000040] -c---------- t40 = LCL_VAR int V01 loc0 NA REG NA
N168 ( 1, 1) [000041] -c---------- t41 = CNS_INT int 0 REG NA
/--* t40 int
+--* t41 int
N170 ( 5, 4) [000042] J------N---- * EQ void REG NA
N172 ( 7, 6) [000043] ------------ * JTRUE void REG NA
------------ BB09 [03C..05E) -> BB11 (cond), preds={BB08} succs={BB10,BB11}
N176 (???,???) [000233] ------------ IL_OFFSET void IL offset: 0x3c REG NA
N178 ( 1, 1) [000081] ------------ NO_OP void REG NA
N180 (???,???) [000234] ------------ IL_OFFSET void IL offset: 0x3d REG NA
N182 ( 3, 2) [000082] ------------ t82 = LCL_VAR byref V00 this rcx REG rcx
/--* t82 byref
N184 ( 4, 3) [000193] -c---------- t193 = * LEA(b+24) byref REG NA
/--* t193 byref
N186 ( 6, 5) [000083] *--XG------- t83 = * IND int REG rcx
/--* t83 int
N188 ( 10, 8) [000085] DA-XG------- * STORE_LCL_VAR int V02 loc1 NA REG NA
N190 (???,???) [000235] ------------ IL_OFFSET void IL offset: 0x44 REG NA
N192 ( 3, 2) [000086] ------------ t86 = LCL_VAR byref V00 this rcx REG rcx
/--* t86 byref
N194 ( 5, 4) [000195] -c---------- t195 = * LEA(b+32) byref REG NA
/--* t195 byref
N196 ( 8, 6) [000087] *c-XG------- t87 = * IND struct REG NA
N198 (???,???) [000273] Dc-----N---- t273 = LCL_VAR_ADDR byref V03 loc2 NA REG NA
/--* t273 byref
+--* t87 struct
N200 ( 12, 9) [000090] sA---------- * STORE_BLK struct<System.ReadOnlySpan`1[Byte], 16> (copy) (Unroll) REG NA
N202 (???,???) [000236] ------------ IL_OFFSET void IL offset: 0x4b REG NA
N204 ( 3, 2) [000091] ------------ t91 = LCL_VAR int V02 loc1 rcx REG rcx
/--* t91 int
N206 ( 7, 5) [000096] DA---------- * STORE_LCL_VAR int V18 tmp9 NA REG NA
N208 ( 3, 3) [000093] ------------ t93 = LCL_VAR_ADDR byref V03 loc2 rcx REG rcx
/--* t93 byref
N210 (???,???) [000274] ------------ t274 = * PUTARG_REG byref REG rcx
/--* t274 byref this in rcx
N212 ( 17, 10) [000094] --CXG------- t94 = * CALL int System.ReadOnlySpan`1[Byte][System.Byte].get_Length REG rax
/--* t94 int
N214 ( 21, 13) [000099] DA-XG------- * STORE_LCL_VAR int V19 tmp10 NA REG NA
N216 (???,???) [000237] ------------ IL_OFFSET void IL offset: 0x53 REG NA
N218 ( 3, 2) [000097] ------------ t97 = LCL_VAR int V18 tmp9 rcx REG rcx
N220 ( 3, 2) [000100] -c---------- t100 = LCL_VAR int V19 tmp10 NA REG NA
/--* t97 int
+--* t100 int
N222 ( 10, 5) [000101] N--------U-- t101 = * GE int REG rcx
/--* t101 int
N224 ( 14, 8) [000105] DA---------- * STORE_LCL_VAR int V05 loc4 NA REG NA
N226 (???,???) [000238] ------------ IL_OFFSET void IL offset: 0x5a REG NA
N228 ( 3, 2) [000106] -c---------- t106 = LCL_VAR int V05 loc4 NA REG NA
N230 ( 1, 1) [000107] -c---------- t107 = CNS_INT int 0 REG NA
/--* t106 int
+--* t107 int
N232 ( 5, 4) [000108] J------N---- * EQ void REG NA
N234 ( 7, 6) [000109] ------------ * JTRUE void REG NA
------------ BB10 [05E..069) -> BB15 (always), preds={BB09} succs={BB15}
N238 (???,???) [000239] ------------ IL_OFFSET void IL offset: 0x5e REG NA
N240 ( 1, 1) [000130] ------------ NO_OP void REG NA
N242 (???,???) [000240] ------------ IL_OFFSET void IL offset: 0x5f REG NA
N244 ( 3, 2) [000131] ------------ t131 = LCL_VAR byref V00 this rcx REG rcx
/--* t131 byref
N246 (???,???) [000275] ------------ t275 = * PUTARG_REG byref REG rcx
/--* t275 byref arg0 in rcx
N248 ( 17, 8) [000132] --CXG------- t132 = * CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].<ReadByte>g__ReadByteSlow|18_0 REG rax
/--* t132 int
N250 ( 21, 11) [000134] DA-XG------- * STORE_LCL_VAR int V21 tmp12 NA REG NA
N252 (???,???) [000241] ------------ IL_OFFSET void IL offset: 0x65 REG NA
N254 ( 3, 2) [000135] ------------ t135 = LCL_VAR int V21 tmp12 rcx REG rcx
/--* t135 int
N256 ( 4, 4) [000198] ------------ t198 = * CAST int <- ubyte <- int REG rcx
/--* t198 int
N258 ( 8, 7) [000137] DA---------- * STORE_LCL_VAR int V06 loc5 NA REG NA
N260 (???,???) [000242] ------------ IL_OFFSET void IL offset: 0x67 REG NA
N262 ( 0, 0) [000138] ------------ NOP void REG NA
------------ BB11 [069..081) -> BB15 (always), preds={BB09} succs={BB15}
N266 (???,???) [000243] ------------ IL_OFFSET void IL offset: 0x69 REG NA
N268 ( 3, 3) [000111] ------------ t111 = LCL_VAR_ADDR byref V03 loc2 rcx REG rcx
/--* t111 byref
N270 (???,???) [000276] ------------ t276 = * PUTARG_REG byref REG rcx
N272 ( 3, 2) [000112] ------------ t112 = LCL_VAR int V02 loc1 rdx REG rdx
/--* t112 int
N274 (???,???) [000277] ------------ t277 = * PUTARG_REG int REG rdx
/--* t276 byref this in rcx
+--* t277 int arg1 in rdx
N276 ( 20, 13) [000113] --CXG------- t113 = * CALL byref System.ReadOnlySpan`1[Byte][System.Byte].get_Item REG rax
/--* t113 byref
N278 ( 24, 16) [000115] DA-XG------- * STORE_LCL_VAR byref V20 tmp11 NA REG NA
N280 (???,???) [000244] ------------ IL_OFFSET void IL offset: 0x71 REG NA
N282 ( 3, 2) [000116] ------------ t116 = LCL_VAR byref V20 tmp11 rdx REG rdx
/--* t116 byref
N284 ( 7, 5) [000117] *--XG------- t117 = * IND ubyte REG rdx
/--* t117 ubyte
N286 ( 11, 8) [000119] DA-XG------- * STORE_LCL_VAR int V04 loc3 NA REG NA
N288 (???,???) [000245] ------------ IL_OFFSET void IL offset: 0x73 REG NA
N290 ( 3, 2) [000121] ------------ t121 = LCL_VAR int V02 loc1 rdx REG rdx
N292 ( 1, 1) [000122] -c---------- t122 = CNS_INT int 1 REG NA
/--* t121 int
+--* t122 int
N294 ( 5, 4) [000123] ------------ t123 = * ADD int REG rdx
N296 ( 3, 2) [000120] ------------ t120 = LCL_VAR byref V00 this rcx REG rcx
/--* t120 byref
N298 ( 4, 3) [000202] -c---------- t202 = * LEA(b+24) byref REG NA
/--* t202 byref
+--* t123 int
N300 (???,???) [000246] -A-XG------- * STOREIND int REG NA
N302 (???,???) [000247] ------------ IL_OFFSET void IL offset: 0x7c REG NA
N304 ( 3, 2) [000126] ------------ t126 = LCL_VAR int V04 loc3 rdx REG rdx
/--* t126 int
N306 ( 7, 5) [000128] DA---------- * STORE_LCL_VAR int V06 loc5 NA REG NA
N308 (???,???) [000248] ------------ IL_OFFSET void IL offset: 0x7f REG NA
N310 ( 0, 0) [000129] ------------ NOP void REG NA
------------ BB12 [081..09E) -> BB14 (cond), preds={BB08} succs={BB13,BB14}
N314 (???,???) [000249] ------------ IL_OFFSET void IL offset: 0x81 REG NA
N316 ( 3, 2) [000204] ------------ t204 = LCL_VAR byref V00 this rdx REG rdx
/--* t204 byref
N318 ( 4, 3) [000205] ---X---N---- * NULLCHECK int REG NA
N320 ( 3, 2) [000206] ------------ t206 = LCL_VAR byref V00 this rdx REG rdx
N322 ( 1, 1) [000207] -c---------- t207 = CNS_INT long 64 field offset Fseq[_input] REG NA
/--* t206 byref
+--* t207 long
N324 ( 5, 4) [000208] ------------ t208 = * ADD byref REG rdx
/--* t208 byref
N326 (???,???) [000278] ------------ t278 = * PUTARG_REG byref REG rdx
N328 ( 2, 10) [000046] H----------- t46 = CNS_INT(h) long 0x7ff93af7cd80 class REG rcx
/--* t46 long
N330 (???,???) [000279] ------------ t279 = * PUTARG_REG long REG rcx
/--* t278 byref arg1 in rdx
+--* t279 long arg0 in rcx
N332 ( 25, 24) [000048] --CXG------- t48 = * CALL help ref HELPER.CORINFO_HELP_BOX REG rax
/--* t48 ref
N334 ( 29, 27) [000214] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp18 NA REG NA
N336 ( 3, 2) [000215] ------------ t215 = LCL_VAR ref V27 tmp18 rdx REG rdx
/--* t215 ref
N338 (???,???) [000280] ------------ t280 = * PUTARG_REG ref REG rdx
N340 ( 2, 10) [000049] H------N---- t49 = CNS_INT(h) long 0x7ff93b569758 class REG rcx
/--* t49 long
N342 (???,???) [000281] ------------ t281 = * PUTARG_REG long REG rcx
/--* t280 ref arg1 in rdx
+--* t281 long arg0 in rcx
N344 ( 51, 46) [000050] --CXG------- t50 = * CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS REG rax
/--* t50 ref
N346 ( 55, 49) [000052] DA-XG------- * STORE_LCL_VAR ref V07 loc6 NA REG NA
N348 (???,???) [000250] ------------ IL_OFFSET void IL offset: 0x93 REG NA
N350 ( 3, 2) [000053] -c---------- t53 = LCL_VAR ref V07 loc6 NA REG NA
N352 ( 1, 1) [000054] -c---------- t54 = CNS_INT ref null REG NA
/--* t53 ref
+--* t54 ref
N354 ( 8, 4) [000055] N----------- t55 = * NE int REG rcx
/--* t55 int
N356 ( 12, 7) [000057] DA---------- * STORE_LCL_VAR int V08 loc7 NA REG NA
N358 (???,???) [000251] ------------ IL_OFFSET void IL offset: 0x9a REG NA
N360 ( 3, 2) [000058] -c---------- t58 = LCL_VAR int V08 loc7 NA REG NA
N362 ( 1, 1) [000059] -c---------- t59 = CNS_INT int 0 REG NA
/--* t58 int
+--* t59 int
N364 ( 5, 4) [000060] J------N---- * EQ void REG NA
N366 ( 7, 6) [000061] ------------ * JTRUE void REG NA
------------ BB13 [09E..0AA) -> BB15 (always), preds={BB12} succs={BB15}
N370 (???,???) [000252] ------------ IL_OFFSET void IL offset: 0x9e REG NA
N372 ( 1, 1) [000072] ------------ NO_OP void REG NA
N374 (???,???) [000253] ------------ IL_OFFSET void IL offset: 0x9f REG NA
N376 ( 3, 2) [000073] ------------ t73 = LCL_VAR ref V07 loc6 rcx REG rcx
/--* t73 ref
N378 (???,???) [000282] ------------ t282 = * PUTARG_REG ref REG rcx
N380 ( 3, 2) [000283] ------------ t283 = LCL_VAR ref V07 loc6 rax REG rax
/--* t283 ref
N382 ( 4, 3) [000284] -c---------- t284 = * LEA(b+0) byref REG NA
/--* t284 byref
N384 ( 7, 5) [000285] ------------ t285 = * IND long REG rax
/--* t285 long
N386 ( 8, 6) [000286] -c---------- t286 = * LEA(b+72) long REG NA
/--* t286 long
N388 ( 11, 8) [000287] ------------ t287 = * IND long REG rax
/--* t287 long
N390 ( 12, 9) [000288] -c---------- t288 = * LEA(b+56) long REG NA
/--* t288 long
N392 ( 15, 11) [000289] -c---------- t289 = * IND long REG NA
/--* t282 ref this in rcx
+--* t289 long control expr
N394 ( 23, 11) [000074] --CXG------- t74 = * CALLV ind int Hagar.Buffers.ReaderInput.ReadByte REG rax
/--* t74 int
N396 ( 27, 14) [000076] DA-XG------- * STORE_LCL_VAR int V17 tmp8 NA REG NA
N398 (???,???) [000254] ------------ IL_OFFSET void IL offset: 0xa6 REG NA
N400 ( 3, 2) [000077] ------------ t77 = LCL_VAR int V17 tmp8 rax REG rax
/--* t77 int
N402 ( 4, 4) [000218] ------------ t218 = * CAST int <- ubyte <- int REG rax
/--* t218 int
N404 ( 8, 7) [000079] DA---------- * STORE_LCL_VAR int V06 loc5 NA REG NA
N406 (???,???) [000255] ------------ IL_OFFSET void IL offset: 0xa8 REG NA
N408 ( 0, 0) [000080] ------------ NOP void REG NA
------------ BB14 [0AA..0B4) -> BB15 (always), preds={BB12} succs={BB15}
N412 (???,???) [000256] ------------ IL_OFFSET void IL offset: 0xaa REG NA
N414 ( 1, 1) [000062] ------------ NO_OP void REG NA
N416 (???,???) [000257] ------------ IL_OFFSET void IL offset: 0xab REG NA
N418 ( 14, 5) [000063] --CXG------- t63 = CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].ThrowNotSupportedInput REG rax
/--* t63 int
N420 ( 18, 8) [000065] DA-XG------- * STORE_LCL_VAR int V16 tmp7 NA REG NA
N422 (???,???) [000258] ------------ IL_OFFSET void IL offset: 0xb0 REG NA
N424 ( 3, 2) [000066] ------------ t66 = LCL_VAR int V16 tmp7 rax REG rax
/--* t66 int
N426 ( 4, 4) [000219] ------------ t219 = * CAST int <- ubyte <- int REG rax
/--* t219 int
N428 ( 8, 7) [000068] DA---------- * STORE_LCL_VAR int V06 loc5 NA REG NA
N430 (???,???) [000259] ------------ IL_OFFSET void IL offset: 0xb2 REG NA
N432 ( 0, 0) [000069] ------------ NOP void REG NA
------------ BB15 [0B4..0B7) (return), preds={BB10,BB11,BB13,BB14} succs={}
N436 (???,???) [000260] ------------ IL_OFFSET void IL offset: 0xb4 REG NA
N438 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V06 loc5 rax REG rax
/--* t70 int
N440 ( 4, 3) [000071] ------------ * RETURN int REG NA
-------------------------------------------------------------------------------------------------------------------
Final allocation
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
0.#0 BB1 PredBB0 | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
4.#1 BB2 PredBB1 | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
16.#2 BB3 PredBB2 | | | | | | | | | |
19.#3 rax Kill Keep rax | | | | | | | | | |
19.#4 rcx Kill Keep rcx | | | | | | | | | |
19.#5 rdx Kill Keep rdx | | | | | | | | | |
19.#6 r8 Kill Keep r8 | | | | | | | | | |
19.#7 r9 Kill Keep r9 | | | | | | | | | |
19.#8 r10 Kill Keep r10 | | | | | | | | | |
19.#9 r11 Kill Keep r11 | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
20.#10 BB4 PredBB2 | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
22.#11 BB5 PredBB4 | | | | | | | | | |
31.#12 C0 Def Alloc rcx | |C0 a| | | | | | | |
32.#13 rcx Fixd Keep rcx | |C0 a| | | | | | | |
32.#14 C0 Use * Keep rcx | |C0 i| | | | | | | |
33.#15 rcx Fixd Keep rcx | | | | | | | | | |
33.#16 I1 Def Alloc rcx | |I1 a| | | | | | | |
34.#17 rcx Fixd Keep rcx | |I1 a| | | | | | | |
34.#18 I1 Use * Keep rcx | |I1 i| | | | | | | |
35.#19 rax Kill Keep rax | | | | | | | | | |
35.#20 rcx Kill Keep rcx | | | | | | | | | |
35.#21 rdx Kill Keep rdx | | | | | | | | | |
35.#22 r8 Kill Keep r8 | | | | | | | | | |
35.#23 r9 Kill Keep r9 | | | | | | | | | |
35.#24 r10 Kill Keep r10 | | | | | | | | | |
35.#25 r11 Kill Keep r11 | | | | | | | | | |
35.#26 rax Fixd Keep rax | | | | | | | | | |
35.#27 I2 Def Alloc rax |I2 a| | | | | | | | |
36.#28 I2 Use * Keep rax |I2 i| | | | | | | | |
39.#29 I3 Def Alloc rcx | |I3 a| | | | | | | |
40.#30 rcx Fixd Keep rcx | |I3 a| | | | | | | |
40.#31 I3 Use * Keep rcx | |I3 i| | | | | | | |
41.#32 rcx Fixd Keep rcx | | | | | | | | | |
41.#33 I4 Def Alloc rcx | |I4 a| | | | | | | |
42.#34 rcx Fixd Keep rcx | |I4 a| | | | | | | |
42.#35 I4 Use * Keep rcx | |I4 i| | | | | | | |
43.#36 rax Kill Keep rax | | | | | | | | | |
43.#37 rcx Kill Keep rcx | | | | | | | | | |
43.#38 rdx Kill Keep rdx | | | | | | | | | |
43.#39 r8 Kill Keep r8 | | | | | | | | | |
43.#40 r9 Kill Keep r9 | | | | | | | | | |
43.#41 r10 Kill Keep r10 | | | | | | | | | |
43.#42 r11 Kill Keep r11 | | | | | | | | | |
43.#43 rax Fixd Keep rax | | | | | | | | | |
43.#44 I5 Def Alloc rax |I5 a| | | | | | | | |
44.#45 I5 Use * Keep rax |I5 i| | | | | | | | |
49.#46 C6 Def Alloc rcx | |C6 a| | | | | | | |
50.#47 rcx Fixd Keep rcx | |C6 a| | | | | | | |
50.#48 C6 Use * Keep rcx | |C6 i| | | | | | | |
51.#49 rcx Fixd Keep rcx | | | | | | | | | |
51.#50 I7 Def Alloc rcx | |I7 a| | | | | | | |
52.#51 rcx Fixd Keep rcx | |I7 a| | | | | | | |
52.#52 I7 Use * Keep rcx | |I7 i| | | | | | | |
53.#53 rax Kill Keep rax | | | | | | | | | |
53.#54 rcx Kill Keep rcx | | | | | | | | | |
53.#55 rdx Kill Keep rdx | | | | | | | | | |
53.#56 r8 Kill Keep r8 | | | | | | | | | |
53.#57 r9 Kill Keep r9 | | | | | | | | | |
53.#58 r10 Kill Keep r10 | | | | | | | | | |
53.#59 r11 Kill Keep r11 | | | | | | | | | |
53.#60 rax Fixd Keep rax | | | | | | | | | |
53.#61 I8 Def Alloc rax |I8 a| | | | | | | | |
54.#62 I8 Use * Keep rax |I8 i| | | | | | | | |
57.#63 I9 Def Alloc rcx | |I9 a| | | | | | | |
58.#64 rcx Fixd Keep rcx | |I9 a| | | | | | | |
58.#65 I9 Use * Keep rcx | |I9 i| | | | | | | |
59.#66 rcx Fixd Keep rcx | | | | | | | | | |
59.#67 I10 Def Alloc rcx | |I10a| | | | | | | |
60.#68 rcx Fixd Keep rcx | |I10a| | | | | | | |
60.#69 I10 Use * Keep rcx | |I10i| | | | | | | |
61.#70 rax Kill Keep rax | | | | | | | | | |
61.#71 rcx Kill Keep rcx | | | | | | | | | |
61.#72 rdx Kill Keep rdx | | | | | | | | | |
61.#73 r8 Kill Keep r8 | | | | | | | | | |
61.#74 r9 Kill Keep r9 | | | | | | | | | |
61.#75 r10 Kill Keep r10 | | | | | | | | | |
61.#76 r11 Kill Keep r11 | | | | | | | | | |
61.#77 rax Fixd Keep rax | | | | | | | | | |
61.#78 I11 Def Alloc rax |I11a| | | | | | | | |
62.#79 I11 Use * Keep rax |I11i| | | | | | | | |
67.#80 I12 Def Alloc rcx | |I12a| | | | | | | |
68.#81 rcx Fixd Keep rcx | |I12a| | | | | | | |
68.#82 I12 Use * Keep rcx | |I12i| | | | | | | |
69.#83 rcx Fixd Keep rcx | | | | | | | | | |
69.#84 I13 Def Alloc rcx | |I13a| | | | | | | |
71.#85 I14 Def Alloc rdx | |I13a|I14a| | | | | | |
72.#86 rdx Fixd Keep rdx | |I13a|I14a| | | | | | |
72.#87 I14 Use * Keep rdx | |I13a|I14i| | | | | | |
73.#88 rdx Fixd Keep rdx | |I13a| | | | | | | |
73.#89 I15 Def Alloc rdx | |I13a|I15a| | | | | | |
74.#90 rcx Fixd Keep rcx | |I13a|I15a| | | | | | |
74.#91 I13 Use * Keep rcx | |I13i|I15a| | | | | | |
74.#92 rdx Fixd Keep rdx | | |I15a| | | | | | |
74.#93 I15 Use * Keep rdx | | |I15i| | | | | | |
75.#94 rax Kill Keep rax | | | | | | | | | |
75.#95 rcx Kill Keep rcx | | | | | | | | | |
75.#96 rdx Kill Keep rdx | | | | | | | | | |
75.#97 r8 Kill Keep r8 | | | | | | | | | |
75.#98 r9 Kill Keep r9 | | | | | | | | | |
75.#99 r10 Kill Keep r10 | | | | | | | | | |
75.#100 r11 Kill Keep r11 | | | | | | | | | |
75.#101 rax Fixd Keep rax | | | | | | | | | |
75.#102 I16 Def Alloc rax |I16a| | | | | | | | |
76.#103 I16 Use * Keep rax |I16i| | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
88.#104 BB6 PredBB5 | | | | | | | | | |
93.#105 C17 Def Alloc rcx | |C17a| | | | | | | |
94.#106 rcx Fixd Keep rcx | |C17a| | | | | | | |
94.#107 C17 Use * Keep rcx | |C17i| | | | | | | |
95.#108 rcx Fixd Keep rcx | | | | | | | | | |
95.#109 I18 Def Alloc rcx | |I18a| | | | | | | |
96.#110 rcx Fixd Keep rcx | |I18a| | | | | | | |
96.#111 I18 Use * Keep rcx | |I18i| | | | | | | |
97.#112 rax Kill Keep rax | | | | | | | | | |
97.#113 rcx Kill Keep rcx | | | | | | | | | |
97.#114 rdx Kill Keep rdx | | | | | | | | | |
97.#115 r8 Kill Keep r8 | | | | | | | | | |
97.#116 r9 Kill Keep r9 | | | | | | | | | |
97.#117 r10 Kill Keep r10 | | | | | | | | | |
97.#118 r11 Kill Keep r11 | | | | | | | | | |
97.#119 rax Fixd Keep rax | | | | | | | | | |
97.#120 I19 Def Alloc rax |I19a| | | | | | | | |
98.#121 I19 Use * Keep rax |I19i| | | | | | | | |
101.#122 I20 Def Alloc rcx | |I20a| | | | | | | |
102.#123 rcx Fixd Keep rcx | |I20a| | | | | | | |
102.#124 I20 Use * Keep rcx | |I20i| | | | | | | |
103.#125 rcx Fixd Keep rcx | | | | | | | | | |
103.#126 I21 Def Alloc rcx | |I21a| | | | | | | |
104.#127 rcx Fixd Keep rcx | |I21a| | | | | | | |
104.#128 I21 Use * Keep rcx | |I21i| | | | | | | |
105.#129 rax Kill Keep rax | | | | | | | | | |
105.#130 rcx Kill Keep rcx | | | | | | | | | |
105.#131 rdx Kill Keep rdx | | | | | | | | | |
105.#132 r8 Kill Keep r8 | | | | | | | | | |
105.#133 r9 Kill Keep r9 | | | | | | | | | |
105.#134 r10 Kill Keep r10 | | | | | | | | | |
105.#135 r11 Kill Keep r11 | | | | | | | | | |
105.#136 rax Fixd Keep rax | | | | | | | | | |
105.#137 I22 Def Alloc rax |I22a| | | | | | | | |
106.#138 I22 Use * Keep rax |I22i| | | | | | | | |
111.#139 C23 Def Alloc rcx | |C23a| | | | | | | |
112.#140 rcx Fixd Keep rcx | |C23a| | | | | | | |
112.#141 C23 Use * Keep rcx | |C23i| | | | | | | |
113.#142 rcx Fixd Keep rcx | | | | | | | | | |
113.#143 I24 Def Alloc rcx | |I24a| | | | | | | |
114.#144 rcx Fixd Keep rcx | |I24a| | | | | | | |
114.#145 I24 Use * Keep rcx | |I24i| | | | | | | |
115.#146 rax Kill Keep rax | | | | | | | | | |
115.#147 rcx Kill Keep rcx | | | | | | | | | |
115.#148 rdx Kill Keep rdx | | | | | | | | | |
115.#149 r8 Kill Keep r8 | | | | | | | | | |
115.#150 r9 Kill Keep r9 | | | | | | | | | |
115.#151 r10 Kill Keep r10 | | | | | | | | | |
115.#152 r11 Kill Keep r11 | | | | | | | | | |
115.#153 rax Fixd Keep rax | | | | | | | | | |
115.#154 I25 Def Alloc rax |I25a| | | | | | | | |
116.#155 I25 Use * Keep rax |I25i| | | | | | | | |
119.#156 I26 Def Alloc rcx | |I26a| | | | | | | |
120.#157 rcx Fixd Keep rcx | |I26a| | | | | | | |
120.#158 I26 Use * Keep rcx | |I26i| | | | | | | |
121.#159 rcx Fixd Keep rcx | | | | | | | | | |
121.#160 I27 Def Alloc rcx | |I27a| | | | | | | |
122.#161 rcx Fixd Keep rcx | |I27a| | | | | | | |
122.#162 I27 Use * Keep rcx | |I27i| | | | | | | |
123.#163 rax Kill Keep rax | | | | | | | | | |
123.#164 rcx Kill Keep rcx | | | | | | | | | |
123.#165 rdx Kill Keep rdx | | | | | | | | | |
123.#166 r8 Kill Keep r8 | | | | | | | | | |
123.#167 r9 Kill Keep r9 | | | | | | | | | |
123.#168 r10 Kill Keep r10 | | | | | | | | | |
123.#169 r11 Kill Keep r11 | | | | | | | | | |
123.#170 rax Fixd Keep rax | | | | | | | | | |
123.#171 I28 Def Alloc rax |I28a| | | | | | | | |
124.#172 I28 Use * Keep rax |I28i| | | | | | | | |
129.#173 I29 Def Alloc rcx | |I29a| | | | | | | |
130.#174 rcx Fixd Keep rcx | |I29a| | | | | | | |
130.#175 I29 Use * Keep rcx | |I29i| | | | | | | |
131.#176 rcx Fixd Keep rcx | | | | | | | | | |
131.#177 I30 Def Alloc rcx | |I30a| | | | | | | |
133.#178 I31 Def Alloc rdx | |I30a|I31a| | | | | | |
134.#179 rdx Fixd Keep rdx | |I30a|I31a| | | | | | |
134.#180 I31 Use * Keep rdx | |I30a|I31i| | | | | | |
135.#181 rdx Fixd Keep rdx | |I30a| | | | | | | |
135.#182 I32 Def Alloc rdx | |I30a|I32a| | | | | | |
136.#183 rcx Fixd Keep rcx | |I30a|I32a| | | | | | |
136.#184 I30 Use * Keep rcx | |I30i|I32a| | | | | | |
136.#185 rdx Fixd Keep rdx | | |I32a| | | | | | |
136.#186 I32 Use * Keep rdx | | |I32i| | | | | | |
137.#187 rax Kill Keep rax | | | | | | | | | |
137.#188 rcx Kill Keep rcx | | | | | | | | | |
137.#189 rdx Kill Keep rdx | | | | | | | | | |
137.#190 r8 Kill Keep r8 | | | | | | | | | |
137.#191 r9 Kill Keep r9 | | | | | | | | | |
137.#192 r10 Kill Keep r10 | | | | | | | | | |
137.#193 r11 Kill Keep r11 | | | | | | | | | |
137.#194 rax Fixd Keep rax | | | | | | | | | |
137.#195 I33 Def Alloc rax |I33a| | | | | | | | |
138.#196 I33 Use * Keep rax |I33i| | | | | | | | |
145.#197 I34 Def Alloc rcx | |I34a| | | | | | | |
146.#198 I34 Use * Keep rcx | |I34i| | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
148.#199 BB7 PredBB5 | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
156.#200 BB8 PredBB6 | | | | | | | | | |
159.#201 I35 Def Alloc rcx | |I35a| | | | | | | |
160.#202 I35 Use * Keep rcx | |I35i| | | | | | | |
161.#203 I36 Def Alloc rcx | |I36a| | | | | | | |
162.#204 I36 Use * Keep rcx | |I36i| | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
174.#205 BB9 PredBB8 | | | | | | | | | |
183.#206 I37 Def Alloc rcx | |I37a| | | | | | | |
186.#207 I37 Use * Keep rcx | |I37i| | | | | | | |
187.#208 I38 Def Alloc rcx | |I38a| | | | | | | |
188.#209 I38 Use * Keep rcx | |I38i| | | | | | | |
193.#210 I39 Def Alloc rcx | |I39a| | | | | | | |
200.#211 I40 Def Alloc mm0 | |I39a| | | | | | | |
200.#212 I39 Use * Keep rcx | |I39i| | | | | | | |
200.#213 I40 Use * Keep mm0 | | | | | | | | | |
205.#214 I41 Def Alloc rcx | |I41a| | | | | | | |
206.#215 I41 Use * Keep rcx | |I41i| | | | | | | |
209.#216 I42 Def Alloc rcx | |I42a| | | | | | | |
210.#217 rcx Fixd Keep rcx | |I42a| | | | | | | |
210.#218 I42 Use * Keep rcx | |I42i| | | | | | | |
211.#219 rcx Fixd Keep rcx | | | | | | | | | |
211.#220 I43 Def Alloc rcx | |I43a| | | | | | | |
212.#221 rcx Fixd Keep rcx | |I43a| | | | | | | |
212.#222 I43 Use * Keep rcx | |I43i| | | | | | | |
213.#223 rax Kill Keep rax | | | | | | | | | |
213.#224 rcx Kill Keep rcx | | | | | | | | | |
213.#225 rdx Kill Keep rdx | | | | | | | | | |
213.#226 r8 Kill Keep r8 | | | | | | | | | |
213.#227 r9 Kill Keep r9 | | | | | | | | | |
213.#228 r10 Kill Keep r10 | | | | | | | | | |
213.#229 r11 Kill Keep r11 | | | | | | | | | |
213.#230 rax Fixd Keep rax | | | | | | | | | |
213.#231 I44 Def Alloc rax |I44a| | | | | | | | |
214.#232 I44 Use * Keep rax |I44i| | | | | | | | |
219.#233 I45 Def Alloc rcx | |I45a| | | | | | | |
222.#234 I45 Use * Keep rcx | |I45i| | | | | | | |
223.#235 I46 Def Alloc rcx | |I46a| | | | | | | |
224.#236 I46 Use * Keep rcx | |I46i| | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
236.#237 BB10 PredBB9 | | | | | | | | | |
245.#238 I47 Def Alloc rcx | |I47a| | | | | | | |
246.#239 rcx Fixd Keep rcx | |I47a| | | | | | | |
246.#240 I47 Use * Keep rcx | |I47i| | | | | | | |
247.#241 rcx Fixd Keep rcx | | | | | | | | | |
247.#242 I48 Def Alloc rcx | |I48a| | | | | | | |
248.#243 rcx Fixd Keep rcx | |I48a| | | | | | | |
248.#244 I48 Use * Keep rcx | |I48i| | | | | | | |
249.#245 rax Kill Keep rax | | | | | | | | | |
249.#246 rcx Kill Keep rcx | | | | | | | | | |
249.#247 rdx Kill Keep rdx | | | | | | | | | |
249.#248 r8 Kill Keep r8 | | | | | | | | | |
249.#249 r9 Kill Keep r9 | | | | | | | | | |
249.#250 r10 Kill Keep r10 | | | | | | | | | |
249.#251 r11 Kill Keep r11 | | | | | | | | | |
249.#252 rax Fixd Keep rax | | | | | | | | | |
249.#253 I49 Def Alloc rax |I49a| | | | | | | | |
250.#254 I49 Use * Keep rax |I49i| | | | | | | | |
255.#255 I50 Def Alloc rcx | |I50a| | | | | | | |
256.#256 I50 Use * Keep rcx | |I50i| | | | | | | |
257.#257 I51 Def Alloc rcx | |I51a| | | | | | | |
258.#258 I51 Use * Keep rcx | |I51i| | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
264.#259 BB11 PredBB9 | | | | | | | | | |
269.#260 I52 Def Alloc rcx | |I52a| | | | | | | |
270.#261 rcx Fixd Keep rcx | |I52a| | | | | | | |
270.#262 I52 Use * Keep rcx | |I52i| | | | | | | |
271.#263 rcx Fixd Keep rcx | | | | | | | | | |
271.#264 I53 Def Alloc rcx | |I53a| | | | | | | |
273.#265 I54 Def Alloc rdx | |I53a|I54a| | | | | | |
274.#266 rdx Fixd Keep rdx | |I53a|I54a| | | | | | |
274.#267 I54 Use * Keep rdx | |I53a|I54i| | | | | | |
275.#268 rdx Fixd Keep rdx | |I53a| | | | | | | |
275.#269 I55 Def Alloc rdx | |I53a|I55a| | | | | | |
276.#270 rcx Fixd Keep rcx | |I53a|I55a| | | | | | |
276.#271 I53 Use * Keep rcx | |I53i|I55a| | | | | | |
276.#272 rdx Fixd Keep rdx | | |I55a| | | | | | |
276.#273 I55 Use * Keep rdx | | |I55i| | | | | | |
277.#274 rax Kill Keep rax | | | | | | | | | |
277.#275 rcx Kill Keep rcx | | | | | | | | | |
277.#276 rdx Kill Keep rdx | | | | | | | | | |
277.#277 r8 Kill Keep r8 | | | | | | | | | |
277.#278 r9 Kill Keep r9 | | | | | | | | | |
277.#279 r10 Kill Keep r10 | | | | | | | | | |
277.#280 r11 Kill Keep r11 | | | | | | | | | |
277.#281 rax Fixd Keep rax | | | | | | | | | |
277.#282 I56 Def Alloc rax |I56a| | | | | | | | |
278.#283 I56 Use * Keep rax |I56i| | | | | | | | |
283.#284 I57 Def Alloc rdx | | |I57a| | | | | | |
284.#285 I57 Use * Keep rdx | | |I57i| | | | | | |
285.#286 I58 Def Alloc rdx | | |I58a| | | | | | |
286.#287 I58 Use * Keep rdx | | |I58i| | | | | | |
291.#288 I59 Def Alloc rdx | | |I59a| | | | | | |
294.#289 I59 Use * Keep rdx | | |I59i| | | | | | |
295.#290 I60 Def Alloc rdx | | |I60a| | | | | | |
297.#291 I61 Def Alloc rcx | |I61a|I60a| | | | | | |
300.#292 I61 Use * Keep rcx | |I61i|I60a| | | | | | |
300.#293 I60 Use * Keep rdx | | |I60i| | | | | | |
305.#294 I62 Def Alloc rdx | | |I62a| | | | | | |
306.#295 I62 Use * Keep rdx | | |I62i| | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
312.#296 BB12 PredBB8 | | | | | | | | | |
317.#297 I63 Def Alloc rdx | | |I63a| | | | | | |
318.#298 I63 Use * Keep rdx | | |I63i| | | | | | |
321.#299 I64 Def Alloc rdx | | |I64a| | | | | | |
324.#300 I64 Use * Keep rdx | | |I64i| | | | | | |
325.#301 I65 Def Alloc rdx | | |I65a| | | | | | |
326.#302 rdx Fixd Keep rdx | | |I65a| | | | | | |
326.#303 I65 Use * Keep rdx | | |I65i| | | | | | |
327.#304 rdx Fixd Keep rdx | | | | | | | | | |
327.#305 I66 Def Alloc rdx | | |I66a| | | | | | |
329.#306 C67 Def Alloc rcx | |C67a|I66a| | | | | | |
330.#307 rcx Fixd Keep rcx | |C67a|I66a| | | | | | |
330.#308 C67 Use * Keep rcx | |C67i|I66a| | | | | | |
331.#309 rcx Fixd Keep rcx | | |I66a| | | | | | |
331.#310 I68 Def Alloc rcx | |I68a|I66a| | | | | | |
332.#311 rdx Fixd Keep rdx | |I68a|I66a| | | | | | |
332.#312 I66 Use * Keep rdx | |I68a|I66i| | | | | | |
332.#313 rcx Fixd Keep rcx | |I68a| | | | | | | |
332.#314 I68 Use * Keep rcx | |I68i| | | | | | | |
333.#315 rax Kill Keep rax | | | | | | | | | |
333.#316 rcx Kill Keep rcx | | | | | | | | | |
333.#317 rdx Kill Keep rdx | | | | | | | | | |
333.#318 r8 Kill Keep r8 | | | | | | | | | |
333.#319 r9 Kill Keep r9 | | | | | | | | | |
333.#320 r10 Kill Keep r10 | | | | | | | | | |
333.#321 r11 Kill Keep r11 | | | | | | | | | |
333.#322 rax Fixd Keep rax | | | | | | | | | |
333.#323 I69 Def Alloc rax |I69a| | | | | | | | |
334.#324 I69 Use * Keep rax |I69i| | | | | | | | |
337.#325 I70 Def Alloc rdx | | |I70a| | | | | | |
338.#326 rdx Fixd Keep rdx | | |I70a| | | | | | |
338.#327 I70 Use * Keep rdx | | |I70i| | | | | | |
339.#328 rdx Fixd Keep rdx | | | | | | | | | |
339.#329 I71 Def Alloc rdx | | |I71a| | | | | | |
341.#330 C72 Def Alloc rcx | |C72a|I71a| | | | | | |
342.#331 rcx Fixd Keep rcx | |C72a|I71a| | | | | | |
342.#332 C72 Use * Keep rcx | |C72i|I71a| | | | | | |
343.#333 rcx Fixd Keep rcx | | |I71a| | | | | | |
343.#334 I73 Def Alloc rcx | |I73a|I71a| | | | | | |
344.#335 rdx Fixd Keep rdx | |I73a|I71a| | | | | | |
344.#336 I71 Use * Keep rdx | |I73a|I71i| | | | | | |
344.#337 rcx Fixd Keep rcx | |I73a| | | | | | | |
344.#338 I73 Use * Keep rcx | |I73i| | | | | | | |
345.#339 rax Kill Keep rax | | | | | | | | | |
345.#340 rcx Kill Keep rcx | | | | | | | | | |
345.#341 rdx Kill Keep rdx | | | | | | | | | |
345.#342 r8 Kill Keep r8 | | | | | | | | | |
345.#343 r9 Kill Keep r9 | | | | | | | | | |
345.#344 r10 Kill Keep r10 | | | | | | | | | |
345.#345 r11 Kill Keep r11 | | | | | | | | | |
345.#346 rax Fixd Keep rax | | | | | | | | | |
345.#347 I74 Def Alloc rax |I74a| | | | | | | | |
346.#348 I74 Use * Keep rax |I74i| | | | | | | | |
355.#349 I75 Def Alloc rcx | |I75a| | | | | | | |
356.#350 I75 Use * Keep rcx | |I75i| | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
368.#351 BB13 PredBB12 | | | | | | | | | |
377.#352 I76 Def Alloc rcx | |I76a| | | | | | | |
378.#353 rcx Fixd Keep rcx | |I76a| | | | | | | |
378.#354 I76 Use * Keep rcx | |I76i| | | | | | | |
379.#355 rcx Fixd Keep rcx | | | | | | | | | |
379.#356 I77 Def Alloc rcx | |I77a| | | | | | | |
381.#357 I78 Def Alloc rax |I78a|I77a| | | | | | | |
384.#358 I78 Use * Keep rax |I78i|I77a| | | | | | | |
385.#359 I79 Def Alloc rax |I79a|I77a| | | | | | | |
388.#360 I79 Use * Keep rax |I79i|I77a| | | | | | | |
389.#361 I80 Def Alloc rax |I80a|I77a| | | | | | | |
394.#362 rcx Fixd Keep rcx |I80a|I77a| | | | | | | |
394.#363 I77 Use * Keep rcx |I80a|I77i| | | | | | | |
394.#364 I80 Use * Keep rax |I80i| | | | | | | | |
395.#365 rax Kill Keep rax | | | | | | | | | |
395.#366 rcx Kill Keep rcx | | | | | | | | | |
395.#367 rdx Kill Keep rdx | | | | | | | | | |
395.#368 r8 Kill Keep r8 | | | | | | | | | |
395.#369 r9 Kill Keep r9 | | | | | | | | | |
395.#370 r10 Kill Keep r10 | | | | | | | | | |
395.#371 r11 Kill Keep r11 | | | | | | | | | |
395.#372 rax Fixd Keep rax | | | | | | | | | |
395.#373 I81 Def Alloc rax |I81a| | | | | | | | |
396.#374 I81 Use * Keep rax |I81i| | | | | | | | |
401.#375 I82 Def Alloc rax |I82a| | | | | | | | |
402.#376 I82 Use * Keep rax |I82i| | | | | | | | |
403.#377 I83 Def Alloc rax |I83a| | | | | | | | |
404.#378 I83 Use * Keep rax |I83i| | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
410.#379 BB14 PredBB12 | | | | | | | | | |
419.#380 rax Kill Keep rax | | | | | | | | | |
419.#381 rcx Kill Keep rcx | | | | | | | | | |
419.#382 rdx Kill Keep rdx | | | | | | | | | |
419.#383 r8 Kill Keep r8 | | | | | | | | | |
419.#384 r9 Kill Keep r9 | | | | | | | | | |
419.#385 r10 Kill Keep r10 | | | | | | | | | |
419.#386 r11 Kill Keep r11 | | | | | | | | | |
419.#387 rax Fixd Keep rax | | | | | | | | | |
419.#388 I84 Def Alloc rax |I84a| | | | | | | | |
420.#389 I84 Use * Keep rax |I84i| | | | | | | | |
425.#390 I85 Def Alloc rax |I85a| | | | | | | | |
426.#391 I85 Use * Keep rax |I85i| | | | | | | | |
427.#392 I86 Def Alloc rax |I86a| | | | | | | | |
428.#393 I86 Use * Keep rax |I86i| | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
434.#394 BB15 PredBB10 | | | | | | | | | |
439.#395 I87 Def Alloc rax |I87a| | | | | | | | |
440.#396 rax Fixd Keep rax |I87a| | | | | | | | |
440.#397 I87 Use * Keep rax |I87i| | | | | | | | |
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
Total Tracked Vars: 0
Total Reg Cand Vars: 0
Total number of Intervals: 87
Total number of RefPositions: 397
Total Spill Count: 0 Weighted: 0.000000
Total CopyReg Count: 0 Weighted: 0.000000
Total ResolutionMov Count: 0 Weighted: 0.000000
Total number of split edges: 0
Total Number of spill temps created: 0
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters:
BB01 [???..???), preds={} succs={BB02}
=====
N002. NOP
BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
=====
N006. CNS_INT(h) 0x7ff9392a5420 global ptr
N008. IND
N010. CNS_INT 0
N012. EQ
N014. JTRUE
BB03 [???..???), preds={BB02} succs={BB04}
=====
N018. CALL help
BB04 [???..???), preds={BB02,BB03} succs={BB05}
=====
BB05 [000..01C) -> BB07 (cond), preds={BB04} succs={BB06,BB07}
=====
N024. IL_OFFSET IL offset: 0x0
N026. NO_OP
N028. IL_OFFSET IL offset: 0x1
N030. rcx = CNS_INT(h) 0x7ff93af7cd80 class
N032. rcx = PUTARG_REG; rcx
N034. rax = CALL help; rcx
N036. V10 MEM; rax
N038. rcx = V10 MEM
N040. rcx = PUTARG_REG; rcx
N042. rax = CALL ; rcx
N044. V11 MEM; rax
N046. IL_OFFSET IL offset: 0xb
N048. rcx = CNS_INT(h) 0x7ff93af7cd80 class
N050. rcx = PUTARG_REG; rcx
N052. rax = CALL help; rcx
N054. V12 MEM; rax
N056. rcx = V12 MEM
N058. rcx = PUTARG_REG; rcx
N060. rax = CALL ; rcx
N062. V13 MEM; rax
N064. IL_OFFSET IL offset: 0x15
N066. rcx = V11 MEM
N068. rcx = PUTARG_REG; rcx
N070. rdx = V13 MEM
N072. rdx = PUTARG_REG; rdx
N074. rax = CALL ; rcx,rdx
N076. V14 MEM; rax
N078. IL_OFFSET IL offset: 0x1a
N080. V14 MEM
N082. CNS_INT 0
N084. NE
N086. JTRUE
BB06 [01C..037) -> BB08 (always), preds={BB05} succs={BB08}
=====
N090. IL_OFFSET IL offset: 0x1c
N092. rcx = CNS_INT(h) 0x7ff93af7cd80 class
N094. rcx = PUTARG_REG; rcx
N096. rax = CALL help; rcx
N098. V22 MEM; rax
N100. rcx = V22 MEM
N102. rcx = PUTARG_REG; rcx
N104. rax = CALL ; rcx
N106. V23 MEM; rax
N108. IL_OFFSET IL offset: 0x26
N110. rcx = CNS_INT(h) 0x7ff93b56a7f8 class
N112. rcx = PUTARG_REG; rcx
N114. rax = CALL help; rcx
N116. V24 MEM; rax
N118. rcx = V24 MEM
N120. rcx = PUTARG_REG; rcx
N122. rax = CALL ; rcx
N124. V25 MEM; rax
N126. IL_OFFSET IL offset: 0x30
N128. rcx = V23 MEM
N130. rcx = PUTARG_REG; rcx
N132. rdx = V25 MEM
N134. rdx = PUTARG_REG; rdx
N136. rax = CALL ; rcx,rdx
N138. V26 MEM; rax
N140. IL_OFFSET IL offset: 0x35
N142. NOP
N144. rcx = V26 MEM
N146. V15 MEM; rcx
BB07 [037..038), preds={BB05} succs={BB08}
=====
N150. IL_OFFSET IL offset: 0x37
N152. CNS_INT 1
N154. V15 MEM
BB08 [038..03C) -> BB12 (cond), preds={BB06,BB07} succs={BB09,BB12}
=====
N158. rcx = V15 MEM
N160. rcx = CAST ; rcx
N162. V01 MEM; rcx
N164. IL_OFFSET IL offset: 0x39
N166. V01 MEM
N168. CNS_INT 0
N170. EQ
N172. JTRUE
BB09 [03C..05E) -> BB11 (cond), preds={BB08} succs={BB10,BB11}
=====
N176. IL_OFFSET IL offset: 0x3c
N178. NO_OP
N180. IL_OFFSET IL offset: 0x3d
N182. rcx = V00 MEM
N184. STK = LEA(b+24); rcx
N186. rcx = IND ; STK
N188. V02 MEM; rcx
N190. IL_OFFSET IL offset: 0x44
N192. rcx = V00 MEM
N194. STK = LEA(b+32); rcx
N196. STK = IND ; STK
N198. LCL_VAR_ADDR V03 loc2 NA
N200. STORE_BLK; STK
N202. IL_OFFSET IL offset: 0x4b
N204. rcx = V02 MEM
N206. V18 MEM; rcx
N208. rcx = LCL_VAR_ADDR V03 loc2 rcx
N210. rcx = PUTARG_REG; rcx
N212. rax = CALL ; rcx
N214. V19 MEM; rax
N216. IL_OFFSET IL offset: 0x53
N218. rcx = V18 MEM
N220. V19 MEM
N222. rcx = GE ; rcx
N224. V05 MEM; rcx
N226. IL_OFFSET IL offset: 0x5a
N228. V05 MEM
N230. CNS_INT 0
N232. EQ
N234. JTRUE
BB10 [05E..069) -> BB15 (always), preds={BB09} succs={BB15}
=====
N238. IL_OFFSET IL offset: 0x5e
N240. NO_OP
N242. IL_OFFSET IL offset: 0x5f
N244. rcx = V00 MEM
N246. rcx = PUTARG_REG; rcx
N248. rax = CALL ; rcx
N250. V21 MEM; rax
N252. IL_OFFSET IL offset: 0x65
N254. rcx = V21 MEM
N256. rcx = CAST ; rcx
N258. V06 MEM; rcx
N260. IL_OFFSET IL offset: 0x67
N262. NOP
BB11 [069..081) -> BB15 (always), preds={BB09} succs={BB15}
=====
N266. IL_OFFSET IL offset: 0x69
N268. rcx = LCL_VAR_ADDR V03 loc2 rcx
N270. rcx = PUTARG_REG; rcx
N272. rdx = V02 MEM
N274. rdx = PUTARG_REG; rdx
N276. rax = CALL ; rcx,rdx
N278. V20 MEM; rax
N280. IL_OFFSET IL offset: 0x71
N282. rdx = V20 MEM
N284. rdx = IND ; rdx
N286. V04 MEM; rdx
N288. IL_OFFSET IL offset: 0x73
N290. rdx = V02 MEM
N292. CNS_INT 1
N294. rdx = ADD ; rdx
N296. rcx = V00 MEM
N298. STK = LEA(b+24); rcx
N300. STOREIND ; STK,rdx
N302. IL_OFFSET IL offset: 0x7c
N304. rdx = V04 MEM
N306. V06 MEM; rdx
N308. IL_OFFSET IL offset: 0x7f
N310. NOP
BB12 [081..09E) -> BB14 (cond), preds={BB08} succs={BB13,BB14}
=====
N314. IL_OFFSET IL offset: 0x81
N316. rdx = V00 MEM
N318. NULLCHECK; rdx
N320. rdx = V00 MEM
N322. CNS_INT 64 field offset Fseq[_input]
N324. rdx = ADD ; rdx
N326. rdx = PUTARG_REG; rdx
N328. rcx = CNS_INT(h) 0x7ff93af7cd80 class
N330. rcx = PUTARG_REG; rcx
N332. rax = CALL help; rdx,rcx
N334. V27 MEM; rax
N336. rdx = V27 MEM
N338. rdx = PUTARG_REG; rdx
N340. rcx = CNS_INT(h) 0x7ff93b569758 class
N342. rcx = PUTARG_REG; rcx
N344. rax = CALL help; rdx,rcx
N346. V07 MEM; rax
N348. IL_OFFSET IL offset: 0x93
N350. V07 MEM
N352. CNS_INT null
N354. rcx = NE
N356. V08 MEM; rcx
N358. IL_OFFSET IL offset: 0x9a
N360. V08 MEM
N362. CNS_INT 0
N364. EQ
N366. JTRUE
BB13 [09E..0AA) -> BB15 (always), preds={BB12} succs={BB15}
=====
N370. IL_OFFSET IL offset: 0x9e
N372. NO_OP
N374. IL_OFFSET IL offset: 0x9f
N376. rcx = V07 MEM
N378. rcx = PUTARG_REG; rcx
N380. rax = V07 MEM
N382. STK = LEA(b+0) ; rax
N384. rax = IND ; STK
N386. STK = LEA(b+72); rax
N388. rax = IND ; STK
N390. STK = LEA(b+56); rax
N392. STK = IND ; STK
N394. rax = CALLV ind; rcx,STK
N396. V17 MEM; rax
N398. IL_OFFSET IL offset: 0xa6
N400. rax = V17 MEM
N402. rax = CAST ; rax
N404. V06 MEM; rax
N406. IL_OFFSET IL offset: 0xa8
N408. NOP
BB14 [0AA..0B4) -> BB15 (always), preds={BB12} succs={BB15}
=====
N412. IL_OFFSET IL offset: 0xaa
N414. NO_OP
N416. IL_OFFSET IL offset: 0xab
N418. rax = CALL
N420. V16 MEM; rax
N422. IL_OFFSET IL offset: 0xb0
N424. rax = V16 MEM
N426. rax = CAST ; rax
N428. V06 MEM; rax
N430. IL_OFFSET IL offset: 0xb2
N432. NOP
BB15 [0B4..0B7) (return), preds={BB10,BB11,BB13,BB14} succs={}
=====
N436. IL_OFFSET IL offset: 0xb4
N438. rax = V06 MEM
N440. RETURN ; rax
*************** Finishing PHASE Linear scan register alloc
*************** In genGenerateCode()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target hascall LIR
BB02 [0013] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
BB03 [0014] 1 BB02 0.50 [???..???) internal LIR
BB04 [0012] 2 BB02,BB03 1 [???..???) i internal label target hascall LIR
BB05 [0001] 1 BB04 1 [000..01C)-> BB07 ( cond ) i hascall LIR
BB06 [0002] 1 BB05 1 [01C..037)-> BB08 (always) i hascall LIR
BB07 [0003] 1 BB05 1 [037..038) i label target LIR
BB08 [0004] 2 BB06,BB07 1 [038..03C)-> BB12 ( cond ) i label target LIR
BB09 [0005] 1 BB08 1 [03C..05E)-> BB11 ( cond ) i hascall LIR
BB10 [0006] 1 BB09 1 [05E..069)-> BB15 (always) i hascall gcsafe LIR
BB11 [0007] 1 BB09 1 [069..081)-> BB15 (always) i label target hascall LIR
BB12 [0008] 1 BB08 1 [081..09E)-> BB14 ( cond ) i label target hascall nullcheck LIR
BB13 [0009] 1 BB12 1 [09E..0AA)-> BB15 (always) i hascall gcsafe LIR
BB14 [0010] 1 BB12 1 [0AA..0B4)-> BB15 (always) i label target hascall gcsafe LIR
BB15 [0011] 4 BB10,BB11,BB13,BB14 1 [0B4..0B7) (return) i label target LIR
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
; Assembly listing for method Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this
; Emitting BLENDED_CODE for X64 CPU with AVX - Windows
; debuggable code
; rbp based frame
; fully interruptible
Finalizing stack frame
Modified regs: [rax rcx rdx r8-r11 mm0]
Callee-saved registers pushed: 0 []
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Assign V01 loc0, size=4, stkOffs=-0x14
Assign V02 loc1, size=4, stkOffs=-0x18
Assign V03 loc2, size=16, stkOffs=-0x28
Assign V04 loc3, size=4, stkOffs=-0x2c
Assign V05 loc4, size=4, stkOffs=-0x30
Assign V06 loc5, size=4, stkOffs=-0x34
Pad V07 loc6, size=8, stkOffs=-0x38, pad=4
Assign V07 loc6, size=8, stkOffs=-0x40
Assign V08 loc7, size=4, stkOffs=-0x44
Pad V10 tmp1, size=8, stkOffs=-0x48, pad=4
Assign V10 tmp1, size=8, stkOffs=-0x50
Assign V11 tmp2, size=8, stkOffs=-0x58
Assign V12 tmp3, size=8, stkOffs=-0x60
Assign V13 tmp4, size=8, stkOffs=-0x68
Assign V14 tmp5, size=4, stkOffs=-0x6c
Assign V15 tmp6, size=4, stkOffs=-0x70
Assign V16 tmp7, size=4, stkOffs=-0x74
Assign V17 tmp8, size=4, stkOffs=-0x78
Assign V18 tmp9, size=4, stkOffs=-0x7c
Assign V19 tmp10, size=4, stkOffs=-0x80
Assign V20 tmp11, size=8, stkOffs=-0x88
Assign V21 tmp12, size=4, stkOffs=-0x8c
Pad V22 tmp13, size=8, stkOffs=-0x90, pad=4
Assign V22 tmp13, size=8, stkOffs=-0x98
Assign V23 tmp14, size=8, stkOffs=-0xa0
Assign V24 tmp15, size=8, stkOffs=-0xa8
Assign V25 tmp16, size=8, stkOffs=-0xb0
Assign V26 tmp17, size=4, stkOffs=-0xb4
Pad V27 tmp18, size=8, stkOffs=-0xb8, pad=4
Assign V27 tmp18, size=8, stkOffs=-0xc0
Assign V09 OutArgs, size=32, stkOffs=-0xe0
--- delta bump 8 for RA
--- delta bump 8 for FP
--- delta bump 0 for RBP frame
--- virtual stack offset to actual stack offset delta is 16
-- V00 was 0, now 16
-- V01 was -20, now -4
-- V02 was -24, now -8
-- V03 was -40, now -24
-- V04 was -44, now -28
-- V05 was -48, now -32
-- V06 was -52, now -36
-- V07 was -64, now -48
-- V08 was -68, now -52
-- V09 was -224, now -208
-- V10 was -80, now -64
-- V11 was -88, now -72
-- V12 was -96, now -80
-- V13 was -104, now -88
-- V14 was -108, now -92
-- V15 was -112, now -96
-- V16 was -116, now -100
-- V17 was -120, now -104
-- V18 was -124, now -108
-- V19 was -128, now -112
-- V20 was -136, now -120
-- V21 was -140, now -124
-- V22 was -152, now -136
-- V23 was -160, now -144
-- V24 was -168, now -152
-- V25 was -176, now -160
-- V26 was -180, now -164
-- V27 was -192, now -176
; Final local variable assignments
;
; V00 this [V00 ] ( 1, 1 ) byref -> [rbp+0x10] this
; V01 loc0 [V01 ] ( 1, 1 ) bool -> [rbp-0x04] must-init
; V02 loc1 [V02 ] ( 1, 1 ) int -> [rbp-0x08] must-init
; V03 loc2 [V03 ] ( 1, 1 ) struct (16) [rbp-0x18] do-not-enreg[XSB] must-init addr-exposed ld-addr-op
; V04 loc3 [V04 ] ( 1, 1 ) ubyte -> [rbp-0x1C] must-init
; V05 loc4 [V05 ] ( 1, 1 ) bool -> [rbp-0x20] must-init
; V06 loc5 [V06 ] ( 1, 1 ) ubyte -> [rbp-0x24] must-init
; V07 loc6 [V07 ] ( 1, 1 ) ref -> [rbp-0x30] must-init class-hnd
; V08 loc7 [V08 ] ( 1, 1 ) bool -> [rbp-0x34] must-init
; V09 OutArgs [V09 ] ( 1, 1 ) lclBlk (32) [rsp+0x00] "OutgoingArgSpace"
; V10 tmp1 [V10 ] ( 1, 1 ) struct ( 8) [rbp-0x40] do-not-enreg[SB] must-init "struct address for call/obj"
; V11 tmp2 [V11 ] ( 1, 1 ) ref -> [rbp-0x48] must-init class-hnd "impSpillStackEnsure"
; V12 tmp3 [V12 ] ( 1, 1 ) struct ( 8) [rbp-0x50] do-not-enreg[SB] must-init "struct address for call/obj"
; V13 tmp4 [V13 ] ( 1, 1 ) ref -> [rbp-0x58] must-init class-hnd "impSpillStackEnsure"
; V14 tmp5 [V14 ] ( 1, 1 ) int -> [rbp-0x5C] "impSpillStackEnsure"
; V15 tmp6 [V15 ] ( 1, 1 ) int -> [rbp-0x60] must-init
; V16 tmp7 [V16 ] ( 1, 1 ) int -> [rbp-0x64] "impSpillStackEnsure"
; V17 tmp8 [V17 ] ( 1, 1 ) int -> [rbp-0x68] "impSpillStackEnsure"
; V18 tmp9 [V18 ] ( 1, 1 ) int -> [rbp-0x6C] "impSpillStackEnsure"
; V19 tmp10 [V19 ] ( 1, 1 ) int -> [rbp-0x70] "impSpillStackEnsure"
; V20 tmp11 [V20 ] ( 1, 1 ) byref -> [rbp-0x78] must-init "impSpillStackEnsure"
; V21 tmp12 [V21 ] ( 1, 1 ) int -> [rbp-0x7C] "impSpillStackEnsure"
; V22 tmp13 [V22 ] ( 1, 1 ) struct ( 8) [rbp-0x88] do-not-enreg[SB] must-init "struct address for call/obj"
; V23 tmp14 [V23 ] ( 1, 1 ) ref -> [rbp-0x90] must-init class-hnd "impSpillStackEnsure"
; V24 tmp15 [V24 ] ( 1, 1 ) struct ( 8) [rbp-0x98] do-not-enreg[SB] must-init "struct address for call/obj"
; V25 tmp16 [V25 ] ( 1, 1 ) ref -> [rbp-0xA0] must-init class-hnd "impSpillStackEnsure"
; V26 tmp17 [V26 ] ( 1, 1 ) int -> [rbp-0xA4] "impSpillStackEnsure"
; V27 tmp18 [V27 ] ( 1, 1 ) ref -> [rbp-0xB0] must-init "argument with side effect"
;
; Lcl frame size = 208
Setting stack level from -572662307 to 0
=============== Generating BB01 [???..???), preds={} succs={BB02} flags=0x00000002.20030060: i internal label target hascall LIR
BB01 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M45291_BB01:
Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB01, IL range [???..???)
Scope info: ignoring block beginning
Generating: N002 ( 0, 0) [000000] ------------ NOP void REG NA
Scope info: end block BB01, IL range [???..???)
Scope info: ignoring block end
=============== Generating BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} flags=0x00000000.20000040: internal LIR
BB02 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M45291_BB02:
Scope info: begin block BB02, IL range [???..???)
Scope info: ignoring block beginning
Added IP mapping: NO_MAP STACK_EMPTY (G_M45291_IG02,ins#0,ofs#0) label
Generating: N006 ( 2, 10) [000171] Hc---------- t171 = CNS_INT(h) long 0x7ff9392a5420 global ptr REG NA
/--* t171 long
Generating: N008 ( 4, 12) [000172] nc---------- t172 = * IND int REG NA
Generating: N010 ( 1, 1) [000173] -c---------- t173 = CNS_INT int 0 REG NA
/--* t172 int
+--* t173 int
Generating: N012 ( 6, 14) [000174] J------N---- * EQ void REG NA
IN0001: cmp dword ptr [(reloc)], 0
Generating: N014 ( 8, 16) [000221] ------------ * JTRUE void REG NA
IN0002: je L_M45291_BB04
Scope info: end block BB02, IL range [???..???)
Scope info: ignoring block end
=============== Generating BB03 [???..???), preds={BB02} succs={BB04} flags=0x00000000.20000040: internal LIR
BB03 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M45291_BB03:
G_M45291_IG02: ; offs=000000H, funclet=00, bbWeight=1
Label: IG03, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB03, IL range [???..???)
Scope info: ignoring block beginning
genIPmappingAdd: ignoring duplicate IL offset 0xffffffff
Generating: N018 ( 14, 5) [000175] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE REG NA
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0003: call CORINFO_HELP_DBG_IS_JUST_MY_CODE
Scope info: end block BB03, IL range [???..???)
Scope info: ignoring block end
=============== Generating BB04 [???..???), preds={BB02,BB03} succs={BB05} flags=0x00000002.20030060: i internal label target hascall LIR
BB04 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M45291_BB04:
G_M45291_IG03: ; offs=00000DH, funclet=00, bbWeight=0.50
Label: IG04, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB04, IL range [???..???)
Scope info: ignoring block beginning
genIPmappingAdd: ignoring duplicate IL offset 0xffffffff
Scope info: end block BB04, IL range [???..???)
Scope info: ignoring block end
=============== Generating BB05 [000..01C) -> BB07 (cond), preds={BB04} succs={BB06,BB07} flags=0x00000002.20000020: i hascall LIR
BB05 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M45291_BB05:
Scope info: begin block BB05, IL range [000..01C)
Scope info: opening scope, LVnum=0 [000..0B7)
Scope info: >> new scope, VarNum=0, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
Scope info: opening scope, LVnum=7 [000..0B7)
Scope info: >> new scope, VarNum=7, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
Scope info: opening scope, LVnum=6 [000..0B7)
Scope info: >> new scope, VarNum=6, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
Scope info: opening scope, LVnum=5 [000..0B7)
Scope info: >> new scope, VarNum=5, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
Scope info: opening scope, LVnum=4 [000..0B7)
Scope info: >> new scope, VarNum=4, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
Scope info: opening scope, LVnum=3 [000..0B7)
Scope info: >> new scope, VarNum=3, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
Scope info: opening scope, LVnum=2 [000..0B7)
Scope info: >> new scope, VarNum=2, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
Scope info: opening scope, LVnum=1 [000..0B7)
Scope info: >> new scope, VarNum=1, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
Scope info: opening scope, LVnum=8 [000..0B7)
Scope info: >> new scope, VarNum=8, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
Scope info: open scopes =
0 (V00 this) [000..0B7)
7 (V07 loc6) [000..0B7)
6 (V06 loc5) [000..0B7)
5 (V05 loc4) [000..0B7)
4 (V04 loc3) [000..0B7)
3 (V03 loc2) [000..0B7)
2 (V02 loc1) [000..0B7)
1 (V01 loc0) [000..0B7)
8 (V08 loc7) [000..0B7)
Added IP mapping: 0x0000 STACK_EMPTY (G_M45291_IG04,ins#0,ofs#0) label
Generating: N024 (???,???) [000222] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N026 ( 1, 1) [000001] ------------ NO_OP void REG NA
IN0004: nop
Added IP mapping: 0x0001 STACK_EMPTY (G_M45291_IG04,ins#1,ofs#1)
Generating: N028 (???,???) [000223] ------------ IL_OFFSET void IL offset: 0x1 REG NA
Generating: N030 ( 2, 10) [000002] H----------- t2 = CNS_INT(h) long 0x7ff93af7cd80 class REG rcx
IN0005: mov rcx, 0x7FF93AF7CD80
/--* t2 long
Generating: N032 (???,???) [000261] ------------ t261 = * PUTARG_REG long REG rcx
/--* t261 long arg0 in rcx
Generating: N034 ( 16, 16) [000003] --C-G------- t3 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE REG rax
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0006: call CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
GC regs: 00000000 {} => 00000001 {rax}
/--* t3 ref
Generating: N036 ( 20, 19) [000007] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V10 tmp1 NA REG NA
GC regs: 00000001 {rax} => 00000000 {}
IN0007: mov gword ptr [V10 rbp-40H], rax
Generating: N038 ( 3, 4) [000008] ------------ t8 = LCL_FLD ref V10 tmp1 [+0] rcx REG rcx
IN0008: mov rcx, gword ptr [V10 rbp-40H]
GC regs: 00000000 {} => 00000002 {rcx}
/--* t8 ref
Generating: N040 (???,???) [000262] ------------ t262 = * PUTARG_REG ref REG rcx
GC regs: 00000002 {rcx} => 00000000 {}
GC regs: 00000000 {} => 00000002 {rcx}
/--* t262 ref arg0 in rcx
Generating: N042 ( 17, 10) [000004] --CXG------- t4 = * CALL ref System.Type.GetTypeFromHandle REG rax
GC regs: 00000002 {rcx} => 00000000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Added IP mapping: 0x0006 CALL_INSTRUCTION (G_M45291_IG04,ins#5,ofs#24)
IN0009: call System.Type:GetTypeFromHandle(System.RuntimeTypeHandle):System.Type
GC regs: 00000000 {} => 00000001 {rax}
/--* t4 ref
Generating: N044 ( 21, 13) [000012] DA-XG------- * STORE_LCL_VAR ref V11 tmp2 NA REG NA
GC regs: 00000001 {rax} => 00000000 {}
IN000a: mov gword ptr [V11 rbp-48H], rax
Added IP mapping: 0x000B (G_M45291_IG04,ins#7,ofs#33)
Generating: N046 (???,???) [000224] ------------ IL_OFFSET void IL offset: 0xb REG NA
Generating: N048 ( 2, 10) [000014] H----------- t14 = CNS_INT(h) long 0x7ff93af7cd80 class REG rcx
IN000b: mov rcx, 0x7FF93AF7CD80
/--* t14 long
Generating: N050 (???,???) [000263] ------------ t263 = * PUTARG_REG long REG rcx
/--* t263 long arg0 in rcx
Generating: N052 ( 16, 16) [000015] --C-G------- t15 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE REG rax
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN000c: call CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
GC regs: 00000000 {} => 00000001 {rax}
/--* t15 ref
Generating: N054 ( 20, 19) [000019] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V12 tmp3 NA REG NA
GC regs: 00000001 {rax} => 00000000 {}
IN000d: mov gword ptr [V12 rbp-50H], rax
Generating: N056 ( 3, 4) [000020] ------------ t20 = LCL_FLD ref V12 tmp3 [+0] rcx REG rcx
IN000e: mov rcx, gword ptr [V12 rbp-50H]
GC regs: 00000000 {} => 00000002 {rcx}
/--* t20 ref
Generating: N058 (???,???) [000264] ------------ t264 = * PUTARG_REG ref REG rcx
GC regs: 00000002 {rcx} => 00000000 {}
GC regs: 00000000 {} => 00000002 {rcx}
/--* t264 ref arg0 in rcx
Generating: N060 ( 17, 10) [000016] --CXG------- t16 = * CALL ref System.Type.GetTypeFromHandle REG rax
GC regs: 00000002 {rcx} => 00000000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Added IP mapping: 0x0010 CALL_INSTRUCTION (G_M45291_IG04,ins#11,ofs#56)
IN000f: call System.Type:GetTypeFromHandle(System.RuntimeTypeHandle):System.Type
GC regs: 00000000 {} => 00000001 {rax}
/--* t16 ref
Generating: N062 ( 21, 13) [000024] DA-XG------- * STORE_LCL_VAR ref V13 tmp4 NA REG NA
GC regs: 00000001 {rax} => 00000000 {}
IN0010: mov gword ptr [V13 rbp-58H], rax
Added IP mapping: 0x0015 (G_M45291_IG04,ins#13,ofs#65)
Generating: N064 (???,???) [000225] ------------ IL_OFFSET void IL offset: 0x15 REG NA
Generating: N066 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V11 tmp2 rcx REG rcx
IN0011: mov rcx, gword ptr [V11 rbp-48H]
GC regs: 00000000 {} => 00000002 {rcx}
/--* t13 ref
Generating: N068 (???,???) [000265] ------------ t265 = * PUTARG_REG ref REG rcx
GC regs: 00000002 {rcx} => 00000000 {}
GC regs: 00000000 {} => 00000002 {rcx}
Generating: N070 ( 3, 2) [000025] ------------ t25 = LCL_VAR ref V13 tmp4 rdx REG rdx
IN0012: mov rdx, gword ptr [V13 rbp-58H]
GC regs: 00000002 {rcx} => 00000006 {rcx rdx}
/--* t25 ref
Generating: N072 (???,???) [000266] ------------ t266 = * PUTARG_REG ref REG rdx
GC regs: 00000006 {rcx rdx} => 00000002 {rcx}
GC regs: 00000002 {rcx} => 00000006 {rcx rdx}
/--* t265 ref arg0 in rcx
+--* t266 ref arg1 in rdx
Generating: N074 ( 20, 11) [000026] --CXG------- t26 = * CALL int System.Type.op_Equality REG rax
GC regs: 00000006 {rcx rdx} => 00000004 {rdx}
GC regs: 00000004 {rdx} => 00000000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Added IP mapping: 0x0015 CALL_INSTRUCTION (G_M45291_IG04,ins#15,ofs#73)
IN0013: call System.Type:op_Equality(System.Type,System.Type):bool
/--* t26 int
Generating: N076 ( 24, 14) [000028] DA-XG------- * STORE_LCL_VAR int V14 tmp5 NA REG NA
IN0014: mov dword ptr [V14 rbp-5CH], eax
Added IP mapping: 0x001A (G_M45291_IG04,ins#17,ofs#81)
Generating: N078 (???,???) [000226] ------------ IL_OFFSET void IL offset: 0x1a REG NA
Generating: N080 ( 3, 2) [000029] -c---------- t29 = LCL_VAR int V14 tmp5 NA REG NA
Generating: N082 ( 1, 1) [000030] -c---------- t30 = CNS_INT int 0 REG NA
/--* t29 int
+--* t30 int
Generating: N084 ( 5, 4) [000031] J------N---- * NE void REG NA
IN0015: cmp dword ptr [V14 rbp-5CH], 0
Generating: N086 ( 7, 6) [000032] ------------ * JTRUE void REG NA
IN0016: jne L_M45291_BB07
Scope info: end block BB05, IL range [000..01C)
Scope info: open scopes =
0 (V00 this) [000..0B7)
7 (V07 loc6) [000..0B7)
6 (V06 loc5) [000..0B7)
5 (V05 loc4) [000..0B7)
4 (V04 loc3) [000..0B7)
3 (V03 loc2) [000..0B7)
2 (V02 loc1) [000..0B7)
1 (V01 loc0) [000..0B7)
8 (V08 loc7) [000..0B7)
=============== Generating BB06 [01C..037) -> BB08 (always), preds={BB05} succs={BB08} flags=0x00000002.20000020: i hascall LIR
BB06 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M45291_BB06:
Scope info: begin block BB06, IL range [01C..037)
Scope info: open scopes =
0 (V00 this) [000..0B7)
7 (V07 loc6) [000..0B7)
6 (V06 loc5) [000..0B7)
5 (V05 loc4) [000..0B7)
4 (V04 loc3) [000..0B7)
3 (V03 loc2) [000..0B7)
2 (V02 loc1) [000..0B7)
1 (V01 loc0) [000..0B7)
8 (V08 loc7) [000..0B7)
Added IP mapping: 0x001C STACK_EMPTY (G_M45291_IG04,ins#19,ofs#91) label
Generating: N090 (???,???) [000227] ------------ IL_OFFSET void IL offset: 0x1c REG NA
Generating: N092 ( 2, 10) [000139] H----------- t139 = CNS_INT(h) long 0x7ff93af7cd80 class REG rcx
IN0017: mov rcx, 0x7FF93AF7CD80
/--* t139 long
Generating: N094 (???,???) [000267] ------------ t267 = * PUTARG_REG long REG rcx
/--* t267 long arg0 in rcx
Generating: N096 ( 16, 16) [000140] --C-G------- t140 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE REG rax
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0018: call CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
GC regs: 00000000 {} => 00000001 {rax}
/--* t140 ref
Generating: N098 ( 20, 19) [000144] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V22 tmp13 NA REG NA
GC regs: 00000001 {rax} => 00000000 {}
IN0019: mov gword ptr [V22 rbp-88H], rax
Generating: N100 ( 3, 4) [000145] ------------ t145 = LCL_FLD ref V22 tmp13 [+0] rcx REG rcx
IN001a: mov rcx, gword ptr [V22 rbp-88H]
GC regs: 00000000 {} => 00000002 {rcx}
/--* t145 ref
Generating: N102 (???,???) [000268] ------------ t268 = * PUTARG_REG ref REG rcx
GC regs: 00000002 {rcx} => 00000000 {}
GC regs: 00000000 {} => 00000002 {rcx}
/--* t268 ref arg0 in rcx
Generating: N104 ( 17, 10) [000141] --CXG------- t141 = * CALL ref System.Type.GetTypeFromHandle REG rax
GC regs: 00000002 {rcx} => 00000000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Added IP mapping: 0x0021 CALL_INSTRUCTION (G_M45291_IG04,ins#23,ofs#120)
IN001b: call System.Type:GetTypeFromHandle(System.RuntimeTypeHandle):System.Type
GC regs: 00000000 {} => 00000001 {rax}
/--* t141 ref
Generating: N106 ( 21, 13) [000149] DA-XG------- * STORE_LCL_VAR ref V23 tmp14 NA REG NA
GC regs: 00000001 {rax} => 00000000 {}
IN001c: mov gword ptr [V23 rbp-90H], rax
Added IP mapping: 0x0026 (G_M45291_IG04,ins#25,ofs#132)
Generating: N108 (???,???) [000228] ------------ IL_OFFSET void IL offset: 0x26 REG NA
Generating: N110 ( 2, 10) [000151] H----------- t151 = CNS_INT(h) long 0x7ff93b56a7f8 class REG rcx
IN001d: mov rcx, 0x7FF93B56A7F8
/--* t151 long
Generating: N112 (???,???) [000269] ------------ t269 = * PUTARG_REG long REG rcx
/--* t269 long arg0 in rcx
Generating: N114 ( 16, 16) [000152] --C-G------- t152 = * CALL help ref HELPER.CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE REG rax
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN001e: call CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
GC regs: 00000000 {} => 00000001 {rax}
/--* t152 ref
Generating: N116 ( 20, 19) [000156] DA--G------- * STORE_LCL_VAR struct<System.RuntimeTypeHandle, 8> V24 tmp15 NA REG NA
GC regs: 00000001 {rax} => 00000000 {}
IN001f: mov gword ptr [V24 rbp-98H], rax
Generating: N118 ( 3, 4) [000157] ------------ t157 = LCL_FLD ref V24 tmp15 [+0] rcx REG rcx
IN0020: mov rcx, gword ptr [V24 rbp-98H]
GC regs: 00000000 {} => 00000002 {rcx}
/--* t157 ref
Generating: N120 (???,???) [000270] ------------ t270 = * PUTARG_REG ref REG rcx
GC regs: 00000002 {rcx} => 00000000 {}
GC regs: 00000000 {} => 00000002 {rcx}
/--* t270 ref arg0 in rcx
Generating: N122 ( 17, 10) [000153] --CXG------- t153 = * CALL ref System.Type.GetTypeFromHandle REG rax
GC regs: 00000002 {rcx} => 00000000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Added IP mapping: 0x002B CALL_INSTRUCTION (G_M45291_IG04,ins#29,ofs#161)
IN0021: call System.Type:GetTypeFromHandle(System.RuntimeTypeHandle):System.Type
GC regs: 00000000 {} => 00000001 {rax}
/--* t153 ref
Generating: N124 ( 21, 13) [000161] DA-XG------- * STORE_LCL_VAR ref V25 tmp16 NA REG NA
GC regs: 00000001 {rax} => 00000000 {}
IN0022: mov gword ptr [V25 rbp-A0H], rax
Added IP mapping: 0x0030 (G_M45291_IG04,ins#31,ofs#173)
Generating: N126 (???,???) [000229] ------------ IL_OFFSET void IL offset: 0x30 REG NA
Generating: N128 ( 3, 2) [000150] ------------ t150 = LCL_VAR ref V23 tmp14 rcx REG rcx
IN0023: mov rcx, gword ptr [V23 rbp-90H]
GC regs: 00000000 {} => 00000002 {rcx}
/--* t150 ref
Generating: N130 (???,???) [000271] ------------ t271 = * PUTARG_REG ref REG rcx
GC regs: 00000002 {rcx} => 00000000 {}
GC regs: 00000000 {} => 00000002 {rcx}
Generating: N132 ( 3, 2) [000162] ------------ t162 = LCL_VAR ref V25 tmp16 rdx REG rdx
IN0024: mov rdx, gword ptr [V25 rbp-A0H]
GC regs: 00000002 {rcx} => 00000006 {rcx rdx}
/--* t162 ref
Generating: N134 (???,???) [000272] ------------ t272 = * PUTARG_REG ref REG rdx
GC regs: 00000006 {rcx rdx} => 00000002 {rcx}
GC regs: 00000002 {rcx} => 00000006 {rcx rdx}
/--* t271 ref arg0 in rcx
+--* t272 ref arg1 in rdx
Generating: N136 ( 20, 11) [000163] --CXG------- t163 = * CALL int System.Type.op_Equality REG rax
GC regs: 00000006 {rcx rdx} => 00000004 {rdx}
GC regs: 00000004 {rdx} => 00000000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Added IP mapping: 0x0030 CALL_INSTRUCTION (G_M45291_IG04,ins#33,ofs#187)
IN0025: call System.Type:op_Equality(System.Type,System.Type):bool
/--* t163 int
Generating: N138 ( 24, 14) [000165] DA-XG------- * STORE_LCL_VAR int V26 tmp17 NA REG NA
IN0026: mov dword ptr [V26 rbp-A4H], eax
Added IP mapping: 0x0035 (G_M45291_IG04,ins#35,ofs#198)
Generating: N140 (???,???) [000230] ------------ IL_OFFSET void IL offset: 0x35 REG NA
Generating: N142 ( 0, 0) [000167] ------------ NOP void REG NA
Generating: N144 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V26 tmp17 rcx REG rcx
IN0027: mov ecx, dword ptr [V26 rbp-A4H]
/--* t166 int
Generating: N146 ( 7, 5) [000169] DA---------- * STORE_LCL_VAR int V15 tmp6 NA REG NA
IN0028: mov dword ptr [V15 rbp-60H], ecx
Scope info: end block BB06, IL range [01C..037)
Scope info: open scopes =
0 (V00 this) [000..0B7)
7 (V07 loc6) [000..0B7)
6 (V06 loc5) [000..0B7)
5 (V05 loc4) [000..0B7)
4 (V04 loc3) [000..0B7)
3 (V03 loc2) [000..0B7)
2 (V02 loc1) [000..0B7)
1 (V01 loc0) [000..0B7)
8 (V08 loc7) [000..0B7)
IN0029: jmp L_M45291_BB08
=============== Generating BB07 [037..038), preds={BB05} succs={BB08} flags=0x00000000.20030020: i label target LIR
BB07 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M45291_BB07:
G_M45291_IG04: ; offs=000012H, funclet=00, bbWeight=1
Label: IG05, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB07, IL range [037..038)
Scope info: open scopes =
0 (V00 this) [000..0B7)
7 (V07 loc6) [000..0B7)
6 (V06 loc5) [000..0B7)
5 (V05 loc4) [000..0B7)
4 (V04 loc3) [000..0B7)
3 (V03 loc2) [000..0B7)
2 (V02 loc1) [000..0B7)
1 (V01 loc0) [000..0B7)
8 (V08 loc7) [000..0B7)
Added IP mapping: 0x0037 STACK_EMPTY (G_M45291_IG05,ins#0,ofs#0) label
Generating: N150 (???,???) [000231] ------------ IL_OFFSET void IL offset: 0x37 REG NA
Generating: N152 ( 1, 1) [000033] -c---------- t33 = CNS_INT int 1 REG NA
/--* t33 int
Generating: N154 ( 5, 4) [000035] DA---------- * STORE_LCL_VAR int V15 tmp6 NA REG NA
IN002a: mov dword ptr [V15 rbp-60H], 1
Scope info: end block BB07, IL range [037..038)
Scope info: open scopes =
0 (V00 this) [000..0B7)
7 (V07 loc6) [000..0B7)
6 (V06 loc5) [000..0B7)
5 (V05 loc4) [000..0B7)
4 (V04 loc3) [000..0B7)
3 (V03 loc2) [000..0B7)
2 (V02 loc1) [000..0B7)
1 (V01 loc0) [000..0B7)
8 (V08 loc7) [000..0B7)
=============== Generating BB08 [038..03C) -> BB12 (cond), preds={BB06,BB07} succs={BB09,BB12} flags=0x00000000.20030020: i label target LIR
BB08 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M45291_BB08:
G_M45291_IG05: ; offs=0000E6H, funclet=00, bbWeight=1
Label: IG06, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB08, IL range [038..03C)
Scope info: open scopes =
0 (V00 this) [000..0B7)
7 (V07 loc6) [000..0B7)
6 (V06 loc5) [000..0B7)
5 (V05 loc4) [000..0B7)
4 (V04 loc3) [000..0B7)
3 (V03 loc2) [000..0B7)
2 (V02 loc1) [000..0B7)
1 (V01 loc0) [000..0B7)
8 (V08 loc7) [000..0B7)
Generating: N158 ( 3, 2) [000037] ------------ t37 = LCL_VAR int V15 tmp6 rcx REG rcx
IN002b: mov ecx, dword ptr [V15 rbp-60H]
/--* t37 int
Generating: N160 ( 4, 4) [000191] ------------ t191 = * CAST int <- bool <- int REG rcx
IN002c: movzx rcx, cl
/--* t191 int
Generating: N162 ( 8, 7) [000039] DA---------- * STORE_LCL_VAR int V01 loc0 NA REG NA
IN002d: mov dword ptr [V01 rbp-04H], ecx
Added IP mapping: 0x0039 STACK_EMPTY (G_M45291_IG06,ins#3,ofs#9) label
Generating: N164 (???,???) [000232] ------------ IL_OFFSET void IL offset: 0x39 REG NA
Generating: N166 ( 3, 2) [000040] -c---------- t40 = LCL_VAR int V01 loc0 NA REG NA
Generating: N168 ( 1, 1) [000041] -c---------- t41 = CNS_INT int 0 REG NA
/--* t40 int
+--* t41 int
Generating: N170 ( 5, 4) [000042] J------N---- * EQ void REG NA
IN002e: cmp dword ptr [V01 rbp-04H], 0
Generating: N172 ( 7, 6) [000043] ------------ * JTRUE void REG NA
IN002f: je L_M45291_BB12
Scope info: end block BB08, IL range [038..03C)
Scope info: open scopes =
0 (V00 this) [000..0B7)
7 (V07 loc6) [000..0B7)
6 (V06 loc5) [000..0B7)
5 (V05 loc4) [000..0B7)
4 (V04 loc3) [000..0B7)
3 (V03 loc2) [000..0B7)
2 (V02 loc1) [000..0B7)
1 (V01 loc0) [000..0B7)
8 (V08 loc7) [000..0B7)
=============== Generating BB09 [03C..05E) -> BB11 (cond), preds={BB08} succs={BB10,BB11} flags=0x00000002.20000020: i hascall LIR
BB09 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M45291_BB09:
Scope info: begin block BB09, IL range [03C..05E)
Scope info: open scopes =
0 (V00 this) [000..0B7)
7 (V07 loc6) [000..0B7)
6 (V06 loc5) [000..0B7)
5 (V05 loc4) [000..0B7)
4 (V04 loc3) [000..0B7)
3 (V03 loc2) [000..0B7)
2 (V02 loc1) [000..0B7)
1 (V01 loc0) [000..0B7)
8 (V08 loc7) [000..0B7)
Added IP mapping: 0x003C STACK_EMPTY (G_M45291_IG06,ins#5,ofs#19) label
Generating: N176 (???,???) [000233] ------------ IL_OFFSET void IL offset: 0x3c REG NA
Generating: N178 ( 1, 1) [000081] ------------ NO_OP void REG NA
IN0030: nop
Added IP mapping: 0x003D STACK_EMPTY (G_M45291_IG06,ins#6,ofs#20)
Generating: N180 (???,???) [000234] ------------ IL_OFFSET void IL offset: 0x3d REG NA
Generating: N182 ( 3, 2) [000082] ------------ t82 = LCL_VAR byref V00 this rcx REG rcx
IN0031: mov rcx, bword ptr [V00 rbp+10H]
Byref regs: 00000000 {} => 00000002 {rcx}
/--* t82 byref
Generating: N184 ( 4, 3) [000193] -c---------- t193 = * LEA(b+24) byref REG NA
/--* t193 byref
Generating: N186 ( 6, 5) [000083] *--XG------- t83 = * IND int REG rcx
Byref regs: 00000002 {rcx} => 00000000 {}
IN0032: mov ecx, dword ptr [rcx+24]
/--* t83 int
Generating: N188 ( 10, 8) [000085] DA-XG------- * STORE_LCL_VAR int V02 loc1 NA REG NA
IN0033: mov dword ptr [V02 rbp-08H], ecx
Added IP mapping: 0x0044 STACK_EMPTY (G_M45291_IG06,ins#9,ofs#30)
Generating: N190 (???,???) [000235] ------------ IL_OFFSET void IL offset: 0x44 REG NA
Generating: N192 ( 3, 2) [000086] ------------ t86 = LCL_VAR byref V00 this rcx REG rcx
IN0034: mov rcx, bword ptr [V00 rbp+10H]
Byref regs: 00000000 {} => 00000002 {rcx}
/--* t86 byref
Generating: N194 ( 5, 4) [000195] -c---------- t195 = * LEA(b+32) byref REG NA
/--* t195 byref
Generating: N196 ( 8, 6) [000087] *c-XG------- t87 = * IND struct REG NA
Generating: N198 (???,???) [000273] Dc-----N---- t273 = LCL_VAR_ADDR byref V03 loc2 NA REG NA
/--* t273 byref
+--* t87 struct
Generating: N200 ( 12, 9) [000090] sA---------- * STORE_BLK struct<System.ReadOnlySpan`1[Byte], 16> (copy) (Unroll) REG NA
G_M45291_IG06: ; offs=0000EDH, funclet=00, bbWeight=1
Byref regs: 00000002 {rcx} => 00000000 {}
IN0035: vmovdqu xmm0, xmmword ptr [rcx+32]
IN0036: vmovdqu xmmword ptr [V03 rbp-18H], xmm0
Added IP mapping: 0x004B STACK_EMPTY (G_M45291_IG07,ins#2,ofs#12)
Generating: N202 (???,???) [000236] ------------ IL_OFFSET void IL offset: 0x4b REG NA
Generating: N204 ( 3, 2) [000091] ------------ t91 = LCL_VAR int V02 loc1 rcx REG rcx
G_M45291_IG07: ; offs=00010FH, funclet=00, bbWeight=1
IN0037: mov ecx, dword ptr [V02 rbp-08H]
/--* t91 int
Generating: N206 ( 7, 5) [000096] DA---------- * STORE_LCL_VAR int V18 tmp9 NA REG NA
IN0038: mov dword ptr [V18 rbp-6CH], ecx
Generating: N208 ( 3, 3) [000093] ------------ t93 = LCL_VAR_ADDR byref V03 loc2 rcx REG rcx
IN0039: lea rcx, bword ptr [V03 rbp-18H]
Byref regs: 00000000 {} => 00000002 {rcx}
/--* t93 byref
Generating: N210 (???,???) [000274] ------------ t274 = * PUTARG_REG byref REG rcx
Byref regs: 00000002 {rcx} => 00000000 {}
Byref regs: 00000000 {} => 00000002 {rcx}
/--* t274 byref this in rcx
Generating: N212 ( 17, 10) [000094] --CXG------- t94 = * CALL int System.ReadOnlySpan`1[Byte][System.Byte].get_Length REG rax
Byref regs: 00000002 {rcx} => 00000000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Added IP mapping: 0x004E CALL_INSTRUCTION (G_M45291_IG08,ins#3,ofs#10)
IN003a: call System.ReadOnlySpan`1[Byte][System.Byte]:get_Length():int:this
/--* t94 int
Generating: N214 ( 21, 13) [000099] DA-XG------- * STORE_LCL_VAR int V19 tmp10 NA REG NA
IN003b: mov dword ptr [V19 rbp-70H], eax
Added IP mapping: 0x0053 (G_M45291_IG08,ins#5,ofs#18)
Generating: N216 (???,???) [000237] ------------ IL_OFFSET void IL offset: 0x53 REG NA
Generating: N218 ( 3, 2) [000097] ------------ t97 = LCL_VAR int V18 tmp9 rcx REG rcx
IN003c: mov ecx, dword ptr [V18 rbp-6CH]
Generating: N220 ( 3, 2) [000100] -c---------- t100 = LCL_VAR int V19 tmp10 NA REG NA
/--* t97 int
+--* t100 int
Generating: N222 ( 10, 5) [000101] N--------U-- t101 = * GE int REG rcx
IN003d: cmp ecx, dword ptr [V19 rbp-70H]
IN003e: setae cl
IN003f: movzx rcx, cl
/--* t101 int
Generating: N224 ( 14, 8) [000105] DA---------- * STORE_LCL_VAR int V05 loc4 NA REG NA
IN0040: mov dword ptr [V05 rbp-20H], ecx
Added IP mapping: 0x005A STACK_EMPTY (G_M45291_IG08,ins#10,ofs#33)
Generating: N226 (???,???) [000238] ------------ IL_OFFSET void IL offset: 0x5a REG NA
Generating: N228 ( 3, 2) [000106] -c---------- t106 = LCL_VAR int V05 loc4 NA REG NA
Generating: N230 ( 1, 1) [000107] -c---------- t107 = CNS_INT int 0 REG NA
/--* t106 int
+--* t107 int
Generating: N232 ( 5, 4) [000108] J------N---- * EQ void REG NA
IN0041: cmp dword ptr [V05 rbp-20H], 0
Generating: N234 ( 7, 6) [000109] ------------ * JTRUE void REG NA
IN0042: je L_M45291_BB11
Scope info: end block BB09, IL range [03C..05E)
Scope info: open scopes =
0 (V00 this) [000..0B7)
7 (V07 loc6) [000..0B7)
6 (V06 loc5) [000..0B7)
5 (V05 loc4) [000..0B7)
4 (V04 loc3) [000..0B7)
3 (V03 loc2) [000..0B7)
2 (V02 loc1) [000..0B7)
1 (V01 loc0) [000..0B7)
8 (V08 loc7) [000..0B7)
=============== Generating BB10 [05E..069) -> BB15 (always), preds={BB09} succs={BB15} flags=0x00000002.20080020: i hascall gcsafe LIR
BB10 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M45291_BB10:
Scope info: begin block BB10, IL range [05E..069)
Scope info: open scopes =
0 (V00 this) [000..0B7)
7 (V07 loc6) [000..0B7)
6 (V06 loc5) [000..0B7)
5 (V05 loc4) [000..0B7)
4 (V04 loc3) [000..0B7)
3 (V03 loc2) [000..0B7)
2 (V02 loc1) [000..0B7)
1 (V01 loc0) [000..0B7)
8 (V08 loc7) [000..0B7)
Added IP mapping: 0x005E STACK_EMPTY (G_M45291_IG08,ins#12,ofs#43) label
Generating: N238 (???,???) [000239] ------------ IL_OFFSET void IL offset: 0x5e REG NA
Generating: N240 ( 1, 1) [000130] ------------ NO_OP void REG NA
IN0043: nop
Added IP mapping: 0x005F STACK_EMPTY (G_M45291_IG08,ins#13,ofs#44)
Generating: N242 (???,???) [000240] ------------ IL_OFFSET void IL offset: 0x5f REG NA
Generating: N244 ( 3, 2) [000131] ------------ t131 = LCL_VAR byref V00 this rcx REG rcx
IN0044: mov rcx, bword ptr [V00 rbp+10H]
Byref regs: 00000000 {} => 00000002 {rcx}
/--* t131 byref
Generating: N246 (???,???) [000275] ------------ t275 = * PUTARG_REG byref REG rcx
Byref regs: 00000002 {rcx} => 00000000 {}
Byref regs: 00000000 {} => 00000002 {rcx}
/--* t275 byref arg0 in rcx
Generating: N248 ( 17, 8) [000132] --CXG------- t132 = * CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].<ReadByte>g__ReadByteSlow|18_0 REG rax
Byref regs: 00000002 {rcx} => 00000000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Added IP mapping: 0x0060 CALL_INSTRUCTION (G_M45291_IG08,ins#14,ofs#48)
IN0045: call Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:<ReadByte>g__ReadByteSlow|18_0(byref):ubyte
/--* t132 int
Generating: N250 ( 21, 11) [000134] DA-XG------- * STORE_LCL_VAR int V21 tmp12 NA REG NA
IN0046: mov dword ptr [V21 rbp-7CH], eax
Added IP mapping: 0x0065 (G_M45291_IG08,ins#16,ofs#56)
Generating: N252 (???,???) [000241] ------------ IL_OFFSET void IL offset: 0x65 REG NA
Generating: N254 ( 3, 2) [000135] ------------ t135 = LCL_VAR int V21 tmp12 rcx REG rcx
IN0047: mov ecx, dword ptr [V21 rbp-7CH]
/--* t135 int
Generating: N256 ( 4, 4) [000198] ------------ t198 = * CAST int <- ubyte <- int REG rcx
IN0048: movzx rcx, cl
/--* t198 int
Generating: N258 ( 8, 7) [000137] DA---------- * STORE_LCL_VAR int V06 loc5 NA REG NA
IN0049: mov dword ptr [V06 rbp-24H], ecx
Added IP mapping: 0x0067 STACK_EMPTY (G_M45291_IG08,ins#19,ofs#65)
Generating: N260 (???,???) [000242] ------------ IL_OFFSET void IL offset: 0x67 REG NA
Generating: N262 ( 0, 0) [000138] ------------ NOP void REG NA
IN004a: nop
Scope info: end block BB10, IL range [05E..069)
Scope info: open scopes =
0 (V00 this) [000..0B7)
7 (V07 loc6) [000..0B7)
6 (V06 loc5) [000..0B7)
5 (V05 loc4) [000..0B7)
4 (V04 loc3) [000..0B7)
3 (V03 loc2) [000..0B7)
2 (V02 loc1) [000..0B7)
1 (V01 loc0) [000..0B7)
8 (V08 loc7) [000..0B7)
IN004b: jmp L_M45291_BB15
=============== Generating BB11 [069..081) -> BB15 (always), preds={BB09} succs={BB15} flags=0x00000002.20030020: i label target hascall LIR
BB11 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M45291_BB11:
G_M45291_IG08: ; offs=00011BH, funclet=00, bbWeight=1
Label: IG09, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB11, IL range [069..081)
Scope info: open scopes =
0 (V00 this) [000..0B7)
7 (V07 loc6) [000..0B7)
6 (V06 loc5) [000..0B7)
5 (V05 loc4) [000..0B7)
4 (V04 loc3) [000..0B7)
3 (V03 loc2) [000..0B7)
2 (V02 loc1) [000..0B7)
1 (V01 loc0) [000..0B7)
8 (V08 loc7) [000..0B7)
Added IP mapping: 0x0069 STACK_EMPTY (G_M45291_IG09,ins#0,ofs#0) label
Generating: N266 (???,???) [000243] ------------ IL_OFFSET void IL offset: 0x69 REG NA
Generating: N268 ( 3, 3) [000111] ------------ t111 = LCL_VAR_ADDR byref V03 loc2 rcx REG rcx
IN004c: lea rcx, bword ptr [V03 rbp-18H]
Byref regs: 00000000 {} => 00000002 {rcx}
/--* t111 byref
Generating: N270 (???,???) [000276] ------------ t276 = * PUTARG_REG byref REG rcx
Byref regs: 00000002 {rcx} => 00000000 {}
Byref regs: 00000000 {} => 00000002 {rcx}
Generating: N272 ( 3, 2) [000112] ------------ t112 = LCL_VAR int V02 loc1 rdx REG rdx
IN004d: mov edx, dword ptr [V02 rbp-08H]
/--* t112 int
Generating: N274 (???,???) [000277] ------------ t277 = * PUTARG_REG int REG rdx
/--* t276 byref this in rcx
+--* t277 int arg1 in rdx
Generating: N276 ( 20, 13) [000113] --CXG------- t113 = * CALL byref System.ReadOnlySpan`1[Byte][System.Byte].get_Item REG rax
Byref regs: 00000002 {rcx} => 00000000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Added IP mapping: 0x006C CALL_INSTRUCTION (G_M45291_IG09,ins#2,ofs#7)
IN004e: call System.ReadOnlySpan`1[Byte][System.Byte]:get_Item(int):byref:this
Byref regs: 00000000 {} => 00000001 {rax}
/--* t113 byref
Generating: N278 ( 24, 16) [000115] DA-XG------- * STORE_LCL_VAR byref V20 tmp11 NA REG NA
Byref regs: 00000001 {rax} => 00000000 {}
IN004f: mov bword ptr [V20 rbp-78H], rax
Added IP mapping: 0x0071 (G_M45291_IG09,ins#4,ofs#16)
Generating: N280 (???,???) [000244] ------------ IL_OFFSET void IL offset: 0x71 REG NA
Generating: N282 ( 3, 2) [000116] ------------ t116 = LCL_VAR byref V20 tmp11 rdx REG rdx
IN0050: mov rdx, bword ptr [V20 rbp-78H]
Byref regs: 00000000 {} => 00000004 {rdx}
/--* t116 byref
Generating: N284 ( 7, 5) [000117] *--XG------- t117 = * IND ubyte REG rdx
Byref regs: 00000004 {rdx} => 00000000 {}
IN0051: movzx rdx, byte ptr [rdx]
/--* t117 ubyte
Generating: N286 ( 11, 8) [000119] DA-XG------- * STORE_LCL_VAR int V04 loc3 NA REG NA
IN0052: mov dword ptr [V04 rbp-1CH], edx
Added IP mapping: 0x0073 STACK_EMPTY (G_M45291_IG09,ins#7,ofs#26)
Generating: N288 (???,???) [000245] ------------ IL_OFFSET void IL offset: 0x73 REG NA
Generating: N290 ( 3, 2) [000121] ------------ t121 = LCL_VAR int V02 loc1 rdx REG rdx
IN0053: mov edx, dword ptr [V02 rbp-08H]
Generating: N292 ( 1, 1) [000122] -c---------- t122 = CNS_INT int 1 REG NA
/--* t121 int
+--* t122 int
Generating: N294 ( 5, 4) [000123] ------------ t123 = * ADD int REG rdx
IN0054: inc edx
Generating: N296 ( 3, 2) [000120] ------------ t120 = LCL_VAR byref V00 this rcx REG rcx
IN0055: mov rcx, bword ptr [V00 rbp+10H]
Byref regs: 00000000 {} => 00000002 {rcx}
/--* t120 byref
Generating: N298 ( 4, 3) [000202] -c---------- t202 = * LEA(b+24) byref REG NA
/--* t202 byref
+--* t123 int
Generating: N300 (???,???) [000246] -A-XG------- * STOREIND int REG NA
Byref regs: 00000002 {rcx} => 00000000 {}
IN0056: mov dword ptr [rcx+24], edx
Added IP mapping: 0x007C STACK_EMPTY (G_M45291_IG09,ins#11,ofs#38)
Generating: N302 (???,???) [000247] ------------ IL_OFFSET void IL offset: 0x7c REG NA
Generating: N304 ( 3, 2) [000126] ------------ t126 = LCL_VAR int V04 loc3 rdx REG rdx
IN0057: mov edx, dword ptr [V04 rbp-1CH]
/--* t126 int
Generating: N306 ( 7, 5) [000128] DA---------- * STORE_LCL_VAR int V06 loc5 NA REG NA
IN0058: mov dword ptr [V06 rbp-24H], edx
Added IP mapping: 0x007F STACK_EMPTY (G_M45291_IG09,ins#13,ofs#44)
Generating: N308 (???,???) [000248] ------------ IL_OFFSET void IL offset: 0x7f REG NA
Generating: N310 ( 0, 0) [000129] ------------ NOP void REG NA
IN0059: nop
Scope info: end block BB11, IL range [069..081)
Scope info: open scopes =
0 (V00 this) [000..0B7)
7 (V07 loc6) [000..0B7)
6 (V06 loc5) [000..0B7)
5 (V05 loc4) [000..0B7)
4 (V04 loc3) [000..0B7)
3 (V03 loc2) [000..0B7)
2 (V02 loc1) [000..0B7)
1 (V01 loc0) [000..0B7)
8 (V08 loc7) [000..0B7)
IN005a: jmp L_M45291_BB15
=============== Generating BB12 [081..09E) -> BB14 (cond), preds={BB08} succs={BB13,BB14} flags=0x00000002.20030420: i label target hascall nullcheck LIR
BB12 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M45291_BB12:
G_M45291_IG09: ; offs=000162H, funclet=00, bbWeight=1
Label: IG10, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB12, IL range [081..09E)
Scope info: open scopes =
0 (V00 this) [000..0B7)
7 (V07 loc6) [000..0B7)
6 (V06 loc5) [000..0B7)
5 (V05 loc4) [000..0B7)
4 (V04 loc3) [000..0B7)
3 (V03 loc2) [000..0B7)
2 (V02 loc1) [000..0B7)
1 (V01 loc0) [000..0B7)
8 (V08 loc7) [000..0B7)
Added IP mapping: 0x0081 STACK_EMPTY (G_M45291_IG10,ins#0,ofs#0) label
Generating: N314 (???,???) [000249] ------------ IL_OFFSET void IL offset: 0x81 REG NA
Generating: N316 ( 3, 2) [000204] ------------ t204 = LCL_VAR byref V00 this rdx REG rdx
IN005b: mov rdx, bword ptr [V00 rbp+10H]
Byref regs: 00000000 {} => 00000004 {rdx}
/--* t204 byref
Generating: N318 ( 4, 3) [000205] ---X---N---- * NULLCHECK int REG NA
Byref regs: 00000004 {rdx} => 00000000 {}
IN005c: cmp dword ptr [rdx], edx
Generating: N320 ( 3, 2) [000206] ------------ t206 = LCL_VAR byref V00 this rdx REG rdx
IN005d: mov rdx, bword ptr [V00 rbp+10H]
Byref regs: 00000000 {} => 00000004 {rdx}
Generating: N322 ( 1, 1) [000207] -c---------- t207 = CNS_INT long 64 field offset Fseq[_input] REG NA
/--* t206 byref
+--* t207 long
Generating: N324 ( 5, 4) [000208] ------------ t208 = * ADD byref REG rdx
Byref regs: 00000004 {rdx} => 00000000 {}
IN005e: add rdx, 64
Byref regs: 00000000 {} => 00000004 {rdx}
/--* t208 byref
Generating: N326 (???,???) [000278] ------------ t278 = * PUTARG_REG byref REG rdx
Byref regs: 00000004 {rdx} => 00000000 {}
Byref regs: 00000000 {} => 00000004 {rdx}
Generating: N328 ( 2, 10) [000046] H----------- t46 = CNS_INT(h) long 0x7ff93af7cd80 class REG rcx
IN005f: mov rcx, 0x7FF93AF7CD80
/--* t46 long
Generating: N330 (???,???) [000279] ------------ t279 = * PUTARG_REG long REG rcx
/--* t278 byref arg1 in rdx
+--* t279 long arg0 in rcx
Generating: N332 ( 25, 24) [000048] --CXG------- t48 = * CALL help ref HELPER.CORINFO_HELP_BOX REG rax
Byref regs: 00000004 {rdx} => 00000000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0060: call CORINFO_HELP_BOX
GC regs: 00000000 {} => 00000001 {rax}
/--* t48 ref
Generating: N334 ( 29, 27) [000214] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp18 NA REG NA
GC regs: 00000001 {rax} => 00000000 {}
IN0061: mov gword ptr [V27 rbp-B0H], rax
Generating: N336 ( 3, 2) [000215] ------------ t215 = LCL_VAR ref V27 tmp18 rdx REG rdx
IN0062: mov rdx, gword ptr [V27 rbp-B0H]
GC regs: 00000000 {} => 00000004 {rdx}
/--* t215 ref
Generating: N338 (???,???) [000280] ------------ t280 = * PUTARG_REG ref REG rdx
GC regs: 00000004 {rdx} => 00000000 {}
GC regs: 00000000 {} => 00000004 {rdx}
Generating: N340 ( 2, 10) [000049] H------N---- t49 = CNS_INT(h) long 0x7ff93b569758 class REG rcx
IN0063: mov rcx, 0x7FF93B569758
/--* t49 long
Generating: N342 (???,???) [000281] ------------ t281 = * PUTARG_REG long REG rcx
/--* t280 ref arg1 in rdx
+--* t281 long arg0 in rcx
Generating: N344 ( 51, 46) [000050] --CXG------- t50 = * CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS REG rax
GC regs: 00000004 {rdx} => 00000000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0064: call CORINFO_HELP_ISINSTANCEOFCLASS
GC regs: 00000000 {} => 00000001 {rax}
/--* t50 ref
Generating: N346 ( 55, 49) [000052] DA-XG------- * STORE_LCL_VAR ref V07 loc6 NA REG NA
GC regs: 00000001 {rax} => 00000000 {}
IN0065: mov gword ptr [V07 rbp-30H], rax
Added IP mapping: 0x0093 STACK_EMPTY (G_M45291_IG10,ins#11,ofs#62)
Generating: N348 (???,???) [000250] ------------ IL_OFFSET void IL offset: 0x93 REG NA
Generating: N350 ( 3, 2) [000053] -c---------- t53 = LCL_VAR ref V07 loc6 NA REG NA
Generating: N352 ( 1, 1) [000054] -c---------- t54 = CNS_INT ref null REG NA
/--* t53 ref
+--* t54 ref
Generating: N354 ( 8, 4) [000055] N----------- t55 = * NE int REG rcx
IN0066: cmp gword ptr [V07 rbp-30H], 0
IN0067: setne cl
IN0068: movzx rcx, cl
/--* t55 int
Generating: N356 ( 12, 7) [000057] DA---------- * STORE_LCL_VAR int V08 loc7 NA REG NA
IN0069: mov dword ptr [V08 rbp-34H], ecx
Added IP mapping: 0x009A STACK_EMPTY (G_M45291_IG10,ins#15,ofs#76)
Generating: N358 (???,???) [000251] ------------ IL_OFFSET void IL offset: 0x9a REG NA
Generating: N360 ( 3, 2) [000058] -c---------- t58 = LCL_VAR int V08 loc7 NA REG NA
Generating: N362 ( 1, 1) [000059] -c---------- t59 = CNS_INT int 0 REG NA
/--* t58 int
+--* t59 int
Generating: N364 ( 5, 4) [000060] J------N---- * EQ void REG NA
IN006a: cmp dword ptr [V08 rbp-34H], 0
Generating: N366 ( 7, 6) [000061] ------------ * JTRUE void REG NA
IN006b: je L_M45291_BB14
Scope info: end block BB12, IL range [081..09E)
Scope info: open scopes =
0 (V00 this) [000..0B7)
7 (V07 loc6) [000..0B7)
6 (V06 loc5) [000..0B7)
5 (V05 loc4) [000..0B7)
4 (V04 loc3) [000..0B7)
3 (V03 loc2) [000..0B7)
2 (V02 loc1) [000..0B7)
1 (V01 loc0) [000..0B7)
8 (V08 loc7) [000..0B7)
=============== Generating BB13 [09E..0AA) -> BB15 (always), preds={BB12} succs={BB15} flags=0x00000002.20080020: i hascall gcsafe LIR
BB13 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M45291_BB13:
Scope info: begin block BB13, IL range [09E..0AA)
Scope info: open scopes =
0 (V00 this) [000..0B7)
7 (V07 loc6) [000..0B7)
6 (V06 loc5) [000..0B7)
5 (V05 loc4) [000..0B7)
4 (V04 loc3) [000..0B7)
3 (V03 loc2) [000..0B7)
2 (V02 loc1) [000..0B7)
1 (V01 loc0) [000..0B7)
8 (V08 loc7) [000..0B7)
Added IP mapping: 0x009E STACK_EMPTY (G_M45291_IG10,ins#17,ofs#86) label
Generating: N370 (???,???) [000252] ------------ IL_OFFSET void IL offset: 0x9e REG NA
Generating: N372 ( 1, 1) [000072] ------------ NO_OP void REG NA
IN006c: nop
Added IP mapping: 0x009F STACK_EMPTY (G_M45291_IG10,ins#18,ofs#87)
Generating: N374 (???,???) [000253] ------------ IL_OFFSET void IL offset: 0x9f REG NA
Generating: N376 ( 3, 2) [000073] ------------ t73 = LCL_VAR ref V07 loc6 rcx REG rcx
IN006d: mov rcx, gword ptr [V07 rbp-30H]
GC regs: 00000000 {} => 00000002 {rcx}
/--* t73 ref
Generating: N378 (???,???) [000282] ------------ t282 = * PUTARG_REG ref REG rcx
GC regs: 00000002 {rcx} => 00000000 {}
GC regs: 00000000 {} => 00000002 {rcx}
Generating: N380 ( 3, 2) [000283] ------------ t283 = LCL_VAR ref V07 loc6 rax REG rax
IN006e: mov rax, gword ptr [V07 rbp-30H]
GC regs: 00000002 {rcx} => 00000003 {rax rcx}
/--* t283 ref
Generating: N382 ( 4, 3) [000284] -c---------- t284 = * LEA(b+0) byref REG NA
/--* t284 byref
Generating: N384 ( 7, 5) [000285] ------------ t285 = * IND long REG rax
GC regs: 00000003 {rax rcx} => 00000002 {rcx}
IN006f: mov rax, qword ptr [rax]
/--* t285 long
Generating: N386 ( 8, 6) [000286] -c---------- t286 = * LEA(b+72) long REG NA
/--* t286 long
Generating: N388 ( 11, 8) [000287] ------------ t287 = * IND long REG rax
IN0070: mov rax, qword ptr [rax+72]
/--* t287 long
Generating: N390 ( 12, 9) [000288] -c---------- t288 = * LEA(b+56) long REG NA
/--* t288 long
Generating: N392 ( 15, 11) [000289] -c---------- t289 = * IND long REG NA
/--* t282 ref this in rcx
+--* t289 long control expr
Generating: N394 ( 23, 11) [000074] --CXG------- t74 = * CALLV ind int Hagar.Buffers.ReaderInput.ReadByte REG rax
GC regs: 00000002 {rcx} => 00000000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Added IP mapping: 0x00A1 CALL_INSTRUCTION (G_M45291_IG10,ins#22,ofs#102)
IN0071: call qword ptr [rax+56]Hagar.Buffers.ReaderInput:ReadByte():ubyte:this
/--* t74 int
Generating: N396 ( 27, 14) [000076] DA-XG------- * STORE_LCL_VAR int V17 tmp8 NA REG NA
IN0072: mov dword ptr [V17 rbp-68H], eax
Added IP mapping: 0x00A6 (G_M45291_IG10,ins#24,ofs#108)
Generating: N398 (???,???) [000254] ------------ IL_OFFSET void IL offset: 0xa6 REG NA
Generating: N400 ( 3, 2) [000077] ------------ t77 = LCL_VAR int V17 tmp8 rax REG rax
IN0073: mov eax, dword ptr [V17 rbp-68H]
/--* t77 int
Generating: N402 ( 4, 4) [000218] ------------ t218 = * CAST int <- ubyte <- int REG rax
IN0074: movzx rax, al
/--* t218 int
Generating: N404 ( 8, 7) [000079] DA---------- * STORE_LCL_VAR int V06 loc5 NA REG NA
IN0075: mov dword ptr [V06 rbp-24H], eax
Added IP mapping: 0x00A8 STACK_EMPTY (G_M45291_IG10,ins#27,ofs#117)
Generating: N406 (???,???) [000255] ------------ IL_OFFSET void IL offset: 0xa8 REG NA
Generating: N408 ( 0, 0) [000080] ------------ NOP void REG NA
IN0076: nop
Scope info: end block BB13, IL range [09E..0AA)
Scope info: open scopes =
0 (V00 this) [000..0B7)
7 (V07 loc6) [000..0B7)
6 (V06 loc5) [000..0B7)
5 (V05 loc4) [000..0B7)
4 (V04 loc3) [000..0B7)
3 (V03 loc2) [000..0B7)
2 (V02 loc1) [000..0B7)
1 (V01 loc0) [000..0B7)
8 (V08 loc7) [000..0B7)
IN0077: jmp L_M45291_BB15
=============== Generating BB14 [0AA..0B4) -> BB15 (always), preds={BB12} succs={BB15} flags=0x00000002.200b0020: i label target hascall gcsafe LIR
BB14 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M45291_BB14:
G_M45291_IG10: ; offs=000194H, funclet=00, bbWeight=1
Label: IG11, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB14, IL range [0AA..0B4)
Scope info: open scopes =
0 (V00 this) [000..0B7)
7 (V07 loc6) [000..0B7)
6 (V06 loc5) [000..0B7)
5 (V05 loc4) [000..0B7)
4 (V04 loc3) [000..0B7)
3 (V03 loc2) [000..0B7)
2 (V02 loc1) [000..0B7)
1 (V01 loc0) [000..0B7)
8 (V08 loc7) [000..0B7)
Added IP mapping: 0x00AA STACK_EMPTY (G_M45291_IG11,ins#0,ofs#0) label
Generating: N412 (???,???) [000256] ------------ IL_OFFSET void IL offset: 0xaa REG NA
Generating: N414 ( 1, 1) [000062] ------------ NO_OP void REG NA
IN0078: nop
Added IP mapping: 0x00AB STACK_EMPTY (G_M45291_IG11,ins#1,ofs#1)
Generating: N416 (???,???) [000257] ------------ IL_OFFSET void IL offset: 0xab REG NA
Generating: N418 ( 14, 5) [000063] --CXG------- t63 = CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].ThrowNotSupportedInput REG rax
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Added IP mapping: 0x00AB STACK_EMPTY CALL_INSTRUCTION (G_M45291_IG11,ins#1,ofs#1)
IN0079: call Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ThrowNotSupportedInput():ubyte
/--* t63 int
Generating: N420 ( 18, 8) [000065] DA-XG------- * STORE_LCL_VAR int V16 tmp7 NA REG NA
IN007a: mov dword ptr [V16 rbp-64H], eax
Added IP mapping: 0x00B0 (G_M45291_IG11,ins#3,ofs#9)
Generating: N422 (???,???) [000258] ------------ IL_OFFSET void IL offset: 0xb0 REG NA
Generating: N424 ( 3, 2) [000066] ------------ t66 = LCL_VAR int V16 tmp7 rax REG rax
IN007b: mov eax, dword ptr [V16 rbp-64H]
/--* t66 int
Generating: N426 ( 4, 4) [000219] ------------ t219 = * CAST int <- ubyte <- int REG rax
IN007c: movzx rax, al
/--* t219 int
Generating: N428 ( 8, 7) [000068] DA---------- * STORE_LCL_VAR int V06 loc5 NA REG NA
IN007d: mov dword ptr [V06 rbp-24H], eax
Added IP mapping: 0x00B2 STACK_EMPTY (G_M45291_IG11,ins#6,ofs#18)
Generating: N430 (???,???) [000259] ------------ IL_OFFSET void IL offset: 0xb2 REG NA
Generating: N432 ( 0, 0) [000069] ------------ NOP void REG NA
IN007e: nop
Scope info: end block BB14, IL range [0AA..0B4)
Scope info: open scopes =
0 (V00 this) [000..0B7)
7 (V07 loc6) [000..0B7)
6 (V06 loc5) [000..0B7)
5 (V05 loc4) [000..0B7)
4 (V04 loc3) [000..0B7)
3 (V03 loc2) [000..0B7)
2 (V02 loc1) [000..0B7)
1 (V01 loc0) [000..0B7)
8 (V08 loc7) [000..0B7)
IN007f: jmp L_M45291_BB15
=============== Generating BB15 [0B4..0B7) (return), preds={BB10,BB11,BB13,BB14} succs={} flags=0x00000000.20030020: i label target LIR
BB15 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M45291_BB15:
G_M45291_IG11: ; offs=00020FH, funclet=00, bbWeight=1
Label: IG12, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB15, IL range [0B4..0B7)
Scope info: open scopes =
0 (V00 this) [000..0B7)
7 (V07 loc6) [000..0B7)
6 (V06 loc5) [000..0B7)
5 (V05 loc4) [000..0B7)
4 (V04 loc3) [000..0B7)
3 (V03 loc2) [000..0B7)
2 (V02 loc1) [000..0B7)
1 (V01 loc0) [000..0B7)
8 (V08 loc7) [000..0B7)
Added IP mapping: 0x00B4 STACK_EMPTY (G_M45291_IG12,ins#0,ofs#0) label
Generating: N436 (???,???) [000260] ------------ IL_OFFSET void IL offset: 0xb4 REG NA
Generating: N438 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V06 loc5 rax REG rax
IN0080: mov eax, dword ptr [V06 rbp-24H]
/--* t70 int
Generating: N440 ( 4, 3) [000071] ------------ * RETURN int REG NA
Scope info: end block BB15, IL range [0B4..0B7)
Scope info: ending scope, LVnum=0 [000..0B7)
Scope info: ending scope, LVnum=7 [000..0B7)
Scope info: ending scope, LVnum=6 [000..0B7)
Scope info: ending scope, LVnum=5 [000..0B7)
Scope info: ending scope, LVnum=4 [000..0B7)
Scope info: ending scope, LVnum=3 [000..0B7)
Scope info: ending scope, LVnum=2 [000..0B7)
Scope info: ending scope, LVnum=1 [000..0B7)
Scope info: ending scope, LVnum=8 [000..0B7)
Scope info: open scopes =
<none>
Added IP mapping: EPILOG STACK_EMPTY (G_M45291_IG12,ins#1,ofs#3) label
Reserving epilog IG for block BB15
G_M45291_IG12: ; offs=000227H, funclet=00, bbWeight=1
*************** After placeholder IG creation
G_M45291_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M45291_IG02: ; offs=000000H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG03: ; offs=00000DH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG04: ; offs=000012H, size=00D4H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG05: ; offs=0000E6H, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG06: ; offs=0000EDH, size=0022H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG07: ; offs=00010FH, size=000CH, nogc, extend
G_M45291_IG08: ; offs=00011BH, size=0047H, extend
G_M45291_IG09: ; offs=000162H, size=0032H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG10: ; offs=000194H, size=007BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG11: ; offs=00020FH, size=0018H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG12: ; offs=000227H, size=0003H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG13: ; epilog placeholder, next placeholder=<END>, BB15 [0011], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Liveness not changing: 0000000000000000 {}
# compCycleEstimate = 566, compSizeEstimate = 417 Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this
; Final local variable assignments
;
; V00 this [V00 ] ( 1, 1 ) byref -> [rbp+0x10] this
; V01 loc0 [V01 ] ( 1, 1 ) bool -> [rbp-0x04] must-init
; V02 loc1 [V02 ] ( 1, 1 ) int -> [rbp-0x08] must-init
; V03 loc2 [V03 ] ( 1, 1 ) struct (16) [rbp-0x18] do-not-enreg[XSB] must-init addr-exposed ld-addr-op
; V04 loc3 [V04 ] ( 1, 1 ) ubyte -> [rbp-0x1C] must-init
; V05 loc4 [V05 ] ( 1, 1 ) bool -> [rbp-0x20] must-init
; V06 loc5 [V06 ] ( 1, 1 ) ubyte -> [rbp-0x24] must-init
; V07 loc6 [V07 ] ( 1, 1 ) ref -> [rbp-0x30] must-init class-hnd
; V08 loc7 [V08 ] ( 1, 1 ) bool -> [rbp-0x34] must-init
; V09 OutArgs [V09 ] ( 1, 1 ) lclBlk (32) [rsp+0x00] "OutgoingArgSpace"
; V10 tmp1 [V10 ] ( 1, 1 ) struct ( 8) [rbp-0x40] do-not-enreg[SB] must-init "struct address for call/obj"
; V11 tmp2 [V11 ] ( 1, 1 ) ref -> [rbp-0x48] must-init class-hnd "impSpillStackEnsure"
; V12 tmp3 [V12 ] ( 1, 1 ) struct ( 8) [rbp-0x50] do-not-enreg[SB] must-init "struct address for call/obj"
; V13 tmp4 [V13 ] ( 1, 1 ) ref -> [rbp-0x58] must-init class-hnd "impSpillStackEnsure"
; V14 tmp5 [V14 ] ( 1, 1 ) int -> [rbp-0x5C] "impSpillStackEnsure"
; V15 tmp6 [V15 ] ( 1, 1 ) int -> [rbp-0x60] must-init
; V16 tmp7 [V16 ] ( 1, 1 ) int -> [rbp-0x64] "impSpillStackEnsure"
; V17 tmp8 [V17 ] ( 1, 1 ) int -> [rbp-0x68] "impSpillStackEnsure"
; V18 tmp9 [V18 ] ( 1, 1 ) int -> [rbp-0x6C] "impSpillStackEnsure"
; V19 tmp10 [V19 ] ( 1, 1 ) int -> [rbp-0x70] "impSpillStackEnsure"
; V20 tmp11 [V20 ] ( 1, 1 ) byref -> [rbp-0x78] must-init "impSpillStackEnsure"
; V21 tmp12 [V21 ] ( 1, 1 ) int -> [rbp-0x7C] "impSpillStackEnsure"
; V22 tmp13 [V22 ] ( 1, 1 ) struct ( 8) [rbp-0x88] do-not-enreg[SB] must-init "struct address for call/obj"
; V23 tmp14 [V23 ] ( 1, 1 ) ref -> [rbp-0x90] must-init class-hnd "impSpillStackEnsure"
; V24 tmp15 [V24 ] ( 1, 1 ) struct ( 8) [rbp-0x98] do-not-enreg[SB] must-init "struct address for call/obj"
; V25 tmp16 [V25 ] ( 1, 1 ) ref -> [rbp-0xA0] must-init class-hnd "impSpillStackEnsure"
; V26 tmp17 [V26 ] ( 1, 1 ) int -> [rbp-0xA4] "impSpillStackEnsure"
; V27 tmp18 [V27 ] ( 1, 1 ) ref -> [rbp-0xB0] must-init "argument with side effect"
;
; Lcl frame size = 208
*************** Before prolog / epilog generation
G_M45291_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M45291_IG02: ; offs=000000H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG03: ; offs=00000DH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG04: ; offs=000012H, size=00D4H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG05: ; offs=0000E6H, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG06: ; offs=0000EDH, size=0022H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG07: ; offs=00010FH, size=000CH, nogc, extend
G_M45291_IG08: ; offs=00011BH, size=0047H, extend
G_M45291_IG09: ; offs=000162H, size=0032H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG10: ; offs=000194H, size=007BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG11: ; offs=00020FH, size=0018H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG12: ; offs=000227H, size=0003H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG13: ; epilog placeholder, next placeholder=<END>, BB15 [0011], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
*************** In genFnProlog()
Added IP mapping to front: PROLOG STACK_EMPTY (G_M45291_IG01,ins#0,ofs#0) label
__prolog:
Found 40 lvMustInit int-sized stack slots, frame offsets 176 through 0
IN0081: push rbp
IN0082: sub rsp, 208
IN0083: vzeroupper
IN0084: lea rbp, [rsp+D0H]
Notify VM instruction set (AVX2) must be supported.
IN0085: vxorps xmm4, xmm4
IN0086: vmovdqa xmmword ptr [rbp-B0H], xmm4
IN0087: vmovdqa xmmword ptr [rbp-A0H], xmm4
IN0088: mov rax, -144
IN0089: vmovdqa xmmword ptr [rax+rbp], xmm4
IN008a: vmovdqa xmmword ptr [rbp+rax+10H], xmm4
IN008b: vmovdqa xmmword ptr [rbp+rax+20H], xmm4
IN008c: add rax, 48
IN008d: jne SHORT -5 instr
*************** In genFnPrologCalleeRegArgs() for int regs
IN008e: mov bword ptr [V00 rbp+10H], rcx
*************** In genEnregisterIncomingStackArgs()
G_M45291_IG01: ; offs=000000H, funclet=00, bbWeight=1
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
IN008f: lea rsp, [rbp]
IN0090: pop rbp
IN0091: ret
G_M45291_IG13: ; offs=00022AH, funclet=00, bbWeight=1
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M45291_IG01: ; func=00, offs=000000H, size=0052H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
G_M45291_IG02: ; offs=000052H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG03: ; offs=00005FH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG04: ; offs=000064H, size=00D4H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG05: ; offs=000138H, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG06: ; offs=00013FH, size=0022H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG07: ; offs=000161H, size=000CH, nogc, extend
G_M45291_IG08: ; offs=00016DH, size=0047H, extend
G_M45291_IG09: ; offs=0001B4H, size=0032H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG10: ; offs=0001E6H, size=007BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG11: ; offs=000261H, size=0018H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG12: ; offs=000279H, size=0003H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45291_IG13: ; offs=00027CH, size=0006H, epilog, nogc, extend
*************** In emitJumpDistBind()
Adjusted offset of BB02 from 0052 to 0052
Binding: IN0002: 000000 je L_M45291_BB04
Binding L_M45291_BB04 to G_M45291_IG04
Estimate of fwd jump [9E0EE1EC/002]: 0059 -> 0064 = 0009
Shrinking jump [9E0EE1EC/002]
Adjusted offset of BB03 from 005F to 005B
Adjusted offset of BB04 from 0064 to 0060
Binding: IN0016: 000000 jne L_M45291_BB07
Binding L_M45291_BB07 to G_M45291_IG05
Estimate of fwd jump [9E0EF44C/022]: 00B5 -> 0134 = 007D
Shrinking jump [9E0EF44C/022]
Binding: IN0029: 000000 jmp L_M45291_BB08
Binding L_M45291_BB08 to G_M45291_IG06
Estimate of fwd jump [9E0EF644/041]: 012B -> 0137 = 000A
Shrinking jump [9E0EF644/041]
Adjusted offset of BB05 from 0138 to 012D
Adjusted offset of BB06 from 013F to 0134
Binding: IN002f: 000000 je L_M45291_BB12
Binding L_M45291_BB12 to G_M45291_IG10
Estimate of fwd jump [9E0EFA9C/047]: 0141 -> 01DB = 0098
Adjusted offset of BB07 from 0161 to 0156
Adjusted offset of BB08 from 016D to 0162
Binding: IN0042: 000000 je L_M45291_BB11
Binding L_M45291_BB11 to G_M45291_IG09
Estimate of fwd jump [9E0F03A8/066]: 0187 -> 01A9 = 0020
Shrinking jump [9E0F03A8/066]
Binding: IN004b: 000000 jmp L_M45291_BB15
Binding L_M45291_BB15 to G_M45291_IG12
Estimate of fwd jump [9E0F0498/075]: 01A0 -> 026A = 00C8
Adjusted offset of BB09 from 01B4 to 01A5
Binding: IN005a: 000000 jmp L_M45291_BB15
Binding L_M45291_BB15 to G_M45291_IG12
Estimate of fwd jump [9E0F0A8C/090]: 01D2 -> 026A = 0096
Adjusted offset of BB10 from 01E6 to 01D7
Binding: IN006b: 000000 je L_M45291_BB14
Binding L_M45291_BB14 to G_M45291_IG11
Estimate of fwd jump [9E0F13BC/107]: 0227 -> 0252 = 0029
Shrinking jump [9E0F13BC/107]
Binding: IN0077: 000000 jmp L_M45291_BB15
Binding L_M45291_BB15 to G_M45291_IG12
Estimate of fwd jump [9E0F14F4/119]: 0249 -> 0266 = 001B
Shrinking jump [9E0F14F4/119]
Adjusted offset of BB11 from 0261 to 024B
Binding: IN007f: 000000 jmp L_M45291_BB15
Binding L_M45291_BB15 to G_M45291_IG12
Estimate of fwd jump [9E0F1904/127]: 025E -> 0263 = 0003
Shrinking jump [9E0F1904/127]
Adjusted offset of BB12 from 0279 to 0260
Adjusted offset of BB13 from 027C to 0263
Total shrinkage = 25, min extra jump size = 23
Iterating branch shortening. Iteration = 2
Adjusted offset of BB02 from 0052 to 0052
Adjusted offset of BB03 from 005B to 005B
Adjusted offset of BB04 from 0060 to 0060
Adjusted offset of BB05 from 012D to 012D
Adjusted offset of BB06 from 0134 to 0134
Estimate of fwd jump [9E0EFA9C/047]: 0141 -> 01D7 = 0094
Adjusted offset of BB07 from 0156 to 0156
Adjusted offset of BB08 from 0162 to 0162
Estimate of fwd jump [9E0F0498/075]: 01A0 -> 0260 = 00BE
Adjusted offset of BB09 from 01A5 to 01A5
Estimate of fwd jump [9E0F0A8C/090]: 01D2 -> 0260 = 008C
Adjusted offset of BB10 from 01D7 to 01D7
Adjusted offset of BB11 from 024B to 024B
*************** Finishing PHASE Generate code
*************** Starting PHASE Emit code
Hot code size = 0x269 bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0xa)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)
***************************************************************************
Instructions as they come out of the scheduler
G_M45291_IG01: ; func=00, offs=000000H, size=0052H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN0081: 000000 55 push rbp
IN0082: 000001 4881ECD0000000 sub rsp, 208
IN0083: 000008 C5F877 vzeroupper
IN0084: 00000B 488DAC24D0000000 lea rbp, [rsp+D0H]
IN0085: 000013 C5D857E4 vxorps xmm4, xmm4 (ECS:5, ACS:4)
Instruction predicted size = 5, actual = 4
IN0086: 000017 C5F97FA550FFFFFF vmovdqa xmmword ptr [rbp-B0H], xmm4 (ECS:9, ACS:8)
Instruction predicted size = 9, actual = 8
IN0087: 00001F C5F97FA560FFFFFF vmovdqa xmmword ptr [rbp-A0H], xmm4 (ECS:9, ACS:8)
Instruction predicted size = 9, actual = 8
IN0088: 000027 48B870FFFFFFFFFFFFFF mov rax, -144
IN0089: 000031 C5F97F2428 vmovdqa xmmword ptr [rax+rbp], xmm4 (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN008a: 000036 C5F97F640510 vmovdqa xmmword ptr [rbp+rax+10H], xmm4 (ECS:7, ACS:6)
Instruction predicted size = 7, actual = 6
IN008b: 00003C C5F97F640520 vmovdqa xmmword ptr [rbp+rax+20H], xmm4 (ECS:7, ACS:6)
Instruction predicted size = 7, actual = 6
IN008c: 000042 4883C030 add rax, 48
IN008d: 000046 75E9 jne SHORT -5 instr
IN008e: 000048 48894D10 mov bword ptr [rbp+10H], rcx
;; bbWeight=1 PerfScore 10.58
G_M45291_IG02: ; func=00, offs=000052H, size=0009H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
Block predicted offs = 00000052, actual = 0000004C -> size adj = 6
IN0001: 00004C 833DED2171FE00 cmp dword ptr [(reloc)], 0
IN0002: 000053 7405 je SHORT G_M45291_IG04
;; bbWeight=1 PerfScore 3.00
G_M45291_IG03: ; func=00, offs=00005BH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
Block predicted offs = 0000005B, actual = 00000055 -> size adj = 6
IN0003: 000055 E8A6E17D5C call CORINFO_HELP_DBG_IS_JUST_MY_CODE
; gcr arg pop 0
;; bbWeight=0.50 PerfScore 0.50
G_M45291_IG04: ; func=00, offs=000060H, size=00CDH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
Block predicted offs = 00000060, actual = 0000005A -> size adj = 6
IN0004: 00005A 90 nop
IN0005: 00005B 48B980CDF73AF97F0000 mov rcx, 0x7FF93AF7CD80
IN0006: 000065 E806AB7E5C call CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
; gcrRegs +[rax]
; gcr arg pop 0
IN0007: 00006A 488945C0 mov gword ptr [rbp-40H], rax
IN0008: 00006E 488B4DC0 mov rcx, gword ptr [rbp-40H]
; gcrRegs +[rcx]
IN0009: 000072 E8C9FA945C call System.Type:GetTypeFromHandle(System.RuntimeTypeHandle):System.Type
; gcrRegs -[rcx]
; gcr arg pop 0
IN000a: 000077 488945B8 mov gword ptr [rbp-48H], rax
IN000b: 00007B 48B980CDF73AF97F0000 mov rcx, 0x7FF93AF7CD80
IN000c: 000085 E8E6AA7E5C call CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
; gcr arg pop 0
IN000d: 00008A 488945B0 mov gword ptr [rbp-50H], rax
IN000e: 00008E 488B4DB0 mov rcx, gword ptr [rbp-50H]
; gcrRegs +[rcx]
IN000f: 000092 E8A9FA945C call System.Type:GetTypeFromHandle(System.RuntimeTypeHandle):System.Type
; gcrRegs -[rcx]
; gcr arg pop 0
IN0010: 000097 488945A8 mov gword ptr [rbp-58H], rax
IN0011: 00009B 488B4DB8 mov rcx, gword ptr [rbp-48H]
; gcrRegs +[rcx]
IN0012: 00009F 488B55A8 mov rdx, gword ptr [rbp-58H]
; gcrRegs +[rdx]
IN0013: 0000A3 E8587E955C call System.Type:op_Equality(System.Type,System.Type):bool
; gcrRegs -[rax rcx rdx]
; gcr arg pop 0
IN0014: 0000A8 8945A4 mov dword ptr [rbp-5CH], eax
IN0015: 0000AB 837DA400 cmp dword ptr [rbp-5CH], 0
IN0016: 0000AF 7576 jne SHORT G_M45291_IG05
IN0017: 0000B1 48B980CDF73AF97F0000 mov rcx, 0x7FF93AF7CD80
IN0018: 0000BB E8B0AA7E5C call CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
; gcrRegs +[rax]
; gcr arg pop 0
IN0019: 0000C0 48898578FFFFFF mov gword ptr [rbp-88H], rax
IN001a: 0000C7 488B8D78FFFFFF mov rcx, gword ptr [rbp-88H]
; gcrRegs +[rcx]
IN001b: 0000CE E86DFA945C call System.Type:GetTypeFromHandle(System.RuntimeTypeHandle):System.Type
; gcrRegs -[rcx]
; gcr arg pop 0
IN001c: 0000D3 48898570FFFFFF mov gword ptr [rbp-90H], rax
IN001d: 0000DA 48B9F8A7563BF97F0000 mov rcx, 0x7FF93B56A7F8
IN001e: 0000E4 E887AA7E5C call CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
; gcr arg pop 0
IN001f: 0000E9 48898568FFFFFF mov gword ptr [rbp-98H], rax
IN0020: 0000F0 488B8D68FFFFFF mov rcx, gword ptr [rbp-98H]
; gcrRegs +[rcx]
IN0021: 0000F7 E844FA945C call System.Type:GetTypeFromHandle(System.RuntimeTypeHandle):System.Type
; gcrRegs -[rcx]
; gcr arg pop 0
IN0022: 0000FC 48898560FFFFFF mov gword ptr [rbp-A0H], rax
IN0023: 000103 488B8D70FFFFFF mov rcx, gword ptr [rbp-90H]
; gcrRegs +[rcx]
IN0024: 00010A 488B9560FFFFFF mov rdx, gword ptr [rbp-A0H]
; gcrRegs +[rdx]
IN0025: 000111 E8EA7D955C call System.Type:op_Equality(System.Type,System.Type):bool
; gcrRegs -[rax rcx rdx]
; gcr arg pop 0
IN0026: 000116 89855CFFFFFF mov dword ptr [rbp-A4H], eax
IN0027: 00011C 8B8D5CFFFFFF mov ecx, dword ptr [rbp-A4H]
IN0028: 000122 894DA0 mov dword ptr [rbp-60H], ecx
IN0029: 000125 EB07 jmp SHORT G_M45291_IG06
;; bbWeight=1 PerfScore 35.25
G_M45291_IG05: ; func=00, offs=00012DH, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
Block predicted offs = 0000012D, actual = 00000127 -> size adj = 6
IN002a: 000127 C745A001000000 mov dword ptr [rbp-60H], 1
;; bbWeight=1 PerfScore 1.00
G_M45291_IG06: ; func=00, offs=000134H, size=0022H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
Block predicted offs = 00000134, actual = 0000012E -> size adj = 6
IN002b: 00012E 8B4DA0 mov ecx, dword ptr [rbp-60H]
IN002c: 000131 0FB6C9 movzx rcx, cl
IN002d: 000134 894DFC mov dword ptr [rbp-04H], ecx
IN002e: 000137 837DFC00 cmp dword ptr [rbp-04H], 0
IN002f: 00013B 0F8490000000 je G_M45291_IG10
IN0030: 000141 90 nop
IN0031: 000142 488B4D10 mov rcx, bword ptr [rbp+10H]
; byrRegs +[rcx]
IN0032: 000146 8B4918 mov ecx, dword ptr [rcx+24]
; byrRegs -[rcx]
IN0033: 000149 894DF8 mov dword ptr [rbp-08H], ecx
IN0034: 00014C 488B4D10 mov rcx, bword ptr [rbp+10H]
; byrRegs +[rcx]
;; bbWeight=1 PerfScore 9.50
G_M45291_IG07: ; func=00, offs=000156H, size=000CH, nogc, extend
Block predicted offs = 00000156, actual = 00000150 -> size adj = 6
IN0035: 000150 C5FA6F4120 vmovdqu xmm0, xmmword ptr [rcx+32] (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN0036: 000155 C5FA7F45E8 vmovdqu xmmword ptr [rbp-18H], xmm0 (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
;; bbWeight=1 PerfScore 3.00
G_M45291_IG08: ; func=00, offs=000162H, size=0043H, isz, extend
Block predicted offs = 00000162, actual = 0000015A -> size adj = 8
IN0037: 00015A 8B4DF8 mov ecx, dword ptr [rbp-08H]
; byrRegs -[rcx]
IN0038: 00015D 894D94 mov dword ptr [rbp-6CH], ecx
IN0039: 000160 488D4DE8 lea rcx, bword ptr [rbp-18H]
; byrRegs +[rcx]
IN003a: 000164 E8B714CFFD call System.ReadOnlySpan`1[Byte][System.Byte]:get_Length():int:this
; byrRegs -[rcx]
; gcr arg pop 0
IN003b: 000169 894590 mov dword ptr [rbp-70H], eax
IN003c: 00016C 8B4D94 mov ecx, dword ptr [rbp-6CH]
IN003d: 00016F 3B4D90 cmp ecx, dword ptr [rbp-70H]
IN003e: 000172 0F93C1 setae cl
IN003f: 000175 0FB6C9 movzx rcx, cl
IN0040: 000178 894DE0 mov dword ptr [rbp-20H], ecx
IN0041: 00017B 837DE000 cmp dword ptr [rbp-20H], 0
IN0042: 00017F 741C je SHORT G_M45291_IG09
IN0043: 000181 90 nop
IN0044: 000182 488B4D10 mov rcx, bword ptr [rbp+10H]
; byrRegs +[rcx]
IN0045: 000186 E80DC7FFFF call Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:<ReadByte>g__ReadByteSlow|18_0(byref):ubyte
; byrRegs -[rcx]
; gcr arg pop 0
IN0046: 00018B 894584 mov dword ptr [rbp-7CH], eax
IN0047: 00018E 8B4D84 mov ecx, dword ptr [rbp-7CH]
IN0048: 000191 0FB6C9 movzx rcx, cl
IN0049: 000194 894DDC mov dword ptr [rbp-24H], ecx
IN004a: 000197 90 nop
IN004b: 000198 E9BB000000 jmp G_M45291_IG12
;; bbWeight=1 PerfScore 18.50
G_M45291_IG09: ; func=00, offs=0001A5H, size=0032H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
Block predicted offs = 000001A5, actual = 0000019D -> size adj = 8
IN004c: 00019D 488D4DE8 lea rcx, bword ptr [rbp-18H]
; byrRegs +[rcx]
IN004d: 0001A1 8B55F8 mov edx, dword ptr [rbp-08H]
IN004e: 0001A4 E86F14CFFD call System.ReadOnlySpan`1[Byte][System.Byte]:get_Item(int):byref:this
; byrRegs -[rcx] +[rax]
; gcr arg pop 0
IN004f: 0001A9 48894588 mov bword ptr [rbp-78H], rax
IN0050: 0001AD 488B5588 mov rdx, bword ptr [rbp-78H]
; byrRegs +[rdx]
IN0051: 0001B1 0FB612 movzx rdx, byte ptr [rdx]
; byrRegs -[rdx]
IN0052: 0001B4 8955E4 mov dword ptr [rbp-1CH], edx
IN0053: 0001B7 8B55F8 mov edx, dword ptr [rbp-08H]
IN0054: 0001BA FFC2 inc edx
IN0055: 0001BC 488B4D10 mov rcx, bword ptr [rbp+10H]
; byrRegs +[rcx]
IN0056: 0001C0 895118 mov dword ptr [rcx+24], edx
IN0057: 0001C3 8B55E4 mov edx, dword ptr [rbp-1CH]
IN0058: 0001C6 8955DC mov dword ptr [rbp-24H], edx
IN0059: 0001C9 90 nop
IN005a: 0001CA E989000000 jmp G_M45291_IG12
;; bbWeight=1 PerfScore 15.00
G_M45291_IG10: ; func=00, offs=0001D7H, size=0074H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
Block predicted offs = 000001D7, actual = 000001CF -> size adj = 8
; byrRegs -[rax rcx]
IN005b: 0001CF 488B5510 mov rdx, bword ptr [rbp+10H]
; byrRegs +[rdx]
IN005c: 0001D3 3912 cmp dword ptr [rdx], edx
IN005d: 0001D5 488B5510 mov rdx, bword ptr [rbp+10H]
IN005e: 0001D9 4883C240 add rdx, 64
IN005f: 0001DD 48B980CDF73AF97F0000 mov rcx, 0x7FF93AF7CD80
IN0060: 0001E7 E83422C75C call CORINFO_HELP_BOX
; gcrRegs +[rax]
; byrRegs -[rdx]
; gcr arg pop 0
IN0061: 0001EC 48898550FFFFFF mov gword ptr [rbp-B0H], rax
IN0062: 0001F3 488B9550FFFFFF mov rdx, gword ptr [rbp-B0H]
; gcrRegs +[rdx]
IN0063: 0001FA 48B95897563BF97F0000 mov rcx, 0x7FF93B569758
IN0064: 000204 E87712CEFD call CORINFO_HELP_ISINSTANCEOFCLASS
; gcrRegs -[rdx]
; gcr arg pop 0
IN0065: 000209 488945D0 mov gword ptr [rbp-30H], rax
IN0066: 00020D 48837DD000 cmp gword ptr [rbp-30H], 0
IN0067: 000212 0F95C1 setne cl
IN0068: 000215 0FB6C9 movzx rcx, cl
IN0069: 000218 894DCC mov dword ptr [rbp-34H], ecx
IN006a: 00021B 837DCC00 cmp dword ptr [rbp-34H], 0
IN006b: 00021F 7422 je SHORT G_M45291_IG11
IN006c: 000221 90 nop
IN006d: 000222 488B4DD0 mov rcx, gword ptr [rbp-30H]
; gcrRegs +[rcx]
IN006e: 000226 488B45D0 mov rax, gword ptr [rbp-30H]
IN006f: 00022A 488B00 mov rax, qword ptr [rax]
; gcrRegs -[rax]
IN0070: 00022D 488B4048 mov rax, qword ptr [rax+72]
IN0071: 000231 FF5038 call qword ptr [rax+56]Hagar.Buffers.ReaderInput:ReadByte():ubyte:this
; gcrRegs -[rcx]
; gcr arg pop 0
IN0072: 000234 894598 mov dword ptr [rbp-68H], eax
IN0073: 000237 8B4598 mov eax, dword ptr [rbp-68H]
IN0074: 00023A 0FB6C0 movzx rax, al
IN0075: 00023D 8945DC mov dword ptr [rbp-24H], eax
IN0076: 000240 90 nop
IN0077: 000241 EB15 jmp SHORT G_M45291_IG12
;; bbWeight=1 PerfScore 29.75
G_M45291_IG11: ; func=00, offs=00024BH, size=0015H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
Block predicted offs = 0000024B, actual = 00000243 -> size adj = 8
IN0078: 000243 90 nop
IN0079: 000244 E817DEFFFF call Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ThrowNotSupportedInput():ubyte
; gcr arg pop 0
IN007a: 000249 89459C mov dword ptr [rbp-64H], eax
IN007b: 00024C 8B459C mov eax, dword ptr [rbp-64H]
IN007c: 00024F 0FB6C0 movzx rax, al
IN007d: 000252 8945DC mov dword ptr [rbp-24H], eax
IN007e: 000255 90 nop
IN007f: 000256 EB00 jmp SHORT G_M45291_IG12
;; bbWeight=1 PerfScore 6.75
G_M45291_IG12: ; func=00, offs=000260H, size=0003H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
Block predicted offs = 00000260, actual = 00000258 -> size adj = 8
IN0080: 000258 8B45DC mov eax, dword ptr [rbp-24H]
;; bbWeight=1 PerfScore 1.00
G_M45291_IG13: ; func=00, offs=000263H, size=0006H, epilog, nogc, extend
Block predicted offs = 00000263, actual = 0000025B -> size adj = 8
IN008f: 00025B 488D6500 lea rsp, [rbp]
IN0090: 00025F 5D pop rbp
IN0091: 000260 C3 ret
;; bbWeight=1 PerfScore 2.00
Allocated method code size = 617 , actual size = 609
; Total bytes of code 609, prolog size 76, PerfScore 197.53, instruction count 145 (MethodHash=011f4f14) for method Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this
; ============================================================
*************** After end code gen, before unwindEmit()
G_M45291_IG01: ; func=00, offs=000000H, size=004CH, bbWeight=1 PerfScore 10.58, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc, isz <-- Prolog IG
IN0081: 000000 push rbp
IN0082: 000001 sub rsp, 208
IN0083: 000008 vzeroupper
IN0084: 00000B lea rbp, [rsp+D0H]
IN0085: 000013 vxorps xmm4, xmm4
IN0086: 000017 vmovdqa xmmword ptr [rbp-B0H], xmm4
IN0087: 00001F vmovdqa xmmword ptr [rbp-A0H], xmm4
IN0088: 000027 mov rax, -144
IN0089: 000031 vmovdqa xmmword ptr [rax+rbp], xmm4
IN008a: 000036 vmovdqa xmmword ptr [rbp+rax+10H], xmm4
IN008b: 00003C vmovdqa xmmword ptr [rbp+rax+20H], xmm4
IN008c: 000042 add rax, 48
IN008d: 000046 jne SHORT -5 instr
IN008e: 000048 mov bword ptr [V00 rbp+10H], rcx
G_M45291_IG02: ; offs=00004CH, size=0009H, bbWeight=1 PerfScore 3.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0001: 00004C cmp dword ptr [(reloc)], 0
IN0002: 000053 je SHORT G_M45291_IG04
G_M45291_IG03: ; offs=000055H, size=0005H, bbWeight=0.50 PerfScore 0.50, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN0003: 000055 call CORINFO_HELP_DBG_IS_JUST_MY_CODE
G_M45291_IG04: ; offs=00005AH, size=00CDH, bbWeight=1 PerfScore 35.25, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0004: 00005A nop
IN0005: 00005B mov rcx, 0x7FF93AF7CD80
IN0006: 000065 call CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
IN0007: 00006A mov gword ptr [V10 rbp-40H], rax
IN0008: 00006E mov rcx, gword ptr [V10 rbp-40H]
IN0009: 000072 call System.Type:GetTypeFromHandle(System.RuntimeTypeHandle):System.Type
IN000a: 000077 mov gword ptr [V11 rbp-48H], rax
IN000b: 00007B mov rcx, 0x7FF93AF7CD80
IN000c: 000085 call CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
IN000d: 00008A mov gword ptr [V12 rbp-50H], rax
IN000e: 00008E mov rcx, gword ptr [V12 rbp-50H]
IN000f: 000092 call System.Type:GetTypeFromHandle(System.RuntimeTypeHandle):System.Type
IN0010: 000097 mov gword ptr [V13 rbp-58H], rax
IN0011: 00009B mov rcx, gword ptr [V11 rbp-48H]
IN0012: 00009F mov rdx, gword ptr [V13 rbp-58H]
IN0013: 0000A3 call System.Type:op_Equality(System.Type,System.Type):bool
IN0014: 0000A8 mov dword ptr [V14 rbp-5CH], eax
IN0015: 0000AB cmp dword ptr [V14 rbp-5CH], 0
IN0016: 0000AF jne SHORT G_M45291_IG05
IN0017: 0000B1 mov rcx, 0x7FF93AF7CD80
IN0018: 0000BB call CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
IN0019: 0000C0 mov gword ptr [V22 rbp-88H], rax
IN001a: 0000C7 mov rcx, gword ptr [V22 rbp-88H]
IN001b: 0000CE call System.Type:GetTypeFromHandle(System.RuntimeTypeHandle):System.Type
IN001c: 0000D3 mov gword ptr [V23 rbp-90H], rax
IN001d: 0000DA mov rcx, 0x7FF93B56A7F8
IN001e: 0000E4 call CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPEHANDLE
IN001f: 0000E9 mov gword ptr [V24 rbp-98H], rax
IN0020: 0000F0 mov rcx, gword ptr [V24 rbp-98H]
IN0021: 0000F7 call System.Type:GetTypeFromHandle(System.RuntimeTypeHandle):System.Type
IN0022: 0000FC mov gword ptr [V25 rbp-A0H], rax
IN0023: 000103 mov rcx, gword ptr [V23 rbp-90H]
IN0024: 00010A mov rdx, gword ptr [V25 rbp-A0H]
IN0025: 000111 call System.Type:op_Equality(System.Type,System.Type):bool
IN0026: 000116 mov dword ptr [V26 rbp-A4H], eax
IN0027: 00011C mov ecx, dword ptr [V26 rbp-A4H]
IN0028: 000122 mov dword ptr [V15 rbp-60H], ecx
IN0029: 000125 jmp SHORT G_M45291_IG06
G_M45291_IG05: ; offs=000127H, size=0007H, bbWeight=1 PerfScore 1.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN002a: 000127 mov dword ptr [V15 rbp-60H], 1
G_M45291_IG06: ; offs=00012EH, size=0022H, bbWeight=1 PerfScore 9.50, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN002b: 00012E mov ecx, dword ptr [V15 rbp-60H]
IN002c: 000131 movzx rcx, cl
IN002d: 000134 mov dword ptr [V01 rbp-04H], ecx
IN002e: 000137 cmp dword ptr [V01 rbp-04H], 0
IN002f: 00013B je G_M45291_IG10
IN0030: 000141 nop
IN0031: 000142 mov rcx, bword ptr [V00 rbp+10H]
IN0032: 000146 mov ecx, dword ptr [rcx+24]
IN0033: 000149 mov dword ptr [V02 rbp-08H], ecx
IN0034: 00014C mov rcx, bword ptr [V00 rbp+10H]
G_M45291_IG07: ; offs=000150H, size=000AH, bbWeight=1 PerfScore 3.00, nogc, isz, extend
IN0035: 000150 vmovdqu xmm0, xmmword ptr [rcx+32]
IN0036: 000155 vmovdqu xmmword ptr [V03 rbp-18H], xmm0
G_M45291_IG08: ; offs=00015AH, size=0043H, bbWeight=1 PerfScore 18.50, isz, extend
IN0037: 00015A mov ecx, dword ptr [V02 rbp-08H]
IN0038: 00015D mov dword ptr [V18 rbp-6CH], ecx
IN0039: 000160 lea rcx, bword ptr [V03 rbp-18H]
IN003a: 000164 call System.ReadOnlySpan`1[Byte][System.Byte]:get_Length():int:this
IN003b: 000169 mov dword ptr [V19 rbp-70H], eax
IN003c: 00016C mov ecx, dword ptr [V18 rbp-6CH]
IN003d: 00016F cmp ecx, dword ptr [V19 rbp-70H]
IN003e: 000172 setae cl
IN003f: 000175 movzx rcx, cl
IN0040: 000178 mov dword ptr [V05 rbp-20H], ecx
IN0041: 00017B cmp dword ptr [V05 rbp-20H], 0
IN0042: 00017F je SHORT G_M45291_IG09
IN0043: 000181 nop
IN0044: 000182 mov rcx, bword ptr [V00 rbp+10H]
IN0045: 000186 call Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:<ReadByte>g__ReadByteSlow|18_0(byref):ubyte
IN0046: 00018B mov dword ptr [V21 rbp-7CH], eax
IN0047: 00018E mov ecx, dword ptr [V21 rbp-7CH]
IN0048: 000191 movzx rcx, cl
IN0049: 000194 mov dword ptr [V06 rbp-24H], ecx
IN004a: 000197 nop
IN004b: 000198 jmp G_M45291_IG12
G_M45291_IG09: ; offs=00019DH, size=0032H, bbWeight=1 PerfScore 15.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN004c: 00019D lea rcx, bword ptr [V03 rbp-18H]
IN004d: 0001A1 mov edx, dword ptr [V02 rbp-08H]
IN004e: 0001A4 call System.ReadOnlySpan`1[Byte][System.Byte]:get_Item(int):byref:this
IN004f: 0001A9 mov bword ptr [V20 rbp-78H], rax
IN0050: 0001AD mov rdx, bword ptr [V20 rbp-78H]
IN0051: 0001B1 movzx rdx, byte ptr [rdx]
IN0052: 0001B4 mov dword ptr [V04 rbp-1CH], edx
IN0053: 0001B7 mov edx, dword ptr [V02 rbp-08H]
IN0054: 0001BA inc edx
IN0055: 0001BC mov rcx, bword ptr [V00 rbp+10H]
IN0056: 0001C0 mov dword ptr [rcx+24], edx
IN0057: 0001C3 mov edx, dword ptr [V04 rbp-1CH]
IN0058: 0001C6 mov dword ptr [V06 rbp-24H], edx
IN0059: 0001C9 nop
IN005a: 0001CA jmp G_M45291_IG12
G_M45291_IG10: ; offs=0001CFH, size=0074H, bbWeight=1 PerfScore 29.75, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN005b: 0001CF mov rdx, bword ptr [V00 rbp+10H]
IN005c: 0001D3 cmp dword ptr [rdx], edx
IN005d: 0001D5 mov rdx, bword ptr [V00 rbp+10H]
IN005e: 0001D9 add rdx, 64
IN005f: 0001DD mov rcx, 0x7FF93AF7CD80
IN0060: 0001E7 call CORINFO_HELP_BOX
IN0061: 0001EC mov gword ptr [V27 rbp-B0H], rax
IN0062: 0001F3 mov rdx, gword ptr [V27 rbp-B0H]
IN0063: 0001FA mov rcx, 0x7FF93B569758
IN0064: 000204 call CORINFO_HELP_ISINSTANCEOFCLASS
IN0065: 000209 mov gword ptr [V07 rbp-30H], rax
IN0066: 00020D cmp gword ptr [V07 rbp-30H], 0
IN0067: 000212 setne cl
IN0068: 000215 movzx rcx, cl
IN0069: 000218 mov dword ptr [V08 rbp-34H], ecx
IN006a: 00021B cmp dword ptr [V08 rbp-34H], 0
IN006b: 00021F je SHORT G_M45291_IG11
IN006c: 000221 nop
IN006d: 000222 mov rcx, gword ptr [V07 rbp-30H]
IN006e: 000226 mov rax, gword ptr [V07 rbp-30H]
IN006f: 00022A mov rax, qword ptr [rax]
IN0070: 00022D mov rax, qword ptr [rax+72]
IN0071: 000231 call qword ptr [rax+56]Hagar.Buffers.ReaderInput:ReadByte():ubyte:this
IN0072: 000234 mov dword ptr [V17 rbp-68H], eax
IN0073: 000237 mov eax, dword ptr [V17 rbp-68H]
IN0074: 00023A movzx rax, al
IN0075: 00023D mov dword ptr [V06 rbp-24H], eax
IN0076: 000240 nop
IN0077: 000241 jmp SHORT G_M45291_IG12
G_M45291_IG11: ; offs=000243H, size=0015H, bbWeight=1 PerfScore 6.75, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0078: 000243 nop
IN0079: 000244 call Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ThrowNotSupportedInput():ubyte
IN007a: 000249 mov dword ptr [V16 rbp-64H], eax
IN007b: 00024C mov eax, dword ptr [V16 rbp-64H]
IN007c: 00024F movzx rax, al
IN007d: 000252 mov dword ptr [V06 rbp-24H], eax
IN007e: 000255 nop
IN007f: 000256 jmp SHORT G_M45291_IG12
G_M45291_IG12: ; offs=000258H, size=0003H, bbWeight=1 PerfScore 1.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN0080: 000258 mov eax, dword ptr [V06 rbp-24H]
G_M45291_IG13: ; offs=00025BH, size=0006H, bbWeight=1 PerfScore 2.00, epilog, nogc, extend
IN008f: 00025B lea rsp, [rbp]
IN0090: 00025F pop rbp
IN0091: 000260 ret
*************** Finishing PHASE Emit code
*************** Starting PHASE Emit GC+EH tables
Unwind Info:
>> Start offset : 0x000000 (not in unwind data)
>> End offset : 0x000261 (not in unwind data)
Version : 1
Flags : 0x00
SizeOfProlog : 0x08
CountOfUnwindCodes: 3
FrameRegister : none (0)
FrameOffset : N/A (no FrameRegister) (Value=0)
UnwindCodes :
CodeOffset: 0x08 UnwindOp: UWOP_ALLOC_LARGE (1) OpInfo: 0 - Scaled small
Size: 26 * 8 = 208 = 0x000D0
CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5)
allocUnwindInfo(pHotCode=0x00007FF93AB931E0, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x261, unwindSize=0xa, pUnwindBlock=0x000001609E0AD316, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 52
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs NO_MAP : 0x0000004C ( STACK_EMPTY )
IL offs 0x0000 : 0x0000005A ( STACK_EMPTY )
IL offs 0x0001 : 0x0000005B ( STACK_EMPTY )
IL offs 0x0006 : 0x00000072 ( CALL_INSTRUCTION )
IL offs 0x000B : 0x0000007B
IL offs 0x0010 : 0x00000092 ( CALL_INSTRUCTION )
IL offs 0x0015 : 0x0000009B
IL offs 0x0015 : 0x000000A3 ( CALL_INSTRUCTION )
IL offs 0x001A : 0x000000AB
IL offs 0x001C : 0x000000B1 ( STACK_EMPTY )
IL offs 0x0021 : 0x000000CE ( CALL_INSTRUCTION )
IL offs 0x0026 : 0x000000DA
IL offs 0x002B : 0x000000F7 ( CALL_INSTRUCTION )
IL offs 0x0030 : 0x00000103
IL offs 0x0030 : 0x00000111 ( CALL_INSTRUCTION )
IL offs 0x0035 : 0x0000011C
IL offs 0x0037 : 0x00000127 ( STACK_EMPTY )
IL offs 0x0039 : 0x00000137 ( STACK_EMPTY )
IL offs 0x003C : 0x00000141 ( STACK_EMPTY )
IL offs 0x003D : 0x00000142 ( STACK_EMPTY )
IL offs 0x0044 : 0x0000014C ( STACK_EMPTY )
IL offs 0x004B : 0x0000015A ( STACK_EMPTY )
IL offs 0x004E : 0x00000164 ( CALL_INSTRUCTION )
IL offs 0x0053 : 0x0000016C
IL offs 0x005A : 0x0000017B ( STACK_EMPTY )
IL offs 0x005E : 0x00000181 ( STACK_EMPTY )
IL offs 0x005F : 0x00000182 ( STACK_EMPTY )
IL offs 0x0060 : 0x00000186 ( CALL_INSTRUCTION )
IL offs 0x0065 : 0x0000018E
IL offs 0x0067 : 0x00000197 ( STACK_EMPTY )
IL offs 0x0069 : 0x0000019D ( STACK_EMPTY )
IL offs 0x006C : 0x000001A4 ( CALL_INSTRUCTION )
IL offs 0x0071 : 0x000001AD
IL offs 0x0073 : 0x000001B7 ( STACK_EMPTY )
IL offs 0x007C : 0x000001C3 ( STACK_EMPTY )
IL offs 0x007F : 0x000001C9 ( STACK_EMPTY )
IL offs 0x0081 : 0x000001CF ( STACK_EMPTY )
IL offs 0x0093 : 0x0000020D ( STACK_EMPTY )
IL offs 0x009A : 0x0000021B ( STACK_EMPTY )
IL offs 0x009E : 0x00000221 ( STACK_EMPTY )
IL offs 0x009F : 0x00000222 ( STACK_EMPTY )
IL offs 0x00A1 : 0x00000231 ( CALL_INSTRUCTION )
IL offs 0x00A6 : 0x00000237
IL offs 0x00A8 : 0x00000240 ( STACK_EMPTY )
IL offs 0x00AA : 0x00000243 ( STACK_EMPTY )
IL offs 0x00AB : 0x00000244 ( STACK_EMPTY )
IL offs 0x00AB : 0x00000244 ( STACK_EMPTY CALL_INSTRUCTION )
IL offs 0x00B0 : 0x0000024C
IL offs 0x00B2 : 0x00000255 ( STACK_EMPTY )
IL offs 0x00B4 : 0x00000258 ( STACK_EMPTY )
IL offs EPILOG : 0x0000025B ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 10
; Variable debug info: 10 live range(s), 9 var(s) for method Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this
0( UNKNOWN) : From 00000000h to 0000004Ch, in rcx
0( UNKNOWN) : From 0000005Ah to 0000025Bh, in rbp[16] (1 slot)
7( UNKNOWN) : From 0000005Ah to 0000025Bh, in rbp[-48] (1 slot)
6( UNKNOWN) : From 0000005Ah to 0000025Bh, in rbp[-36] (1 slot)
5( UNKNOWN) : From 0000005Ah to 0000025Bh, in rbp[-32] (1 slot)
4( UNKNOWN) : From 0000005Ah to 0000025Bh, in rbp[-28] (1 slot)
3( UNKNOWN) : From 0000005Ah to 0000025Bh, in rbp[-24] (1 slot)
2( UNKNOWN) : From 0000005Ah to 0000025Bh, in rbp[-8] (1 slot)
1( UNKNOWN) : From 0000005Ah to 0000025Bh, in rbp[-4] (1 slot)
8( UNKNOWN) : From 0000005Ah to 0000025Bh, in rbp[-52] (1 slot)
*************** In gcInfoBlockHdrSave()
Set code length to 609.
Set ReturnKind to Scalar.
Set stack base register to rbp.
Set Outgoing stack arg area size to 32.
Stack slot id for offset 16 (0x10) (frame) (byref, untracked) = 0.
Stack slot id for offset -24 (-0x18) (frame) (byref, untracked) = 1.
Stack slot id for offset -48 (-0x30) (frame) (untracked) = 2.
Stack slot id for offset -64 (-0x40) (frame) (untracked) = 3.
Stack slot id for offset -72 (-0x48) (frame) (untracked) = 4.
Stack slot id for offset -80 (-0x50) (frame) (untracked) = 5.
Stack slot id for offset -88 (-0x58) (frame) (untracked) = 6.
Stack slot id for offset -120 (-0x78) (frame) (byref, untracked) = 7.
Stack slot id for offset -136 (-0x88) (frame) (untracked) = 8.
Stack slot id for offset -144 (-0x90) (frame) (untracked) = 9.
Stack slot id for offset -152 (-0x98) (frame) (untracked) = 10.
Stack slot id for offset -160 (-0xa0) (frame) (untracked) = 11.
Stack slot id for offset -176 (-0xb0) (frame) (untracked) = 12.
Register slot id for reg rax = 13.
Register slot id for reg rcx = 14.
Register slot id for reg rdx = 15.
Register slot id for reg rcx (byref) = 16.
Register slot id for reg rax (byref) = 17.
Register slot id for reg rdx (byref) = 18.
Set state of slot 13 at instr offset 0x6a to Live.
Set state of slot 14 at instr offset 0x72 to Live.
Set state of slot 14 at instr offset 0x77 to Dead.
Set state of slot 14 at instr offset 0x92 to Live.
Set state of slot 14 at instr offset 0x97 to Dead.
Set state of slot 14 at instr offset 0x9f to Live.
Set state of slot 15 at instr offset 0xa3 to Live.
Set state of slot 13 at instr offset 0xa8 to Dead.
Set state of slot 14 at instr offset 0xa8 to Dead.
Set state of slot 15 at instr offset 0xa8 to Dead.
Set state of slot 13 at instr offset 0xc0 to Live.
Set state of slot 14 at instr offset 0xce to Live.
Set state of slot 14 at instr offset 0xd3 to Dead.
Set state of slot 14 at instr offset 0xf7 to Live.
Set state of slot 14 at instr offset 0xfc to Dead.
Set state of slot 14 at instr offset 0x10a to Live.
Set state of slot 15 at instr offset 0x111 to Live.
Set state of slot 13 at instr offset 0x116 to Dead.
Set state of slot 14 at instr offset 0x116 to Dead.
Set state of slot 15 at instr offset 0x116 to Dead.
Set state of slot 16 at instr offset 0x146 to Live.
Set state of slot 16 at instr offset 0x149 to Dead.
Set state of slot 16 at instr offset 0x150 to Live.
Set state of slot 16 at instr offset 0x15d to Dead.
Set state of slot 16 at instr offset 0x164 to Live.
Set state of slot 16 at instr offset 0x169 to Dead.
Set state of slot 16 at instr offset 0x186 to Live.
Set state of slot 16 at instr offset 0x18b to Dead.
Set state of slot 16 at instr offset 0x1a1 to Live.
Set state of slot 17 at instr offset 0x1a9 to Live.
Set state of slot 16 at instr offset 0x1a9 to Dead.
Set state of slot 18 at instr offset 0x1b1 to Live.
Set state of slot 18 at instr offset 0x1b4 to Dead.
Set state of slot 16 at instr offset 0x1c0 to Live.
Set state of slot 17 at instr offset 0x1cf to Dead.
Set state of slot 16 at instr offset 0x1cf to Dead.
Set state of slot 18 at instr offset 0x1d3 to Live.
Set state of slot 13 at instr offset 0x1ec to Live.
Set state of slot 18 at instr offset 0x1ec to Dead.
Set state of slot 15 at instr offset 0x1fa to Live.
Set state of slot 15 at instr offset 0x209 to Dead.
Set state of slot 14 at instr offset 0x226 to Live.
Set state of slot 13 at instr offset 0x22d to Dead.
Set state of slot 14 at instr offset 0x234 to Dead.
Defining interruptible range: [0x4c, 0x150).
Defining interruptible range: [0x15a, 0x25b).
*************** Finishing PHASE Emit GC+EH tables
Method code size: 609
Allocations for Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this (MethodHash=011f4f14)
count: 2263, size: 167098, max = 3360
allocateMemory: 196608, nraUsed: 169880
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
AssertionProp | 0 | 0.00%
ASTNode | 38216 | 22.87%
InstDesc | 13192 | 7.89%
ImpStack | 408 | 0.24%
BasicBlock | 4776 | 2.86%
fgArgInfo | 1344 | 0.80%
fgArgInfoPtrArr | 168 | 0.10%
FlowList | 880 | 0.53%
TreeStatementList | 0 | 0.00%
SiScope | 648 | 0.39%
DominatorMemory | 0 | 0.00%
LSRA | 3896 | 2.33%
LSRA_Interval | 7040 | 4.21%
LSRA_RefPosition | 25472 | 15.24%
Reachability | 0 | 0.00%
SSA | 0 | 0.00%
ValueNumber | 0 | 0.00%
LvaTable | 5520 | 3.30%
UnwindInfo | 0 | 0.00%
hashBv | 480 | 0.29%
bitset | 456 | 0.27%
FixedBitVect | 28 | 0.02%
Generic | 3600 | 2.15%
LocalAddressVisitor | 512 | 0.31%
FieldSeqStore | 272 | 0.16%
ZeroOffsetFieldMap | 40 | 0.02%
ArrayInfoMap | 0 | 0.00%
MemoryPhiArg | 0 | 0.00%
CSE | 0 | 0.00%
GC | 5220 | 3.12%
CorTailCallInfo | 0 | 0.00%
Inlining | 120 | 0.07%
ArrayStack | 0 | 0.00%
DebugInfo | 2024 | 1.21%
DebugOnly | 50273 | 30.09%
Codegen | 1176 | 0.70%
LoopOpt | 0 | 0.00%
LoopHoist | 0 | 0.00%
Unknown | 1225 | 0.73%
RangeCheck | 0 | 0.00%
CopyProp | 0 | 0.00%
SideEffects | 0 | 0.00%
ObjectAllocator | 0 | 0.00%
VariableLiveRanges | 0 | 0.00%
ClassLayout | 112 | 0.07%
TailMergeThrows | 0 | 0.00%
EarlyProp | 0 | 0.00%
ZeroInit | 0 | 0.00%
****** DONE compiling Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this
Raw
jitdisasm2.txt
This file has been truncated, but you can view the full file.
Ready
****** START compiling Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this (MethodHash=011f4f14)
Generating code for Windows x64
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = true
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
IL to import:
IL_0000 00 nop
IL_0001 7e 8d 04 00 0a ldsfld 0xA00048D
IL_0006 2d 07 brtrue.s 7 (IL_000f)
IL_0008 7e 9a 04 00 0a ldsfld 0xA00049A
IL_000d 2b 01 br.s 1 (IL_0010)
IL_000f 17 ldc.i4.1
IL_0010 0a stloc.0
IL_0011 06 ldloc.0
IL_0012 2c 45 brfalse.s 69 (IL_0059)
IL_0014 00 nop
IL_0015 02 ldarg.0
IL_0016 7b 94 04 00 0a ldfld 0xA000494
IL_001b 0b stloc.1
IL_001c 02 ldarg.0
IL_001d 7b 93 04 00 0a ldfld 0xA000493
IL_0022 0c stloc.2
IL_0023 07 ldloc.1
IL_0024 12 02 ldloca.s 0x2
IL_0026 28 24 01 00 0a call 0xA000124
IL_002b fe 05 clt.un
IL_002d 16 ldc.i4.0
IL_002e fe 01 ceq
IL_0030 13 04 stloc.s 0x4
IL_0032 11 04 ldloc.s 0x4
IL_0034 2c 0b brfalse.s 11 (IL_0041)
IL_0036 00 nop
IL_0037 02 ldarg.0
IL_0038 28 a9 04 00 0a call 0xA0004A9
IL_003d 13 05 stloc.s 0x5
IL_003f 2b 4b br.s 75 (IL_008c)
IL_0041 12 02 ldloca.s 0x2
IL_0043 07 ldloc.1
IL_0044 28 ac 01 00 0a call 0xA0001AC
IL_0049 47 ldind.u1
IL_004a 0d stloc.3
IL_004b 02 ldarg.0
IL_004c 07 ldloc.1
IL_004d 17 ldc.i4.1
IL_004e 58 add
IL_004f 7d 94 04 00 0a stfld 0xA000494
IL_0054 09 ldloc.3
IL_0055 13 05 stloc.s 0x5
IL_0057 2b 33 br.s 51 (IL_008c)
IL_0059 02 ldarg.0
IL_005a 7b 8f 04 00 0a ldfld 0xA00048F
IL_005f 8c fd 00 00 1b box 0x1B0000FD
IL_0064 75 13 01 00 02 isinst 0x2000113
IL_0069 13 06 stloc.s 0x6
IL_006b 11 06 ldloc.s 0x6
IL_006d 14 ldnull
IL_006e fe 03 cgt.un
IL_0070 13 07 stloc.s 0x7
IL_0072 11 07 ldloc.s 0x7
IL_0074 2c 0c brfalse.s 12 (IL_0082)
IL_0076 00 nop
IL_0077 11 06 ldloc.s 0x6
IL_0079 6f b5 04 00 06 callvirt 0x60004B5
IL_007e 13 05 stloc.s 0x5
IL_0080 2b 0a br.s 10 (IL_008c)
IL_0082 00 nop
IL_0083 28 41 01 00 2b call 0x2B000141
IL_0088 13 05 stloc.s 0x5
IL_008a 2b 00 br.s 0 (IL_008c)
IL_008c 11 05 ldloc.s 0x5
IL_008e 2a ret
'this' passed in register rcx
lvaSetClass: setting class for V07 to (00007FF9399ABB68) Hagar.Buffers.ReaderInput
lvaGrabTemp returning 9 (V09 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
; Initial local variable assignments
;
; V00 this byref this
; V01 loc0 bool
; V02 loc1 int
; V03 loc2 struct <System.ReadOnlySpan`1[Byte], 16>
; V04 loc3 ubyte
; V05 loc4 bool
; V06 loc5 ubyte
; V07 loc6 ref class-hnd
; V08 loc7 bool
; V09 OutArgs lclBlk <na> "OutgoingArgSpace"
*************** In compInitDebuggingInfo() for Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 9
VarNum LVNum Name Beg End
0: 00h 00h V00 this 000h 08Fh
1: 01h 01h V01 loc0 000h 08Fh
2: 02h 02h V02 loc1 000h 08Fh
3: 03h 03h V03 loc2 000h 08Fh
4: 04h 04h V04 loc3 000h 08Fh
5: 05h 05h V05 loc4 000h 08Fh
6: 06h 06h V06 loc5 000h 08Fh
7: 07h 07h V07 loc6 000h 08Fh
8: 08h 08h V08 loc7 000h 08Fh
New Basic Block BB01 [0000] created.
New scratch BB01
Debuggable code - Add new BB01 [0000] to perform initialization of variables
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE )
*************** In fgFindBasicBlocks() for Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this
Marked V01 as a single def local
Marked V02 as a single def local
Marked V04 as a single def local
Marked V05 as a single def local
Marked V07 as a single def local
Marked V08 as a single def local
Jump targets:
IL_000f
IL_0010
IL_0041
IL_0059
IL_0082
IL_008c
New Basic Block BB02 [0001] created.
BB02 [000..008)
New Basic Block BB03 [0002] created.
BB03 [008..00F)
New Basic Block BB04 [0003] created.
BB04 [00F..010)
New Basic Block BB05 [0004] created.
BB05 [010..014)
New Basic Block BB06 [0005] created.
BB06 [014..036)
New Basic Block BB07 [0006] created.
BB07 [036..041)
New Basic Block BB08 [0007] created.
BB08 [041..059)
New Basic Block BB09 [0008] created.
BB09 [059..076)
New Basic Block BB10 [0009] created.
BB10 [076..082)
New Basic Block BB11 [0010] created.
BB11 [082..08C)
New Basic Block BB12 [0011] created.
BB12 [08C..08F)
CLFLG_MINOPT set for method Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this
IL Code Size,Instr 143, 65, Basic Block count 12, Local Variable Num,Ref count 10, 28 for method Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this
IL Code Size,Instr 143, 65, Basic Block count 12, Local Variable Num,Ref count 10, 28 for method Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this
OPTIONS: opts.MinOpts() == true
Basic block list for 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target
BB02 [0001] 1 1 [000..008)-> BB04 ( cond )
BB03 [0002] 1 1 [008..00F)-> BB05 (always)
BB04 [0003] 1 1 [00F..010)
BB05 [0004] 2 1 [010..014)-> BB09 ( cond )
BB06 [0005] 1 1 [014..036)-> BB08 ( cond )
BB07 [0006] 1 1 [036..041)-> BB12 (always)
BB08 [0007] 1 1 [041..059)-> BB12 (always)
BB09 [0008] 1 1 [059..076)-> BB11 ( cond )
BB10 [0009] 1 1 [076..082)-> BB12 (always)
BB11 [0010] 1 1 [082..08C)-> BB12 (always)
BB12 [0011] 4 1 [08C..08F) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Pre-import
*************** Finishing PHASE Pre-import
*************** Starting PHASE Importation
*************** In impImport() for Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this
Marking leading BBF_INTERNAL block BB01 as BBF_IMPORTED
impImportBlockPending for BB02
Importing BB02 (PC=000) of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
[ 0] 0 (0x000) nop
STMT00001 (IL 0x000... ???)
[000001] ------------ * NO_OP void
[ 0] 1 (0x001) ldsfld 0A00048D
[ 1] 6 (0x006) brtrue.s
STMT00002 (IL 0x001... ???)
[000005] ------------ * JTRUE void
[000004] ------------ \--* NE int
[000002] ------------ +--* CNS_INT int 1
[000003] ------------ \--* CNS_INT int 0
impImportBlockPending for BB03
impImportBlockPending for BB04
Importing BB04 (PC=015) of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
[ 0] 15 (0x00f) ldc.i4.1 1
*************** In impGetSpillTmpBase(BB04)
lvaGrabTemps(1) returning 10..10 (long lifetime temps) called for IL Stack Entries
*************** In fgComputeCheapPreds()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target
BB02 [0001] 1 1 [000..008)-> BB04 ( cond ) i
BB03 [0002] 1 1 [008..00F)-> BB05 (always)
BB04 [0003] 1 1 [00F..010)
BB05 [0004] 2 1 [010..014)-> BB09 ( cond )
BB06 [0005] 1 1 [014..036)-> BB08 ( cond )
BB07 [0006] 1 1 [036..041)-> BB12 (always)
BB08 [0007] 1 1 [041..059)-> BB12 (always)
BB09 [0008] 1 1 [059..076)-> BB11 ( cond )
BB10 [0009] 1 1 [076..082)-> BB12 (always)
BB11 [0010] 1 1 [082..08C)-> BB12 (always)
BB12 [0011] 4 1 [08C..08F) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputeCheapPreds()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd cheap preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target
BB02 [0001] 1 BB01 1 [000..008)-> BB04 ( cond ) i
BB03 [0002] 1 BB02 1 [008..00F)-> BB05 (always)
BB04 [0003] 1 BB02 1 [00F..010)
BB05 [0004] 2 BB04,BB03 1 [010..014)-> BB09 ( cond )
BB06 [0005] 1 BB05 1 [014..036)-> BB08 ( cond )
BB07 [0006] 1 BB06 1 [036..041)-> BB12 (always)
BB08 [0007] 1 BB06 1 [041..059)-> BB12 (always)
BB09 [0008] 1 BB05 1 [059..076)-> BB11 ( cond )
BB10 [0009] 1 BB09 1 [076..082)-> BB12 (always)
BB11 [0010] 1 BB09 1 [082..08C)-> BB12 (always)
BB12 [0011] 4 BB11,BB10,BB08,BB07 1 [08C..08F) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
Spilling stack entries into temps
STMT00003 (IL 0x00F... ???)
[000008] -A---------- * ASG int
[000007] D------N---- +--* LCL_VAR int V10 tmp1
[000006] ------------ \--* CNS_INT int 1
impImportBlockPending for BB05
Importing BB05 (PC=016) of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
[ 1] 16 (0x010) stloc.0
STMT00004 (IL ???... ???)
[000012] -A---------- * ASG int
[000011] D------N---- +--* LCL_VAR int V01 loc0
[000010] ------------ \--* LCL_VAR int V10 tmp1
[ 0] 17 (0x011) ldloc.0
[ 1] 18 (0x012) brfalse.s
STMT00005 (IL 0x011... ???)
[000016] ------------ * JTRUE void
[000015] ------------ \--* EQ int
[000013] ------------ +--* LCL_VAR int V01 loc0
[000014] ------------ \--* CNS_INT int 0
impImportBlockPending for BB06
impImportBlockPending for BB09
Importing BB09 (PC=089) of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
[ 0] 89 (0x059) ldarg.0
[ 1] 90 (0x05a) ldfld 0A00048F
[ 1] 95 (0x05f) box 1B0000FD
Compiler::impImportAndPushBox -- handling BOX(value class) via helper call because: optimizing for size
[ 1] 100 (0x064) isinst 02000113
Expanding isinst as call because inline expansion not legal
[ 1] 105 (0x069) stloc.s 6
STMT00006 (IL 0x059... ???)
[000025] -ACXG------- * ASG ref
[000024] D------N---- +--* LCL_VAR ref V07 loc6
[000023] --CXG------- \--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS
[000022] H------N---- arg0 +--* CNS_INT(h) long 0x7ff9399abb68 class
[000021] --CXG------- arg1 \--* CALL help ref HELPER.CORINFO_HELP_BOX
[000019] H----------- arg0 +--* CNS_INT(h) long 0x7ff939412c80 class
[000020] ---XG------- arg1 \--* ADDR byref
[000018] ---XG--N---- \--* FIELD struct _input
[000017] ------------ \--* LCL_VAR byref V00 this
[ 0] 107 (0x06b) ldloc.s 6
[ 1] 109 (0x06d) ldnull
[ 2] 110 (0x06e) cgt.un
[ 1] 112 (0x070) stloc.s 7
STMT00007 (IL 0x06B... ???)
[000030] -A---------- * ASG int
[000029] D------N---- +--* LCL_VAR int V08 loc7
[000028] N--------U-- \--* GT int
[000026] ------------ +--* LCL_VAR ref V07 loc6
[000027] ------------ \--* CNS_INT ref null
[ 0] 114 (0x072) ldloc.s 7
[ 1] 116 (0x074) brfalse.s
STMT00008 (IL 0x072... ???)
[000034] ------------ * JTRUE void
[000033] ------------ \--* EQ int
[000031] ------------ +--* LCL_VAR int V08 loc7
[000032] ------------ \--* CNS_INT int 0
impImportBlockPending for BB10
impImportBlockPending for BB11
Importing BB11 (PC=130) of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
[ 0] 130 (0x082) nop
STMT00009 (IL 0x082... ???)
[000035] ------------ * NO_OP void
[ 0] 131 (0x083) call 2B000141
In Compiler::impImportCall: opcode is call, kind=0, callRetType is ubyte, structSize is 0
lvaGrabTemp returning 11 (V11 tmp2) called for impSpillStackEnsure.
STMT00010 (IL 0x083... ???)
[000038] -AC-G------- * ASG int
[000037] D------N---- +--* LCL_VAR int V11 tmp2
[000036] --C-G------- \--* CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].ThrowNotSupportedInput
[ 1] 136 (0x088) stloc.s 5
STMT00011 (IL 0x088... ???)
[000041] -A---------- * ASG int
[000040] D------N---- +--* LCL_VAR int V06 loc5
[000039] ------------ \--* LCL_VAR int V11 tmp2
[ 0] 138 (0x08a) br.s
STMT00012 (IL 0x08A... ???)
[000042] ------------ * NOP void
impImportBlockPending for BB12
Importing BB12 (PC=140) of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
[ 0] 140 (0x08c) ldloc.s 5
[ 1] 142 (0x08e) ret
STMT00013 (IL 0x08C... ???)
[000044] ------------ * RETURN int
[000043] ------------ \--* LCL_VAR int V06 loc5
Importing BB10 (PC=118) of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
[ 0] 118 (0x076) nop
STMT00014 (IL 0x076... ???)
[000045] ------------ * NO_OP void
[ 0] 119 (0x077) ldloc.s 6
[ 1] 121 (0x079) callvirt 060004B5
In Compiler::impImportCall: opcode is callvirt, kind=4, callRetType is ubyte, structSize is 0
lvaGrabTemp returning 12 (V12 tmp3) called for impSpillStackEnsure.
STMT00015 (IL 0x077... ???)
[000049] -AC-G------- * ASG int
[000048] D------N---- +--* LCL_VAR int V12 tmp3
[000047] --C-G------- \--* CALLV ind int Hagar.Buffers.ReaderInput.ReadByte
[000046] ------------ this in rcx \--* LCL_VAR ref V07 loc6
[ 1] 126 (0x07e) stloc.s 5
STMT00016 (IL 0x07E... ???)
[000052] -A---------- * ASG int
[000051] D------N---- +--* LCL_VAR int V06 loc5
[000050] ------------ \--* LCL_VAR int V12 tmp3
[ 0] 128 (0x080) br.s
STMT00017 (IL 0x080... ???)
[000053] ------------ * NOP void
impImportBlockPending for BB12
Importing BB06 (PC=020) of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
[ 0] 20 (0x014) nop
STMT00018 (IL 0x014... ???)
[000054] ------------ * NO_OP void
[ 0] 21 (0x015) ldarg.0
[ 1] 22 (0x016) ldfld 0A000494
[ 1] 27 (0x01b) stloc.1
STMT00019 (IL 0x015... ???)
[000058] -A-XG------- * ASG int
[000057] D------N---- +--* LCL_VAR int V02 loc1
[000056] ---XG------- \--* FIELD int _bufferPos
[000055] ------------ \--* LCL_VAR byref V00 this
[ 0] 28 (0x01c) ldarg.0
[ 1] 29 (0x01d) ldfld 0A000493
[ 1] 34 (0x022) stloc.2
STMT00020 (IL 0x01C... ???)
[000063] -A-XG------- * ASG struct (copy)
[000061] D------N---- +--* LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16> V03 loc2
[000060] ---XG------- \--* FIELD struct _currentSpan
[000059] ------------ \--* LCL_VAR byref V00 this
[ 0] 35 (0x023) ldloc.1
[ 1] 36 (0x024) ldloca.s 2
[ 2] 38 (0x026) call 0A000124
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
lvaGrabTemp returning 13 (V13 tmp4) called for impSpillStackEnsure.
STMT00021 (IL 0x023... ???)
[000069] -A---------- * ASG int
[000068] D------N---- +--* LCL_VAR int V13 tmp4
[000064] ------------ \--* LCL_VAR int V02 loc1
lvaGrabTemp returning 14 (V14 tmp5) called for impSpillStackEnsure.
STMT00022 (IL ???... ???)
[000072] -AC-G------- * ASG int
[000071] D------N---- +--* LCL_VAR int V14 tmp5
[000067] --C-G------- \--* CALL int System.ReadOnlySpan`1[Byte][System.Byte].get_Length
[000066] ------------ this in rcx \--* ADDR byref
[000065] -------N---- \--* LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16> V03 loc2
[ 2] 43 (0x02b) clt.un
[ 1] 45 (0x02d) ldc.i4.0 0
[ 2] 46 (0x02e) ceq
[ 1] 48 (0x030) stloc.s 4
STMT00023 (IL 0x02B... ???)
[000078] -A---------- * ASG int
[000077] D------N---- +--* LCL_VAR int V05 loc4
[000076] ------------ \--* EQ int
[000074] N--------U-- +--* LT int
[000070] ------------ | +--* LCL_VAR int V13 tmp4
[000073] ------------ | \--* LCL_VAR int V14 tmp5
[000075] ------------ \--* CNS_INT int 0
[ 0] 50 (0x032) ldloc.s 4
[ 1] 52 (0x034) brfalse.s
STMT00024 (IL 0x032... ???)
[000082] ------------ * JTRUE void
[000081] ------------ \--* EQ int
[000079] ------------ +--* LCL_VAR int V05 loc4
[000080] ------------ \--* CNS_INT int 0
impImportBlockPending for BB07
impImportBlockPending for BB08
Importing BB08 (PC=065) of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
[ 0] 65 (0x041) ldloca.s 2
[ 1] 67 (0x043) ldloc.1
[ 2] 68 (0x044) call 0A0001AC
In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0
lvaGrabTemp returning 15 (V15 tmp6) called for impSpillStackEnsure.
STMT00025 (IL 0x041... ???)
[000088] -AC-G------- * ASG byref
[000087] D------N---- +--* LCL_VAR byref V15 tmp6
[000086] --C-G------- \--* CALL byref System.ReadOnlySpan`1[Byte][System.Byte].get_Item
[000084] ------------ this in rcx +--* ADDR byref
[000083] -------N---- | \--* LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16> V03 loc2
[000085] ------------ arg1 \--* LCL_VAR int V02 loc1
[ 1] 73 (0x049) ldind.u1
[ 1] 74 (0x04a) stloc.3
STMT00026 (IL 0x049... ???)
[000092] -A-XG------- * ASG int
[000091] D------N---- +--* LCL_VAR int V04 loc3
[000090] *--XG------- \--* IND ubyte
[000089] ------------ \--* LCL_VAR byref V15 tmp6
[ 0] 75 (0x04b) ldarg.0
[ 1] 76 (0x04c) ldloc.1
[ 2] 77 (0x04d) ldc.i4.1 1
[ 3] 78 (0x04e) add
[ 2] 79 (0x04f) stfld 0A000494
STMT00027 (IL 0x04B... ???)
[000098] -A-XG------- * ASG int
[000097] ---XG--N---- +--* FIELD int _bufferPos
[000093] ------------ | \--* LCL_VAR byref V00 this
[000096] ------------ \--* ADD int
[000094] ------------ +--* LCL_VAR int V02 loc1
[000095] ------------ \--* CNS_INT int 1
[ 0] 84 (0x054) ldloc.3
[ 1] 85 (0x055) stloc.s 5
STMT00028 (IL 0x054... ???)
[000101] -A---------- * ASG int
[000100] D------N---- +--* LCL_VAR int V06 loc5
[000099] ------------ \--* LCL_VAR int V04 loc3
[ 0] 87 (0x057) br.s
STMT00029 (IL 0x057... ???)
[000102] ------------ * NOP void
impImportBlockPending for BB12
Importing BB07 (PC=054) of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
[ 0] 54 (0x036) nop
STMT00030 (IL 0x036... ???)
[000103] ------------ * NO_OP void
[ 0] 55 (0x037) ldarg.0
[ 1] 56 (0x038) call 0A0004A9
In Compiler::impImportCall: opcode is call, kind=0, callRetType is ubyte, structSize is 0
lvaGrabTemp returning 16 (V16 tmp7) called for impSpillStackEnsure.
STMT00031 (IL 0x037... ???)
[000107] -AC-G------- * ASG int
[000106] D------N---- +--* LCL_VAR int V16 tmp7
[000105] --C-G------- \--* CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].ReadByteSlow
[000104] ------------ arg0 \--* LCL_VAR byref V00 this
[ 1] 61 (0x03d) stloc.s 5
STMT00032 (IL 0x03D... ???)
[000110] -A---------- * ASG int
[000109] D------N---- +--* LCL_VAR int V06 loc5
[000108] ------------ \--* LCL_VAR int V16 tmp7
[ 0] 63 (0x03f) br.s
STMT00033 (IL 0x03F... ???)
[000111] ------------ * NOP void
impImportBlockPending for BB12
Importing BB03 (PC=008) of 'Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]]:ReadByte():ubyte:this'
[ 0] 8 (0x008) ldsfld 0A00049A
[ 1] 13 (0x00d) br.s
STMT00034 (IL 0x008... ???)
[000113] ------------ * NOP void
Spilling stack entries into temps
STMT00035 (IL ???... ???)
[000115] -A---------- * ASG int
[000114] D------N---- +--* LCL_VAR int V10 tmp1
[000112] ------------ \--* CNS_INT int 0
impImportBlockPending for BB05
*************** Finishing PHASE Importation
Trees after Importation
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target
BB02 [0001] 1 1 [000..008)-> BB04 ( cond ) i
BB03 [0002] 1 1 [008..00F)-> BB05 (always) i
BB04 [0003] 1 1 [00F..010) i
BB05 [0004] 2 1 [010..014)-> BB09 ( cond ) i
BB06 [0005] 1 1 [014..036)-> BB08 ( cond ) i
BB07 [0006] 1 1 [036..041)-> BB12 (always) i
BB08 [0007] 1 1 [041..059)-> BB12 (always) i
BB09 [0008] 1 1 [059..076)-> BB11 ( cond ) i
BB10 [0009] 1 1 [076..082)-> BB12 (always) i
BB11 [0010] 1 1 [082..08C)-> BB12 (always) i
BB12 [0011] 4 1 [08C..08F) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
***** BB01
STMT00000 (IL ???... ???)
[000000] ------------ * NOP void
------------ BB02 [000..008) -> BB04 (cond), preds={} succs={BB03,BB04}
***** BB02
STMT00001 (IL 0x000...0x000)
[000001] ------------ * NO_OP void
***** BB02
STMT00002 (IL 0x001...0x006)
[000005] ------------ * JTRUE void
[000004] ------------ \--* NE int
[000002] ------------ +--* CNS_INT int 1
[000003] ------------ \--* CNS_INT int 0
------------ BB03 [008..00F) -> BB05 (always), preds={} succs={BB05}
***** BB03
STMT00034 (IL 0x008...0x00D)
[000113] ------------ * NOP void
***** BB03
STMT00035 (IL ???... ???)
[000115] -A---------- * ASG int
[000114] D------N---- +--* LCL_VAR int V10 tmp1
[000112] ------------ \--* CNS_INT int 0
------------ BB04 [00F..010), preds={} succs={BB05}
***** BB04
STMT00003 (IL 0x00F...0x00F)
[000008] -A---------- * ASG int
[000007] D------N---- +--* LCL_VAR int V10 tmp1
[000006] ------------ \--* CNS_INT int 1
------------ BB05 [010..014) -> BB09 (cond), preds={} succs={BB06,BB09}
***** BB05
STMT00004 (IL ???...0x010)
[000012] -A---------- * ASG int
[000011] D------N---- +--* LCL_VAR int V01 loc0
[000010] ------------ \--* LCL_VAR int V10 tmp1
***** BB05
STMT00005 (IL 0x011...0x012)
[000016] ------------ * JTRUE void
[000015] ------------ \--* EQ int
[000013] ------------ +--* LCL_VAR int V01 loc0
[000014] ------------ \--* CNS_INT int 0
------------ BB06 [014..036) -> BB08 (cond), preds={} succs={BB07,BB08}
***** BB06
STMT00018 (IL 0x014...0x014)
[000054] ------------ * NO_OP void
***** BB06
STMT00019 (IL 0x015...0x01B)
[000058] -A-XG------- * ASG int
[000057] D------N---- +--* LCL_VAR int V02 loc1
[000056] ---XG------- \--* FIELD int _bufferPos
[000055] ------------ \--* LCL_VAR byref V00 this
***** BB06
STMT00020 (IL 0x01C...0x022)
[000063] -A-XG------- * ASG struct (copy)
[000061] D------N---- +--* LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16> V03 loc2
[000060] ---XG------- \--* FIELD struct _currentSpan
[000059] ------------ \--* LCL_VAR byref V00 this
***** BB06
STMT00021 (IL 0x023...0x030)
[000069] -A---------- * ASG int
[000068] D------N---- +--* LCL_VAR int V13 tmp4
[000064] ------------ \--* LCL_VAR int V02 loc1
***** BB06
STMT00022 (IL ???... ???)
[000072] -AC-G------- * ASG int
[000071] D------N---- +--* LCL_VAR int V14 tmp5
[000067] --C-G------- \--* CALL int System.ReadOnlySpan`1[Byte][System.Byte].get_Length
[000066] ------------ this in rcx \--* ADDR byref
[000065] -------N---- \--* LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16> V03 loc2
***** BB06
STMT00023 (IL 0x02B... ???)
[000078] -A---------- * ASG int
[000077] D------N---- +--* LCL_VAR int V05 loc4
[000076] ------------ \--* EQ int
[000074] N--------U-- +--* LT int
[000070] ------------ | +--* LCL_VAR int V13 tmp4
[000073] ------------ | \--* LCL_VAR int V14 tmp5
[000075] ------------ \--* CNS_INT int 0
***** BB06
STMT00024 (IL 0x032...0x034)
[000082] ------------ * JTRUE void
[000081] ------------ \--* EQ int
[000079] ------------ +--* LCL_VAR int V05 loc4
[000080] ------------ \--* CNS_INT int 0
------------ BB07 [036..041) -> BB12 (always), preds={} succs={BB12}
***** BB07
STMT00030 (IL 0x036...0x036)
[000103] ------------ * NO_OP void
***** BB07
STMT00031 (IL 0x037...0x03D)
[000107] -AC-G------- * ASG int
[000106] D------N---- +--* LCL_VAR int V16 tmp7
[000105] --C-G------- \--* CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].ReadByteSlow
[000104] ------------ arg0 \--* LCL_VAR byref V00 this
***** BB07
STMT00032 (IL 0x03D... ???)
[000110] -A---------- * ASG int
[000109] D------N---- +--* LCL_VAR int V06 loc5
[000108] ------------ \--* LCL_VAR int V16 tmp7
***** BB07
STMT00033 (IL 0x03F...0x03F)
[000111] ------------ * NOP void
------------ BB08 [041..059) -> BB12 (always), preds={} succs={BB12}
***** BB08
STMT00025 (IL 0x041...0x04A)
[000088] -AC-G------- * ASG byref
[000087] D------N---- +--* LCL_VAR byref V15 tmp6
[000086] --C-G------- \--* CALL byref System.ReadOnlySpan`1[Byte][System.Byte].get_Item
[000084] ------------ this in rcx +--* ADDR byref
[000083] -------N---- | \--* LCL_VAR struct<System.ReadOnlySpan`1[Byte], 16> V03 loc2
[000085] ------------ arg1 \--* LCL_VAR int V02 loc1
***** BB08
STMT00026 (IL 0x049... ???)
[000092] -A-XG------- * ASG int
[000091] D------N---- +--* LCL_VAR int V04 loc3
[000090] *--XG------- \--* IND ubyte
[000089] ------------ \--* LCL_VAR byref V15 tmp6
***** BB08
STMT00027 (IL 0x04B...0x04F)
[000098] -A-XG------- * ASG int
[000097] ---XG--N---- +--* FIELD int _bufferPos
[000093] ------------ | \--* LCL_VAR byref V00 this
[000096] ------------ \--* ADD int
[000094] ------------ +--* LCL_VAR int V02 loc1
[000095] ------------ \--* CNS_INT int 1
***** BB08
STMT00028 (IL 0x054...0x055)
[000101] -A---------- * ASG int
[000100] D------N---- +--* LCL_VAR int V06 loc5
[000099] ------------ \--* LCL_VAR int V04 loc3
***** BB08
STMT00029 (IL 0x057...0x057)
[000102] ------------ * NOP void
------------ BB09 [059..076) -> BB11 (cond), preds={} succs={BB10,BB11}
***** BB09
STMT00006 (IL 0x059...0x069)
[000025] -ACXG------- * ASG ref
[000024] D------N---- +--* LCL_VAR ref V07 loc6
[000023] --CXG------- \--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS
[000022] H------N---- arg0 +--* CNS_INT(h) long 0x7ff9399abb68 class
[000021] --CXG------- arg1 \--* CALL help ref HELPER.CORINFO_HELP_BOX
[000019] H----------- arg0 +--* CNS_INT(h) long 0x7ff939412c80 class
[000020] ---XG------- arg1 \--* ADDR byref
[000018] ---XG--N---- \--* FIELD struct _input
[000017] ------------ \--* LCL_VAR byref V00 this
***** BB09
STMT00007 (IL 0x06B...0x070)
[000030] -A---------- * ASG int
[000029] D------N---- +--* LCL_VAR int V08 loc7
[000028] N--------U-- \--* GT int
[000026] ------------ +--* LCL_VAR ref V07 loc6
[000027] ------------ \--* CNS_INT ref null
***** BB09
STMT00008 (IL 0x072...0x074)
[000034] ------------ * JTRUE void
[000033] ------------ \--* EQ int
[000031] ------------ +--* LCL_VAR int V08 loc7
[000032] ------------ \--* CNS_INT int 0
------------ BB10 [076..082) -> BB12 (always), preds={} succs={BB12}
***** BB10
STMT00014 (IL 0x076...0x076)
[000045] ------------ * NO_OP void
***** BB10
STMT00015 (IL 0x077...0x07E)
[000049] -AC-G------- * ASG int
[000048] D------N---- +--* LCL_VAR int V12 tmp3
[000047] --C-G------- \--* CALLV ind int Hagar.Buffers.ReaderInput.ReadByte
[000046] ------------ this in rcx \--* LCL_VAR ref V07 loc6
***** BB10
STMT00016 (IL 0x07E... ???)
[000052] -A---------- * ASG int
[000051] D------N---- +--* LCL_VAR int V06 loc5
[000050] ------------ \--* LCL_VAR int V12 tmp3
***** BB10
STMT00017 (IL 0x080...0x080)
[000053] ------------ * NOP void
------------ BB11 [082..08C) -> BB12 (always), preds={} succs={BB12}
***** BB11
STMT00009 (IL 0x082...0x082)
[000035] ------------ * NO_OP void
***** BB11
STMT00010 (IL 0x083...0x088)
[000038] -AC-G------- * ASG int
[000037] D------N---- +--* LCL_VAR int V11 tmp2
[000036] --C-G------- \--* CALL int Hagar.Buffers.Reader`1[ReadOnlySequence`1][System.Buffers.ReadOnlySequence`1[System.Byte]].ThrowNotSupportedInput
***** BB11
STMT00011 (IL 0x088... ???)
[000041] -A---------- * ASG int
[000040] D------N---- +--* LCL_VAR int V06 loc5
[000039] ------------ \--* LCL_VAR int V11 tmp2
***** BB11
STMT00012 (IL 0x08A...0x08A)
[000042] ------------ * NOP void
------------ BB12 [08C..08F) (return), preds={} succs={}
***** BB12
STMT00013 (IL 0x08C...0x08E)
[000044] ------------ * RETURN int
[000043] ------------ \--* LCL_VAR int V06 loc5
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Indirect call transform
-- no candidates to transform
*************** Finishing PHASE Indirect call transform [no changes]
*************** Starting PHASE Expand patchpoints
-- no patchpoints to transform
*************** Finishing PHASE Expand patchpoints [no changes]
*************** Starting PHASE Post-import
*************** Finishing PHASE Post-import
*************** Starting PHASE Morph - Init
New BlockSet epoch 1, # of blocks (including unused BB00): 13, bitset array size: 1 (short)
*************** In fgRemoveEmptyBlocks
*************** Finishing PHASE Morph - Init
*************** In fgDebugCheckBBlist
*************** Starting PHASE Morph - Inlining
*************** Finishing PHASE Morph - Inlining [no changes]
*************** Starting PHASE Allocate Objects
no newobjs in this method; punting
*************** Finishing PHASE Allocate Objects [no changes]
*************** Starting PHASE Morph - Add internal blocks
*************** After fgAddInternal()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target
BB02 [0001] 1 1 [000..008)-> BB04 ( cond ) i
BB03 [0002] 1 1 [008..00F)-> BB05 (always) i
BB04 [0003] 1 1 [00F..010) i
BB05 [0004] 2 1 [010..014)-> BB09 ( cond ) i
BB06 [0005] 1 1 [014..036)-> BB08 ( cond ) i
BB07 [0006] 1 1 [036..041)-> BB12 (always) i
BB08 [0007] 1 1 [041..059)-> BB12 (always) i
BB09 [0008] 1 1 [059..076)-> BB11 ( cond ) i
BB10 [0009] 1 1 [076..082)-> BB12 (always) i
BB11 [0010] 1 1 [082..08C)-> BB12 (always) i
BB12 [0011] 4 1 [08C..08F) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** Finishing PHASE Morph - Add internal blocks
*************** Starting PHASE Remove empty try
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try [no changes]
*************** Starting PHASE Remove empty finally
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally [no changes]
*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.
*************** Finishing PHASE Merge callfinally chains [no changes]
*************** Starting PHASE Clone finally
No EH in this method, no cloning.
*************** Finishing PHASE Clone finally [no changes]
*************** Starting PHASE Compute preds
Renumbering the basic blocks for fgComputePred
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target
BB02 [0001] 1 1 [000..008)-> BB04 ( cond ) i
BB03 [0002] 1 1 [008..00F)-> BB05 (always) i
BB04 [0003] 1 1 [00F..010) i
BB05 [0004] 2 1 [010..014)-> BB09 ( cond ) i
BB06 [0005] 1 1 [014..036)-> BB08 ( cond ) i
BB07 [0006] 1 1 [036..041)-> BB12 (always) i
BB08 [0007] 1 1 [041..059)-> BB12 (always) i
BB09 [0008] 1 1 [059..076)-> BB11 ( cond ) i
BB10 [0009] 1 1 [076..082)-> BB12 (always) i
BB11 [0010] 1 1 [082..08C)-> BB12 (always) i
BB12 [0011] 4 1 [08C..08F) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
*************** In fgComputePreds()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target
BB02 [0001] 1 1 [000..008)-> BB04 ( cond ) i
BB03 [0002] 1 1 [008..00F)-> BB05 (always) i
BB04 [0003] 1 1 [00F..010) i
BB05 [0004] 2 1 [010..014)-> BB09 ( cond ) i
BB06 [0005] 1 1 [014..036)-> BB08 ( cond ) i
BB07 [0006] 1 1 [036..041)-> BB12 (always) i
BB08 [0007] 1 1 [041..059)-> BB12 (always) i
BB09 [0008] 1 1 [059..076)-> BB11 ( cond ) i
BB10 [0009] 1 1 [076..082)-> BB12 (always) i
BB11 [0010] 1 1 [082..08C)-> BB12 (always) i
BB12 [0011] 4 1 [08C..08F) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputePreds()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal label target
BB02 [0001] 1 BB01 1 [000..008)-> BB04 ( cond ) i
BB03 [0002] 1 BB02 1 [008..00F)-> BB05 (always) i
BB04 [0003] 1 BB02 1 [00F..010) i label target
BB05 [0004] 2 BB03,BB04 1 [010..014)-> BB09 ( cond ) i label target
BB06 [0005] 1 BB05 1 [014..036)-> BB08 ( cond ) i
BB07 [0006] 1 BB06 1 [036..041)-> BB12 (always) i
BB08 [0007] 1 BB06 1 [041..059)-> BB12 (always) i label target
BB09 [0008] 1 BB05 1 [059..076)-> BB11 ( cond ) i label target
BB10 [0009] 1 BB09 1 [076..082)-> BB12 (always) i
BB11 [0010] 1 BB09 1 [082..08C)-> BB12 (always) i label target
BB12 [0011] 4 BB07,BB08,BB10,BB11 1 [08C..08F) (return) i label target
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Compute preds
*************** Starting PHASE Morph - Promote Structs
*************** In fgResetImplicitByRefRefCount()
*************** In fgPromoteStructs()
promotion opt flag not enabled
**
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