configuration files for lpc812 using SWD from an stlink-v2 discovery board

lpc1114.cfg

#-----------------------------------------
# NXP lpc1114fn23 Cortex-M0 32k flash, 4k ram

set CHIPNAME lpc1114
set CPUTAPID 0x0BB11477
set CPUROMSIZE 0x8000
set CPURAMSIZE 0x1000

# After reset the chip is clocked by the ~12MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 12000

# Include the main configuration file.
source [find lpc11xx.cfg];

lpc1114_nucleo.cfg

#---------------------------------------------------------
# 
#---------------------------------------------------------

source [find interface/stlink-v2-1.cfg]
source [find lpc1114.cfg]

reset_config none
#init

lpc11xx.cfg

#
# NXP lpc11xx family
#

source [find target/swj-dp.tcl]

if { [info exists CHIPNAME] } {
	set _CHIPNAME $CHIPNAME
} else {
	set _CHIPNAME lpc11uxx
}

if { [info exists ENDIAN] } {
	set _ENDIAN $ENDIAN
} else {
	set _ENDIAN little
}

# Work-area is a space in RAM used for flash programming
# By default use 6kB
if { [info exists WORKAREASIZE] } {
   set _WORKAREASIZE $WORKAREASIZE
} else {
   set _WORKAREASIZE 0x1800
}

if { [info exists CPUTAPID] } {
	set _CPUTAPID $CPUTAPID
} else {
	set _CPUTAPID 0x00000000
}

if { [info exists CPUROMSIZE] } {
   set _CPUROMSIZE $CPUROMSIZE
} else {
  error "_CPUROMSIZE not set. Please do not include lpc11xx.cfg directly."
}
# CCLK is the core clock frequency in KHz
if { [info exists CCLK] } {
   set _CCLK $CCLK
} else {
  set _CCLK 12000
}

if { [info exists TRANSPORT] } {
   set _TRANSPORT $TRANSPORT
} else {
  # Default to the SWD transport used by ST-Link v2.
  set _TRANSPORT hla_swd
}

transport select $_TRANSPORT

if { $_TRANSPORT == "hla_swd" } {
   hla newtap $_CHIPNAME cpu -expected-id $_CPUTAPID
   set _TARGETTYPE hla_target
} else {
   error "_TRANSPORT can only be hla_swd"
}

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME $_TARGETTYPE -chain-position $_TARGETNAME

$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
# The LPC11xx devices have 4/8/16kB of flash memory, managed by ROM code
# (including a boot loader which verifies the flash exception table's checksum).
# ISR Vector 7 contains the checksum
#
# note: the lpc2000.c code knows about the lpc1700 variant
# .... calc_checksum inserts a checksum into the flash signature vector
#
#flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \
       lpc1700 $_CCLK calc_checksum
$_TARGETNAME configure -event reset-init {
# Do not remap 0x0000-0x0200 to anything but the flash (i.e. select
# "User Flash Mode" where interrupt vectors are _not_ remapped,
# and reside in flash instead).
#
# Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
# Bit Symbol Value Description
# 1:0 MAP          System memory remap
#            0x0   Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
#            0x1   User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
#            0x2   User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
# 31:2 -     -     Reserved.
	mww 0x40048000 0x02
}

lpc812.cfg

#-----------------------------------------
# NXP lpc812 Cortex-M0+ 16k flash, 4k ram

set CHIPNAME lpc812
set CPUTAPID 0x0bc11477
set CPUROMSIZE 0x4000
set CPURAMSIZE 0x1000

# After reset the chip is clocked by the ~12MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 12000

# Include the main configuration file.
source [find lpc8xx.cfg];

lpc812_nucleo.cfg

#---------------------------------------------------
# lpc812_nucleo.cfg - use stlinkv2 on a nucleo board
#---------------------------------------------------
# openocd -s . -f lpc812_nucleo.cfg

source [find interface/stlink-v2-1.cfg]
source [find lpc812.cfg]

reset_config none
init

lpc812_stlink_v2.cfg

#---------------------------------------------------------
# lpc812_stlink_v2.cfg - use lpc812 with a discovery board
#---------------------------------------------------------

source [find interface/stlink-v2.cfg]
source [find lpc812.cfg]

reset_config none
init

lpc8xx.cfg

#--------------------------------------------------------
# Main file for NXP LPC8xx Cortex-M0+
#
# !!!!!!
#
# This file should not be included directly, rather
# needed variables to the appropriate values.
#
# !!!!!!

if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
  error "_CHIPNAME not set. Please do not include lpc8xx.cfg directly, but the specific chip configuration file (lpc812.cfg, lpc811.cfg, etc)."
}

# After reset the chip is clocked by the ~12MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
if { [info exists CCLK] } {
   set _CCLK $CCLK
} else {
  set _CCLK 12000
}

if { [info exists CPUTAPID] } {
   set _CPUTAPID $CPUTAPID
} else {
  error "_CPUTAPID not set. Please do not include lpc8xx.cfg directly, but the specific chip configuration file (lpc812.cfg, lpc811.cfg, etc)."
}

if { [info exists CPURAMSIZE] } {
   set _CPURAMSIZE $CPURAMSIZE
} else {
  error "_CPURAMSIZE not set. Please do not include lpc8xx.cfg directly, but the specific chip configuration file (lpc812.cfg, lpc811.cfg, etc)."
}

if { [info exists CPUROMSIZE] } {
   set _CPUROMSIZE $CPUROMSIZE
} else {
  error "_CPUROMSIZE not set. Please do not include lpc8xx.cfg directly, but the specific chip configuration file (lpc812.cfg, lpc811.cfg, etc)."
}

if { [info exists TRANSPORT] } {
   set _TRANSPORT $TRANSPORT
} else {
  # Default to the SWD transport used by ST-Link v2.
  set _TRANSPORT hla_swd
}

transport select $_TRANSPORT

if { $_TRANSPORT == "hla_swd" } {
   hla newtap $_CHIPNAME cpu -expected-id $_CPUTAPID
   set _TARGETTYPE hla_target
} else {
   error "_TRANSPORT can only be hla_swd"
}

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME $_TARGETTYPE -chain-position $_TARGETNAME

# The LPC8xx devices have 1/2/4kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE

# The LPC8xx devices have 4/8/16kB of flash memory, managed by ROM code
# (including a boot loader which verifies the flash exception table's checksum).
# Vector at 0x1c contains the checksum
#
# note: the lpc2000.c code knows about the lpc800 variant
# .... calc_checksum inserts a checksum into the flash signature vector
#
# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME lpc800 $_CCLK calc_checksum

$_TARGETNAME configure -event reset-init {
    #mww 0x40048000 0x02 # SYSMEMREMAP 0x2 User Flash Mode, vectors reside in flash
}

$_TARGETNAME configure -event gdb-attach {
    reset halt
}

$_TARGETNAME configure -event gdb-detach {
    resume
}