gistfile1.txt

diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 4579c3c..36d3e66 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -913,7 +913,31 @@ static struct clk dpll4_m6x2_ck_3630 = {
 
 DEFINE_CLK_FIXED_FACTOR(dpll4_x2_ck, "dpll4_ck", &dpll4_ck, 0x0, 2, 1);
 
-static struct dpll_data dpll5_dd = {
+static struct dpll_data dpll5_dd;
+
+static struct dpll_data dpll5_dd_34xx __initdata = {
+       .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
+       .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
+       .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
+       .clk_bypass     = &sys_ck,
+       .clk_ref        = &sys_ck,
+       .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
+       .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
+       .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
+       .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
+       .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
+       .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
+       .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
+       .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
+       .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
+       .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
+       .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
+       .max_multiplier = OMAP3_MAX_DPLL_MULT,
+       .min_divider    = 1,
+       .max_divider    = OMAP3_MAX_DPLL_DIV,
+};
+
+static struct dpll_data dpll5_dd_3630 __initdata = {
        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
        .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
        .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
@@ -3571,6 +3595,11 @@ int __init omap3xxx_clk_init(void)
        else
                dpll4_dd = dpll4_dd_34xx;
 
+       if (cpu_is_omap3630())
+               dpll5_dd = dpll5_dd_3630;
+       else
+               dpll5_dd = dpll5_dd_34xx;
+
        for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
             c++)
                if (c->cpu & cpu_clkflg) {