spidev

diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
index 8cbea91c40385..7081923cba3b1 100644
--- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
@@ -1281,4 +1281,19 @@ pins2 {
 			bias-disable;
 		};
 	};
+
+//	spi4_pins_a: spi4-0 {
+//		pins1 {
+//			pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
+//				 <STM32_PINMUX('E', 14, AF5)>; /* SPI4_MOSI */
+//			bias-disable;
+//			drive-push-pull;
+//			slew-rate = <1>;
+//		};
+//
+//		pins2 {
+//			pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
+//			bias-disable;
+//		};
+//	};
 };
diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts
index 8b0d6c4b3c21d..c0b2efb410a16 100644
--- a/arch/arm/boot/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts
@@ -20,6 +20,7 @@ / {
 	aliases {
 		ethernet0 = &ethernet0;
 		serial0 = &uart4;
+		spi0 = &spi4;
 	};
 
 	chosen {
@@ -125,3 +126,17 @@ brcmf: bcrmf@1 {
 		compatible = "brcm,bcm4329-fmac";
 	};
 };
+
+&spi4 {
+	//pinctrl-names = "default";
+	//pinctrl-0 = <&spi4_pins_a>;
+	cs-gpios = <&gpioe 11 0>;
+	status = "okay";
+
+	spidev@0 {
+		compatible = "spidev";
+		reg = <0>;
+		spi-max-frequency = <4000000>;
+		st,spi-midi-ns = <4000>;
+	};
+};
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 44ac6eb3298d4..639e8e6e9d1da 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -383,7 +383,7 @@ static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi)
 
 	spin_unlock_irqrestore(&spi->lock, flags);
 
-	dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
+	dev_info(spi->dev, "%d x 8-bit fifo size\n", count);
 
 	return count;
 }
@@ -394,7 +394,7 @@ static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi)
  */
 static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi)
 {
-	dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
+	dev_info(spi->dev, "8-bit or 16-bit data frame supported\n");
 	return SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
 }
 
@@ -422,7 +422,7 @@ static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
 
 	spin_unlock_irqrestore(&spi->lock, flags);
 
-	dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
+	dev_info(spi->dev, "%d-bit maximum data frame\n", max_bpw);
 
 	return SPI_BPW_RANGE_MASK(4, max_bpw);
 }
@@ -517,7 +517,7 @@ static void stm32f4_spi_write_tx(struct stm32_spi *spi)
 		}
 	}
 
-	dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
+	dev_info(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
 }
 
 /**
@@ -552,7 +552,7 @@ static void stm32h7_spi_write_txfifo(struct stm32_spi *spi)
 		}
 	}
 
-	dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
+	dev_info(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
 }
 
 /**
@@ -581,7 +581,7 @@ static void stm32f4_spi_read_rx(struct stm32_spi *spi)
 		}
 	}
 
-	dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len);
+	dev_info(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len);
 }
 
 /**
@@ -627,7 +627,7 @@ static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
 			 STM32H7_SPI_SR_RXPLVL_SHIFT;
 	}
 
-	dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
+	dev_info(spi->dev, "%s%s: %d bytes left\n", __func__,
 		flush ? "(flush)" : "", spi->rx_len);
 }
 
@@ -637,7 +637,7 @@ static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
  */
 static void stm32_spi_enable(struct stm32_spi *spi)
 {
-	dev_dbg(spi->dev, "enable controller\n");
+	dev_info(spi->dev, "enable controller\n");
 
 	stm32_spi_set_bits(spi, spi->cfg->regs->en.reg,
 			   spi->cfg->regs->en.mask);
@@ -652,7 +652,7 @@ static void stm32f4_spi_disable(struct stm32_spi *spi)
 	unsigned long flags;
 	u32 sr;
 
-	dev_dbg(spi->dev, "disable controller\n");
+	dev_info(spi->dev, "disable controller\n");
 
 	spin_lock_irqsave(&spi->lock, flags);
 
@@ -708,7 +708,7 @@ static void stm32h7_spi_disable(struct stm32_spi *spi)
 	unsigned long flags;
 	u32 cr1, sr;
 
-	dev_dbg(spi->dev, "disable controller\n");
+	dev_info(spi->dev, "disable controller\n");
 
 	spin_lock_irqsave(&spi->lock, flags);
 
@@ -776,7 +776,7 @@ static bool stm32_spi_can_dma(struct spi_master *master,
 	else
 		dma_size = SPI_DMA_MIN_BYTES;
 
-	dev_dbg(spi->dev, "%s: %s\n", __func__,
+	dev_info(spi->dev, "%s: %s\n", __func__,
 		(transfer->len > dma_size) ? "true" : "false");
 
 	return (transfer->len > dma_size);
@@ -818,7 +818,7 @@ static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id)
 	}
 
 	if (!(sr & mask)) {
-		dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr);
+		dev_info(spi->dev, "spurious IT (sr=0x%08x)\n", sr);
 		spin_unlock_irqrestore(&spi->lock, flags);
 		return IRQ_NONE;
 	}
@@ -915,7 +915,7 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
 		mask |= STM32H7_SPI_SR_RXP;
 
 	if (!(sr & mask)) {
-		dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
+		dev_info(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
 			sr, ier);
 		spin_unlock_irqrestore(&spi->lock, flags);
 		return IRQ_NONE;
@@ -993,7 +993,7 @@ static int stm32_spi_prepare_msg(struct spi_master *master,
 	/* SPI slave device may need time between data frames */
 	spi->cur_midi = 0;
 	if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
-		dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
+		dev_info(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
 
 	if (spi_dev->mode & SPI_CPOL)
 		setb |= spi->cfg->regs->cpol.mask;
@@ -1010,7 +1010,7 @@ static int stm32_spi_prepare_msg(struct spi_master *master,
 	else
 		clrb |= spi->cfg->regs->lsb_first.mask;
 
-	dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
+	dev_info(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
 		spi_dev->mode & SPI_CPOL,
 		spi_dev->mode & SPI_CPHA,
 		spi_dev->mode & SPI_LSB_FIRST,
@@ -1123,14 +1123,14 @@ static void stm32_spi_dma_config(struct stm32_spi *spi,
 		dma_conf->src_addr_width = buswidth;
 		dma_conf->src_maxburst = maxburst;
 
-		dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
+		dev_info(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
 			buswidth, maxburst);
 	} else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
 		dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg;
 		dma_conf->dst_addr_width = buswidth;
 		dma_conf->dst_maxburst = maxburst;
 
-		dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
+		dev_info(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
 			buswidth, maxburst);
 	}
 }
@@ -1526,7 +1526,7 @@ static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
 			       (u32)STM32H7_SPI_CFG2_MIDI >>
 			       STM32H7_SPI_CFG2_MIDI_SHIFT);
 
-		dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
+		dev_info(spi->dev, "period=%dns, midi=%d(=%dns)\n",
 			sck_period_ns, midi, midi * sck_period_ns);
 		cfg2_setb |= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) &
 			     STM32H7_SPI_CFG2_MIDI;
@@ -1627,15 +1627,15 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
 
 	spi->cur_xferlen = transfer->len;
 
-	dev_dbg(spi->dev, "transfer communication mode set to %d\n",
+	dev_info(spi->dev, "transfer communication mode set to %d\n",
 		spi->cur_comm);
-	dev_dbg(spi->dev,
+	dev_info(spi->dev,
 		"data frame of %d-bit, data packet of %d data frames\n",
 		spi->cur_bpw, spi->cur_fthlv);
-	dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
-	dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
+	dev_info(spi->dev, "speed set to %dHz\n", spi->cur_speed);
+	dev_info(spi->dev, "transfer of %d bytes (%d data frames)\n",
 		spi->cur_xferlen, nb_words);
-	dev_dbg(spi->dev, "dma %s\n",
+	dev_info(spi->dev, "dma %s\n",
 		(spi->cur_usedma) ? "enabled" : "disabled");
 
 out: