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High Round-Trip Time warning.

Seas0

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High Round-Trip Time warning.
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Seas0 / syncthing-automerge.py
Created February 15, 2025 01:45 — forked from solarkraft/syncthing-automerge.py
Monitors a Syncthing-synced directory and tries to merge conflicting files (based on https://www.rafa.ee/articles/resolve-syncthing-conflicts-using-three-way-merge/). Probably adaptable for other directory types, but only tested with Logseq (works for me™️).
# This script automatically handles Syncthing conflicts on text files by applying a
# git three-way merge between the previously synced version and each divergent version.
# It depends on the watchdog package and git.
# For automatic dependency installation when running with ´uv run --script deconflicter.py´:
# /// script
# requires-python = ">=3.10"
# dependencies = [
# "watchdog",
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Seas0 / ft2232_to_digilent_jtag.md
Created May 9, 2021 06:07 — forked from rikka0w0/ft2232_to_digilent_jtag.md
FT2232 to Digilent JTag for Xilinx FPGAs (ISE/Vivado)

The Digilent JTag uses FT2232, but its configuration EEPROM contains secrete data needed to be recoginzed by Xilinx ISE/Vivado. The following method only works on linux (tested on Ubuntu16.04), but the patched FT2232 doggle also works on Windows. Since WSL1 does not provide USB device access, the following method will not work for WSL1.

DONT use FT_Prog on offical Digilent cable, as it can trash the firmware! The offical eeprom contains secrete data that cannot be handled correctly by FT_Prog.

Here are steps to create a Digilent-like Jtag that can be used in Xilinx ISE and Vivado

  1. Install softwares: sudo apt-get install libftdi1 ftdi-eeprom
  2. Create a file "flash_digilent.conf" with the following content: