| { | |
| "Back" : "Escape; Back; Ctrl+[; Meta+O", | |
| "Forward" : "Forward; Ctrl+[; Meta+I", | |
| "Change Type..." : "Shift+Y; ", | |
| "Close Window" : "Ctrl+W; X", | |
| "Command Palette" : "Ctrl+P; Space", | |
| "Copy" : "Ctrl+C; Y", | |
| "Disassembly Graph" : "G, L", | |
| "Display as\\Binary" : "D", | |
| "Display as\\Default" : "D", |
brew install llvm --HEAD.# Prefer newer LLVM with fuzzing enabled
# shellcheck source=/dev/null
export CC='clang'
export CXX='clang++'
export LDFLAGS="-L/usr/local/opt/llvm/lib -Wl,-rpath,/usr/local/opt/llvm/lib"
PATH="$(brew --prefix)/opt/llvm/bin:$PATH"I've transformed this gist into a git repository.
Whenever you research a certain vulnerability ask yourself these questions and please answer them for us
Does the exploited service write a log?
(check ls -lrt /var/log or lsof +D /var/log/ or lsof | grep servicename)
| #define _GNU_SOURCE | |
| #include <asm/bootparam.h> | |
| #include <errno.h> | |
| #include <fcntl.h> | |
| #include <linux/kvm.h> | |
| #include <linux/kvm_para.h> | |
| #include <stdarg.h> | |
| #include <stdint.h> | |
| #include <stdio.h> | |
| #include <stdlib.h> |
| " An example for a vimrc file. | |
| " | |
| " Maintainer: Bram Moolenaar <[email protected]> | |
| " Last change: 2019 Jan 26 | |
| " | |
| " To use it, copy it to | |
| " for Unix and OS/2: ~/.vimrc | |
| " for Amiga: s:.vimrc | |
| " for MS-DOS and Win32: $VIM\_vimrc | |
| " for OpenVMS: sys$login:.vimrc |
This document was originally written several years ago. At the time I was working as an execution core verification engineer at Arm. The following points are coloured heavily by working in and around the execution cores of various processors. Apply a pinch of salt; points contain varying degrees of opinion.
It is still my opinion that RISC-V could be much better designed; though I will also say that if I was building a 32 or 64-bit CPU today I'd likely implement the architecture to benefit from the existing tooling.
Mostly based upon the RISC-V ISA spec v2.0. Some updates have been made for v2.2
The RISC-V ISA has pursued minimalism to a fault. There is a large emphasis on minimizing instruction count, normalizing encoding, etc. This pursuit of minimalism has resulted in false orthogonalities (such as reusing the same instruction for branches, calls and returns) and a requirement for superfluous instructions which impacts code density both in terms of size and
| /* | |
| See https://gitlab.com/nedopc/npc5/blob/master/emu-rv32i.c for the latest version, with more features and less bugs :-) | |
| RISCV emulator for the RV32I architecture | |
| based on TinyEMU by Fabrice Bellard, see https://bellard.org/tinyemu/ | |
| stripped down for RV32I only, all "gotos" removed, and fixed some bugs for the compliance test | |
| by Frank Buss, 2018 | |
| Requires libelf-dev: |
MinGW - http://mingw.org/
or
| # source:http://geocities.com/SiliconValley/heights/7052/opcode.txt | |
| From: [email protected] (Mark Hopkins) | |
| Newsgroups: alt.lang.asm | |
| Subject: A Summary of the 80486 Opcodes and Instructions | |
| (1) The 80x86 is an Octal Machine | |
| This is a follow-up and revision of an article posted in alt.lang.asm on | |
| 7-5-92 concerning the 80x86 instruction encoding. | |
| The only proper way to understand 80x86 coding is to realize that ALL 80x86 |
