jakub-g

git show HEAD --stat=200 | tail +7 | awk '{ print $3 " "$4 " " $1}' | sort -n -r | less

iainconnor

# Built application files
/*/build/

# Crashlytics configuations
com_crashlytics_export_strings.xml

# Local configuration file (sdk path, etc)
local.properties

# Gradle generated files

michaeljclark

/*
 * RISC-V Immediate Decoder Template Metaprogram
 *
 * Author: Michael Clark <[email protected]>
 */

#include <cstdio>
#include <cstdint>

/* sign extension template */

chrisdone

Common

export OPT=/opt
export BUILDS=/some/where/mini_linux
mkdir -p $BUILDS

Linux kernel

mcastelino

How to setup the controlling process to handle signals

1. Setup a signal handler for the vcpu thread for that signal. It does not have to do anything
2. When a signal is sent to the thread hosting the VM it will result in EINTR (not a reported kvm exit reason)

                signal(SIGUSR1,sig_func); // Register signal handler inside thread, the function is empty
                ret = ioctl(kvm->vcpus->vcpu_fd, KVM_RUN, 0);

                if (ret < 0) {

seanjensengrey

# source:http://geocities.com/SiliconValley/heights/7052/opcode.txt
From: [email protected] (Mark Hopkins)
Newsgroups: alt.lang.asm
Subject: A Summary of the 80486 Opcodes and Instructions

(1) The 80x86 is an Octal Machine
   This is a follow-up and revision of an article posted in alt.lang.asm on
7-5-92 concerning the 80x86 instruction encoding.
 
   The only proper way to understand 80x86 coding is to realize that ALL 80x86

JKomskis

What to Install

C++ Compiler

Windows

MinGW - http://mingw.org/

or

FrankBuss

/*
See https://gitlab.com/nedopc/npc5/blob/master/emu-rv32i.c for the latest version, with more features and less bugs :-)

RISCV emulator for the RV32I architecture
based on TinyEMU by Fabrice Bellard, see https://bellard.org/tinyemu/
stripped down for RV32I only, all "gotos" removed, and fixed some bugs for the compliance test
by Frank Buss, 2018

Requires libelf-dev:

erincandescent

Foreward

This document was originally written several years ago. At the time I was working as an execution core verification engineer at Arm. The following points are coloured heavily by working in and around the execution cores of various processors. Apply a pinch of salt; points contain varying degrees of opinion.

It is still my opinion that RISC-V could be much better designed; though I will also say that if I was building a 32 or 64-bit CPU today I'd likely implement the architecture to benefit from the existing tooling.

Mostly based upon the RISC-V ISA spec v2.0. Some updates have been made for v2.2

Original Foreword: Some Opinion

The RISC-V ISA has pursued minimalism to a fault. There is a large emphasis on minimizing instruction count, normalizing encoding, etc. This pursuit of minimalism has resulted in false orthogonalities (such as reusing the same instruction for branches, calls and returns) and a requirement for superfluous instructions which impacts code density both in terms of size and

gamozolabs

" An example for a vimrc file.
"
" Maintainer:	Bram Moolenaar <[email protected]>
" Last change:	2019 Jan 26
"
" To use it, copy it to
"     for Unix and OS/2:  ~/.vimrc
"	      for Amiga:  s:.vimrc
"  for MS-DOS and Win32:  $VIM\_vimrc
"	    for OpenVMS:  sys$login:.vimrc