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SwapnilGaikwad/IndexOfAnyLookupCombined_JITDump

Created June 29, 2023 09:39
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IndexOfAnyLookupCombined_JITDump
****** START compiling System.Text.Tests.Demo:IndexOfAnyLookupCombined(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte] (MethodHash=2430e072)
Generating code for Unix arm64
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: optimizer should use profile data
IL to import:
IL_0000 02 ldarg.0
IL_0001 1f 0f ldc.i4.s 0xF
IL_0003 28 12 00 00 0a call 0xA000012
IL_0008 28 13 00 00 0a call 0xA000013
IL_000d 0a stloc.0
IL_000e 02 ldarg.0
IL_000f 28 01 00 00 2b call 0x2B000001
IL_0014 1a ldc.i4.4
IL_0015 28 15 00 00 0a call 0xA000015
IL_001a 28 02 00 00 2b call 0x2B000002
IL_001f 1f 0f ldc.i4.s 0xF
IL_0021 28 12 00 00 0a call 0xA000012
IL_0026 28 13 00 00 0a call 0xA000013
IL_002b 0b stloc.1
IL_002c 28 1d 00 00 0a call 0xA00001D
IL_0031 2c 2e brfalse.s 46 (IL_0061)
IL_0033 07 ldloc.1
IL_0034 20 08 08 08 08 ldc.i4 0x8080808
IL_0039 28 1e 00 00 0a call 0xA00001E
IL_003e 28 02 00 00 2b call 0x2B000002
IL_0043 28 13 00 00 0a call 0xA000013
IL_0048 06 ldloc.0
IL_0049 28 1f 00 00 0a call 0xA00001F
IL_004e 13 04 stloc.s 0x4
IL_0050 03 ldarg.1
IL_0051 04 ldarg.2
IL_0052 73 20 00 00 0a newobj 0xA000020
IL_0057 11 04 ldloc.s 0x4
IL_0059 28 21 00 00 0a call 0xA000021
IL_005e 0c stloc.2
IL_005f 2b 32 br.s 50 (IL_0093)
IL_0061 03 ldarg.1
IL_0062 06 ldloc.0
IL_0063 28 08 00 00 06 call 0x6000008
IL_0068 13 05 stloc.s 0x5
IL_006a 04 ldarg.2
IL_006b 06 ldloc.0
IL_006c 28 08 00 00 06 call 0x6000008
IL_0071 13 06 stloc.s 0x6
IL_0073 07 ldloc.1
IL_0074 28 03 00 00 2b call 0x2B000003
IL_0079 1d ldc.i4.7
IL_007a 28 18 00 00 0a call 0xA000018
IL_007f 28 04 00 00 2b call 0x2B000004
IL_0084 28 05 00 00 2b call 0x2B000005
IL_0089 11 06 ldloc.s 0x6
IL_008b 11 05 ldloc.s 0x5
IL_008d 28 06 00 00 2b call 0x2B000006
IL_0092 0c stloc.2
IL_0093 21 01 02 04 08 10 20 40 80 ldc.i8 0x8040201
IL_009c 28 1b 00 00 0a call 0xA00001B
IL_00a1 28 07 00 00 2b call 0x2B000007
IL_00a6 07 ldloc.1
IL_00a7 28 08 00 00 06 call 0x6000008
IL_00ac 0d stloc.3
IL_00ad 08 ldloc.2
IL_00ae 09 ldloc.3
IL_00af 28 13 00 00 0a call 0xA000013
IL_00b4 09 ldloc.3
IL_00b5 28 08 00 00 2b call 0x2B000008
IL_00ba 2a ret
Notify VM instruction set (AdvSimd) must be supported.
Found Vector128<ubyte>
Found Vector128<ubyte>
Arg #0 passed in register(s) d0
Arg #1 passed in register(s) d1
Arg #2 passed in register(s) d2
lvaGrabTemp returning 10 (V10 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
Local V10 should not be enregistered because: it is address exposed
; Initial local variable assignments
;
; V00 arg0 simd16 HFA(simd16)
; V01 arg1 simd16 HFA(simd16)
; V02 arg2 simd16 HFA(simd16)
; V03 loc0 simd16 HFA(simd16)
; V04 loc1 simd16 HFA(simd16)
; V05 loc2 simd16 HFA(simd16)
; V06 loc3 simd16 HFA(simd16)
; V07 loc4 simd16 HFA(simd16)
; V08 loc5 simd16 HFA(simd16)
; V09 loc6 simd16 HFA(simd16)
; V10 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
*************** In compInitDebuggingInfo() for System.Text.Tests.Demo:IndexOfAnyLookupCombined(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 10
VarNum LVNum Name Beg End
0: 00h 00h V00 arg0 000h 0BBh
1: 01h 01h V01 arg1 000h 0BBh
2: 02h 02h V02 arg2 000h 0BBh
3: 03h 03h V03 loc0 000h 0BBh
4: 04h 04h V04 loc1 000h 0BBh
5: 05h 05h V05 loc2 000h 0BBh
6: 06h 06h V06 loc3 000h 0BBh
7: 07h 07h V07 loc4 000h 0BBh
8: 08h 08h V08 loc5 000h 0BBh
9: 09h 09h V09 loc6 000h 0BBh
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for System.Text.Tests.Demo:IndexOfAnyLookupCombined(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]
Marked V03 as a single def local
Marked V04 as a single def local
Marked V06 as a single def local
Marked V07 as a single def local
Marked V08 as a single def local
Marked V09 as a single def local
Jump targets:
IL_0061
IL_0093
New Basic Block BB01 [0000] created.
BB01 [000..033)
New Basic Block BB02 [0001] created.
BB02 [033..061)
New Basic Block BB03 [0002] created.
BB03 [061..093)
New Basic Block BB04 [0003] created.
BB04 [093..0BB)
Setting edge weights for BB01 -> BB03 to [0 .. 3.402823e+38]
Setting edge weights for BB01 -> BB02 to [0 .. 3.402823e+38]
Setting edge weights for BB02 -> BB04 to [0 .. 3.402823e+38]
Setting edge weights for BB03 -> BB04 to [0 .. 3.402823e+38]
IL Code Size,Instr 187, 61, Basic Block count 4, Local Variable Num,Ref count 11, 26 for method System.Text.Tests.Demo:IndexOfAnyLookupCombined(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]
OPTIONS: opts.MinOpts() == false
Basic block list for 'System.Text.Tests.Demo:IndexOfAnyLookupCombined(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..033)-> BB03 ( cond )
BB02 [0001] 1 BB01 1 [033..061)-> BB04 (always)
BB03 [0002] 1 BB01 1 [061..093)
BB04 [0003] 2 BB02,BB03 1 [093..0BB) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Pre-import
*************** Finishing PHASE Pre-import
Trees after Pre-import
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..033)-> BB03 ( cond )
BB02 [0001] 1 BB01 1 [033..061)-> BB04 (always)
BB03 [0002] 1 BB01 1 [061..093)
BB04 [0003] 2 BB02,BB03 1 [093..0BB) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..033) -> BB03 (cond), preds={} succs={BB02,BB03}
------------ BB02 [033..061) -> BB04 (always), preds={BB01} succs={BB04}
------------ BB03 [061..093), preds={BB01} succs={BB04}
------------ BB04 [093..0BB) (return), preds={BB02,BB03} succs={}
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Profile incorporation
BBOPT set, but no profile data available (hr=80004001)
*************** Finishing PHASE Profile incorporation [no changes]
*************** Starting PHASE Importation
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'System.Text.Tests.Demo:IndexOfAnyLookupCombined(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) ldc.i4.s 15
[ 2] 3 (0x003) call 0A000012
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Vector128.Create: Notify VM instruction set (Vector128) must be supported.
Recognized
Found Vector128<ubyte>
[ 2] 8 (0x008) call 0A000013
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Vector128`1.op_BitwiseAnd: Recognized
Found Vector128<ubyte>
[ 1] 13 (0x00d) stloc.0
STMT00000 ( 0x000[E-] ... ??? )
[000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
[000003] ----------- \--* HWINTRINSIC simd16 ubyte And
[000000] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000002] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
[ 0] 14 (0x00e) ldarg.0
[ 1] 15 (0x00f) call 2B000001
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Vector128.AsInt32: Recognized
Found Vector128<int>
Found Vector128<ubyte>
Found Vector128<int>
[ 1] 20 (0x014) ldc.i4.4 4
[ 2] 21 (0x015) call 0A000015
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Vector128.ShiftRightLogical: Recognized
Found Vector128<int>
[ 1] 26 (0x01a) call 2B000002
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Vector128.AsByte: Recognized
Found Vector128<ubyte>
Found Vector128<int>
Found Vector128<ubyte>
[ 1] 31 (0x01f) ldc.i4.s 15
[ 2] 33 (0x021) call 0A000012
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Vector128.Create: Recognized
Found Vector128<ubyte>
[ 2] 38 (0x026) call 0A000013
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Vector128`1.op_BitwiseAnd: Recognized
Found Vector128<ubyte>
[ 1] 43 (0x02b) stloc.1
STMT00001 ( 0x00E[E-] ... ??? )
[000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000010] ----------- \--* HWINTRINSIC simd16 ubyte And
[000007] ----------- +--* HWINTRINSIC simd16 int ShiftRightLogical
[000005] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000006] ----------- | \--* CNS_INT int 4
[000009] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
[ 0] 44 (0x02c) call 0A00001D
In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0
Named Intrinsic System.Runtime.Intrinsics.Arm.AdvSimd.Arm64.get_IsSupported: Notify VM instruction set (AdvSimd_Arm64) must be supported.
Recognized
[ 1] 49 (0x031) brfalse.s
Folding operator with constant nodes into a constant:
[000014] ----------- * EQ int
[000012] ----------- +--* CNS_INT int 1
[000013] ----------- \--* CNS_INT int 0
Bashed to int constant:
[000014] ----------- * CNS_INT int 0
The block falls through into the next BB02
impImportBlockPending for BB02
Importing BB02 (PC=051) of 'System.Text.Tests.Demo:IndexOfAnyLookupCombined(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]'
[ 0] 51 (0x033) ldloc.1
[ 1] 52 (0x034) ldc.i4 134744072
[ 2] 57 (0x039) call 0A00001E
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Vector128.Create: Recognized
Found Vector128<int>
[ 2] 62 (0x03e) call 2B000002
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Vector128.AsByte: Recognized
Found Vector128<ubyte>
Found Vector128<int>
Found Vector128<ubyte>
[ 2] 67 (0x043) call 0A000013
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Vector128`1.op_BitwiseAnd: Recognized
Found Vector128<ubyte>
[ 1] 72 (0x048) ldloc.0
[ 2] 73 (0x049) call 0A00001F
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Vector128`1.op_BitwiseOr: Recognized
Found Vector128<ubyte>
[ 1] 78 (0x04e) stloc.s 4
STMT00002 ( 0x033[E-] ... ??? )
[000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
[000020] ----------- \--* HWINTRINSIC simd16 ubyte Or
[000018] ----------- +--* HWINTRINSIC simd16 ubyte And
[000015] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000017] ----------- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808>
[000019] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
[ 0] 80 (0x050) ldarg.1
[ 1] 81 (0x051) ldarg.2
[ 2] 82 (0x052) newobj
lvaGrabTemp returning 11 (V11 tmp1) called for NewObj constructor temp.
STMT00003 ( 0x050[E-] ... ??? )
[000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1
[000024] ----------- \--* CNS_INT int 0
0A000020
In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0
Calling impNormStructVal on:
[000023] ----------- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2
resulting tree:
[000023] ----------- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2
Calling impNormStructVal on:
[000022] ----------- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1
resulting tree:
[000022] ----------- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1
INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.Tests.Demo:IndexOfAnyLookupCombined(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]' calling 'System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:.ctor(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):this'
INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success'
STMT00004 ( ??? ... ??? )
[000027] I-C-G------ * CALL void System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:.ctor(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):this (exactContextHnd=0x0xd1ffab1e)
[000026] ----------- this +--* LCL_ADDR byref V11 tmp1 [+0]
[000022] ----------- arg1 +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1
[000023] ----------- arg2 \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2
[ 1] 87 (0x057) ldloc.s 4
[ 2] 89 (0x059) call 0A000021
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Arm.AdvSimd.Arm64.VectorTableLookup: Recognized
Found Vector128<ubyte>
Found Vector128<ubyte>
[ 1] 94 (0x05e) stloc.2
STMT00005 ( 0x057[--] ... ??? )
[000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000033] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000030] -c--------- +--* FIELD_LIST struct
[000031] ----------- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 [+0]
[000032] ----------- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 [+16]
[000029] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
[ 0] 95 (0x05f) br.s
impImportBlockPending for BB04
Importing BB04 (PC=147) of 'System.Text.Tests.Demo:IndexOfAnyLookupCombined(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]'
[ 0] 147 (0x093) ldc.i8 0x8040201008040201
[ 1] 156 (0x09c) call 0A00001B
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Vector128.Create: Recognized
Found Vector128<ulong>
[ 1] 161 (0x0a1) call 2B000007
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Vector128.AsByte: Recognized
Found Vector128<ubyte>
Found Vector128<ulong>
Found Vector128<ubyte>
[ 1] 166 (0x0a6) ldloc.1
[ 2] 167 (0x0a7) call 06000008
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Calling impNormStructVal on:
[000037] ----------- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
resulting tree:
[000037] ----------- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
Calling impNormStructVal on:
[000036] ----------- * CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
resulting tree:
[000036] ----------- * CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.Tests.Demo:IndexOfAnyLookupCombined(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]' calling 'System.Text.Tests.Demo:ShuffleUnsafe(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]'
INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success'
Found Vector128<ubyte>
changing the type of a call [000038] from struct to simd16
STMT00006 ( 0x093[E-] ... ??? )
[000038] I-C-G------ * CALL simd16 System.Text.Tests.Demo:ShuffleUnsafe(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte] (exactContextHnd=0x0xd1ffab1e)
[000036] ----------- arg0 +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] ----------- arg1 \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[ 1] 172 (0x0ac) stloc.3
STMT00007 ( 0x093[E-] ... ??? )
[000040] DAC-------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000039] --C-------- \--* RET_EXPR simd16(for [000038])
[ 0] 173 (0x0ad) ldloc.2
[ 1] 174 (0x0ae) ldloc.3
[ 2] 175 (0x0af) call 0A000013
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Vector128`1.op_BitwiseAnd: Recognized
Found Vector128<ubyte>
[ 1] 180 (0x0b4) ldloc.3
[ 2] 181 (0x0b5) call 2B000008
(Implicit Tail call: prefixFlags |= PREFIX_TAILCALL_IMPLICIT)
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Vector128.Equals: Recognized
Found Vector128<ubyte>
[ 1] 186 (0x0ba) ret
impFixupStructReturnType: retyping
[000045] ----------- * HWINTRINSIC simd16 ubyte CompareEqual
[000043] ----------- +--* HWINTRINSIC simd16 ubyte And
[000041] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000042] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000044] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
STMT00008 ( 0x0AD[E-] ... ??? )
[000046] ----------- * RETURN simd16
[000045] ----------- \--* HWINTRINSIC simd16 ubyte CompareEqual
[000043] ----------- +--* HWINTRINSIC simd16 ubyte And
[000041] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000042] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000044] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
** Note: root method IL was partially imported -- imported 137 of 187 bytes of method IL
*************** Finishing PHASE Importation
Trees after Importation
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..033) i
BB02 [0001] 1 BB01 1 [033..061)-> BB04 (always) i
BB03 [0002] 0 1 [061..093)
BB04 [0003] 2 BB02,BB03 1 [093..0BB) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..033), preds={} succs={BB02}
***** BB01
STMT00000 ( 0x000[E-] ... 0x00D )
[000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
[000003] ----------- \--* HWINTRINSIC simd16 ubyte And
[000000] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000002] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00001 ( 0x00E[E-] ... 0x02B )
[000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000010] ----------- \--* HWINTRINSIC simd16 ubyte And
[000007] ----------- +--* HWINTRINSIC simd16 int ShiftRightLogical
[000005] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000006] ----------- | \--* CNS_INT int 4
[000009] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
------------ BB02 [033..061) -> BB04 (always), preds={BB01} succs={BB04}
***** BB02
STMT00002 ( 0x033[E-] ... 0x04E )
[000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
[000020] ----------- \--* HWINTRINSIC simd16 ubyte Or
[000018] ----------- +--* HWINTRINSIC simd16 ubyte And
[000015] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000017] ----------- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808>
[000019] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
***** BB02
STMT00003 ( 0x050[E-] ... 0x05E )
[000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1
[000024] ----------- \--* CNS_INT int 0
***** BB02
STMT00004 ( ??? ... ??? )
[000027] I-C-G------ * CALL void System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:.ctor(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):this (exactContextHnd=0x0xd1ffab1e)
[000026] ----------- this +--* LCL_ADDR byref V11 tmp1 [+0]
[000022] ----------- arg1 +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1
[000023] ----------- arg2 \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2
***** BB02
STMT00005 ( 0x057[--] ... ??? )
[000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000033] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000030] -c--------- +--* FIELD_LIST struct
[000031] ----------- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 [+0]
[000032] ----------- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 [+16]
[000029] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
------------ BB03 [061..093), preds={} succs={BB04}
------------ BB04 [093..0BB) (return), preds={BB02,BB03} succs={}
***** BB04
STMT00006 ( 0x093[E-] ... 0x0AC )
[000038] I-C-G------ * CALL simd16 System.Text.Tests.Demo:ShuffleUnsafe(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte] (exactContextHnd=0x0xd1ffab1e)
[000036] ----------- arg0 +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] ----------- arg1 \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
***** BB04
STMT00007 ( 0x093[E-] ... ??? )
[000040] DAC-------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000039] --C-------- \--* RET_EXPR simd16(for [000038])
***** BB04
STMT00008 ( 0x0AD[E-] ... 0x0BA )
[000046] ----------- * RETURN simd16
[000045] ----------- \--* HWINTRINSIC simd16 ubyte CompareEqual
[000043] ----------- +--* HWINTRINSIC simd16 ubyte And
[000041] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000042] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000044] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid
*************** Starting PHASE Expand patchpoints
-- no patchpoints to transform
*************** Finishing PHASE Expand patchpoints [no changes]
*************** Starting PHASE Indirect call transform
-- no candidates to transform
*************** Finishing PHASE Indirect call transform [no changes]
*************** Starting PHASE Post-import
BB03 was not imported, marking as removed (0)
Renumbering the basic blocks for fgPostImportationCleanup
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..033) i
BB02 [0001] 1 BB01 1 [033..061)-> BB04 (always) i
BB04 [0003] 1 BB02 1 [093..0BB) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
Renumber BB04 to BB03
*************** After renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..033) i
BB02 [0001] 1 BB01 1 [033..061)-> BB03 (always) i
BB03 [0003] 1 BB02 1 [093..0BB) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
New BlockSet epoch 1, # of blocks (including unused BB00): 4, bitset array size: 1 (short)
*************** Finishing PHASE Post-import
Trees after Post-import
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..033) i
BB02 [0001] 1 BB01 1 [033..061)-> BB03 (always) i
BB03 [0003] 1 BB02 1 [093..0BB) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..033), preds={} succs={BB02}
***** BB01
STMT00000 ( 0x000[E-] ... 0x00D )
[000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
[000003] ----------- \--* HWINTRINSIC simd16 ubyte And
[000000] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000002] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00001 ( 0x00E[E-] ... 0x02B )
[000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000010] ----------- \--* HWINTRINSIC simd16 ubyte And
[000007] ----------- +--* HWINTRINSIC simd16 int ShiftRightLogical
[000005] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000006] ----------- | \--* CNS_INT int 4
[000009] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
------------ BB02 [033..061) -> BB03 (always), preds={BB01} succs={BB03}
***** BB02
STMT00002 ( 0x033[E-] ... 0x04E )
[000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
[000020] ----------- \--* HWINTRINSIC simd16 ubyte Or
[000018] ----------- +--* HWINTRINSIC simd16 ubyte And
[000015] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000017] ----------- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808>
[000019] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
***** BB02
STMT00003 ( 0x050[E-] ... 0x05E )
[000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1
[000024] ----------- \--* CNS_INT int 0
***** BB02
STMT00004 ( ??? ... ??? )
[000027] I-C-G------ * CALL void System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:.ctor(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):this (exactContextHnd=0x0xd1ffab1e)
[000026] ----------- this +--* LCL_ADDR byref V11 tmp1 [+0]
[000022] ----------- arg1 +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1
[000023] ----------- arg2 \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2
***** BB02
STMT00005 ( 0x057[--] ... ??? )
[000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000033] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000030] -c--------- +--* FIELD_LIST struct
[000031] ----------- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 [+0]
[000032] ----------- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 [+16]
[000029] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
------------ BB03 [093..0BB) (return), preds={BB02} succs={}
***** BB03
STMT00006 ( 0x093[E-] ... 0x0AC )
[000038] I-C-G------ * CALL simd16 System.Text.Tests.Demo:ShuffleUnsafe(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte] (exactContextHnd=0x0xd1ffab1e)
[000036] ----------- arg0 +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] ----------- arg1 \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
***** BB03
STMT00007 ( 0x093[E-] ... ??? )
[000040] DAC-------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000039] --C-------- \--* RET_EXPR simd16(for [000038])
***** BB03
STMT00008 ( 0x0AD[E-] ... 0x0BA )
[000046] ----------- * RETURN simd16
[000045] ----------- \--* HWINTRINSIC simd16 ubyte CompareEqual
[000043] ----------- +--* HWINTRINSIC simd16 ubyte And
[000041] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000042] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000044] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid
*************** Starting PHASE Morph - Init
New BlockSet epoch 2, # of blocks (including unused BB00): 4, bitset array size: 1 (short)
*************** Finishing PHASE Morph - Init [no changes]
*************** Starting PHASE Morph - Inlining
Expanding INLINE_CANDIDATE in statement STMT00004 in BB02:
STMT00004 ( ??? ... ??? )
[000027] I-C-G------ * CALL void System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:.ctor(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):this (exactContextHnd=0x0xd1ffab1e)
[000026] ----------- this +--* LCL_ADDR byref V11 tmp1 [+0]
[000022] ----------- arg1 +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1
[000023] ----------- arg2 \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2
thisArg: is a constant or invariant is byref to a struct local
[000026] ----------- * LCL_ADDR byref V11 tmp1 [+0]
Argument #1: is a local var
[000022] ----------- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1
Argument #2: is a local var
[000023] ----------- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2
INLINER: inlineInfo.tokenLookupContextHandle for System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:.ctor(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):this set to 0x0xd1ffab1e:
Invoking compiler for the inlinee method System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:.ctor(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):this :
IL to import:
IL_0000 02 ldarg.0
IL_0001 03 ldarg.1
IL_0002 7d f8 0c 00 0a stfld 0xA000CF8
IL_0007 02 ldarg.0
IL_0008 04 ldarg.2
IL_0009 7d f9 0c 00 0a stfld 0xA000CF9
IL_000e 2a ret
INLINER impTokenLookupContextHandle for System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:.ctor(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):this is 0x0xd1ffab1e.
*************** In compInitDebuggingInfo() for System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:.ctor(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):this
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:.ctor(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):this
Jump targets:
none
New Basic Block BB01 [0004] created.
BB01 [000..00F)
Basic block list for 'System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:.ctor(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):this'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0004] 1 100 [000..00F) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Inline @[000027] Starting PHASE Pre-import
*************** Inline @[000027] Finishing PHASE Pre-import
Trees after Pre-import
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0004] 1 100 [000..00F) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..00F) (return), preds={} succs={}
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Inline @[000027] Starting PHASE Profile incorporation
Have Static PGO: 2 schema records (schema at 0xd1ffab1e, data at 0xd1ffab1e)
Profile summary: 10 runs, 0 block probes, 1 edge probes, 0 class profiles, 0 method profiles, 0 other records
Reconstructing block counts from sparse edge instrumentation
... adding known edge BB01 -> BB01: weight 4651
New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)
... pseudo edge BB01 -> BB01
Solver: 1 blocks, 1 unknown; 1 edges, 0 unknown, 0 zero
Pass [1]: 1 unknown blocks, 0 unknown edges
BB01: 0 incoming unknown, 0 outgoing unknown
BB01: all incoming edge weights known, summing...
BB01 -> BB01 has weight 4651
BB01: all incoming edge weights known, sum is 4651
Solver: converged in 1 passes
Computing inlinee profile scale:
... call site not profiled, will use non-pgo weight to scale
call site count 100 callee entry count 4651 scale 0.02150075
Scaling inlinee blocks
*************** Inline @[000027] Finishing PHASE Profile incorporation
Trees after Profile incorporation
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0004] 1 100 100 [000..00F) (return) IBC
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..00F) (return), preds={} succs={}
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Inline @[000027] Starting PHASE Importation
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:.ctor(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):this'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) ldarg.1
[ 2] 2 (0x002) stfld 0A000CF8
STMT00009 ( 0x000[E-] ... ??? ) <- INLRT @ ???
[000049] nA--------- * STOREIND simd16 (copy)
[000048] ----------- +--* FIELD_ADDR byref System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:Item1
[000047] ----------- | \--* LCL_ADDR byref V11 tmp1 [+0]
[000022] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1
[ 0] 7 (0x007) ldarg.0
[ 1] 8 (0x008) ldarg.2
[ 2] 9 (0x009) stfld 0A000CF9
STMT00010 ( 0x007[E-] ... ??? ) <- INLRT @ ???
[000052] nA--------- * STOREIND simd16 (copy)
[000051] ----------- +--* FIELD_ADDR byref System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:Item2
[000050] ----------- | \--* LCL_ADDR byref V11 tmp1 [+0]
[000023] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2
[ 0] 14 (0x00e) ret
*************** Inline @[000027] Finishing PHASE Importation
Trees after Importation
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0004] 1 100 100 [000..00F) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..00F) (return), preds={} succs={}
***** BB01
STMT00009 ( 0x000[E-] ... ??? ) <- INLRT @ ???
[000049] nA--------- * STOREIND simd16 (copy)
[000048] ----------- +--* FIELD_ADDR byref System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:Item1
[000047] ----------- | \--* LCL_ADDR byref V11 tmp1 [+0]
[000022] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1
***** BB01
STMT00010 ( 0x007[E-] ... ??? ) <- INLRT @ ???
[000052] nA--------- * STOREIND simd16 (copy)
[000051] ----------- +--* FIELD_ADDR byref System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:Item2
[000050] ----------- | \--* LCL_ADDR byref V11 tmp1 [+0]
[000023] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid
*************** Inline @[000027] Starting PHASE Expand patchpoints
-- no patchpoints to transform
*************** Inline @[000027] Finishing PHASE Expand patchpoints [no changes]
*************** Inline @[000027] Starting PHASE Indirect call transform
-- no candidates to transform
*************** Inline @[000027] Finishing PHASE Indirect call transform [no changes]
*************** Inline @[000027] Starting PHASE Post-import
*************** Inline @[000027] Finishing PHASE Post-import [no changes]
----------- Statements (and blocks) added due to the inlining of call [000027] -----------
Arguments setup:
Inlinee method body:
STMT00009 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
[000049] nA--------- * STOREIND simd16 (copy)
[000048] ----------- +--* FIELD_ADDR byref System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:Item1
[000047] ----------- | \--* LCL_ADDR byref V11 tmp1 [+0]
[000022] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1
STMT00010 ( INL01 @ 0x007[E-] ... ??? ) <- INLRT @ ???
[000052] nA--------- * STOREIND simd16 (copy)
[000051] ----------- +--* FIELD_ADDR byref System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:Item2
[000050] ----------- | \--* LCL_ADDR byref V11 tmp1 [+0]
[000023] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2
fgInlineAppendStatements: no gc ref inline locals.
Successfully inlined System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:.ctor(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):this (15 IL bytes) (depth 1) [below ALWAYS_INLINE size]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Text.Tests.Demo:IndexOfAnyLookupCombined(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]' calling 'System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:.ctor(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):this'
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size'
Expanding INLINE_CANDIDATE in statement STMT00006 in BB03:
STMT00006 ( 0x093[E-] ... 0x0AC )
[000038] I-C-G------ * CALL simd16 System.Text.Tests.Demo:ShuffleUnsafe(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte] (exactContextHnd=0x0xd1ffab1e)
[000036] ----------- arg0 +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] ----------- arg1 \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
Argument #0: is a constant or invariant
[000036] ----------- * CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
Argument #1: is a local var
[000037] ----------- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
INLINER: inlineInfo.tokenLookupContextHandle for System.Text.Tests.Demo:ShuffleUnsafe(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte] set to 0x0xd1ffab1e:
Invoking compiler for the inlinee method System.Text.Tests.Demo:ShuffleUnsafe(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte] :
IL to import:
IL_0000 28 22 00 00 0a call 0xA000022
IL_0005 2c 08 brfalse.s 8 (IL_000f)
IL_0007 02 ldarg.0
IL_0008 03 ldarg.1
IL_0009 28 23 00 00 0a call 0xA000023
IL_000e 2a ret
IL_000f 28 1d 00 00 0a call 0xA00001D
IL_0014 2c 08 brfalse.s 8 (IL_001e)
IL_0016 02 ldarg.0
IL_0017 03 ldarg.1
IL_0018 28 24 00 00 0a call 0xA000024
IL_001d 2a ret
IL_001e 02 ldarg.0
IL_001f 03 ldarg.1
IL_0020 28 25 00 00 0a call 0xA000025
IL_0025 2a ret
INLINER impTokenLookupContextHandle for System.Text.Tests.Demo:ShuffleUnsafe(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte] is 0x0xd1ffab1e.
Notify VM instruction set (AdvSimd) must be supported.
Found Vector128<ubyte>
*************** In compInitDebuggingInfo() for System.Text.Tests.Demo:ShuffleUnsafe(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for System.Text.Tests.Demo:ShuffleUnsafe(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]
Named Intrinsic System.Runtime.Intrinsics.X86.Ssse3.get_IsSupported: Unsupported - return falseweight= 79 : state 40 [ call ]
weight= 27 : state 44 [ brfalse.s ]
weight= 10 : state 3 [ ldarg.0 ]
weight= 16 : state 4 [ ldarg.1 ]
weight= 79 : state 40 [ call ]
Named Intrinsic System.Runtime.Intrinsics.Arm.AdvSimd.Arm64.get_IsSupported: Notify VM instruction set (AdvSimd_Arm64) must be supported.
Recognized
weight= 19 : state 42 [ ret ]
weight= 79 : state 40 [ call ]
weight= 27 : state 44 [ brfalse.s ]
Named Intrinsic System.Runtime.Intrinsics.Arm.AdvSimd.Arm64.VectorTableLookup: Recognized
weight= 10 : state 3 [ ldarg.0 ]
weight= 16 : state 4 [ ldarg.1 ]
weight= 79 : state 40 [ call ]
weight= 19 : state 42 [ ret ]
Named Intrinsic System.Runtime.Intrinsics.Vector128.Shuffle: Notify VM instruction set (Vector128) must be supported.
Recognized
weight= 10 : state 3 [ ldarg.0 ]
weight= 16 : state 4 [ ldarg.1 ]
weight= 79 : state 40 [ call ]
weight= 19 : state 42 [ ret ]
Inline candidate returns a struct by value. Multiplier increased to 2.
Inline candidate looks like a wrapper method. Multiplier increased to 3.
Inline candidate has 2 foldable branches. Multiplier increased to 8.
Inline candidate has SIMD type args, locals or return value. Multiplier increased to 11.
Inline has 2 intrinsics. Multiplier increased to 12.6.
Inline has 2 foldable intrinsics. Multiplier increased to 15.6.
Inline candidate callsite is boring. Multiplier increased to 16.9.
calleeNativeSizeEstimate=584
callsiteNativeSizeEstimate=155
benefit multiplier=16.9
threshold=2619
Native estimate for function size is within threshold for inlining 58.4 <= 261.9 (multiplier = 16.9)
Jump targets:
IL_000f
IL_001e
New Basic Block BB01 [0005] created.
BB01 [000..007)
New Basic Block BB02 [0006] created.
BB02 [007..00F)
New Basic Block BB03 [0007] created.
BB03 [00F..016)
New Basic Block BB04 [0008] created.
BB04 [016..01E)
New Basic Block BB05 [0009] created.
BB05 [01E..026)
Setting edge weights for BB01 -> BB03 to [0 .. 3.402823e+38]
Setting edge weights for BB01 -> BB02 to [0 .. 3.402823e+38]
Setting edge weights for BB03 -> BB05 to [0 .. 3.402823e+38]
Setting edge weights for BB03 -> BB04 to [0 .. 3.402823e+38]
lvaGrabTemp returning 12 (V12 tmp2) (a long lifetime temp) called for Inline return value spill temp.
Basic block list for 'System.Text.Tests.Demo:ShuffleUnsafe(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [000..007)-> BB03 ( cond )
BB02 [0006] 1 BB01 1 [007..00F) (return)
BB03 [0007] 1 BB01 1 [00F..016)-> BB05 ( cond )
BB04 [0008] 1 BB03 1 [016..01E) (return)
BB05 [0009] 1 BB03 1 [01E..026) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Inline @[000038] Starting PHASE Pre-import
*************** Inline @[000038] Finishing PHASE Pre-import
Trees after Pre-import
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [000..007)-> BB03 ( cond )
BB02 [0006] 1 BB01 1 [007..00F) (return)
BB03 [0007] 1 BB01 1 [00F..016)-> BB05 ( cond )
BB04 [0008] 1 BB03 1 [016..01E) (return)
BB05 [0009] 1 BB03 1 [01E..026) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..007) -> BB03 (cond), preds={} succs={BB02,BB03}
------------ BB02 [007..00F) (return), preds={BB01} succs={}
------------ BB03 [00F..016) -> BB05 (cond), preds={BB01} succs={BB04,BB05}
------------ BB04 [016..01E) (return), preds={BB03} succs={}
------------ BB05 [01E..026) (return), preds={BB03} succs={}
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Inline @[000038] Starting PHASE Profile incorporation
BBOPT set, but no profile data available (hr=80004001)
Computing inlinee profile scale:
... no callee profile data, will use non-pgo weight to scale
... call site not profiled, will use non-pgo weight to scale
call site count 100 callee entry count 100 scale 1
Scaling inlinee blocks
*************** Inline @[000038] Finishing PHASE Profile incorporation
Trees after Profile incorporation
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [000..007)-> BB03 ( cond )
BB02 [0006] 1 BB01 1 [007..00F) (return)
BB03 [0007] 1 BB01 1 [00F..016)-> BB05 ( cond )
BB04 [0008] 1 BB03 1 [016..01E) (return)
BB05 [0009] 1 BB03 1 [01E..026) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..007) -> BB03 (cond), preds={} succs={BB02,BB03}
------------ BB02 [007..00F) (return), preds={BB01} succs={}
------------ BB03 [00F..016) -> BB05 (cond), preds={BB01} succs={BB04,BB05}
------------ BB04 [016..01E) (return), preds={BB03} succs={}
------------ BB05 [01E..026) (return), preds={BB03} succs={}
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Inline @[000038] Starting PHASE Importation
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'System.Text.Tests.Demo:ShuffleUnsafe(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]'
[ 0] 0 (0x000) call 0A000022
In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0
Named Intrinsic System.Runtime.Intrinsics.X86.Ssse3.get_IsSupported: Unsupported - return false
[ 1] 5 (0x005) brfalse.s
Folding operator with constant nodes into a constant:
[000056] ----------- * EQ int
[000054] ----------- +--* CNS_INT int 0
[000055] ----------- \--* CNS_INT int 0
Bashed to int constant:
[000056] ----------- * CNS_INT int 1
The conditional jump becomes an unconditional jump to BB03
impImportBlockPending for BB03
Importing BB03 (PC=015) of 'System.Text.Tests.Demo:ShuffleUnsafe(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]'
[ 0] 15 (0x00f) call 0A00001D
In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0
Named Intrinsic System.Runtime.Intrinsics.Arm.AdvSimd.Arm64.get_IsSupported: Recognized
[ 1] 20 (0x014) brfalse.s
Folding operator with constant nodes into a constant:
[000059] ----------- * EQ int
[000057] ----------- +--* CNS_INT int 1
[000058] ----------- \--* CNS_INT int 0
Bashed to int constant:
[000059] ----------- * CNS_INT int 0
The block falls through into the next BB04
impImportBlockPending for BB04
Importing BB04 (PC=022) of 'System.Text.Tests.Demo:ShuffleUnsafe(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]'
[ 0] 22 (0x016) ldarg.0
[ 1] 23 (0x017) ldarg.1
[ 2] 24 (0x018) call 0A000024
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Arm.AdvSimd.Arm64.VectorTableLookup: Recognized
Found Vector128<ubyte>
Found Vector128<ubyte>
[ 1] 29 (0x01d) ret
Inlinee Return expression (before normalization) =>
[000061] ----------- * HWINTRINSIC simd16 ubyte VectorTableLookup
[000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
Found Vector128<ubyte>
impFixupStructReturnType: retyping
[000061] ----------- * HWINTRINSIC simd16 ubyte VectorTableLookup
[000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
STMT00011 ( 0x016[E-] ... ??? ) <- INLRT @ 0x093[E-]
[000062] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V12 tmp2
[000061] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
Inlinee Return expression (after normalization) =>
[000063] ----------- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V12 tmp2
** Note: inlinee IL was partially imported -- imported 8 of 38 bytes of method IL
*************** Inline @[000038] Finishing PHASE Importation
Trees after Importation
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [000..007)-> BB03 (always) i
BB02 [0006] 0 1 [007..00F) (return)
BB03 [0007] 1 BB01 1 [00F..016) i
BB04 [0008] 1 BB03 1 [016..01E) (return) i
BB05 [0009] 0 1 [01E..026) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..007) -> BB03 (always), preds={} succs={BB03}
------------ BB02 [007..00F) (return), preds={} succs={}
------------ BB03 [00F..016), preds={BB01} succs={BB04}
------------ BB04 [016..01E) (return), preds={BB03} succs={}
***** BB04
STMT00011 ( 0x016[E-] ... ??? ) <- INLRT @ 0x093[E-]
[000062] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V12 tmp2
[000061] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
------------ BB05 [01E..026) (return), preds={} succs={}
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid
*************** Inline @[000038] Starting PHASE Expand patchpoints
-- no patchpoints to transform
*************** Inline @[000038] Finishing PHASE Expand patchpoints [no changes]
*************** Inline @[000038] Starting PHASE Indirect call transform
-- no candidates to transform
*************** Inline @[000038] Finishing PHASE Indirect call transform [no changes]
*************** Inline @[000038] Starting PHASE Post-import
BB02 was not imported, marking as removed (0)
BB05 was not imported, marking as removed (1)
Renumbering the basic blocks for fgPostImportationCleanup
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [000..007)-> BB03 (always) i
BB03 [0007] 1 BB01 1 [00F..016) i
BB04 [0008] 1 BB03 1 [016..01E) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
Renumber BB03 to BB02
Renumber BB04 to BB03
*************** After renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [000..007)-> BB02 (always) i
BB02 [0007] 1 BB01 1 [00F..016) i
BB03 [0008] 1 BB02 1 [016..01E) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
New BlockSet epoch 1, # of blocks (including unused BB00): 4, bitset array size: 1 (short)
*************** Inline @[000038] Finishing PHASE Post-import
Trees after Post-import
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [000..007)-> BB02 (always) i
BB02 [0007] 1 BB01 1 [00F..016) i
BB03 [0008] 1 BB02 1 [016..01E) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..007) -> BB02 (always), preds={} succs={BB02}
------------ BB02 [00F..016), preds={BB01} succs={BB03}
------------ BB03 [016..01E) (return), preds={BB02} succs={}
***** BB03
STMT00011 ( 0x016[E-] ... ??? ) <- INLRT @ 0x093[E-]
[000062] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V12 tmp2
[000061] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid
----------- Statements (and blocks) added due to the inlining of call [000038] -----------
Arguments setup:
Inlinee method body:New Basic Block BB04 [0010] created.
Setting edge weights for BB03 -> BB04 to [0 .. 3.402823e+38]
Convert bbJumpKind of BB07 to BBJ_NONE
Setting edge weights for BB07 -> BB04 to [0 .. 3.402823e+38]
Setting edge weights for BB03 -> BB05 to [0 .. 3.402823e+38]
fgInlineAppendStatements: no gc ref inline locals.
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB05 [0005] 1 BB03 1 [093..094)-> BB06 (always) i
BB06 [0007] 1 BB05 1 [093..094) i
BB07 [0008] 1 BB06 1 [093..094) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB05 [093..094) -> BB06 (always), preds={BB03} succs={BB06}
------------ BB06 [093..094), preds={BB05} succs={BB07}
------------ BB07 [093..094), preds={BB06} succs={BB04}
***** BB07
STMT00011 ( INL02 @ 0x016[E-] ... ??? ) <- INLRT @ 0x093[E-]
[000062] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V12 tmp2
[000061] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
-------------------------------------------------------------------------------------------------------------------
Successfully inlined System.Text.Tests.Demo:ShuffleUnsafe(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte] (38 IL bytes) (depth 1) [profitable inline]
--------------------------------------------------------------------------------------------
BB03 becomes empty
INLINER: during 'fgInline' result 'success' reason 'profitable inline' for 'System.Text.Tests.Demo:IndexOfAnyLookupCombined(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]' calling 'System.Text.Tests.Demo:ShuffleUnsafe(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]'
INLINER: during 'fgInline' result 'success' reason 'profitable inline'
Replacing the return expression placeholder [000039] with [000063]
[000039] --C-------- * RET_EXPR simd16(for [000038]) -> [000063]
Inserting the inline return expression
[000063] ----------- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V12 tmp2
**************** Inline Tree
Inlines into 06000007 [via ExtendedDefaultPolicy] System.Text.Tests.Demo:IndexOfAnyLookupCombined(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]:
[INL01 IL=0082 TR=000027 060026A7] [INLINED: callee: below ALWAYS_INLINE size] System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:.ctor(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):this
[INL02 IL=0167 TR=000038 06000008] [INLINED: call site: profitable inline] System.Text.Tests.Demo:ShuffleUnsafe(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]
Budget: initialTime=621, finalTime=639, initialBudget=6210, currentBudget=6210
Budget: initialSize=4394, finalSize=4823
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..033) i
BB02 [0001] 1 BB01 1 100 [033..061)-> BB03 (always) i IBC
BB03 [0003] 1 BB02 1 [093..093) i
BB05 [0005] 1 BB03 1 [093..094)-> BB06 (always) i
BB06 [0007] 1 BB05 1 [093..094) i
BB07 [0008] 1 BB06 1 [093..094) i
BB04 [0010] 1 BB07 1 [093..0BB) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
Renumber BB05 to BB04
Renumber BB06 to BB05
Renumber BB07 to BB06
Renumber BB04 to BB07
*************** After renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..033) i
BB02 [0001] 1 BB01 1 100 [033..061)-> BB03 (always) i IBC
BB03 [0003] 1 BB02 1 [093..093) i
BB04 [0005] 1 BB03 1 [093..094)-> BB05 (always) i
BB05 [0007] 1 BB04 1 [093..094) i
BB06 [0008] 1 BB05 1 [093..094) i
BB07 [0010] 1 BB06 1 [093..0BB) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
New BlockSet epoch 3, # of blocks (including unused BB00): 8, bitset array size: 1 (short)
*************** Finishing PHASE Morph - Inlining
Trees after Morph - Inlining
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..033) i
BB02 [0001] 1 BB01 1 100 [033..061)-> BB03 (always) i IBC
BB03 [0003] 1 BB02 1 [093..093) i
BB04 [0005] 1 BB03 1 [093..094)-> BB05 (always) i
BB05 [0007] 1 BB04 1 [093..094) i
BB06 [0008] 1 BB05 1 [093..094) i
BB07 [0010] 1 BB06 1 [093..0BB) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..033), preds={} succs={BB02}
***** BB01
STMT00000 ( 0x000[E-] ... 0x00D )
[000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
[000003] ----------- \--* HWINTRINSIC simd16 ubyte And
[000000] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000002] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00001 ( 0x00E[E-] ... 0x02B )
[000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000010] ----------- \--* HWINTRINSIC simd16 ubyte And
[000007] ----------- +--* HWINTRINSIC simd16 int ShiftRightLogical
[000005] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000006] ----------- | \--* CNS_INT int 4
[000009] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
------------ BB02 [033..061) -> BB03 (always), preds={BB01} succs={BB03}
***** BB02
STMT00002 ( 0x033[E-] ... 0x04E )
[000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
[000020] ----------- \--* HWINTRINSIC simd16 ubyte Or
[000018] ----------- +--* HWINTRINSIC simd16 ubyte And
[000015] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000017] ----------- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808>
[000019] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
***** BB02
STMT00003 ( 0x050[E-] ... 0x05E )
[000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1
[000024] ----------- \--* CNS_INT int 0
***** BB02
STMT00009 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
[000049] nA--------- * STOREIND simd16 (copy)
[000048] ----------- +--* FIELD_ADDR byref System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:Item1
[000047] ----------- | \--* LCL_ADDR byref V11 tmp1 [+0]
[000022] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1
***** BB02
STMT00010 ( INL01 @ 0x007[E-] ... ??? ) <- INLRT @ ???
[000052] nA--------- * STOREIND simd16 (copy)
[000051] ----------- +--* FIELD_ADDR byref System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:Item2
[000050] ----------- | \--* LCL_ADDR byref V11 tmp1 [+0]
[000023] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2
***** BB02
STMT00005 ( 0x057[--] ... ??? )
[000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000033] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000030] -c--------- +--* FIELD_LIST struct
[000031] ----------- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 [+0]
[000032] ----------- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 [+16]
[000029] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
------------ BB03 [093..093), preds={BB02} succs={BB04}
------------ BB04 [093..094) -> BB05 (always), preds={BB03} succs={BB05}
------------ BB05 [093..094), preds={BB04} succs={BB06}
------------ BB06 [093..094), preds={BB05} succs={BB07}
***** BB06
STMT00011 ( INL02 @ 0x016[E-] ... ??? ) <- INLRT @ 0x093[E-]
[000062] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V12 tmp2
[000061] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
------------ BB07 [093..0BB) (return), preds={BB06} succs={}
***** BB07
STMT00007 ( 0x093[E-] ... ??? )
[000040] DAC-------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000063] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V12 tmp2
***** BB07
STMT00008 ( 0x0AD[E-] ... 0x0BA )
[000046] ----------- * RETURN simd16
[000045] ----------- \--* HWINTRINSIC simd16 ubyte CompareEqual
[000043] ----------- +--* HWINTRINSIC simd16 ubyte And
[000041] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000042] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000044] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid
*************** Starting PHASE Allocate Objects
no newobjs in this method; punting
*************** Finishing PHASE Allocate Objects [no changes]
*************** Starting PHASE Morph - Add internal blocks
*************** After fgAddInternal()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..033) i
BB02 [0001] 1 BB01 1 100 [033..061)-> BB03 (always) i IBC
BB03 [0003] 1 BB02 1 [093..093) i
BB04 [0005] 1 BB03 1 [093..094)-> BB05 (always) i
BB05 [0007] 1 BB04 1 [093..094) i
BB06 [0008] 1 BB05 1 [093..094) i
BB07 [0010] 1 BB06 1 [093..0BB) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** Finishing PHASE Morph - Add internal blocks [no changes]
*************** Starting PHASE Remove empty try
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try [no changes]
*************** Starting PHASE Remove empty finally
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally [no changes]
*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.
*************** Finishing PHASE Merge callfinally chains [no changes]
*************** Starting PHASE Clone finally
No EH in this method, no cloning.
*************** Finishing PHASE Clone finally [no changes]
*************** Starting PHASE Tail merge
*************** Finishing PHASE Tail merge [no changes]
*************** Starting PHASE Merge throw blocks
*************** In fgTailMergeThrows
Method does not have multiple noreturn calls.
*************** Finishing PHASE Merge throw blocks [no changes]
*************** Starting PHASE Update flow graph early pass
Compacting BB02 into BB01:
*************** In fgDebugCheckBBlist
Removing unconditional jump to next block (BB01 -> BB03) (converted BB01 to fall-through)
Compacting BB03 into BB01:
*************** In fgDebugCheckBBlist
Compacting BB04 into BB01:
*************** In fgDebugCheckBBlist
Removing unconditional jump to next block (BB01 -> BB05) (converted BB01 to fall-through)
Compacting BB05 into BB01:
*************** In fgDebugCheckBBlist
Compacting BB06 into BB01:
*************** In fgDebugCheckBBlist
Compacting BB07 into BB01:
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Update flow graph early pass
Trees after Update flow graph early pass
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..0BB) (return), preds={} succs={}
***** BB01
STMT00000 ( 0x000[E-] ... 0x00D )
[000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
[000003] ----------- \--* HWINTRINSIC simd16 ubyte And
[000000] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000002] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00001 ( 0x00E[E-] ... 0x02B )
[000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000010] ----------- \--* HWINTRINSIC simd16 ubyte And
[000007] ----------- +--* HWINTRINSIC simd16 int ShiftRightLogical
[000005] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000006] ----------- | \--* CNS_INT int 4
[000009] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00002 ( 0x033[E-] ... 0x04E )
[000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
[000020] ----------- \--* HWINTRINSIC simd16 ubyte Or
[000018] ----------- +--* HWINTRINSIC simd16 ubyte And
[000015] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000017] ----------- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808>
[000019] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
***** BB01
STMT00003 ( 0x050[E-] ... 0x05E )
[000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1
[000024] ----------- \--* CNS_INT int 0
***** BB01
STMT00009 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
[000049] nA--------- * STOREIND simd16 (copy)
[000048] ----------- +--* FIELD_ADDR byref System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:Item1
[000047] ----------- | \--* LCL_ADDR byref V11 tmp1 [+0]
[000022] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1
***** BB01
STMT00010 ( INL01 @ 0x007[E-] ... ??? ) <- INLRT @ ???
[000052] nA--------- * STOREIND simd16 (copy)
[000051] ----------- +--* FIELD_ADDR byref System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:Item2
[000050] ----------- | \--* LCL_ADDR byref V11 tmp1 [+0]
[000023] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2
***** BB01
STMT00005 ( 0x057[--] ... ??? )
[000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000033] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000030] -c--------- +--* FIELD_LIST struct
[000031] ----------- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 [+0]
[000032] ----------- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 [+16]
[000029] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
***** BB01
STMT00011 ( INL02 @ 0x016[E-] ... ??? ) <- INLRT @ 0x093[E-]
[000062] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V12 tmp2
[000061] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
***** BB01
STMT00007 ( 0x093[E-] ... ??? )
[000040] DAC-------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000063] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V12 tmp2
***** BB01
STMT00008 ( 0x0AD[E-] ... 0x0BA )
[000046] ----------- * RETURN simd16
[000045] ----------- \--* HWINTRINSIC simd16 ubyte CompareEqual
[000043] ----------- +--* HWINTRINSIC simd16 ubyte And
[000041] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000042] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000044] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid
*************** Starting PHASE Morph - Promote Structs
lvaTable before fgPromoteStructs
; Initial local variable assignments
;
; V00 arg0 simd16 HFA(simd16)
; V01 arg1 simd16 HFA(simd16)
; V02 arg2 simd16 HFA(simd16)
; V03 loc0 simd16 HFA(simd16)
; V04 loc1 simd16 HFA(simd16)
; V05 loc2 simd16 HFA(simd16)
; V06 loc3 simd16 HFA(simd16)
; V07 loc4 simd16 HFA(simd16)
; V08 loc5 simd16 HFA(simd16)
; V09 loc6 simd16 HFA(simd16)
; V10 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
; V11 tmp1 struct <System.ValueTuple`2, 32> HFA(simd16) ld-addr-op "NewObj constructor temp"
; V12 tmp2 simd16 HFA(simd16) "Inline return value spill temp"
struct promotion of V10 is disabled because it has already been marked address exposed
*************** Finishing PHASE Morph - Promote Structs [no changes]
*************** Starting PHASE Morph - Structs/AddrExp
LocalAddressVisitor visiting statement:
STMT00000 ( 0x000[E-] ... 0x00D )
[000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
[000003] ----------- \--* HWINTRINSIC simd16 ubyte And
[000000] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000002] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
LocalAddressVisitor visiting statement:
STMT00001 ( 0x00E[E-] ... 0x02B )
[000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000010] ----------- \--* HWINTRINSIC simd16 ubyte And
[000007] ----------- +--* HWINTRINSIC simd16 int ShiftRightLogical
[000005] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000006] ----------- | \--* CNS_INT int 4
[000009] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
LocalAddressVisitor visiting statement:
STMT00002 ( 0x033[E-] ... 0x04E )
[000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
[000020] ----------- \--* HWINTRINSIC simd16 ubyte Or
[000018] ----------- +--* HWINTRINSIC simd16 ubyte And
[000015] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000017] ----------- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808>
[000019] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
LocalAddressVisitor visiting statement:
STMT00003 ( 0x050[E-] ... 0x05E )
[000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1
[000024] ----------- \--* CNS_INT int 0
LocalAddressVisitor visiting statement:
STMT00009 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
[000049] nA--------- * STOREIND simd16 (copy)
[000048] ----------- +--* FIELD_ADDR byref System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:Item1
[000047] ----------- | \--* LCL_ADDR byref V11 tmp1 [+0]
[000022] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1
Local V11 should not be enregistered because: was accessed as a local field
LocalAddressVisitor modified statement:
STMT00009 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
[000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 [+0]
[000022] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1
LocalAddressVisitor visiting statement:
STMT00010 ( INL01 @ 0x007[E-] ... ??? ) <- INLRT @ ???
[000052] nA--------- * STOREIND simd16 (copy)
[000051] ----------- +--* FIELD_ADDR byref System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:Item2
[000050] ----------- | \--* LCL_ADDR byref V11 tmp1 [+0]
[000023] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2
Local V11 should not be enregistered because: was accessed as a local field
LocalAddressVisitor modified statement:
STMT00010 ( INL01 @ 0x007[E-] ... ??? ) <- INLRT @ ???
[000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 [+16]
[000023] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2
LocalAddressVisitor visiting statement:
STMT00005 ( 0x057[--] ... ??? )
[000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000033] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000030] -c--------- +--* FIELD_LIST struct
[000031] ----------- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 [+0]
[000032] ----------- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 [+16]
[000029] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
Local V11 should not be enregistered because: was accessed as a local field
Local V11 should not be enregistered because: was accessed as a local field
LocalAddressVisitor visiting statement:
STMT00011 ( INL02 @ 0x016[E-] ... ??? ) <- INLRT @ 0x093[E-]
[000062] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V12 tmp2
[000061] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
LocalAddressVisitor visiting statement:
STMT00007 ( 0x093[E-] ... ??? )
[000040] DAC-------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000063] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V12 tmp2
LocalAddressVisitor visiting statement:
STMT00008 ( 0x0AD[E-] ... 0x0BA )
[000046] ----------- * RETURN simd16
[000045] ----------- \--* HWINTRINSIC simd16 ubyte CompareEqual
[000043] ----------- +--* HWINTRINSIC simd16 ubyte And
[000041] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000042] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000044] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
*************** Finishing PHASE Morph - Structs/AddrExp
Trees after Morph - Structs/AddrExp
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..0BB) (return), preds={} succs={}
***** BB01
STMT00000 ( 0x000[E-] ... 0x00D )
[000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
[000003] ----------- \--* HWINTRINSIC simd16 ubyte And
[000000] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000002] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00001 ( 0x00E[E-] ... 0x02B )
[000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000010] ----------- \--* HWINTRINSIC simd16 ubyte And
[000007] ----------- +--* HWINTRINSIC simd16 int ShiftRightLogical
[000005] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000006] ----------- | \--* CNS_INT int 4
[000009] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00002 ( 0x033[E-] ... 0x04E )
[000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
[000020] ----------- \--* HWINTRINSIC simd16 ubyte Or
[000018] ----------- +--* HWINTRINSIC simd16 ubyte And
[000015] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000017] ----------- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808>
[000019] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
***** BB01
STMT00003 ( 0x050[E-] ... 0x05E )
[000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1
[000024] ----------- \--* CNS_INT int 0
***** BB01
STMT00009 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
[000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 [+0]
[000022] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1
***** BB01
STMT00010 ( INL01 @ 0x007[E-] ... ??? ) <- INLRT @ ???
[000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 [+16]
[000023] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2
***** BB01
STMT00005 ( 0x057[--] ... ??? )
[000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000033] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000030] -c--------- +--* FIELD_LIST struct
[000031] ----------- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 [+0]
[000032] ----------- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 [+16]
[000029] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
***** BB01
STMT00011 ( INL02 @ 0x016[E-] ... ??? ) <- INLRT @ 0x093[E-]
[000062] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V12 tmp2
[000061] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
***** BB01
STMT00007 ( 0x093[E-] ... ??? )
[000040] DAC-------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000063] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V12 tmp2
***** BB01
STMT00008 ( 0x0AD[E-] ... 0x0BA )
[000046] ----------- * RETURN simd16
[000045] ----------- \--* HWINTRINSIC simd16 ubyte CompareEqual
[000043] ----------- +--* HWINTRINSIC simd16 ubyte And
[000041] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000042] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000044] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid
*************** Starting PHASE Early liveness
Local V10 should not be enregistered because: struct size does not match reg size
Local V11 should not be enregistered because: struct size does not match reg size
Tracked variable (10 out of 13) table:
V00 arg0 [simd16]: refCnt = 2, refCntWtd = 0
V01 arg1 [simd16]: refCnt = 1, refCntWtd = 0
V02 arg2 [simd16]: refCnt = 1, refCntWtd = 0
V03 loc0 [simd16]: refCnt = 2, refCntWtd = 0
V04 loc1 [simd16]: refCnt = 3, refCntWtd = 0
V05 loc2 [simd16]: refCnt = 2, refCntWtd = 0
V06 loc3 [simd16]: refCnt = 3, refCntWtd = 0
V07 loc4 [simd16]: refCnt = 2, refCntWtd = 0
V11 tmp1 [struct]: refCnt = 5, refCntWtd = 0
V12 tmp2 [simd16]: refCnt = 2, refCntWtd = 0
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(3)={V00 V01 V02 }
DEF(7)={ V03 V04 V05 V06 V07 V11 V12}
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (3)={V00 V01 V02}
OUT(0)={ }
*************** Finishing PHASE Early liveness
Trees after Early liveness
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..0BB) (return), preds={} succs={}
***** BB01
STMT00000 ( 0x000[E-] ... 0x00D )
[000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
[000003] ----------- \--* HWINTRINSIC simd16 ubyte And
[000000] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000002] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00001 ( 0x00E[E-] ... 0x02B )
[000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000010] ----------- \--* HWINTRINSIC simd16 ubyte And
[000007] ----------- +--* HWINTRINSIC simd16 int ShiftRightLogical
[000005] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 (last use)
[000006] ----------- | \--* CNS_INT int 4
[000009] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00002 ( 0x033[E-] ... 0x04E )
[000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
[000020] ----------- \--* HWINTRINSIC simd16 ubyte Or
[000018] ----------- +--* HWINTRINSIC simd16 ubyte And
[000015] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000017] ----------- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808>
[000019] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 (last use)
***** BB01
STMT00003 ( 0x050[E-] ... 0x05E )
[000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1
[000024] ----------- \--* CNS_INT int 0
***** BB01
STMT00009 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
[000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 [+0]
[000022] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1 (last use)
***** BB01
STMT00010 ( INL01 @ 0x007[E-] ... ??? ) <- INLRT @ ???
[000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 [+16]
[000023] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2 (last use)
***** BB01
STMT00005 ( 0x057[--] ... ??? )
[000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000033] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000030] -c--------- +--* FIELD_LIST struct
[000031] ----------- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 [+0]
[000032] ----------- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 [+16] (last use)
[000029] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 (last use)
***** BB01
STMT00011 ( INL02 @ 0x016[E-] ... ??? ) <- INLRT @ 0x093[E-]
[000062] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V12 tmp2
[000061] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 (last use)
***** BB01
STMT00007 ( 0x093[E-] ... ??? )
[000040] DAC-------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000063] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V12 tmp2 (last use)
***** BB01
STMT00008 ( 0x0AD[E-] ... 0x0BA )
[000046] ----------- * RETURN simd16
[000045] ----------- \--* HWINTRINSIC simd16 ubyte CompareEqual
[000043] ----------- +--* HWINTRINSIC simd16 ubyte And
[000041] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 (last use)
[000042] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000044] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 (last use)
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid
*************** Starting PHASE Forward Substitution
===> BB01
[000004]: no next stmt use
[000011]: next stmt has non-last use
[000021]: no next stmt use
[000025]: mismatched types (store)
[000034]: no next stmt use
[000062]: [000063] is last use of [000062] (V12) -- fwd subbing [000061]; new next stmt is
STMT00007 ( 0x093[E-] ... ??? )
[000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000061] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 (last use)
removing useless STMT00011 ( INL02 @ 0x016[E-] ... ??? ) <- INLRT @ 0x093[E-]
[000062] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V12 tmp2
[000061] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 (last use)
from BB01
[000034]: no next stmt use
[000040]: next stmt has non-last use
*************** Finishing PHASE Forward Substitution
Trees after Forward Substitution
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..0BB) (return), preds={} succs={}
***** BB01
STMT00000 ( 0x000[E-] ... 0x00D )
[000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
[000003] ----------- \--* HWINTRINSIC simd16 ubyte And
[000000] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000002] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00001 ( 0x00E[E-] ... 0x02B )
[000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000010] ----------- \--* HWINTRINSIC simd16 ubyte And
[000007] ----------- +--* HWINTRINSIC simd16 int ShiftRightLogical
[000005] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 (last use)
[000006] ----------- | \--* CNS_INT int 4
[000009] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00002 ( 0x033[E-] ... 0x04E )
[000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
[000020] ----------- \--* HWINTRINSIC simd16 ubyte Or
[000018] ----------- +--* HWINTRINSIC simd16 ubyte And
[000015] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000017] ----------- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808>
[000019] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 (last use)
***** BB01
STMT00003 ( 0x050[E-] ... 0x05E )
[000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1
[000024] ----------- \--* CNS_INT int 0
***** BB01
STMT00009 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
[000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 [+0]
[000022] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1 (last use)
***** BB01
STMT00010 ( INL01 @ 0x007[E-] ... ??? ) <- INLRT @ ???
[000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 [+16]
[000023] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2 (last use)
***** BB01
STMT00005 ( 0x057[--] ... ??? )
[000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000033] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000030] -c--------- +--* FIELD_LIST struct
[000031] ----------- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 [+0]
[000032] ----------- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 [+16] (last use)
[000029] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 (last use)
***** BB01
STMT00007 ( 0x093[E-] ... ??? )
[000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000061] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 (last use)
***** BB01
STMT00008 ( 0x0AD[E-] ... 0x0BA )
[000046] ----------- * RETURN simd16
[000045] ----------- \--* HWINTRINSIC simd16 ubyte CompareEqual
[000043] ----------- +--* HWINTRINSIC simd16 ubyte And
[000041] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 (last use)
[000042] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000044] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 (last use)
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid
*************** Starting PHASE Physical promotion
*************** Finishing PHASE Physical promotion [no changes]
*************** Starting PHASE Morph - ByRefs
*************** Finishing PHASE Morph - ByRefs [no changes]
*************** Starting PHASE Morph - Global
*************** In fgMorphBlocks()
Morphing BB01 of 'System.Text.Tests.Demo:IndexOfAnyLookupCombined(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]'
fgMorphTree BB01, STMT00000 (before)
[000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
[000003] ----------- \--* HWINTRINSIC simd16 ubyte And
[000000] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000002] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
MorphCopyBlock:
PrepareDst for [000004] have found a local var V03.
block assignment to morph:
[000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
[000003] -----+----- \--* HWINTRINSIC simd16 ubyte And
[000000] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000002] -----+----- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
src is not an L-value this requires a CopyBlock.
MorphCopyBlock (after):
[000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
[000003] -----+----- \--* HWINTRINSIC simd16 ubyte And
[000000] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000002] -----+----- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
fgMorphTree BB01, STMT00001 (before)
[000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000010] ----------- \--* HWINTRINSIC simd16 ubyte And
[000007] ----------- +--* HWINTRINSIC simd16 int ShiftRightLogical
[000005] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 (last use)
[000006] ----------- | \--* CNS_INT int 4
[000009] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
MorphCopyBlock:
PrepareDst for [000011] have found a local var V04.
block assignment to morph:
[000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000010] -----+----- \--* HWINTRINSIC simd16 ubyte And
[000007] -----+----- +--* HWINTRINSIC simd16 int ShiftRightLogical
[000005] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 (last use)
[000006] -----+-N--- | \--* CNS_INT int 4
[000009] -----+----- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
src is not an L-value this requires a CopyBlock.
MorphCopyBlock (after):
[000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000010] -----+----- \--* HWINTRINSIC simd16 ubyte And
[000007] -----+----- +--* HWINTRINSIC simd16 int ShiftRightLogical
[000005] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 (last use)
[000006] -----+-N--- | \--* CNS_INT int 4
[000009] -----+----- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
fgMorphTree BB01, STMT00002 (before)
[000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
[000020] ----------- \--* HWINTRINSIC simd16 ubyte Or
[000018] ----------- +--* HWINTRINSIC simd16 ubyte And
[000015] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000017] ----------- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808>
[000019] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 (last use)
MorphCopyBlock:
PrepareDst for [000021] have found a local var V07.
block assignment to morph:
[000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
[000020] -----+----- \--* HWINTRINSIC simd16 ubyte Or
[000018] -----+----- +--* HWINTRINSIC simd16 ubyte And
[000015] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000017] -----+----- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808>
[000019] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 (last use)
src is not an L-value this requires a CopyBlock.
MorphCopyBlock (after):
[000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
[000020] -----+----- \--* HWINTRINSIC simd16 ubyte Or
[000018] -----+----- +--* HWINTRINSIC simd16 ubyte And
[000015] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000017] -----+----- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808>
[000019] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 (last use)
fgMorphTree BB01, STMT00003 (before)
[000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1
[000024] ----------- \--* CNS_INT int 0
MorphInitBlock:
PrepareDst for [000025] have found a local var V11.
GenTreeNode creates assertion:
[000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1
In BB01 New Local Constant Assertion: V11 == ZeroObj, index = #01
MorphInitBlock (after):
[000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1
[000024] -----+----- \--* CNS_INT int 0
fgMorphTree BB01, STMT00009 (before)
[000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 [+0]
[000022] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1 (last use)
MorphCopyBlock:
The assignment [000049] using V11 removes: Constant Assertion: V11 == ZeroObj
PrepareDst for [000049] have found a local var V11.
block assignment to morph:
[000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 [+0]
[000022] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1 (last use)
this requires a CopyBlock.
Local V11 should not be enregistered because: was accessed as a local field
MorphCopyBlock (after):
[000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 [+0]
[000022] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1 (last use)
fgMorphTree BB01, STMT00010 (before)
[000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 [+16]
[000023] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2 (last use)
MorphCopyBlock:
PrepareDst for [000052] have found a local var V11.
block assignment to morph:
[000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 [+16]
[000023] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2 (last use)
this requires a CopyBlock.
Local V11 should not be enregistered because: was accessed as a local field
MorphCopyBlock (after):
[000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 [+16]
[000023] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2 (last use)
fgMorphTree BB01, STMT00005 (before)
[000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000033] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000030] -c--------- +--* FIELD_LIST struct
[000031] ----------- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 [+0]
[000032] ----------- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 [+16] (last use)
[000029] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 (last use)
MorphCopyBlock:
PrepareDst for [000034] have found a local var V05.
block assignment to morph:
[000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000033] -----+----- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000030] -c---+----- +--* FIELD_LIST struct
[000031] -----+----- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 [+0]
[000032] -----+----- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 [+16] (last use)
[000029] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 (last use)
src is not an L-value this requires a CopyBlock.
MorphCopyBlock (after):
[000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000033] -----+----- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000030] -c---+----- +--* FIELD_LIST struct
[000031] -----+----- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 [+0]
[000032] -----+----- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 [+16] (last use)
[000029] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 (last use)
fgMorphTree BB01, STMT00007 (before)
[000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000061] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 (last use)
MorphCopyBlock:
PrepareDst for [000040] have found a local var V06.
block assignment to morph:
[000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000061] -----+----- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000060] -----+----- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 (last use)
src is not an L-value this requires a CopyBlock.
MorphCopyBlock (after):
[000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000061] -----+----- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000060] -----+----- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 (last use)
fgMorphTree BB01, STMT00008 (before)
[000046] ----------- * RETURN simd16
[000045] ----------- \--* HWINTRINSIC simd16 ubyte CompareEqual
[000043] ----------- +--* HWINTRINSIC simd16 ubyte And
[000041] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 (last use)
[000042] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000044] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 (last use)
*************** In fgMarkDemotedImplicitByRefArgs()
*************** Finishing PHASE Morph - Global
Trees after Morph - Global
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..0BB) (return), preds={} succs={}
***** BB01
STMT00000 ( 0x000[E-] ... 0x00D )
[000004] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
[000003] -----+----- \--* HWINTRINSIC simd16 ubyte And
[000000] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000002] -----+----- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00001 ( 0x00E[E-] ... 0x02B )
[000011] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000010] -----+----- \--* HWINTRINSIC simd16 ubyte And
[000007] -----+----- +--* HWINTRINSIC simd16 int ShiftRightLogical
[000005] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000006] -----+-N--- | \--* CNS_INT int 4
[000009] -----+----- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00002 ( 0x033[E-] ... 0x04E )
[000021] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
[000020] -----+----- \--* HWINTRINSIC simd16 ubyte Or
[000018] -----+----- +--* HWINTRINSIC simd16 ubyte And
[000015] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000017] -----+----- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808>
[000019] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
***** BB01
STMT00003 ( 0x050[E-] ... 0x05E )
[000025] DA---+----- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1
[000024] -----+----- \--* CNS_INT int 0
***** BB01
STMT00009 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
[000049] UA---+----- * STORE_LCL_FLD simd16 V11 tmp1 [+0]
[000022] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1
***** BB01
STMT00010 ( INL01 @ 0x007[E-] ... ??? ) <- INLRT @ ???
[000052] UA---+----- * STORE_LCL_FLD simd16 V11 tmp1 [+16]
[000023] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2
***** BB01
STMT00005 ( 0x057[--] ... ??? )
[000034] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000033] -----+----- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000030] -c---+----- +--* FIELD_LIST struct
[000031] -----+----- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 [+0]
[000032] -----+----- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 [+16]
[000029] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
***** BB01
STMT00007 ( 0x093[E-] ... ??? )
[000040] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000061] -----+----- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000060] -----+----- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
***** BB01
STMT00008 ( 0x0AD[E-] ... 0x0BA )
[000046] -----+----- * RETURN simd16
[000045] -----+----- \--* HWINTRINSIC simd16 ubyte CompareEqual
[000043] -----+----- +--* HWINTRINSIC simd16 ubyte And
[000041] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000042] -----+----- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000044] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid
*************** Starting PHASE GS Cookie
No GS security needed
*************** Finishing PHASE GS Cookie [no changes]
*************** Starting PHASE Compute edge weights (1, false)
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
-- no profile data, so using default called count
-- not optimizing or no profile data, so not computing edge weights
*************** Finishing PHASE Compute edge weights (1, false) [no changes]
*************** Starting PHASE Create EH funclets
*************** Finishing PHASE Create EH funclets [no changes]
*************** Starting PHASE Invert loops
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
=============== No blocks renumbered!
New BlockSet epoch 4, # of blocks (including unused BB00): 2, bitset array size: 1 (short)
*************** Finishing PHASE Invert loops
Trees after Invert loops
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..0BB) (return), preds={} succs={}
***** BB01
STMT00000 ( 0x000[E-] ... 0x00D )
[000004] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
[000003] -----+----- \--* HWINTRINSIC simd16 ubyte And
[000000] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000002] -----+----- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00001 ( 0x00E[E-] ... 0x02B )
[000011] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000010] -----+----- \--* HWINTRINSIC simd16 ubyte And
[000007] -----+----- +--* HWINTRINSIC simd16 int ShiftRightLogical
[000005] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000006] -----+-N--- | \--* CNS_INT int 4
[000009] -----+----- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00002 ( 0x033[E-] ... 0x04E )
[000021] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
[000020] -----+----- \--* HWINTRINSIC simd16 ubyte Or
[000018] -----+----- +--* HWINTRINSIC simd16 ubyte And
[000015] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000017] -----+----- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808>
[000019] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
***** BB01
STMT00003 ( 0x050[E-] ... 0x05E )
[000025] DA---+----- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1
[000024] -----+----- \--* CNS_INT int 0
***** BB01
STMT00009 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
[000049] UA---+----- * STORE_LCL_FLD simd16 V11 tmp1 [+0]
[000022] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1
***** BB01
STMT00010 ( INL01 @ 0x007[E-] ... ??? ) <- INLRT @ ???
[000052] UA---+----- * STORE_LCL_FLD simd16 V11 tmp1 [+16]
[000023] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2
***** BB01
STMT00005 ( 0x057[--] ... ??? )
[000034] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000033] -----+----- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000030] -c---+----- +--* FIELD_LIST struct
[000031] -----+----- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 [+0]
[000032] -----+----- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 [+16]
[000029] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
***** BB01
STMT00007 ( 0x093[E-] ... ??? )
[000040] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000061] -----+----- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000060] -----+----- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
***** BB01
STMT00008 ( 0x0AD[E-] ... 0x0BA )
[000046] -----+----- * RETURN simd16
[000045] -----+----- \--* HWINTRINSIC simd16 ubyte CompareEqual
[000043] -----+----- +--* HWINTRINSIC simd16 ubyte And
[000041] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000042] -----+----- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000044] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid
*************** Starting PHASE Optimize control flow
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Optimize control flow
Trees after Optimize control flow
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..0BB) (return), preds={} succs={}
***** BB01
STMT00000 ( 0x000[E-] ... 0x00D )
[000004] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
[000003] -----+----- \--* HWINTRINSIC simd16 ubyte And
[000000] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000002] -----+----- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00001 ( 0x00E[E-] ... 0x02B )
[000011] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000010] -----+----- \--* HWINTRINSIC simd16 ubyte And
[000007] -----+----- +--* HWINTRINSIC simd16 int ShiftRightLogical
[000005] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000006] -----+-N--- | \--* CNS_INT int 4
[000009] -----+----- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00002 ( 0x033[E-] ... 0x04E )
[000021] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
[000020] -----+----- \--* HWINTRINSIC simd16 ubyte Or
[000018] -----+----- +--* HWINTRINSIC simd16 ubyte And
[000015] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000017] -----+----- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808>
[000019] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
***** BB01
STMT00003 ( 0x050[E-] ... 0x05E )
[000025] DA---+----- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1
[000024] -----+----- \--* CNS_INT int 0
***** BB01
STMT00009 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
[000049] UA---+----- * STORE_LCL_FLD simd16 V11 tmp1 [+0]
[000022] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1
***** BB01
STMT00010 ( INL01 @ 0x007[E-] ... ??? ) <- INLRT @ ???
[000052] UA---+----- * STORE_LCL_FLD simd16 V11 tmp1 [+16]
[000023] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2
***** BB01
STMT00005 ( 0x057[--] ... ??? )
[000034] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000033] -----+----- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000030] -c---+----- +--* FIELD_LIST struct
[000031] -----+----- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 [+0]
[000032] -----+----- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 [+16]
[000029] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
***** BB01
STMT00007 ( 0x093[E-] ... ??? )
[000040] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000061] -----+----- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000060] -----+----- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
***** BB01
STMT00008 ( 0x0AD[E-] ... 0x0BA )
[000046] -----+----- * RETURN simd16
[000045] -----+----- \--* HWINTRINSIC simd16 ubyte CompareEqual
[000043] -----+----- +--* HWINTRINSIC simd16 ubyte And
[000041] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000042] -----+----- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000044] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid
*************** Starting PHASE Post-morph tail merge
*************** Finishing PHASE Post-morph tail merge [no changes]
*************** Starting PHASE Compute blocks reachability
Return blocks: BB01
Renumbering the basic blocks for fgComputeReachability pass #1
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
=============== No blocks renumbered!
Enter blocks: BB01
Dominator computation start blocks (those blocks with no incoming edges):
BB01
After computing reachability sets:
------------------------------------------------
BBnum Reachable by
------------------------------------------------
BB01 : BB01
*************** In fgComputeDoms
*************** In fgDebugCheckBBlist
------------------------------------------------
BBnum Dominated by
------------------------------------------------
BB01: BB01
Inside fgBuildDomTree
After computing the Dominance Tree:
After numbering the dominator tree:
BB01: pre=01, post=01
*************** Finishing PHASE Compute blocks reachability [no changes]
*************** Starting PHASE Set block weights
*************** Finishing PHASE Set block weights [no changes]
*************** Starting PHASE Find loops
*************** In optFindLoops()
*************** In optMarkLoopHeads()
0 loop heads marked
*************** Finishing PHASE Find loops
Trees after Find loops
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..0BB) (return), preds={} succs={}
***** BB01
STMT00000 ( 0x000[E-] ... 0x00D )
[000004] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
[000003] -----+----- \--* HWINTRINSIC simd16 ubyte And
[000000] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000002] -----+----- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00001 ( 0x00E[E-] ... 0x02B )
[000011] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000010] -----+----- \--* HWINTRINSIC simd16 ubyte And
[000007] -----+----- +--* HWINTRINSIC simd16 int ShiftRightLogical
[000005] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000006] -----+-N--- | \--* CNS_INT int 4
[000009] -----+----- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00002 ( 0x033[E-] ... 0x04E )
[000021] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
[000020] -----+----- \--* HWINTRINSIC simd16 ubyte Or
[000018] -----+----- +--* HWINTRINSIC simd16 ubyte And
[000015] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000017] -----+----- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808>
[000019] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
***** BB01
STMT00003 ( 0x050[E-] ... 0x05E )
[000025] DA---+----- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1
[000024] -----+----- \--* CNS_INT int 0
***** BB01
STMT00009 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
[000049] UA---+----- * STORE_LCL_FLD simd16 V11 tmp1 [+0]
[000022] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1
***** BB01
STMT00010 ( INL01 @ 0x007[E-] ... ??? ) <- INLRT @ ???
[000052] UA---+----- * STORE_LCL_FLD simd16 V11 tmp1 [+16]
[000023] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2
***** BB01
STMT00005 ( 0x057[--] ... ??? )
[000034] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000033] -----+----- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000030] -c---+----- +--* FIELD_LIST struct
[000031] -----+----- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 [+0]
[000032] -----+----- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 [+16]
[000029] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
***** BB01
STMT00007 ( 0x093[E-] ... ??? )
[000040] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000061] -----+----- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000060] -----+----- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
***** BB01
STMT00008 ( 0x0AD[E-] ... 0x0BA )
[000046] -----+----- * RETURN simd16
[000045] -----+----- \--* HWINTRINSIC simd16 ubyte CompareEqual
[000043] -----+----- +--* HWINTRINSIC simd16 ubyte And
[000041] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000042] -----+----- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000044] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable
*************** Starting PHASE Clone loops
*************** In optCloneLoops()
No loops to clone
*************** Finishing PHASE Clone loops [no changes]
*************** Starting PHASE Unroll loops
*************** Finishing PHASE Unroll loops [no changes]
*************** Starting PHASE Clear loop info
*************** Finishing PHASE Clear loop info [no changes]
*************** Starting PHASE Morph array ops
No multi-dimensional array references in the function
*************** Finishing PHASE Morph array ops [no changes]
*************** Starting PHASE Mark local vars
*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
*** marking local variables in block BB01 (weight=1)
STMT00000 ( 0x000[E-] ... 0x00D )
[000004] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
[000003] -----+----- \--* HWINTRINSIC simd16 ubyte And
[000000] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000002] -----+----- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
New refCnts for V03: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 1, refCntWtd = 1
STMT00001 ( 0x00E[E-] ... 0x02B )
[000011] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000010] -----+----- \--* HWINTRINSIC simd16 ubyte And
[000007] -----+----- +--* HWINTRINSIC simd16 int ShiftRightLogical
[000005] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
[000006] -----+-N--- | \--* CNS_INT int 4
[000009] -----+----- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
New refCnts for V04: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 2, refCntWtd = 2
STMT00002 ( 0x033[E-] ... 0x04E )
[000021] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
[000020] -----+----- \--* HWINTRINSIC simd16 ubyte Or
[000018] -----+----- +--* HWINTRINSIC simd16 ubyte And
[000015] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
[000017] -----+----- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808>
[000019] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
New refCnts for V07: refCnt = 1, refCntWtd = 1
New refCnts for V04: refCnt = 2, refCntWtd = 2
New refCnts for V03: refCnt = 2, refCntWtd = 2
STMT00003 ( 0x050[E-] ... 0x05E )
[000025] DA---+----- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1
[000024] -----+----- \--* CNS_INT int 0
New refCnts for V11: refCnt = 1, refCntWtd = 2
V11 needs explicit zero init. Disqualified as a single-def register candidate.
STMT00009 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
[000049] UA---+----- * STORE_LCL_FLD simd16 V11 tmp1 [+0]
[000022] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1
New refCnts for V11: refCnt = 2, refCntWtd = 4
New refCnts for V01: refCnt = 1, refCntWtd = 1
STMT00010 ( INL01 @ 0x007[E-] ... ??? ) <- INLRT @ ???
[000052] UA---+----- * STORE_LCL_FLD simd16 V11 tmp1 [+16]
[000023] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2
New refCnts for V11: refCnt = 3, refCntWtd = 6
New refCnts for V02: refCnt = 1, refCntWtd = 1
STMT00005 ( 0x057[--] ... ??? )
[000034] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000033] -----+----- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000030] -c---+----- +--* FIELD_LIST struct
[000031] -----+----- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 [+0]
[000032] -----+----- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 [+16]
[000029] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
New refCnts for V05: refCnt = 1, refCntWtd = 1
New refCnts for V11: refCnt = 4, refCntWtd = 8
New refCnts for V11: refCnt = 5, refCntWtd = 10
New refCnts for V07: refCnt = 2, refCntWtd = 2
STMT00007 ( 0x093[E-] ... ??? )
[000040] DA---+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000061] -----+----- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
[000060] -----+----- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
[000037] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
New refCnts for V06: refCnt = 1, refCntWtd = 1
New refCnts for V04: refCnt = 3, refCntWtd = 3
STMT00008 ( 0x0AD[E-] ... 0x0BA )
[000046] -----+----- * RETURN simd16
[000045] -----+----- \--* HWINTRINSIC simd16 ubyte CompareEqual
[000043] -----+----- +--* HWINTRINSIC simd16 ubyte And
[000041] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
[000042] -----+----- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
[000044] -----+----- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
New refCnts for V05: refCnt = 2, refCntWtd = 2
New refCnts for V06: refCnt = 2, refCntWtd = 2
New refCnts for V06: refCnt = 3, refCntWtd = 3
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 3, refCntWtd = 3
New refCnts for V00: refCnt = 4, refCntWtd = 4
New refCnts for V01: refCnt = 2, refCntWtd = 2
New refCnts for V01: refCnt = 3, refCntWtd = 3
New refCnts for V02: refCnt = 2, refCntWtd = 2
New refCnts for V02: refCnt = 3, refCntWtd = 3
*************** Finishing PHASE Mark local vars [no changes]
*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()
*************** Finishing PHASE Find oper order
Trees after Find oper order
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..0BB) (return), preds={} succs={}
***** BB01
STMT00000 ( 0x000[E-] ... 0x00D )
( 9, 7) [000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
( 5, 4) [000003] ----------- \--* HWINTRINSIC simd16 ubyte And
( 1, 1) [000000] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
( 3, 2) [000002] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00001 ( 0x00E[E-] ... 0x02B )
( 7, 7) [000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
( 7, 7) [000010] ----------- \--* HWINTRINSIC simd16 ubyte And
( 3, 4) [000007] ----------- +--* HWINTRINSIC simd16 int ShiftRightLogical
( 1, 1) [000005] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
( 1, 2) [000006] -------N--- | \--* CNS_INT int 4
( 3, 2) [000009] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00002 ( 0x033[E-] ... 0x04E )
( 13, 10) [000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
( 9, 7) [000020] ----------- \--* HWINTRINSIC simd16 ubyte Or
( 5, 4) [000018] ----------- +--* HWINTRINSIC simd16 ubyte And
( 1, 1) [000015] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
( 3, 2) [000017] ----------- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808>
( 3, 2) [000019] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
***** BB01
STMT00003 ( 0x050[E-] ... 0x05E )
( 11, 9) [000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1
( 1, 2) [000024] ----------- \--* CNS_INT int 0
***** BB01
STMT00009 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
( 5, 6) [000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 [+0]
( 1, 1) [000022] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1
***** BB01
STMT00010 ( INL01 @ 0x007[E-] ... ??? ) <- INLRT @ ???
( 5, 6) [000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 [+16]
( 1, 1) [000023] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2
***** BB01
STMT00005 ( 0x057[--] ... ??? )
( 14, 14) [000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
( 10, 11) [000033] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
( 6, 8) [000030] -c--------- +--* FIELD_LIST struct
( 3, 4) [000031] ----------- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 [+0]
( 3, 4) [000032] ----------- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 [+16]
( 3, 2) [000029] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
***** BB01
STMT00007 ( 0x093[E-] ... ??? )
( 5, 4) [000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
( 5, 4) [000061] --------R-- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
( 3, 2) [000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
( 1, 1) [000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
***** BB01
STMT00008 ( 0x0AD[E-] ... 0x0BA )
( 8, 7) [000046] ----------- * RETURN simd16
( 7, 6) [000045] ----------- \--* HWINTRINSIC simd16 ubyte CompareEqual
( 5, 4) [000043] ----------- +--* HWINTRINSIC simd16 ubyte And
( 3, 2) [000041] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
( 1, 1) [000042] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
( 1, 1) [000044] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable
*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has 6 tree nodes
*************** Finishing PHASE Set block order
Trees after Set block order
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..0BB) (return), preds={} succs={}
***** BB01
STMT00000 ( 0x000[E-] ... 0x00D )
N004 ( 9, 7) [000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
N003 ( 5, 4) [000003] ----------- \--* HWINTRINSIC simd16 ubyte And
N001 ( 1, 1) [000000] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
N002 ( 3, 2) [000002] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00001 ( 0x00E[E-] ... 0x02B )
N006 ( 7, 7) [000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
N005 ( 7, 7) [000010] ----------- \--* HWINTRINSIC simd16 ubyte And
N003 ( 3, 4) [000007] ----------- +--* HWINTRINSIC simd16 int ShiftRightLogical
N001 ( 1, 1) [000005] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0
N002 ( 1, 2) [000006] -------N--- | \--* CNS_INT int 4
N004 ( 3, 2) [000009] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00002 ( 0x033[E-] ... 0x04E )
N006 ( 13, 10) [000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
N005 ( 9, 7) [000020] ----------- \--* HWINTRINSIC simd16 ubyte Or
N003 ( 5, 4) [000018] ----------- +--* HWINTRINSIC simd16 ubyte And
N001 ( 1, 1) [000015] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
N002 ( 3, 2) [000017] ----------- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808>
N004 ( 3, 2) [000019] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0
***** BB01
STMT00003 ( 0x050[E-] ... 0x05E )
N002 ( 11, 9) [000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1
N001 ( 1, 2) [000024] ----------- \--* CNS_INT int 0
***** BB01
STMT00009 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
N002 ( 5, 6) [000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 [+0]
N001 ( 1, 1) [000022] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1
***** BB01
STMT00010 ( INL01 @ 0x007[E-] ... ??? ) <- INLRT @ ???
N002 ( 5, 6) [000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 [+16]
N001 ( 1, 1) [000023] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2
***** BB01
STMT00005 ( 0x057[--] ... ??? )
N006 ( 14, 14) [000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
N005 ( 10, 11) [000033] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
N003 ( 6, 8) [000030] -c--------- +--* FIELD_LIST struct
N001 ( 3, 4) [000031] ----------- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 [+0]
N002 ( 3, 4) [000032] ----------- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 [+16]
N004 ( 3, 2) [000029] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4
***** BB01
STMT00007 ( 0x093[E-] ... ??? )
N004 ( 5, 4) [000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
N003 ( 5, 4) [000061] --------R-- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
N002 ( 3, 2) [000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
N001 ( 1, 1) [000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1
***** BB01
STMT00008 ( 0x0AD[E-] ... 0x0BA )
N006 ( 8, 7) [000046] ----------- * RETURN simd16
N005 ( 7, 6) [000045] ----------- \--* HWINTRINSIC simd16 ubyte CompareEqual
N003 ( 5, 4) [000043] ----------- +--* HWINTRINSIC simd16 ubyte And
N001 ( 3, 2) [000041] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2
N002 ( 1, 1) [000042] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
N004 ( 1, 1) [000044] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable
*************** Starting PHASE Build SSA representation
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 2.
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]
Inside fgBuildDomTree
After computing the Dominance Tree:
*************** In fgLocalVarLiveness()
In fgLocalVarLivenessInit
Local V10 should not be enregistered because: struct size does not match reg size
Local V11 should not be enregistered because: struct size does not match reg size
Tracked variable (9 out of 13) table:
V11 tmp1 [struct]: refCnt = 5, refCntWtd = 10
V00 arg0 [simd16]: refCnt = 4, refCntWtd = 4
V01 arg1 [simd16]: refCnt = 3, refCntWtd = 3
V02 arg2 [simd16]: refCnt = 3, refCntWtd = 3
V04 loc1 [simd16]: refCnt = 3, refCntWtd = 3
V06 loc3 [simd16]: refCnt = 3, refCntWtd = 3
V03 loc0 [simd16]: refCnt = 2, refCntWtd = 2
V05 loc2 [simd16]: refCnt = 2, refCntWtd = 2
V07 loc4 [simd16]: refCnt = 2, refCntWtd = 2
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(3)={ V00 V01 V02 }
DEF(6)={V11 V04 V06 V03 V05 V07}
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (3)={V00 V01 V02}
OUT(0)={ }
*************** In optRemoveRedundantZeroInits()
Marking V03 as having an explicit init
Marking V04 as having an explicit init
Marking V07 as having an explicit init
Marking V11 as having an explicit init
Marking V05 as having an explicit init
Marking V06 as having an explicit init
*************** In SsaBuilder::InsertPhiFunctions()
Inserting phi functions:
*************** In SsaBuilder::RenameVariables()
V00.1: defined in BB00 2 uses (global)
V01.1: defined in BB00 1 uses (global)
V02.1: defined in BB00 1 uses (global)
V03.1: defined in BB00 0 uses (local)
V03.2: defined in BB01 1 uses (local)
V04.1: defined in BB00 0 uses (local)
V04.2: defined in BB01 2 uses (local)
V05.1: defined in BB00 0 uses (local)
V05.2: defined in BB01 1 uses (local)
V06.1: defined in BB00 0 uses (local)
V06.2: defined in BB01 2 uses (local)
V07.1: defined in BB00 0 uses (local)
V07.2: defined in BB01 1 uses (local)
V11.1: defined in BB00 0 uses (local)
V11.2: defined in BB01 1 uses (local)
V11.3: defined in BB01 1 uses (local)
V11.4: defined in BB01 2 uses (local)
*************** Finishing PHASE Build SSA representation
Trees after Build SSA representation
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..0BB) (return), preds={} succs={}
***** BB01
STMT00000 ( 0x000[E-] ... 0x00D )
N004 ( 9, 7) [000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 d:2
N003 ( 5, 4) [000003] ----------- \--* HWINTRINSIC simd16 ubyte And
N001 ( 1, 1) [000000] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1
N002 ( 3, 2) [000002] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00001 ( 0x00E[E-] ... 0x02B )
N006 ( 7, 7) [000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 d:2
N005 ( 7, 7) [000010] ----------- \--* HWINTRINSIC simd16 ubyte And
N003 ( 3, 4) [000007] ----------- +--* HWINTRINSIC simd16 int ShiftRightLogical
N001 ( 1, 1) [000005] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 (last use)
N002 ( 1, 2) [000006] -------N--- | \--* CNS_INT int 4
N004 ( 3, 2) [000009] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
***** BB01
STMT00002 ( 0x033[E-] ... 0x04E )
N006 ( 13, 10) [000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 d:2
N005 ( 9, 7) [000020] ----------- \--* HWINTRINSIC simd16 ubyte Or
N003 ( 5, 4) [000018] ----------- +--* HWINTRINSIC simd16 ubyte And
N001 ( 1, 1) [000015] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2
N002 ( 3, 2) [000017] ----------- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808>
N004 ( 3, 2) [000019] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 u:2 (last use)
***** BB01
STMT00003 ( 0x050[E-] ... 0x05E )
N002 ( 11, 9) [000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1 d:2
N001 ( 1, 2) [000024] ----------- \--* CNS_INT int 0
***** BB01
STMT00009 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
N002 ( 5, 6) [000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:2->3[+0]
N001 ( 1, 1) [000022] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1 u:1 (last use)
***** BB01
STMT00010 ( INL01 @ 0x007[E-] ... ??? ) <- INLRT @ ???
N002 ( 5, 6) [000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:3->4[+16]
N001 ( 1, 1) [000023] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2 u:1 (last use)
***** BB01
STMT00005 ( 0x057[--] ... ??? )
N006 ( 14, 14) [000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 d:2
N005 ( 10, 11) [000033] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
N003 ( 6, 8) [000030] -c--------- +--* FIELD_LIST struct
N001 ( 3, 4) [000031] ----------- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 u:4[+0]
N002 ( 3, 4) [000032] ----------- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 u:4[+16] (last use)
N004 ( 3, 2) [000029] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 u:2 (last use)
***** BB01
STMT00007 ( 0x093[E-] ... ??? )
N004 ( 5, 4) [000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 d:2
N003 ( 5, 4) [000061] --------R-- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
N002 ( 3, 2) [000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
N001 ( 1, 1) [000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 (last use)
***** BB01
STMT00008 ( 0x0AD[E-] ... 0x0BA )
N006 ( 8, 7) [000046] ----------- * RETURN simd16
N005 ( 7, 6) [000045] ----------- \--* HWINTRINSIC simd16 ubyte CompareEqual
N003 ( 5, 4) [000043] ----------- +--* HWINTRINSIC simd16 ubyte And
N001 ( 3, 2) [000041] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 u:2 (last use)
N002 ( 1, 1) [000042] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2
N004 ( 1, 1) [000044] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 (last use)
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[info] HasGlobalUse overestimated for V00.1
[info] HasGlobalUse overestimated for V01.1
[info] HasGlobalUse overestimated for V02.1
SSA checks completed successfully
*************** In fgDebugCheckLoopTable
*************** Starting PHASE Early Value Propagation
no arrays or null checks in the method
*************** Finishing PHASE Early Value Propagation [no changes]
*************** Starting PHASE Do value numbering
*************** In fgValueNumber()
Memory Initial Value in BB01 is: $100
The SSA definition for ByrefExposed (#1) at start of BB01 is $100 {InitVal($49)}
The SSA definition for GcHeap (#1) at start of BB01 is $100 {InitVal($49)}
***** BB01, STMT00000(before)
N004 ( 9, 7) [000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 d:2
N003 ( 5, 4) [000003] ----------- \--* HWINTRINSIC simd16 ubyte And
N001 ( 1, 1) [000000] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1
N002 ( 3, 2) [000002] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
N001 [000000] LCL_VAR V00 arg0 u:1 => $80 {InitVal($40)}
N002 [000002] CNS_VEC <0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> => $140 {Simd16Cns[0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f]}
simdTypeVN is $180 {SimdType(simd16, ubyte)}
N003 [000003] HWINTRINSIC => $1c0 {HWI_AdvSimd_And($80, $140, $180)}
Tree [000004] assigned VN to local var V03/2: $1c0 {HWI_AdvSimd_And($80, $140, $180)}
N004 [000004] STORE_LCL_VAR V03 loc0 d:2 => $VN.Void
***** BB01, STMT00000(after)
N004 ( 9, 7) [000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 d:2 $VN.Void
N003 ( 5, 4) [000003] ----------- \--* HWINTRINSIC simd16 ubyte And $1c0
N001 ( 1, 1) [000000] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 $80
N002 ( 3, 2) [000002] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> $140
---------
***** BB01, STMT00001(before)
N006 ( 7, 7) [000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 d:2
N005 ( 7, 7) [000010] ----------- \--* HWINTRINSIC simd16 ubyte And
N003 ( 3, 4) [000007] ----------- +--* HWINTRINSIC simd16 int ShiftRightLogical
N001 ( 1, 1) [000005] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 (last use)
N002 ( 1, 2) [000006] -------N--- | \--* CNS_INT int 4
N004 ( 3, 2) [000009] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
N001 [000005] LCL_VAR V00 arg0 u:1 (last use) => $80 {InitVal($40)}
N002 [000006] CNS_INT 4 => $44 {IntCns 4}
simdTypeVN is $181 {SimdType(simd16, int)}
N003 [000007] HWINTRINSIC => $1c1 {HWI_AdvSimd_ShiftRightLogical($80, $44, $181)}
N004 [000009] CNS_VEC <0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> => $140 {Simd16Cns[0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f]}
simdTypeVN is $180 {SimdType(simd16, ubyte)}
N005 [000010] HWINTRINSIC => $1c2 {HWI_AdvSimd_And($1c1, $140, $180)}
Tree [000011] assigned VN to local var V04/2: $1c2 {HWI_AdvSimd_And($1c1, $140, $180)}
N006 [000011] STORE_LCL_VAR V04 loc1 d:2 => $VN.Void
***** BB01, STMT00001(after)
N006 ( 7, 7) [000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 d:2 $VN.Void
N005 ( 7, 7) [000010] ----------- \--* HWINTRINSIC simd16 ubyte And $1c2
N003 ( 3, 4) [000007] ----------- +--* HWINTRINSIC simd16 int ShiftRightLogical $1c1
N001 ( 1, 1) [000005] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 (last use) $80
N002 ( 1, 2) [000006] -------N--- | \--* CNS_INT int 4 $44
N004 ( 3, 2) [000009] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> $140
---------
***** BB01, STMT00002(before)
N006 ( 13, 10) [000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 d:2
N005 ( 9, 7) [000020] ----------- \--* HWINTRINSIC simd16 ubyte Or
N003 ( 5, 4) [000018] ----------- +--* HWINTRINSIC simd16 ubyte And
N001 ( 1, 1) [000015] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2
N002 ( 3, 2) [000017] ----------- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808>
N004 ( 3, 2) [000019] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 u:2 (last use)
N001 [000015] LCL_VAR V04 loc1 u:2 => $1c2 {HWI_AdvSimd_And($1c1, $140, $180)}
N002 [000017] CNS_VEC <0x08080808, 0x08080808, 0x08080808, 0x08080808> => $143 {Simd16Cns[0x08080808, 0x08080808, 0x08080808, 0x08080808]}
simdTypeVN is $180 {SimdType(simd16, ubyte)}
N003 [000018] HWINTRINSIC => $1c3 {HWI_AdvSimd_And($1c2, $143, $180)}
N004 [000019] LCL_VAR V03 loc0 u:2 (last use) => $1c0 {HWI_AdvSimd_And($80, $140, $180)}
simdTypeVN is $180 {SimdType(simd16, ubyte)}
N005 [000020] HWINTRINSIC => $1c4 {HWI_AdvSimd_Or($1c3, $1c0, $180)}
Tree [000021] assigned VN to local var V07/2: $1c4 {HWI_AdvSimd_Or($1c3, $1c0, $180)}
N006 [000021] STORE_LCL_VAR V07 loc4 d:2 => $VN.Void
***** BB01, STMT00002(after)
N006 ( 13, 10) [000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 d:2 $VN.Void
N005 ( 9, 7) [000020] ----------- \--* HWINTRINSIC simd16 ubyte Or $1c4
N003 ( 5, 4) [000018] ----------- +--* HWINTRINSIC simd16 ubyte And $1c3
N001 ( 1, 1) [000015] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 $1c2
N002 ( 3, 2) [000017] ----------- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808> $143
N004 ( 3, 2) [000019] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 u:2 (last use) $1c0
---------
***** BB01, STMT00003(before)
N002 ( 11, 9) [000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1 d:2
N001 ( 1, 2) [000024] ----------- \--* CNS_INT int 0
N001 [000024] CNS_INT 0 => $40 {IntCns 0}
Tree [000025] assigned VN to local var V11/2: $c1 {ZeroObj($200: System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]])}
N002 [000025] STORE_LCL_VAR V11 tmp1 d:2 => $VN.Void
***** BB01, STMT00003(after)
N002 ( 11, 9) [000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1 d:2 $VN.Void
N001 ( 1, 2) [000024] ----------- \--* CNS_INT int 0 $40
---------
***** BB01, STMT00009(before)
N002 ( 5, 6) [000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:2->3[+0]
N001 ( 1, 1) [000022] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1 u:1 (last use)
N001 [000022] LCL_VAR V01 arg1 u:1 (last use) => $81 {InitVal($41)}
VNForStore:
VNForMapPhysicalStore:struct returns $240 {$c1[0:15] := $81]}
Tree [000049] assigned VN to local var V11/3: $240 {$c1[0:15] := $81]}
N002 [000049] STORE_LCL_FLD V11 tmp1 ud:2->3[+0] => $VN.Void
***** BB01, STMT00009(after)
N002 ( 5, 6) [000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:2->3[+0] $VN.Void
N001 ( 1, 1) [000022] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1 u:1 (last use) $81
---------
***** BB01, STMT00010(before)
N002 ( 5, 6) [000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:3->4[+16]
N001 ( 1, 1) [000023] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2 u:1 (last use)
N001 [000023] LCL_VAR V02 arg2 u:1 (last use) => $82 {InitVal($42)}
VNForStore:
VNForMapPhysicalStore:struct returns $241 {$240[16:31] := $82]}
Tree [000052] assigned VN to local var V11/4: $241 {$240[16:31] := $82]}
N002 [000052] STORE_LCL_FLD V11 tmp1 ud:3->4[+16] => $VN.Void
***** BB01, STMT00010(after)
N002 ( 5, 6) [000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:3->4[+16] $VN.Void
N001 ( 1, 1) [000023] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2 u:1 (last use) $82
---------
***** BB01, STMT00005(before)
N006 ( 14, 14) [000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 d:2
N005 ( 10, 11) [000033] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
N003 ( 6, 8) [000030] -c--------- +--* FIELD_LIST struct
N001 ( 3, 4) [000031] ----------- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 u:4[+0]
N002 ( 3, 4) [000032] ----------- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 u:4[+16] (last use)
N004 ( 3, 2) [000029] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 u:2 (last use)
VNForLoad:
select($241 {$240[16:31] := $82]}, [0:15]) ==> disjoint, remaining budget is 99
select($240 {$c1[0:15] := $81]}, [0:15]) ==> $81
VNForMapPhysicalSelect($241, [0:15]):simd16 returns $81 {InitVal($41)}
VNForLoad:
select($241 {$240[16:31] := $82]}, [0:15]) ==> disjoint, remaining budget is 99
select($240 {$c1[0:15] := $81]}, [0:15]) ==> $81
VNForMapPhysicalSelect($241, [0:15]):simd16 returns $81 {InitVal($41)}
N001 [000031] LCL_FLD V11 tmp1 u:4[+0] => $81 {InitVal($41)}
VNForLoad:
select($241 {$240[16:31] := $82]}, [16:31]) ==> $82
VNForMapPhysicalSelect($241, [16:31]):simd16 returns $82 {InitVal($42)}
VNForLoad:
select($241 {$240[16:31] := $82]}, [16:31]) ==> $82
VNForMapPhysicalSelect($241, [16:31]):simd16 returns $82 {InitVal($42)}
N002 [000032] LCL_FLD V11 tmp1 u:4[+16] (last use) => $82 {InitVal($42)}
N003 [000030] FIELD_LIST => $c2 {MemOpaque:NotInLoop}
N004 [000029] LCL_VAR V07 loc4 u:2 (last use) => $1c4 {HWI_AdvSimd_Or($1c3, $1c0, $180)}
simdTypeVN is $180 {SimdType(simd16, ubyte)}
N005 [000033] HWINTRINSIC => $1c5 {HWI_AdvSimd_Arm64_VectorTableLookup($c2, $1c4, $180)}
Tree [000034] assigned VN to local var V05/2: $1c5 {HWI_AdvSimd_Arm64_VectorTableLookup($c2, $1c4, $180)}
N006 [000034] STORE_LCL_VAR V05 loc2 d:2 => $VN.Void
***** BB01, STMT00005(after)
N006 ( 14, 14) [000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 d:2 $VN.Void
N005 ( 10, 11) [000033] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup $1c5
N003 ( 6, 8) [000030] -c--------- +--* FIELD_LIST struct $c2
N001 ( 3, 4) [000031] ----------- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 u:4[+0] $81
N002 ( 3, 4) [000032] ----------- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 u:4[+16] (last use) $82
N004 ( 3, 2) [000029] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 u:2 (last use) $1c4
---------
***** BB01, STMT00007(before)
N004 ( 5, 4) [000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 d:2
N003 ( 5, 4) [000061] --------R-- \--* HWINTRINSIC simd16 ubyte VectorTableLookup
N002 ( 3, 2) [000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010>
N001 ( 1, 1) [000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 (last use)
N001 [000037] LCL_VAR V04 loc1 u:2 (last use) => $1c2 {HWI_AdvSimd_And($1c1, $140, $180)}
N002 [000060] CNS_VEC <0x08040201, 0x80402010, 0x08040201, 0x80402010> => $144 {Simd16Cns[0x08040201, 0x80402010, 0x08040201, 0x80402010]}
simdTypeVN is $180 {SimdType(simd16, ubyte)}
N003 [000061] HWINTRINSIC => $1c6 {HWI_AdvSimd_Arm64_VectorTableLookup($144, $1c2, $180)}
Tree [000040] assigned VN to local var V06/2: $1c6 {HWI_AdvSimd_Arm64_VectorTableLookup($144, $1c2, $180)}
N004 [000040] STORE_LCL_VAR V06 loc3 d:2 => $VN.Void
***** BB01, STMT00007(after)
N004 ( 5, 4) [000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 d:2 $VN.Void
N003 ( 5, 4) [000061] --------R-- \--* HWINTRINSIC simd16 ubyte VectorTableLookup $1c6
N002 ( 3, 2) [000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010> $144
N001 ( 1, 1) [000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 (last use) $1c2
---------
***** BB01, STMT00008(before)
N006 ( 8, 7) [000046] ----------- * RETURN simd16
N005 ( 7, 6) [000045] ----------- \--* HWINTRINSIC simd16 ubyte CompareEqual
N003 ( 5, 4) [000043] ----------- +--* HWINTRINSIC simd16 ubyte And
N001 ( 3, 2) [000041] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 u:2 (last use)
N002 ( 1, 1) [000042] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2
N004 ( 1, 1) [000044] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 (last use)
N001 [000041] LCL_VAR V05 loc2 u:2 (last use) => $1c5 {HWI_AdvSimd_Arm64_VectorTableLookup($c2, $1c4, $180)}
N002 [000042] LCL_VAR V06 loc3 u:2 => $1c6 {HWI_AdvSimd_Arm64_VectorTableLookup($144, $1c2, $180)}
simdTypeVN is $180 {SimdType(simd16, ubyte)}
N003 [000043] HWINTRINSIC => $1c7 {HWI_AdvSimd_And($1c5, $1c6, $180)}
N004 [000044] LCL_VAR V06 loc3 u:2 (last use) => $1c6 {HWI_AdvSimd_Arm64_VectorTableLookup($144, $1c2, $180)}
simdTypeVN is $180 {SimdType(simd16, ubyte)}
N005 [000045] HWINTRINSIC => $1c8 {HWI_AdvSimd_CompareEqual($1c7, $1c6, $180)}
N006 [000046] RETURN => $VN.Void
***** BB01, STMT00008(after)
N006 ( 8, 7) [000046] ----------- * RETURN simd16 $VN.Void
N005 ( 7, 6) [000045] ----------- \--* HWINTRINSIC simd16 ubyte CompareEqual $1c8
N003 ( 5, 4) [000043] ----------- +--* HWINTRINSIC simd16 ubyte And $1c7
N001 ( 3, 2) [000041] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 u:2 (last use) $1c5
N002 ( 1, 1) [000042] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 $1c6
N004 ( 1, 1) [000044] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 (last use) $1c6
finish(BB01).
*************** Finishing PHASE Do value numbering
Trees after Do value numbering
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..0BB) (return), preds={} succs={}
***** BB01
STMT00000 ( 0x000[E-] ... 0x00D )
N004 ( 9, 7) [000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 d:2 $VN.Void
N003 ( 5, 4) [000003] ----------- \--* HWINTRINSIC simd16 ubyte And $1c0
N001 ( 1, 1) [000000] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 $80
N002 ( 3, 2) [000002] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> $140
***** BB01
STMT00001 ( 0x00E[E-] ... 0x02B )
N006 ( 7, 7) [000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 d:2 $VN.Void
N005 ( 7, 7) [000010] ----------- \--* HWINTRINSIC simd16 ubyte And $1c2
N003 ( 3, 4) [000007] ----------- +--* HWINTRINSIC simd16 int ShiftRightLogical $1c1
N001 ( 1, 1) [000005] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 (last use) $80
N002 ( 1, 2) [000006] -------N--- | \--* CNS_INT int 4 $44
N004 ( 3, 2) [000009] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> $140
***** BB01
STMT00002 ( 0x033[E-] ... 0x04E )
N006 ( 13, 10) [000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 d:2 $VN.Void
N005 ( 9, 7) [000020] ----------- \--* HWINTRINSIC simd16 ubyte Or $1c4
N003 ( 5, 4) [000018] ----------- +--* HWINTRINSIC simd16 ubyte And $1c3
N001 ( 1, 1) [000015] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 $1c2
N002 ( 3, 2) [000017] ----------- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808> $143
N004 ( 3, 2) [000019] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 u:2 (last use) $1c0
***** BB01
STMT00003 ( 0x050[E-] ... 0x05E )
N002 ( 11, 9) [000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1 d:2 $VN.Void
N001 ( 1, 2) [000024] ----------- \--* CNS_INT int 0 $40
***** BB01
STMT00009 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
N002 ( 5, 6) [000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:2->3[+0] $VN.Void
N001 ( 1, 1) [000022] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1 u:1 (last use) $81
***** BB01
STMT00010 ( INL01 @ 0x007[E-] ... ??? ) <- INLRT @ ???
N002 ( 5, 6) [000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:3->4[+16] $VN.Void
N001 ( 1, 1) [000023] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2 u:1 (last use) $82
***** BB01
STMT00005 ( 0x057[--] ... ??? )
N006 ( 14, 14) [000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 d:2 $VN.Void
N005 ( 10, 11) [000033] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup $1c5
N003 ( 6, 8) [000030] -c--------- +--* FIELD_LIST struct $c2
N001 ( 3, 4) [000031] ----------- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 u:4[+0] $81
N002 ( 3, 4) [000032] ----------- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 u:4[+16] (last use) $82
N004 ( 3, 2) [000029] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 u:2 (last use) $1c4
***** BB01
STMT00007 ( 0x093[E-] ... ??? )
N004 ( 5, 4) [000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 d:2 $VN.Void
N003 ( 5, 4) [000061] --------R-- \--* HWINTRINSIC simd16 ubyte VectorTableLookup $1c6
N002 ( 3, 2) [000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010> $144
N001 ( 1, 1) [000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 (last use) $1c2
***** BB01
STMT00008 ( 0x0AD[E-] ... 0x0BA )
N006 ( 8, 7) [000046] ----------- * RETURN simd16 $VN.Void
N005 ( 7, 6) [000045] ----------- \--* HWINTRINSIC simd16 ubyte CompareEqual $1c8
N003 ( 5, 4) [000043] ----------- +--* HWINTRINSIC simd16 ubyte And $1c7
N001 ( 3, 2) [000041] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 u:2 (last use) $1c5
N002 ( 1, 1) [000042] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 $1c6
N004 ( 1, 1) [000044] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 (last use) $1c6
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[info] HasGlobalUse overestimated for V00.1
[info] HasGlobalUse overestimated for V01.1
[info] HasGlobalUse overestimated for V02.1
SSA checks completed successfully
*************** In fgDebugCheckLoopTable
*************** Starting PHASE Hoist loop code
No loops; no hoisting
*************** Finishing PHASE Hoist loop code [no changes]
*************** Starting PHASE VN based copy prop
Copy Assertion for BB01
curSsaName stack: { }
Live vars after [000004]: {V00 V01 V02} => {V00 V01 V02 V03}
Live vars after [000005]: {V00 V01 V02 V03} => {V01 V02 V03}
Live vars after [000011]: {V01 V02 V03} => {V01 V02 V03 V04}
Live vars after [000019]: {V01 V02 V03 V04} => {V01 V02 V04}
Live vars after [000021]: {V01 V02 V04} => {V01 V02 V04 V07}
Live vars after [000025]: {V01 V02 V04 V07} => {V01 V02 V04 V07 V11}
Live vars after [000022]: {V01 V02 V04 V07 V11} => {V02 V04 V07 V11}
Live vars after [000023]: {V02 V04 V07 V11} => {V04 V07 V11}
Live vars after [000032]: {V04 V07 V11} => {V04 V07}
Live vars after [000029]: {V04 V07} => {V04}
Live vars after [000034]: {V04} => {V04 V05}
Live vars after [000037]: {V04 V05} => {V05}
Live vars after [000040]: {V05} => {V05 V06}
Live vars after [000041]: {V05 V06} => {V06}
Live vars after [000044]: {V06} => {}
*************** Finishing PHASE VN based copy prop [no changes]
*************** Starting PHASE Redundant branch opts
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Redundant branch opts [no changes]
*************** Starting PHASE Optimize Valnum CSEs
Candidate CSE #01, key=$140 in BB01, [cost= 3, size= 2]:
N004 ( 3, 2) CSE #01 (use)[000009] ----------- * CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> $140
Blocks that generate CSE def/uses
BB01 cseGen = 0000000000000003 CSE #01.c
[info] HasGlobalUse overestimated for V00.1
[info] HasGlobalUse overestimated for V01.1
[info] HasGlobalUse overestimated for V02.1
SSA checks completed successfully
Performing DataFlow for ValnumCSE's
After performing DataFlow for ValnumCSE's
BB01
in: 0000000000000000
gen: 0000000000000003 CSE #01.c
out: 0000000000000003 CSE #01.c
Labeling the CSEs with Use/Def information
BB01 [000002] Def of CSE #01 [weight=1]
BB01 [000009] Use of CSE #01 [weight=1]
************ Trees at start of optValnumCSE_Heuristic()
------------ BB01 [000..0BB) (return), preds={} succs={}
***** BB01
STMT00000 ( 0x000[E-] ... 0x00D )
N004 ( 9, 7) [000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 d:2 $VN.Void
N003 ( 5, 4) [000003] ----------- \--* HWINTRINSIC simd16 ubyte And $1c0
N001 ( 1, 1) [000000] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 $80
N002 ( 3, 2) CSE #01 (def)[000002] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> $140
***** BB01
STMT00001 ( 0x00E[E-] ... 0x02B )
N006 ( 7, 7) [000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 d:2 $VN.Void
N005 ( 7, 7) [000010] ----------- \--* HWINTRINSIC simd16 ubyte And $1c2
N003 ( 3, 4) [000007] ----------- +--* HWINTRINSIC simd16 int ShiftRightLogical $1c1
N001 ( 1, 1) [000005] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 (last use) $80
N002 ( 1, 2) [000006] -------N--- | \--* CNS_INT int 4 $44
N004 ( 3, 2) CSE #01 (use)[000009] ----------- \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> $140
***** BB01
STMT00002 ( 0x033[E-] ... 0x04E )
N006 ( 13, 10) [000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 d:2 $VN.Void
N005 ( 9, 7) [000020] ----------- \--* HWINTRINSIC simd16 ubyte Or $1c4
N003 ( 5, 4) [000018] ----------- +--* HWINTRINSIC simd16 ubyte And $1c3
N001 ( 1, 1) [000015] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 $1c2
N002 ( 3, 2) [000017] ----------- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808> $143
N004 ( 3, 2) [000019] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 u:2 (last use) $1c0
***** BB01
STMT00003 ( 0x050[E-] ... 0x05E )
N002 ( 11, 9) [000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1 d:2 $VN.Void
N001 ( 1, 2) [000024] ----------- \--* CNS_INT int 0 $40
***** BB01
STMT00009 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
N002 ( 5, 6) [000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:2->3[+0] $VN.Void
N001 ( 1, 1) [000022] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1 u:1 (last use) $81
***** BB01
STMT00010 ( INL01 @ 0x007[E-] ... ??? ) <- INLRT @ ???
N002 ( 5, 6) [000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:3->4[+16] $VN.Void
N001 ( 1, 1) [000023] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2 u:1 (last use) $82
***** BB01
STMT00005 ( 0x057[--] ... ??? )
N006 ( 14, 14) [000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 d:2 $VN.Void
N005 ( 10, 11) [000033] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup $1c5
N003 ( 6, 8) [000030] -c--------- +--* FIELD_LIST struct $c2
N001 ( 3, 4) [000031] ----------- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 u:4[+0] $81
N002 ( 3, 4) [000032] ----------- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 u:4[+16] (last use) $82
N004 ( 3, 2) [000029] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 u:2 (last use) $1c4
***** BB01
STMT00007 ( 0x093[E-] ... ??? )
N004 ( 5, 4) [000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 d:2 $VN.Void
N003 ( 5, 4) [000061] --------R-- \--* HWINTRINSIC simd16 ubyte VectorTableLookup $1c6
N002 ( 3, 2) [000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010> $144
N001 ( 1, 1) [000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 (last use) $1c2
***** BB01
STMT00008 ( 0x0AD[E-] ... 0x0BA )
N006 ( 8, 7) [000046] ----------- * RETURN simd16 $VN.Void
N005 ( 7, 6) [000045] ----------- \--* HWINTRINSIC simd16 ubyte CompareEqual $1c8
N003 ( 5, 4) [000043] ----------- +--* HWINTRINSIC simd16 ubyte And $1c7
N001 ( 3, 2) [000041] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 u:2 (last use) $1c5
N002 ( 1, 1) [000042] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 $1c6
N004 ( 1, 1) [000044] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 (last use) $1c6
-------------------------------------------------------------------------------------------------------------------
Aggressive CSE Promotion cutoff is 200.000000
Moderate CSE Promotion cutoff is 100.000000
enregCount is 8
Framesize estimate is 0x0020
We have a small frame
Sorted CSE candidates:
CSE #01, {$140, $2 } useCnt=1: [def=100.000000, use=100.000000, cost= 3 ]
:: N002 ( 3, 2) CSE #01 (def)[000002] ----------- * CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> $140
Considering CSE #01 {$140, $2 } [def=100.000000, use=100.000000, cost= 3 ]
CSE Expression :
N002 ( 3, 2) CSE #01 (def)[000002] ----------- * CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> $140
Aggressive CSE Promotion (300.000000 >= 200.000000)
cseRefCnt=300.000000, aggressiveRefCnt=200.000000, moderateRefCnt=100.000000
defCnt=100.000000, useCnt=100.000000, cost=3, size=2
def_cost=1, use_cost=1, extra_no_cost=2, extra_yes_cost=0
CSE cost savings check (302.000000 >= 200.000000) passes
Promoting CSE:
lvaGrabTemp returning 13 (V13 rat0) (a long lifetime temp) called for CSE - aggressive.
CSE #01 is single-def, so associated CSE temp V13 will be in SSA
New refCnts for V13: refCnt = 2, refCntWtd = 2
New refCnts for V13: refCnt = 3, refCntWtd = 3
CSE #01 def at [000002] replaced in BB01 with def of V13
optValnumCSE morphed tree:
N007 ( 10, 9) [000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 d:2 $VN.Void
N006 ( 6, 6) [000003] -A--------- \--* HWINTRINSIC simd16 ubyte And $1c0
N001 ( 1, 1) [000000] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 $80
N005 ( 4, 4) [000067] -A--------- \--* COMMA simd16 $140
N003 ( 3, 3) CSE #01 (def)[000065] DA--------- +--* STORE_LCL_VAR simd16 V13 cse0 d:1 $VN.Void
N002 ( 3, 2) [000002] ----------- | \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> $140
N004 ( 1, 1) [000066] ----------- \--* LCL_VAR simd16 V13 cse0 u:1 $140
Working on the replacement of the CSE #01 use at [000009] in BB01
optValnumCSE morphed tree:
N006 ( 5, 6) [000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 d:2 $VN.Void
N005 ( 5, 6) [000010] ----------- \--* HWINTRINSIC simd16 ubyte And $1c2
N003 ( 3, 4) [000007] ----------- +--* HWINTRINSIC simd16 int ShiftRightLogical $1c1
N001 ( 1, 1) [000005] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 (last use) $80
N002 ( 1, 2) [000006] -------N--- | \--* CNS_INT int 4 $44
N004 ( 1, 1) [000068] ----------- \--* LCL_VAR simd16 V13 cse0 u:1 $140
*************** Finishing PHASE Optimize Valnum CSEs
Trees after Optimize Valnum CSEs
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..0BB) (return), preds={} succs={}
***** BB01
STMT00000 ( 0x000[E-] ... 0x00D )
N007 ( 10, 9) [000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 d:2 $VN.Void
N006 ( 6, 6) [000003] -A--------- \--* HWINTRINSIC simd16 ubyte And $1c0
N001 ( 1, 1) [000000] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 $80
N005 ( 4, 4) [000067] -A--------- \--* COMMA simd16 $140
N003 ( 3, 3) [000065] DA--------- +--* STORE_LCL_VAR simd16 V13 cse0 d:1 $VN.Void
N002 ( 3, 2) [000002] ----------- | \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> $140
N004 ( 1, 1) [000066] ----------- \--* LCL_VAR simd16 V13 cse0 u:1 $140
***** BB01
STMT00001 ( 0x00E[E-] ... 0x02B )
N006 ( 5, 6) [000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 d:2 $VN.Void
N005 ( 5, 6) [000010] ----------- \--* HWINTRINSIC simd16 ubyte And $1c2
N003 ( 3, 4) [000007] ----------- +--* HWINTRINSIC simd16 int ShiftRightLogical $1c1
N001 ( 1, 1) [000005] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 (last use) $80
N002 ( 1, 2) [000006] -------N--- | \--* CNS_INT int 4 $44
N004 ( 1, 1) [000068] ----------- \--* LCL_VAR simd16 V13 cse0 u:1 $140
***** BB01
STMT00002 ( 0x033[E-] ... 0x04E )
N006 ( 13, 10) [000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 d:2 $VN.Void
N005 ( 9, 7) [000020] ----------- \--* HWINTRINSIC simd16 ubyte Or $1c4
N003 ( 5, 4) [000018] ----------- +--* HWINTRINSIC simd16 ubyte And $1c3
N001 ( 1, 1) [000015] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 $1c2
N002 ( 3, 2) [000017] ----------- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808> $143
N004 ( 3, 2) [000019] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 u:2 (last use) $1c0
***** BB01
STMT00003 ( 0x050[E-] ... 0x05E )
N002 ( 11, 9) [000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1 d:2 $VN.Void
N001 ( 1, 2) [000024] ----------- \--* CNS_INT int 0 $40
***** BB01
STMT00009 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
N002 ( 5, 6) [000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:2->3[+0] $VN.Void
N001 ( 1, 1) [000022] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1 u:1 (last use) $81
***** BB01
STMT00010 ( INL01 @ 0x007[E-] ... ??? ) <- INLRT @ ???
N002 ( 5, 6) [000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:3->4[+16] $VN.Void
N001 ( 1, 1) [000023] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2 u:1 (last use) $82
***** BB01
STMT00005 ( 0x057[--] ... ??? )
N006 ( 14, 14) [000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 d:2 $VN.Void
N005 ( 10, 11) [000033] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup $1c5
N003 ( 6, 8) [000030] -c--------- +--* FIELD_LIST struct $c2
N001 ( 3, 4) [000031] ----------- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 u:4[+0] $81
N002 ( 3, 4) [000032] ----------- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 u:4[+16] (last use) $82
N004 ( 3, 2) [000029] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 u:2 (last use) $1c4
***** BB01
STMT00007 ( 0x093[E-] ... ??? )
N004 ( 5, 4) [000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 d:2 $VN.Void
N003 ( 5, 4) [000061] --------R-- \--* HWINTRINSIC simd16 ubyte VectorTableLookup $1c6
N002 ( 3, 2) [000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010> $144
N001 ( 1, 1) [000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 (last use) $1c2
***** BB01
STMT00008 ( 0x0AD[E-] ... 0x0BA )
N006 ( 8, 7) [000046] ----------- * RETURN simd16 $VN.Void
N005 ( 7, 6) [000045] ----------- \--* HWINTRINSIC simd16 ubyte CompareEqual $1c8
N003 ( 5, 4) [000043] ----------- +--* HWINTRINSIC simd16 ubyte And $1c7
N001 ( 3, 2) [000041] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 u:2 (last use) $1c5
N002 ( 1, 1) [000042] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 $1c6
N004 ( 1, 1) [000044] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 (last use) $1c6
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[info] HasGlobalUse overestimated for V00.1
[info] HasGlobalUse overestimated for V01.1
[info] HasGlobalUse overestimated for V02.1
SSA checks completed successfully
*************** In fgDebugCheckLoopTable
Disabling SSA checking before assertion prop
*************** Starting PHASE Assertion prop
*************** Finishing PHASE Assertion prop [no changes]
*************** Starting PHASE Optimize index checks
*************** Finishing PHASE Optimize index checks [no changes]
*************** Starting PHASE VN-based dead store removal
Considering [000004] for removal...
-- no; 'explicit init'
Considering [000011] for removal...
-- no; 'explicit init'
Considering [000034] for removal...
-- no; 'explicit init'
Considering [000040] for removal...
-- no; 'explicit init'
Considering [000021] for removal...
-- no; 'explicit init'
Considering [000025] for removal...
-- no; 'explicit init'
Considering [000049] for removal...
VNForLoad:
VNForMapPhysicalSelect($c1, [0:15]):simd16 returns $141 {Simd16Cns[0x00000000, 0x00000000, 0x00000000, 0x00000000]}
-- no; not redundant
Considering [000052] for removal...
VNForLoad:
select($240 {$c1[0:15] := $81]}, [16:31]) ==> disjoint, remaining budget is 99
VNForMapPhysicalSelect($240, [16:31]):simd16 returns $141 {Simd16Cns[0x00000000, 0x00000000, 0x00000000, 0x00000000]}
-- no; not redundant
*************** Finishing PHASE VN-based dead store removal [no changes]
*************** Starting PHASE Stress gtSplitTree
*************** Finishing PHASE Stress gtSplitTree [no changes]
*************** Starting PHASE Expand runtime lookups
*************** Finishing PHASE Expand runtime lookups [no changes]
*************** Starting PHASE Expand static init
Nothing to expand.
*************** Finishing PHASE Expand static init [no changes]
*************** Starting PHASE Insert GC Polls
*************** Finishing PHASE Insert GC Polls [no changes]
*************** Starting PHASE Optimize bools
*************** In optOptimizeBools()
optimized 0 BBJ_COND cases, 0 BBJ_RETURN cases in 1 passes
*************** Finishing PHASE Optimize bools [no changes]
*************** Starting PHASE If conversion
*************** Finishing PHASE If conversion [no changes]
*************** Starting PHASE Optimize layout
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Optimize layout
Trees after Optimize layout
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..0BB) (return), preds={} succs={}
***** BB01
STMT00000 ( 0x000[E-] ... 0x00D )
N007 ( 10, 9) [000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 d:2 $VN.Void
N006 ( 6, 6) [000003] -A--------- \--* HWINTRINSIC simd16 ubyte And $1c0
N001 ( 1, 1) [000000] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 $80
N005 ( 4, 4) [000067] -A--------- \--* COMMA simd16 $140
N003 ( 3, 3) [000065] DA--------- +--* STORE_LCL_VAR simd16 V13 cse0 d:1 $VN.Void
N002 ( 3, 2) [000002] ----------- | \--* CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> $140
N004 ( 1, 1) [000066] ----------- \--* LCL_VAR simd16 V13 cse0 u:1 $140
***** BB01
STMT00001 ( 0x00E[E-] ... 0x02B )
N006 ( 5, 6) [000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 d:2 $VN.Void
N005 ( 5, 6) [000010] ----------- \--* HWINTRINSIC simd16 ubyte And $1c2
N003 ( 3, 4) [000007] ----------- +--* HWINTRINSIC simd16 int ShiftRightLogical $1c1
N001 ( 1, 1) [000005] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 (last use) $80
N002 ( 1, 2) [000006] -------N--- | \--* CNS_INT int 4 $44
N004 ( 1, 1) [000068] ----------- \--* LCL_VAR simd16 V13 cse0 u:1 $140
***** BB01
STMT00002 ( 0x033[E-] ... 0x04E )
N006 ( 13, 10) [000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 d:2 $VN.Void
N005 ( 9, 7) [000020] ----------- \--* HWINTRINSIC simd16 ubyte Or $1c4
N003 ( 5, 4) [000018] ----------- +--* HWINTRINSIC simd16 ubyte And $1c3
N001 ( 1, 1) [000015] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 $1c2
N002 ( 3, 2) [000017] ----------- | \--* CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808> $143
N004 ( 3, 2) [000019] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 u:2 (last use) $1c0
***** BB01
STMT00003 ( 0x050[E-] ... 0x05E )
N002 ( 11, 9) [000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1 d:2 $VN.Void
N001 ( 1, 2) [000024] ----------- \--* CNS_INT int 0 $40
***** BB01
STMT00009 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ ???
N002 ( 5, 6) [000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:2->3[+0] $VN.Void
N001 ( 1, 1) [000022] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1 u:1 (last use) $81
***** BB01
STMT00010 ( INL01 @ 0x007[E-] ... ??? ) <- INLRT @ ???
N002 ( 5, 6) [000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:3->4[+16] $VN.Void
N001 ( 1, 1) [000023] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2 u:1 (last use) $82
***** BB01
STMT00005 ( 0x057[--] ... ??? )
N006 ( 14, 14) [000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 d:2 $VN.Void
N005 ( 10, 11) [000033] ----------- \--* HWINTRINSIC simd16 ubyte VectorTableLookup $1c5
N003 ( 6, 8) [000030] -c--------- +--* FIELD_LIST struct $c2
N001 ( 3, 4) [000031] ----------- ofs 0 | +--* LCL_FLD simd16 V11 tmp1 u:4[+0] $81
N002 ( 3, 4) [000032] ----------- ofs 16 | \--* LCL_FLD simd16 V11 tmp1 u:4[+16] (last use) $82
N004 ( 3, 2) [000029] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 u:2 (last use) $1c4
***** BB01
STMT00007 ( 0x093[E-] ... ??? )
N004 ( 5, 4) [000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 d:2 $VN.Void
N003 ( 5, 4) [000061] --------R-- \--* HWINTRINSIC simd16 ubyte VectorTableLookup $1c6
N002 ( 3, 2) [000060] ----------- +--* CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010> $144
N001 ( 1, 1) [000037] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 (last use) $1c2
***** BB01
STMT00008 ( 0x0AD[E-] ... 0x0BA )
N006 ( 8, 7) [000046] ----------- * RETURN simd16 $VN.Void
N005 ( 7, 6) [000045] ----------- \--* HWINTRINSIC simd16 ubyte CompareEqual $1c8
N003 ( 5, 4) [000043] ----------- +--* HWINTRINSIC simd16 ubyte And $1c7
N001 ( 3, 2) [000041] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 u:2 (last use) $1c5
N002 ( 1, 1) [000042] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 $1c6
N004 ( 1, 1) [000044] ----------- \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 (last use) $1c6
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid
*************** Starting PHASE Determine first cold block
No procedure splitting will be done for this method
*************** Finishing PHASE Determine first cold block [no changes]
*************** Starting PHASE Rationalize IR
*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..0BB) (return), preds={} succs={}
[000069] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 1, 1) [000000] ----------- t0 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 $80
N002 ( 3, 2) [000002] ----------- t2 = CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> $140
/--* t2 simd16
N003 ( 3, 3) [000065] DA--------- * STORE_LCL_VAR simd16 V13 cse0 d:1 $VN.Void
N004 ( 1, 1) [000066] ----------- t66 = LCL_VAR simd16 V13 cse0 u:1 $140
/--* t0 simd16
+--* t66 simd16
N006 ( 6, 6) [000003] ----------- t3 = * HWINTRINSIC simd16 ubyte And $1c0
/--* t3 simd16
N007 ( 10, 9) [000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 d:2 $VN.Void
[000070] ----------- IL_OFFSET void INLRT @ 0x00E[E-]
N001 ( 1, 1) [000005] ----------- t5 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 (last use) $80
N002 ( 1, 2) [000006] -------N--- t6 = CNS_INT int 4 $44
/--* t5 simd16
+--* t6 int
N003 ( 3, 4) [000007] ----------- t7 = * HWINTRINSIC simd16 int ShiftRightLogical $1c1
N004 ( 1, 1) [000068] ----------- t68 = LCL_VAR simd16 V13 cse0 u:1 $140
/--* t7 simd16
+--* t68 simd16
N005 ( 5, 6) [000010] ----------- t10 = * HWINTRINSIC simd16 ubyte And $1c2
/--* t10 simd16
N006 ( 5, 6) [000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 d:2 $VN.Void
[000071] ----------- IL_OFFSET void INLRT @ 0x033[E-]
N001 ( 1, 1) [000015] ----------- t15 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 $1c2
N002 ( 3, 2) [000017] ----------- t17 = CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808> $143
/--* t15 simd16
+--* t17 simd16
N003 ( 5, 4) [000018] ----------- t18 = * HWINTRINSIC simd16 ubyte And $1c3
N004 ( 3, 2) [000019] ----------- t19 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 u:2 (last use) $1c0
/--* t18 simd16
+--* t19 simd16
N005 ( 9, 7) [000020] ----------- t20 = * HWINTRINSIC simd16 ubyte Or $1c4
/--* t20 simd16
N006 ( 13, 10) [000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 d:2 $VN.Void
[000072] ----------- IL_OFFSET void INLRT @ 0x050[E-]
N001 ( 1, 2) [000024] ----------- t24 = CNS_INT int 0 $40
/--* t24 int
N002 ( 11, 9) [000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1 d:2 $VN.Void
[000073] ----------- IL_OFFSET void INL01 @ 0x000[E-] <- INLRT @ ???
N001 ( 1, 1) [000022] ----------- t22 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1 u:1 (last use) $81
/--* t22 simd16
N002 ( 5, 6) [000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:2->3[+0] $VN.Void
[000074] ----------- IL_OFFSET void INL01 @ 0x007[E-] <- INLRT @ ???
N001 ( 1, 1) [000023] ----------- t23 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2 u:1 (last use) $82
/--* t23 simd16
N002 ( 5, 6) [000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:3->4[+16] $VN.Void
[000075] ----------- IL_OFFSET void INLRT @ 0x057[--]
N001 ( 3, 4) [000031] ----------- t31 = LCL_FLD simd16 V11 tmp1 u:4[+0] $81
N002 ( 3, 4) [000032] ----------- t32 = LCL_FLD simd16 V11 tmp1 u:4[+16] (last use) $82
/--* t31 simd16
+--* t32 simd16
N003 ( 6, 8) [000030] -c--------- t30 = * FIELD_LIST struct $c2
N004 ( 3, 2) [000029] ----------- t29 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 u:2 (last use) $1c4
/--* t30 struct
+--* t29 simd16
N005 ( 10, 11) [000033] ----------- t33 = * HWINTRINSIC simd16 ubyte VectorTableLookup $1c5
/--* t33 simd16
N006 ( 14, 14) [000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 d:2 $VN.Void
[000076] ----------- IL_OFFSET void INLRT @ 0x093[E-]
N001 ( 1, 1) [000037] ----------- t37 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 (last use) $1c2
N002 ( 3, 2) [000060] ----------- t60 = CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010> $144
/--* t60 simd16
+--* t37 simd16
N003 ( 5, 4) [000061] ----------- t61 = * HWINTRINSIC simd16 ubyte VectorTableLookup $1c6
/--* t61 simd16
N004 ( 5, 4) [000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 d:2 $VN.Void
[000077] ----------- IL_OFFSET void INLRT @ 0x0AD[E-]
N001 ( 3, 2) [000041] ----------- t41 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 u:2 (last use) $1c5
N002 ( 1, 1) [000042] ----------- t42 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 $1c6
/--* t41 simd16
+--* t42 simd16
N003 ( 5, 4) [000043] ----------- t43 = * HWINTRINSIC simd16 ubyte And $1c7
N004 ( 1, 1) [000044] ----------- t44 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 (last use) $1c6
/--* t43 simd16
+--* t44 simd16
N005 ( 7, 6) [000045] ----------- t45 = * HWINTRINSIC simd16 ubyte CompareEqual $1c8
/--* t45 simd16
N006 ( 8, 7) [000046] ----------- * RETURN simd16 $VN.Void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid
*************** Starting PHASE Do 'simple' lowering
*************** Finishing PHASE Do 'simple' lowering [no changes]
*************** Starting PHASE Lowering nodeinfo
lowering store lcl var/field (before):
N002 ( 3, 2) [000002] ----------- t2 = CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> $140
/--* t2 simd16
N003 ( 3, 3) [000065] DA--------- * STORE_LCL_VAR simd16 V13 cse0 d:1 $VN.Void
lowering store lcl var/field (after):
N002 ( 3, 2) [000002] ----------- t2 = CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> $140
/--* t2 simd16
N003 ( 3, 3) [000065] DA--------- * STORE_LCL_VAR simd16 V13 cse0 d:1 $VN.Void
lowering store lcl var/field (before):
N001 ( 1, 1) [000000] ----------- t0 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 $80
N002 ( 3, 2) [000002] ----------- t2 = CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> $140
/--* t2 simd16
N003 ( 3, 3) [000065] DA--------- * STORE_LCL_VAR simd16 V13 cse0 d:1 $VN.Void
N004 ( 1, 1) [000066] ----------- t66 = LCL_VAR simd16 V13 cse0 u:1 $140
/--* t0 simd16
+--* t66 simd16
N006 ( 6, 6) [000003] ----------- t3 = * HWINTRINSIC simd16 ubyte And $1c0
/--* t3 simd16
N007 ( 10, 9) [000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 d:2 $VN.Void
lowering store lcl var/field (after):
N001 ( 1, 1) [000000] ----------- t0 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 $80
N002 ( 3, 2) [000002] ----------- t2 = CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> $140
/--* t2 simd16
N003 ( 3, 3) [000065] DA--------- * STORE_LCL_VAR simd16 V13 cse0 d:1 $VN.Void
N004 ( 1, 1) [000066] ----------- t66 = LCL_VAR simd16 V13 cse0 u:1 $140
/--* t0 simd16
+--* t66 simd16
N006 ( 6, 6) [000003] ----------- t3 = * HWINTRINSIC simd16 ubyte And $1c0
/--* t3 simd16
N007 ( 10, 9) [000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 d:2 $VN.Void
lowering store lcl var/field (before):
N001 ( 1, 1) [000005] ----------- t5 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 (last use) $80
N002 ( 1, 2) [000006] -c-----N--- t6 = CNS_INT int 4 $44
/--* t5 simd16
+--* t6 int
N003 ( 3, 4) [000007] ----------- t7 = * HWINTRINSIC simd16 int ShiftRightLogical $1c1
N004 ( 1, 1) [000068] ----------- t68 = LCL_VAR simd16 V13 cse0 u:1 $140
/--* t7 simd16
+--* t68 simd16
N005 ( 5, 6) [000010] ----------- t10 = * HWINTRINSIC simd16 ubyte And $1c2
/--* t10 simd16
N006 ( 5, 6) [000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 d:2 $VN.Void
lowering store lcl var/field (after):
N001 ( 1, 1) [000005] ----------- t5 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 (last use) $80
N002 ( 1, 2) [000006] -c-----N--- t6 = CNS_INT int 4 $44
/--* t5 simd16
+--* t6 int
N003 ( 3, 4) [000007] ----------- t7 = * HWINTRINSIC simd16 int ShiftRightLogical $1c1
N004 ( 1, 1) [000068] ----------- t68 = LCL_VAR simd16 V13 cse0 u:1 $140
/--* t7 simd16
+--* t68 simd16
N005 ( 5, 6) [000010] ----------- t10 = * HWINTRINSIC simd16 ubyte And $1c2
/--* t10 simd16
N006 ( 5, 6) [000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 d:2 $VN.Void
lowering store lcl var/field (before):
N001 ( 1, 1) [000015] ----------- t15 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 $1c2
N002 ( 3, 2) [000017] ----------- t17 = CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808> $143
/--* t15 simd16
+--* t17 simd16
N003 ( 5, 4) [000018] ----------- t18 = * HWINTRINSIC simd16 ubyte And $1c3
N004 ( 3, 2) [000019] ----------- t19 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 u:2 (last use) $1c0
/--* t18 simd16
+--* t19 simd16
N005 ( 9, 7) [000020] ----------- t20 = * HWINTRINSIC simd16 ubyte Or $1c4
/--* t20 simd16
N006 ( 13, 10) [000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 d:2 $VN.Void
lowering store lcl var/field (after):
N001 ( 1, 1) [000015] ----------- t15 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 $1c2
N002 ( 3, 2) [000017] ----------- t17 = CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808> $143
/--* t15 simd16
+--* t17 simd16
N003 ( 5, 4) [000018] ----------- t18 = * HWINTRINSIC simd16 ubyte And $1c3
N004 ( 3, 2) [000019] ----------- t19 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 u:2 (last use) $1c0
/--* t18 simd16
+--* t19 simd16
N005 ( 9, 7) [000020] ----------- t20 = * HWINTRINSIC simd16 ubyte Or $1c4
/--* t20 simd16
N006 ( 13, 10) [000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 d:2 $VN.Void
lowering store lcl var/field (before):
N001 ( 1, 2) [000024] ----------- t24 = CNS_INT int 0 $40
/--* t24 int
N002 ( 11, 9) [000025] DA--------- * STORE_LCL_VAR struct<System.ValueTuple`2, 32> V11 tmp1 d:2 $VN.Void
Local V11 should not be enregistered because: written/read in a block op
lowering store lcl var/field (after):
N001 ( 1, 2) [000024] -c--------- t24 = CNS_INT int 0 $40
[000078] Dc--------- t78 = LCL_ADDR byref V11 tmp1 [+0]
/--* t78 byref
+--* t24 int
N002 ( 11, 9) [000025] sA--------- * STORE_BLK struct<System.ValueTuple`2, 32> (init) (Unroll)
lowering store lcl var/field (before):
N001 ( 1, 1) [000022] ----------- t22 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1 u:1 (last use) $81
/--* t22 simd16
N002 ( 5, 6) [000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:2->3[+0] $VN.Void
lowering store lcl var/field (after):
N001 ( 1, 1) [000022] ----------- t22 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1 u:1 (last use) $81
/--* t22 simd16
N002 ( 5, 6) [000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:2->3[+0] $VN.Void
lowering store lcl var/field (before):
N001 ( 1, 1) [000023] ----------- t23 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2 u:1 (last use) $82
/--* t23 simd16
N002 ( 5, 6) [000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:3->4[+16] $VN.Void
lowering store lcl var/field (after):
N001 ( 1, 1) [000023] ----------- t23 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2 u:1 (last use) $82
/--* t23 simd16
N002 ( 5, 6) [000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:3->4[+16] $VN.Void
lowering store lcl var/field (before):
N001 ( 3, 4) [000031] ----------- t31 = LCL_FLD simd16 V11 tmp1 u:4[+0] $81
N002 ( 3, 4) [000032] ----------- t32 = LCL_FLD simd16 V11 tmp1 u:4[+16] (last use) $82
/--* t31 simd16
+--* t32 simd16
N003 ( 6, 8) [000030] -c--------- t30 = * FIELD_LIST struct $c2
N004 ( 3, 2) [000029] ----------- t29 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 u:2 (last use) $1c4
/--* t30 struct
+--* t29 simd16
N005 ( 10, 11) [000033] ----------- t33 = * HWINTRINSIC simd16 ubyte VectorTableLookup $1c5
/--* t33 simd16
N006 ( 14, 14) [000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 d:2 $VN.Void
lowering store lcl var/field (after):
N001 ( 3, 4) [000031] ----------- t31 = LCL_FLD simd16 V11 tmp1 u:4[+0] $81
N002 ( 3, 4) [000032] ----------- t32 = LCL_FLD simd16 V11 tmp1 u:4[+16] (last use) $82
/--* t31 simd16
+--* t32 simd16
N003 ( 6, 8) [000030] -c--------- t30 = * FIELD_LIST struct $c2
N004 ( 3, 2) [000029] ----------- t29 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 u:2 (last use) $1c4
/--* t30 struct
+--* t29 simd16
N005 ( 10, 11) [000033] ----------- t33 = * HWINTRINSIC simd16 ubyte VectorTableLookup $1c5
/--* t33 simd16
N006 ( 14, 14) [000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 d:2 $VN.Void
lowering store lcl var/field (before):
N001 ( 1, 1) [000037] ----------- t37 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 (last use) $1c2
N002 ( 3, 2) [000060] ----------- t60 = CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010> $144
/--* t60 simd16
+--* t37 simd16
N003 ( 5, 4) [000061] ----------- t61 = * HWINTRINSIC simd16 ubyte VectorTableLookup $1c6
/--* t61 simd16
N004 ( 5, 4) [000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 d:2 $VN.Void
lowering store lcl var/field (after):
N001 ( 1, 1) [000037] ----------- t37 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 (last use) $1c2
N002 ( 3, 2) [000060] ----------- t60 = CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010> $144
/--* t60 simd16
+--* t37 simd16
N003 ( 5, 4) [000061] ----------- t61 = * HWINTRINSIC simd16 ubyte VectorTableLookup $1c6
/--* t61 simd16
N004 ( 5, 4) [000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 d:2 $VN.Void
lowering GT_RETURN
N006 ( 8, 7) [000046] ----------- * RETURN simd16 $VN.Void
============Lower has completed modifying nodes.
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..0BB) (return), preds={} succs={}
[000069] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 1, 1) [000000] ----------- t0 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 $80
N002 ( 3, 2) [000002] ----------- t2 = CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> $140
/--* t2 simd16
N003 ( 3, 3) [000065] DA--------- * STORE_LCL_VAR simd16 V13 cse0 d:1 $VN.Void
N004 ( 1, 1) [000066] ----------- t66 = LCL_VAR simd16 V13 cse0 u:1 $140
/--* t0 simd16
+--* t66 simd16
N006 ( 6, 6) [000003] ----------- t3 = * HWINTRINSIC simd16 ubyte And $1c0
/--* t3 simd16
N007 ( 10, 9) [000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 d:2 $VN.Void
[000070] ----------- IL_OFFSET void INLRT @ 0x00E[E-]
N001 ( 1, 1) [000005] ----------- t5 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 (last use) $80
N002 ( 1, 2) [000006] -c-----N--- t6 = CNS_INT int 4 $44
/--* t5 simd16
+--* t6 int
N003 ( 3, 4) [000007] ----------- t7 = * HWINTRINSIC simd16 int ShiftRightLogical $1c1
N004 ( 1, 1) [000068] ----------- t68 = LCL_VAR simd16 V13 cse0 u:1 $140
/--* t7 simd16
+--* t68 simd16
N005 ( 5, 6) [000010] ----------- t10 = * HWINTRINSIC simd16 ubyte And $1c2
/--* t10 simd16
N006 ( 5, 6) [000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 d:2 $VN.Void
[000071] ----------- IL_OFFSET void INLRT @ 0x033[E-]
N001 ( 1, 1) [000015] ----------- t15 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 $1c2
N002 ( 3, 2) [000017] ----------- t17 = CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808> $143
/--* t15 simd16
+--* t17 simd16
N003 ( 5, 4) [000018] ----------- t18 = * HWINTRINSIC simd16 ubyte And $1c3
N004 ( 3, 2) [000019] ----------- t19 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 u:2 (last use) $1c0
/--* t18 simd16
+--* t19 simd16
N005 ( 9, 7) [000020] ----------- t20 = * HWINTRINSIC simd16 ubyte Or $1c4
/--* t20 simd16
N006 ( 13, 10) [000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 d:2 $VN.Void
[000072] ----------- IL_OFFSET void INLRT @ 0x050[E-]
N001 ( 1, 2) [000024] -c--------- t24 = CNS_INT int 0 $40
[000078] Dc--------- t78 = LCL_ADDR byref V11 tmp1 [+0]
/--* t78 byref
+--* t24 int
N002 ( 11, 9) [000025] sA--------- * STORE_BLK struct<System.ValueTuple`2, 32> (init) (Unroll)
[000073] ----------- IL_OFFSET void INL01 @ 0x000[E-] <- INLRT @ ???
N001 ( 1, 1) [000022] ----------- t22 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1 u:1 (last use) $81
/--* t22 simd16
N002 ( 5, 6) [000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:2->3[+0] $VN.Void
[000074] ----------- IL_OFFSET void INL01 @ 0x007[E-] <- INLRT @ ???
N001 ( 1, 1) [000023] ----------- t23 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2 u:1 (last use) $82
/--* t23 simd16
N002 ( 5, 6) [000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:3->4[+16] $VN.Void
[000075] ----------- IL_OFFSET void INLRT @ 0x057[--]
N001 ( 3, 4) [000031] ----------- t31 = LCL_FLD simd16 V11 tmp1 u:4[+0] $81
N002 ( 3, 4) [000032] ----------- t32 = LCL_FLD simd16 V11 tmp1 u:4[+16] (last use) $82
/--* t31 simd16
+--* t32 simd16
N003 ( 6, 8) [000030] -c--------- t30 = * FIELD_LIST struct $c2
N004 ( 3, 2) [000029] ----------- t29 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 u:2 (last use) $1c4
/--* t30 struct
+--* t29 simd16
N005 ( 10, 11) [000033] ----------- t33 = * HWINTRINSIC simd16 ubyte VectorTableLookup $1c5
/--* t33 simd16
N006 ( 14, 14) [000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 d:2 $VN.Void
[000076] ----------- IL_OFFSET void INLRT @ 0x093[E-]
N001 ( 1, 1) [000037] ----------- t37 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 (last use) $1c2
N002 ( 3, 2) [000060] ----------- t60 = CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010> $144
/--* t60 simd16
+--* t37 simd16
N003 ( 5, 4) [000061] ----------- t61 = * HWINTRINSIC simd16 ubyte VectorTableLookup $1c6
/--* t61 simd16
N004 ( 5, 4) [000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 d:2 $VN.Void
[000077] ----------- IL_OFFSET void INLRT @ 0x0AD[E-]
N001 ( 3, 2) [000041] ----------- t41 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 u:2 (last use) $1c5
N002 ( 1, 1) [000042] ----------- t42 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 $1c6
/--* t41 simd16
+--* t42 simd16
N003 ( 5, 4) [000043] ----------- t43 = * HWINTRINSIC simd16 ubyte And $1c7
N004 ( 1, 1) [000044] ----------- t44 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 (last use) $1c6
/--* t43 simd16
+--* t44 simd16
N005 ( 7, 6) [000045] ----------- t45 = * HWINTRINSIC simd16 ubyte CompareEqual $1c8
/--* t45 simd16
N006 ( 8, 7) [000046] ----------- * RETURN simd16 $VN.Void
-------------------------------------------------------------------------------------------------------------------
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V13: refCnt = 1, refCntWtd = 1
New refCnts for V13: refCnt = 2, refCntWtd = 2
New refCnts for V03: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V13: refCnt = 3, refCntWtd = 3
New refCnts for V04: refCnt = 1, refCntWtd = 1
New refCnts for V04: refCnt = 2, refCntWtd = 2
New refCnts for V03: refCnt = 2, refCntWtd = 2
New refCnts for V07: refCnt = 1, refCntWtd = 1
New refCnts for V11: refCnt = 1, refCntWtd = 2
New refCnts for V01: refCnt = 1, refCntWtd = 1
New refCnts for V11: refCnt = 2, refCntWtd = 4
New refCnts for V02: refCnt = 1, refCntWtd = 1
New refCnts for V11: refCnt = 3, refCntWtd = 6
New refCnts for V11: refCnt = 4, refCntWtd = 8
New refCnts for V11: refCnt = 5, refCntWtd = 10
New refCnts for V07: refCnt = 2, refCntWtd = 2
New refCnts for V05: refCnt = 1, refCntWtd = 1
New refCnts for V04: refCnt = 3, refCntWtd = 3
New refCnts for V06: refCnt = 1, refCntWtd = 1
New refCnts for V05: refCnt = 2, refCntWtd = 2
New refCnts for V06: refCnt = 2, refCntWtd = 2
New refCnts for V06: refCnt = 3, refCntWtd = 3
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 3, refCntWtd = 3
New refCnts for V00: refCnt = 4, refCntWtd = 4
New refCnts for V01: refCnt = 2, refCntWtd = 2
New refCnts for V01: refCnt = 3, refCntWtd = 3
New refCnts for V02: refCnt = 2, refCntWtd = 2
New refCnts for V02: refCnt = 3, refCntWtd = 3
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 arg0 simd16 HFA(simd16) single-def
; V01 arg1 simd16 HFA(simd16) single-def
; V02 arg2 simd16 HFA(simd16) single-def
; V03 loc0 simd16 HFA(simd16)
; V04 loc1 simd16 HFA(simd16)
; V05 loc2 simd16 HFA(simd16)
; V06 loc3 simd16 HFA(simd16)
; V07 loc4 simd16 HFA(simd16)
; V08 loc5 simd16 HFA(simd16)
; V09 loc6 simd16 HFA(simd16)
; V10 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
; V11 tmp1 struct <System.ValueTuple`2, 32> HFA(simd16) do-not-enreg[SF] ld-addr-op "NewObj constructor temp"
; V12 tmp2 simd16 HFA(simd16) "Inline return value spill temp"
; V13 cse0 simd16 "CSE - aggressive"
In fgLocalVarLivenessInit
Local V10 should not be enregistered because: struct size does not match reg size
Local V11 should not be enregistered because: struct size does not match reg size
Tracked variable (10 out of 14) table:
V11 tmp1 [struct]: refCnt = 5, refCntWtd = 10
V00 arg0 [simd16]: refCnt = 4, refCntWtd = 4
V01 arg1 [simd16]: refCnt = 3, refCntWtd = 3
V02 arg2 [simd16]: refCnt = 3, refCntWtd = 3
V04 loc1 [simd16]: refCnt = 3, refCntWtd = 3
V06 loc3 [simd16]: refCnt = 3, refCntWtd = 3
V13 cse0 [simd16]: refCnt = 3, refCntWtd = 3
V03 loc0 [simd16]: refCnt = 2, refCntWtd = 2
V05 loc2 [simd16]: refCnt = 2, refCntWtd = 2
V07 loc4 [simd16]: refCnt = 2, refCntWtd = 2
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(3)={ V00 V01 V02 }
DEF(7)={V11 V04 V06 V13 V03 V05 V07} + ByrefExposed + GcHeap
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (3)={V00 V01 V02}
OUT(0)={ }
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC LIR
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgRemoveDeadBlocks()
Removing unreachable blocks for fgRemoveDeadBlocks iteration #1
*************** In fgDebugCheckBBlist
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V13: refCnt = 1, refCntWtd = 1
New refCnts for V13: refCnt = 2, refCntWtd = 2
New refCnts for V03: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V13: refCnt = 3, refCntWtd = 3
New refCnts for V04: refCnt = 1, refCntWtd = 1
New refCnts for V04: refCnt = 2, refCntWtd = 2
New refCnts for V03: refCnt = 2, refCntWtd = 2
New refCnts for V07: refCnt = 1, refCntWtd = 1
New refCnts for V11: refCnt = 1, refCntWtd = 2
New refCnts for V01: refCnt = 1, refCntWtd = 1
New refCnts for V11: refCnt = 2, refCntWtd = 4
New refCnts for V02: refCnt = 1, refCntWtd = 1
New refCnts for V11: refCnt = 3, refCntWtd = 6
New refCnts for V11: refCnt = 4, refCntWtd = 8
New refCnts for V11: refCnt = 5, refCntWtd = 10
New refCnts for V07: refCnt = 2, refCntWtd = 2
New refCnts for V05: refCnt = 1, refCntWtd = 1
New refCnts for V04: refCnt = 3, refCntWtd = 3
New refCnts for V06: refCnt = 1, refCntWtd = 1
New refCnts for V05: refCnt = 2, refCntWtd = 2
New refCnts for V06: refCnt = 2, refCntWtd = 2
New refCnts for V06: refCnt = 3, refCntWtd = 3
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 3, refCntWtd = 3
New refCnts for V00: refCnt = 4, refCntWtd = 4
New refCnts for V01: refCnt = 2, refCntWtd = 2
New refCnts for V01: refCnt = 3, refCntWtd = 3
New refCnts for V02: refCnt = 2, refCntWtd = 2
New refCnts for V02: refCnt = 3, refCntWtd = 3
*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..0BB) (return), preds={} succs={}
[000069] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 1, 1) [000000] ----------- t0 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 $80
N002 ( 3, 2) [000002] ----------- t2 = CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> $140
/--* t2 simd16
N003 ( 3, 3) [000065] DA--------- * STORE_LCL_VAR simd16 V13 cse0 d:1 $VN.Void
N004 ( 1, 1) [000066] ----------- t66 = LCL_VAR simd16 V13 cse0 u:1 $140
/--* t0 simd16
+--* t66 simd16
N006 ( 6, 6) [000003] ----------- t3 = * HWINTRINSIC simd16 ubyte And $1c0
/--* t3 simd16
N007 ( 10, 9) [000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 d:2 $VN.Void
[000070] ----------- IL_OFFSET void INLRT @ 0x00E[E-]
N001 ( 1, 1) [000005] ----------- t5 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 (last use) $80
N002 ( 1, 2) [000006] -c-----N--- t6 = CNS_INT int 4 $44
/--* t5 simd16
+--* t6 int
N003 ( 3, 4) [000007] ----------- t7 = * HWINTRINSIC simd16 int ShiftRightLogical $1c1
N004 ( 1, 1) [000068] ----------- t68 = LCL_VAR simd16 V13 cse0 u:1 (last use) $140
/--* t7 simd16
+--* t68 simd16
N005 ( 5, 6) [000010] ----------- t10 = * HWINTRINSIC simd16 ubyte And $1c2
/--* t10 simd16
N006 ( 5, 6) [000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 d:2 $VN.Void
[000071] ----------- IL_OFFSET void INLRT @ 0x033[E-]
N001 ( 1, 1) [000015] ----------- t15 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 $1c2
N002 ( 3, 2) [000017] ----------- t17 = CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808> $143
/--* t15 simd16
+--* t17 simd16
N003 ( 5, 4) [000018] ----------- t18 = * HWINTRINSIC simd16 ubyte And $1c3
N004 ( 3, 2) [000019] ----------- t19 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 u:2 (last use) $1c0
/--* t18 simd16
+--* t19 simd16
N005 ( 9, 7) [000020] ----------- t20 = * HWINTRINSIC simd16 ubyte Or $1c4
/--* t20 simd16
N006 ( 13, 10) [000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 d:2 $VN.Void
[000072] ----------- IL_OFFSET void INLRT @ 0x050[E-]
N001 ( 1, 2) [000024] -c--------- t24 = CNS_INT int 0 $40
[000078] Dc--------- t78 = LCL_ADDR byref V11 tmp1 [+0]
/--* t78 byref
+--* t24 int
N002 ( 11, 9) [000025] sA--------- * STORE_BLK struct<System.ValueTuple`2, 32> (init) (Unroll)
[000073] ----------- IL_OFFSET void INL01 @ 0x000[E-] <- INLRT @ ???
N001 ( 1, 1) [000022] ----------- t22 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1 u:1 (last use) $81
/--* t22 simd16
N002 ( 5, 6) [000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:2->3[+0] $VN.Void
[000074] ----------- IL_OFFSET void INL01 @ 0x007[E-] <- INLRT @ ???
N001 ( 1, 1) [000023] ----------- t23 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2 u:1 (last use) $82
/--* t23 simd16
N002 ( 5, 6) [000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:3->4[+16] $VN.Void
[000075] ----------- IL_OFFSET void INLRT @ 0x057[--]
N001 ( 3, 4) [000031] ----------- t31 = LCL_FLD simd16 V11 tmp1 u:4[+0] $81
N002 ( 3, 4) [000032] ----------- t32 = LCL_FLD simd16 V11 tmp1 u:4[+16] (last use) $82
/--* t31 simd16
+--* t32 simd16
N003 ( 6, 8) [000030] -c--------- t30 = * FIELD_LIST struct $c2
N004 ( 3, 2) [000029] ----------- t29 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 u:2 (last use) $1c4
/--* t30 struct
+--* t29 simd16
N005 ( 10, 11) [000033] ----------- t33 = * HWINTRINSIC simd16 ubyte VectorTableLookup $1c5
/--* t33 simd16
N006 ( 14, 14) [000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 d:2 $VN.Void
[000076] ----------- IL_OFFSET void INLRT @ 0x093[E-]
N001 ( 1, 1) [000037] ----------- t37 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 (last use) $1c2
N002 ( 3, 2) [000060] ----------- t60 = CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010> $144
/--* t60 simd16
+--* t37 simd16
N003 ( 5, 4) [000061] ----------- t61 = * HWINTRINSIC simd16 ubyte VectorTableLookup $1c6
/--* t61 simd16
N004 ( 5, 4) [000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 d:2 $VN.Void
[000077] ----------- IL_OFFSET void INLRT @ 0x0AD[E-]
N001 ( 3, 2) [000041] ----------- t41 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 u:2 (last use) $1c5
N002 ( 1, 1) [000042] ----------- t42 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 $1c6
/--* t41 simd16
+--* t42 simd16
N003 ( 5, 4) [000043] ----------- t43 = * HWINTRINSIC simd16 ubyte And $1c7
N004 ( 1, 1) [000044] ----------- t44 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 (last use) $1c6
/--* t43 simd16
+--* t44 simd16
N005 ( 7, 6) [000045] ----------- t45 = * HWINTRINSIC simd16 ubyte CompareEqual $1c8
/--* t45 simd16
N006 ( 8, 7) [000046] ----------- * RETURN simd16 $VN.Void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid
*************** Starting PHASE Calculate stack level slots
*************** Finishing PHASE Calculate stack level slots [no changes]
*************** Starting PHASE Linear scan register alloc
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01
use: {V00 V01 V02}
def: {V03 V04 V05 V06 V07 V11 V13}
in: {V00 V01 V02}
out: {}
Interval 0: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
Interval 0: (V00) simd16 RefPositions {} physReg:NA Preferences=[allFloat]
Interval 1: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
Interval 1: (V01) simd16 RefPositions {} physReg:NA Preferences=[allFloat]
Interval 2: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
Interval 2: (V02) simd16 RefPositions {} physReg:NA Preferences=[allFloat]
Interval 3: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
Interval 3: (V03) simd16 RefPositions {} physReg:NA Preferences=[allFloat]
Interval 4: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
Interval 4: (V04) simd16 RefPositions {} physReg:NA Preferences=[allFloat]
Interval 5: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
Interval 5: (V05) simd16 RefPositions {} physReg:NA Preferences=[allFloat]
Interval 6: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
Interval 6: (V06) simd16 RefPositions {} physReg:NA Preferences=[allFloat]
Interval 7: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
Interval 7: (V07) simd16 RefPositions {} physReg:NA Preferences=[allFloat]
Local V11 should not be enregistered because: struct size does not match reg size
Interval 8: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
Interval 8: (V13) simd16 RefPositions {} physReg:NA Preferences=[allFloat]
Interval 9: double RefPositions {} physReg:NA Preferences=[allFloat]
Interval 10: double RefPositions {} physReg:NA Preferences=[allFloat]
Interval 11: double RefPositions {} physReg:NA Preferences=[allFloat]
Interval 12: double RefPositions {} physReg:NA Preferences=[allFloat]
Interval 13: double RefPositions {} physReg:NA Preferences=[allFloat]
Interval 14: double RefPositions {} physReg:NA Preferences=[allFloat]
Interval 15: double RefPositions {} physReg:NA Preferences=[allFloat]
Interval 16: double RefPositions {} physReg:NA Preferences=[allFloat]
Interval 17: double RefPositions {} physReg:NA Preferences=[allFloat]
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = false, singleExit = true
; Decided to create an EBP based frame for ETW stackwalking (IL Code Size)
*************** In lvaAssignFrameOffsets(REGALLOC_FRAME_LAYOUT)
Setting genSaveFpLrWithAllCalleeSavedRegisters to false
Pad V00 arg0, size=16, stkOffs=-0x90, pad=0
Assign V00 arg0, size=16, stkOffs=-0xa0
Pad V01 arg1, size=16, stkOffs=-0xa0, pad=0
Assign V01 arg1, size=16, stkOffs=-0xb0
Pad V02 arg2, size=16, stkOffs=-0xb0, pad=0
Assign V02 arg2, size=16, stkOffs=-0xc0
Pad V03 loc0, size=16, stkOffs=-0xc0, pad=0
Assign V03 loc0, size=16, stkOffs=-0xd0
Pad V04 loc1, size=16, stkOffs=-0xd0, pad=0
Assign V04 loc1, size=16, stkOffs=-0xe0
Pad V05 loc2, size=16, stkOffs=-0xe0, pad=0
Assign V05 loc2, size=16, stkOffs=-0xf0
Pad V06 loc3, size=16, stkOffs=-0xf0, pad=0
Assign V06 loc3, size=16, stkOffs=-0x100
Pad V07 loc4, size=16, stkOffs=-0x100, pad=0
Assign V07 loc4, size=16, stkOffs=-0x110
Pad V08 loc5, size=16, stkOffs=-0x110, pad=0
Assign V08 loc5, size=16, stkOffs=-0x120
Pad V09 loc6, size=16, stkOffs=-0x120, pad=0
Assign V09 loc6, size=16, stkOffs=-0x130
Pad V11 tmp1, size=32, stkOffs=-0x137, pad=7
Assign V11 tmp1, size=32, stkOffs=-0x157
Pad V12 tmp2, size=16, stkOffs=-0x166, pad=15
Assign V12 tmp2, size=16, stkOffs=-0x176
Pad V13 cse0, size=16, stkOffs=-0x185, pad=15
Assign V13 cse0, size=16, stkOffs=-0x195
--- delta bump 456 for FP frame
--- virtual stack offset to actual stack offset delta is 456
-- V00 was -160, now 296
-- V01 was -176, now 280
-- V02 was -192, now 264
-- V03 was -208, now 248
-- V04 was -224, now 232
-- V05 was -240, now 216
-- V06 was -256, now 200
-- V07 was -272, now 184
-- V08 was -288, now 168
-- V09 was -304, now 152
-- V10 was 0, now 456
-- V11 was -343, now 113
-- V12 was -374, now 82
-- V13 was -405, now 51
compRsvdRegCheck
frame size = 456
compArgSize = 48
Returning true (ARM64)
Reserved REG_OPT_RSVD (xip1) due to large frame
TUPLE STYLE DUMP BEFORE LSRA
Start LSRA Block Sequence:
Current block: BB01
Final LSRA Block Sequence:
BB01 ( 1 )
BB01 [000..0BB) (return), preds={} succs={}
=====
N000. IL_OFFSET INLRT @ 0x000[E-]
N001. V00(t0)
N002. t2 = CNS_VEC <0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
N003. V13(t65); t2
N004. V13(t66)
N006. t3 = HWINTRINSIC; t0,t66
N007. V03(t4); t3
N000. IL_OFFSET INLRT @ 0x00E[E-]
N001. V00(t5*)
N002. CNS_INT 4
N003. t7 = HWINTRINSIC; t5*
N004. V13(t68*)
N005. t10 = HWINTRINSIC; t7,t68*
N006. V04(t11); t10
N000. IL_OFFSET INLRT @ 0x033[E-]
N001. V04(t15)
N002. t17 = CNS_VEC <0x08080808, 0x08080808, 0x08080808, 0x08080808>
N003. t18 = HWINTRINSIC; t15,t17
N004. V03(t19*)
N005. t20 = HWINTRINSIC; t18,t19*
N006. V07(t21); t20
N000. IL_OFFSET INLRT @ 0x050[E-]
N001. CNS_INT 0
N000. LCL_ADDR V11 tmp1 [+0]
N002. STORE_BLK
N000. IL_OFFSET INL01 @ 0x000[E-] <- INLRT @ ???
N001. V01(t22*)
N002. V11 MEM; t22*
N000. IL_OFFSET INL01 @ 0x007[E-] <- INLRT @ ???
N001. V02(t23*)
N002. V11 MEM; t23*
N000. IL_OFFSET INLRT @ 0x057[--]
N001. t31 = V11 MEM
N002. t32 = V11 MEM
N003. t30 = FIELD_LIST; t31,t32
N004. V07(t29*)
N005. t33 = HWINTRINSIC; t30,t29*
N006. V05(t34); t33
N000. IL_OFFSET INLRT @ 0x093[E-]
N001. V04(t37*)
N002. t60 = CNS_VEC <0x08040201, 0x80402010, 0x08040201, 0x80402010>
N003. t61 = HWINTRINSIC; t60,t37*
N004. V06(t40); t61
N000. IL_OFFSET INLRT @ 0x0AD[E-]
N001. V05(t41*)
N002. V06(t42)
N003. t43 = HWINTRINSIC; t41*,t42
N004. V06(t44*)
N005. t45 = HWINTRINSIC; t43,t44*
N006. RETURN ; t45
buildIntervals second part ========
Float arg V00 in reg d0
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[d0] minReg=1 fixed wt=100.00>
Float arg V01 in reg d1
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[d1] minReg=1 fixed wt=100.00>
Float arg V02 in reg d2
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[d2] minReg=1 fixed wt=100.00>
NEW BLOCK BB01
<RefPosition #3 @1 RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
DefList: { }
N003 (???,???) [000069] ----------- * IL_OFFSET void INLRT @ 0x000[E-] REG NA
DefList: { }
N005 ( 1, 1) [000000] ----------- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 NA REG NA $80
DefList: { }
N007 ( 3, 2) [000002] ----------- * CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> REG NA $140
Interval 18: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28]
<RefPosition #4 @7 RefTypeDef <Ivl:18 internal> CNS_VEC BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #5 @7 RefTypeUse <Ivl:18 internal> CNS_VEC BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00>
Interval 19: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #6 @8 RefTypeDef <Ivl:19> CNS_VEC BB01 regmask=[allFloat] minReg=1 wt=400.00>
DefList: { N007.t2. CNS_VEC }
N009 ( 3, 3) [000065] DA--------- * STORE_LCL_VAR simd16 V13 cse0 d:1 NA REG NA $VN.Void
<RefPosition #7 @9 RefTypeUse <Ivl:19> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
Assigning related <V13/L8> to <I19>
<RefPosition #8 @10 RefTypeDef <Ivl:8 V13> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
DefList: { }
N011 ( 1, 1) [000066] ----------- * LCL_VAR simd16 V13 cse0 u:1 NA REG NA $140
DefList: { }
N013 ( 6, 6) [000003] ----------- * HWINTRINSIC simd16 ubyte And REG NA $1c0
<RefPosition #9 @13 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=400.00>
<RefPosition #10 @13 RefTypeUse <Ivl:8 V13> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
Interval 20: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #11 @14 RefTypeDef <Ivl:20> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
DefList: { N013.t3. HWINTRINSIC }
N015 ( 10, 9) [000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 d:2 NA REG NA $VN.Void
<RefPosition #12 @15 RefTypeUse <Ivl:20> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
Assigning related <V03/L3> to <I20>
<RefPosition #13 @16 RefTypeDef <Ivl:3 V03> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=200.00>
DefList: { }
N017 (???,???) [000070] ----------- * IL_OFFSET void INLRT @ 0x00E[E-] REG NA
DefList: { }
N019 ( 1, 1) [000005] ----------- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 NA (last use) REG NA $80
DefList: { }
N021 ( 1, 2) [000006] -c-----N--- * CNS_INT int 4 REG NA $44
Contained
DefList: { }
N023 ( 3, 4) [000007] ----------- * HWINTRINSIC simd16 int ShiftRightLogical REG NA $1c1
<RefPosition #14 @23 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=400.00>
Interval 21: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #15 @24 RefTypeDef <Ivl:21> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
DefList: { N023.t7. HWINTRINSIC }
N025 ( 1, 1) [000068] ----------- * LCL_VAR simd16 V13 cse0 u:1 NA (last use) REG NA $140
DefList: { N023.t7. HWINTRINSIC }
N027 ( 5, 6) [000010] ----------- * HWINTRINSIC simd16 ubyte And REG NA $1c2
<RefPosition #16 @27 RefTypeUse <Ivl:21> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #17 @27 RefTypeUse <Ivl:8 V13> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
Interval 22: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #18 @28 RefTypeDef <Ivl:22> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
DefList: { N027.t10. HWINTRINSIC }
N029 ( 5, 6) [000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 d:2 NA REG NA $VN.Void
<RefPosition #19 @29 RefTypeUse <Ivl:22> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
Assigning related <V04/L4> to <I22>
<RefPosition #20 @30 RefTypeDef <Ivl:4 V04> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
DefList: { }
N031 (???,???) [000071] ----------- * IL_OFFSET void INLRT @ 0x033[E-] REG NA
DefList: { }
N033 ( 1, 1) [000015] ----------- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 NA REG NA $1c2
DefList: { }
N035 ( 3, 2) [000017] ----------- * CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808> REG NA $143
Interval 23: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28]
<RefPosition #21 @35 RefTypeDef <Ivl:23 internal> CNS_VEC BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #22 @35 RefTypeUse <Ivl:23 internal> CNS_VEC BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00>
Interval 24: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #23 @36 RefTypeDef <Ivl:24> CNS_VEC BB01 regmask=[allFloat] minReg=1 wt=400.00>
DefList: { N035.t17. CNS_VEC }
N037 ( 5, 4) [000018] ----------- * HWINTRINSIC simd16 ubyte And REG NA $1c3
<RefPosition #24 @37 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
<RefPosition #25 @37 RefTypeUse <Ivl:24> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
Interval 25: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #26 @38 RefTypeDef <Ivl:25> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
DefList: { N037.t18. HWINTRINSIC }
N039 ( 3, 2) [000019] ----------- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 u:2 NA (last use) REG NA $1c0
DefList: { N037.t18. HWINTRINSIC }
N041 ( 9, 7) [000020] ----------- * HWINTRINSIC simd16 ubyte Or REG NA $1c4
<RefPosition #27 @41 RefTypeUse <Ivl:25> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #28 @41 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=200.00>
Interval 26: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #29 @42 RefTypeDef <Ivl:26> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
DefList: { N041.t20. HWINTRINSIC }
N043 ( 13, 10) [000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 d:2 NA REG NA $VN.Void
<RefPosition #30 @43 RefTypeUse <Ivl:26> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
Assigning related <V07/L7> to <I26>
<RefPosition #31 @44 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=200.00>
DefList: { }
N045 (???,???) [000072] ----------- * IL_OFFSET void INLRT @ 0x050[E-] REG NA
DefList: { }
N047 ( 1, 2) [000024] -c--------- * CNS_INT int 0 REG NA $40
Contained
DefList: { }
N049 (???,???) [000078] Dc--------- * LCL_ADDR byref V11 tmp1 [+0] NA REG NA
Contained
DefList: { }
N051 ( 11, 9) [000025] sA--------- * STORE_BLK struct<System.ValueTuple`2, 32> (init) (Unroll) REG NA
Interval 27: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28]
<RefPosition #32 @51 RefTypeDef <Ivl:27 internal> STORE_BLK BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
Interval 28: float RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #33 @51 RefTypeDef <Ivl:28 internal> STORE_BLK BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #34 @51 RefTypeUse <Ivl:27 internal> STORE_BLK BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00>
<RefPosition #35 @51 RefTypeUse <Ivl:28 internal> STORE_BLK BB01 regmask=[allFloat] minReg=1 last wt=400.00>
DefList: { }
N053 (???,???) [000073] ----------- * IL_OFFSET void INL01 @ 0x000[E-] <- INLRT @ ??? REG NA
DefList: { }
N055 ( 1, 1) [000022] ----------- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1 u:1 NA (last use) REG NA $81
DefList: { }
N057 ( 5, 6) [000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:2->3[+0] NA REG NA $VN.Void
<RefPosition #36 @57 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
DefList: { }
N059 (???,???) [000074] ----------- * IL_OFFSET void INL01 @ 0x007[E-] <- INLRT @ ??? REG NA
DefList: { }
N061 ( 1, 1) [000023] ----------- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2 u:1 NA (last use) REG NA $82
DefList: { }
N063 ( 5, 6) [000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:3->4[+16] NA REG NA $VN.Void
<RefPosition #37 @63 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
DefList: { }
N065 (???,???) [000075] ----------- * IL_OFFSET void INLRT @ 0x057[--] REG NA
DefList: { }
N067 ( 3, 4) [000031] ----------- * LCL_FLD simd16 V11 tmp1 u:4[+0] NA REG NA $81
Interval 29: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #38 @68 RefTypeDef <Ivl:29> LCL_FLD BB01 regmask=[allFloat] minReg=1 wt=400.00>
DefList: { N067.t31. LCL_FLD }
N069 ( 3, 4) [000032] ----------- * LCL_FLD simd16 V11 tmp1 u:4[+16] NA (last use) REG NA $82
Interval 30: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #39 @70 RefTypeDef <Ivl:30> LCL_FLD BB01 regmask=[allFloat] minReg=1 wt=400.00>
DefList: { N067.t31. LCL_FLD; N069.t32. LCL_FLD }
N071 ( 6, 8) [000030] -c--------- * FIELD_LIST struct REG NA $c2
Contained
DefList: { N067.t31. LCL_FLD; N069.t32. LCL_FLD }
N073 ( 3, 2) [000029] ----------- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 u:2 NA (last use) REG NA $1c4
DefList: { N067.t31. LCL_FLD; N069.t32. LCL_FLD }
N075 ( 10, 11) [000033] ----------- * HWINTRINSIC simd16 ubyte VectorTableLookup REG NA $1c5
<RefPosition #40 @75 RefTypeUse <Ivl:29> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #41 @75 RefTypeUse <Ivl:30> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #42 @75 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=200.00>
Interval 31: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #43 @76 RefTypeDef <Ivl:31> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
DefList: { N075.t33. HWINTRINSIC }
N077 ( 14, 14) [000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 d:2 NA REG NA $VN.Void
<RefPosition #44 @77 RefTypeUse <Ivl:31> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
Assigning related <V05/L5> to <I31>
<RefPosition #45 @78 RefTypeDef <Ivl:5 V05> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=200.00>
DefList: { }
N079 (???,???) [000076] ----------- * IL_OFFSET void INLRT @ 0x093[E-] REG NA
DefList: { }
N081 ( 1, 1) [000037] ----------- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 NA (last use) REG NA $1c2
DefList: { }
N083 ( 3, 2) [000060] ----------- * CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010> REG NA $144
Interval 32: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28]
<RefPosition #46 @83 RefTypeDef <Ivl:32 internal> CNS_VEC BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #47 @83 RefTypeUse <Ivl:32 internal> CNS_VEC BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00>
Interval 33: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #48 @84 RefTypeDef <Ivl:33> CNS_VEC BB01 regmask=[allFloat] minReg=1 wt=400.00>
DefList: { N083.t60. CNS_VEC }
N085 ( 5, 4) [000061] ----------- * HWINTRINSIC simd16 ubyte VectorTableLookup REG NA $1c6
<RefPosition #49 @85 RefTypeUse <Ivl:33> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #50 @85 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
Interval 34: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #51 @86 RefTypeDef <Ivl:34> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
DefList: { N085.t61. HWINTRINSIC }
N087 ( 5, 4) [000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 d:2 NA REG NA $VN.Void
<RefPosition #52 @87 RefTypeUse <Ivl:34> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
Assigning related <V06/L6> to <I34>
<RefPosition #53 @88 RefTypeDef <Ivl:6 V06> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
DefList: { }
N089 (???,???) [000077] ----------- * IL_OFFSET void INLRT @ 0x0AD[E-] REG NA
DefList: { }
N091 ( 3, 2) [000041] ----------- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 u:2 NA (last use) REG NA $1c5
DefList: { }
N093 ( 1, 1) [000042] ----------- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 NA REG NA $1c6
DefList: { }
N095 ( 5, 4) [000043] ----------- * HWINTRINSIC simd16 ubyte And REG NA $1c7
<RefPosition #54 @95 RefTypeUse <Ivl:5 V05> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=200.00>
<RefPosition #55 @95 RefTypeUse <Ivl:6 V06> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
Interval 35: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #56 @96 RefTypeDef <Ivl:35> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
DefList: { N095.t43. HWINTRINSIC }
N097 ( 1, 1) [000044] ----------- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 NA (last use) REG NA $1c6
DefList: { N095.t43. HWINTRINSIC }
N099 ( 7, 6) [000045] ----------- * HWINTRINSIC simd16 ubyte CompareEqual REG NA $1c8
<RefPosition #57 @99 RefTypeUse <Ivl:35> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #58 @99 RefTypeUse <Ivl:6 V06> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
Interval 36: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #59 @100 RefTypeDef <Ivl:36> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
DefList: { N099.t45. HWINTRINSIC }
N101 ( 8, 7) [000046] ----------- * RETURN simd16 REG NA $VN.Void
<RefPosition #60 @101 RefTypeFixedReg <Reg:d0 > BB01 regmask=[d0] minReg=1 wt=100.00>
<RefPosition #61 @101 RefTypeUse <Ivl:36> BB01 regmask=[d0] minReg=1 last fixed wt=100.00>
CHECKING LAST USES for BB01, liveout={}
==============================
use: {V00 V01 V02}
def: {V03 V04 V05 V06 V07 V11 V13}
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: (V00) simd16 RefPositions {#0@0 #9@13 #14@23} physReg:d0 Preferences=[d0]
Interval 1: (V01) simd16 RefPositions {#1@0 #36@57} physReg:d1 Preferences=[d1]
Interval 2: (V02) simd16 RefPositions {#2@0 #37@63} physReg:d2 Preferences=[d2]
Interval 3: (V03) simd16 RefPositions {#13@16 #28@41} physReg:NA Preferences=[allFloat]
Interval 4: (V04) simd16 RefPositions {#20@30 #24@37 #50@85} physReg:NA Preferences=[allFloat]
Interval 5: (V05) simd16 RefPositions {#45@78 #54@95} physReg:NA Preferences=[allFloat]
Interval 6: (V06) simd16 RefPositions {#53@88 #55@95 #58@99} physReg:NA Preferences=[allFloat]
Interval 7: (V07) simd16 RefPositions {#31@44 #42@75} physReg:NA Preferences=[allFloat]
Interval 8: (V13) simd16 RefPositions {#8@10 #10@13 #17@27} physReg:NA Preferences=[allFloat]
Interval 9: (U00) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V00/L0>
Interval 10: (U01) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V01/L1>
Interval 11: (U02) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V02/L2>
Interval 12: (U04) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V04/L4>
Interval 13: (U06) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V06/L6>
Interval 14: (U13) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V13/L8>
Interval 15: (U03) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V03/L3>
Interval 16: (U05) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V05/L5>
Interval 17: (U07) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V07/L7>
Interval 18: int (INTERNAL) RefPositions {#4@7 #5@7} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 19: simd16 (constant) RefPositions {#6@8 #7@9} physReg:NA Preferences=[allFloat] RelatedInterval <V13/L8>
Interval 20: simd16 RefPositions {#11@14 #12@15} physReg:NA Preferences=[allFloat] RelatedInterval <V03/L3>
Interval 21: simd16 RefPositions {#15@24 #16@27} physReg:NA Preferences=[allFloat]
Interval 22: simd16 RefPositions {#18@28 #19@29} physReg:NA Preferences=[allFloat] RelatedInterval <V04/L4>
Interval 23: int (INTERNAL) RefPositions {#21@35 #22@35} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 24: simd16 (constant) RefPositions {#23@36 #25@37} physReg:NA Preferences=[allFloat]
Interval 25: simd16 RefPositions {#26@38 #27@41} physReg:NA Preferences=[allFloat]
Interval 26: simd16 RefPositions {#29@42 #30@43} physReg:NA Preferences=[allFloat] RelatedInterval <V07/L7>
Interval 27: int (INTERNAL) RefPositions {#32@51 #34@51} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 28: float (INTERNAL) RefPositions {#33@51 #35@51} physReg:NA Preferences=[allFloat]
Interval 29: simd16 RefPositions {#38@68 #40@75} physReg:NA Preferences=[allFloat]
Interval 30: simd16 RefPositions {#39@70 #41@75} physReg:NA Preferences=[allFloat]
Interval 31: simd16 RefPositions {#43@76 #44@77} physReg:NA Preferences=[allFloat] RelatedInterval <V05/L5>
Interval 32: int (INTERNAL) RefPositions {#46@83 #47@83} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 33: simd16 (constant) RefPositions {#48@84 #49@85} physReg:NA Preferences=[allFloat]
Interval 34: simd16 RefPositions {#51@86 #52@87} physReg:NA Preferences=[allFloat] RelatedInterval <V06/L6>
Interval 35: simd16 RefPositions {#56@96 #57@99} physReg:NA Preferences=[allFloat]
Interval 36: simd16 RefPositions {#59@100 #61@101} physReg:NA Preferences=[d0]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[d0] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[d1] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[d2] minReg=1 fixed regOptional wt=100.00>
<RefPosition #3 @1 RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #4 @7 RefTypeDef <Ivl:18 internal> CNS_VEC BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #5 @7 RefTypeUse <Ivl:18 internal> CNS_VEC BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00>
<RefPosition #6 @8 RefTypeDef <Ivl:19> CNS_VEC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #7 @9 RefTypeUse <Ivl:19> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #8 @10 RefTypeDef <Ivl:8 V13> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #9 @13 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #10 @13 RefTypeUse <Ivl:8 V13> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #11 @14 RefTypeDef <Ivl:20> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #12 @15 RefTypeUse <Ivl:20> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #13 @16 RefTypeDef <Ivl:3 V03> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=200.00>
<RefPosition #14 @23 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=400.00>
<RefPosition #15 @24 RefTypeDef <Ivl:21> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #16 @27 RefTypeUse <Ivl:21> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #17 @27 RefTypeUse <Ivl:8 V13> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
<RefPosition #18 @28 RefTypeDef <Ivl:22> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #19 @29 RefTypeUse <Ivl:22> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #20 @30 RefTypeDef <Ivl:4 V04> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #21 @35 RefTypeDef <Ivl:23 internal> CNS_VEC BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #22 @35 RefTypeUse <Ivl:23 internal> CNS_VEC BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00>
<RefPosition #23 @36 RefTypeDef <Ivl:24> CNS_VEC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #24 @37 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #25 @37 RefTypeUse <Ivl:24> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #26 @38 RefTypeDef <Ivl:25> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #27 @41 RefTypeUse <Ivl:25> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #28 @41 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=200.00>
<RefPosition #29 @42 RefTypeDef <Ivl:26> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #30 @43 RefTypeUse <Ivl:26> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #31 @44 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=200.00>
<RefPosition #32 @51 RefTypeDef <Ivl:27 internal> STORE_BLK BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #33 @51 RefTypeDef <Ivl:28 internal> STORE_BLK BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #34 @51 RefTypeUse <Ivl:27 internal> STORE_BLK BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00>
<RefPosition #35 @51 RefTypeUse <Ivl:28 internal> STORE_BLK BB01 regmask=[allFloat] minReg=1 last wt=400.00>
<RefPosition #36 @57 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
<RefPosition #37 @63 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
<RefPosition #38 @68 RefTypeDef <Ivl:29> LCL_FLD BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #39 @70 RefTypeDef <Ivl:30> LCL_FLD BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #40 @75 RefTypeUse <Ivl:29> BB01 regmask=[allFloat] minReg=2 last wt=100.00>
<RefPosition #41 @75 RefTypeUse <Ivl:30> BB01 regmask=[allFloat] minReg=2 last wt=100.00>
<RefPosition #42 @75 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=200.00>
<RefPosition #43 @76 RefTypeDef <Ivl:31> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #44 @77 RefTypeUse <Ivl:31> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #45 @78 RefTypeDef <Ivl:5 V05> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=200.00>
<RefPosition #46 @83 RefTypeDef <Ivl:32 internal> CNS_VEC BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #47 @83 RefTypeUse <Ivl:32 internal> CNS_VEC BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00>
<RefPosition #48 @84 RefTypeDef <Ivl:33> CNS_VEC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #49 @85 RefTypeUse <Ivl:33> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #50 @85 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
<RefPosition #51 @86 RefTypeDef <Ivl:34> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #52 @87 RefTypeUse <Ivl:34> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #53 @88 RefTypeDef <Ivl:6 V06> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #54 @95 RefTypeUse <Ivl:5 V05> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=200.00>
<RefPosition #55 @95 RefTypeUse <Ivl:6 V06> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #56 @96 RefTypeDef <Ivl:35> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #57 @99 RefTypeUse <Ivl:35> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #58 @99 RefTypeUse <Ivl:6 V06> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
<RefPosition #59 @100 RefTypeDef <Ivl:36> HWINTRINSIC BB01 regmask=[d0] minReg=1 wt=400.00>
<RefPosition #60 @101 RefTypeFixedReg <Reg:d0 > BB01 regmask=[d0] minReg=1 wt=100.00>
<RefPosition #61 @101 RefTypeUse <Ivl:36> BB01 regmask=[d0] minReg=1 last fixed wt=100.00>
------------
REFPOSITIONS DURING VALIDATE INTERVALS (RefPositions per interval)
------------
-----------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[d0] minReg=1 fixed regOptional wt=100.00>
<RefPosition #9 @13 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #14 @23 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=400.00>
-----------------
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[d1] minReg=1 fixed regOptional wt=100.00>
<RefPosition #36 @57 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
-----------------
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[d2] minReg=1 fixed regOptional wt=100.00>
<RefPosition #37 @63 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
-----------------
<RefPosition #20 @30 RefTypeDef <Ivl:4 V04> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #24 @37 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #50 @85 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
-----------------
<RefPosition #53 @88 RefTypeDef <Ivl:6 V06> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #55 @95 RefTypeUse <Ivl:6 V06> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #58 @99 RefTypeUse <Ivl:6 V06> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
-----------------
<RefPosition #8 @10 RefTypeDef <Ivl:8 V13> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #10 @13 RefTypeUse <Ivl:8 V13> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #17 @27 RefTypeUse <Ivl:8 V13> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
-----------------
<RefPosition #13 @16 RefTypeDef <Ivl:3 V03> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=200.00>
<RefPosition #28 @41 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=200.00>
-----------------
<RefPosition #45 @78 RefTypeDef <Ivl:5 V05> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=200.00>
<RefPosition #54 @95 RefTypeUse <Ivl:5 V05> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=200.00>
-----------------
<RefPosition #31 @44 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=200.00>
<RefPosition #42 @75 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=200.00>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters: V00 V01 V02
BB01 [000..0BB) (return), preds={} succs={}
=====
N003. IL_OFFSET INLRT @ 0x000[E-]
N005. V00(L0)
N007. CNS_VEC <0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
Def:<T18>(#4)
Use:<T18>(#5) *
Def:<I19>(#6) Pref:<V13/L8>
N009. V13(L8)
Use:<I19>(#7) *
Def:<V13/L8>(#8)
N011. V13(L8)
N013. HWINTRINSIC
Use:<V00/L0>(#9)
Use:<V13/L8>(#10)
Def:<I20>(#11) Pref:<V03/L3>
N015. V03(L3)
Use:<I20>(#12) *
Def:<V03/L3>(#13)
N017. IL_OFFSET INLRT @ 0x00E[E-]
N019. V00(L0)
N021. CNS_INT 4
N023. HWINTRINSIC
Use:<V00/L0>(#14) *
Def:<I21>(#15)
N025. V13(L8)
N027. HWINTRINSIC
Use:<I21>(#16) *
Use:<V13/L8>(#17) *
Def:<I22>(#18) Pref:<V04/L4>
N029. V04(L4)
Use:<I22>(#19) *
Def:<V04/L4>(#20)
N031. IL_OFFSET INLRT @ 0x033[E-]
N033. V04(L4)
N035. CNS_VEC <0x08080808, 0x08080808, 0x08080808, 0x08080808>
Def:<T23>(#21)
Use:<T23>(#22) *
Def:<I24>(#23)
N037. HWINTRINSIC
Use:<V04/L4>(#24)
Use:<I24>(#25) *
Def:<I25>(#26)
N039. V03(L3)
N041. HWINTRINSIC
Use:<I25>(#27) *
Use:<V03/L3>(#28) *
Def:<I26>(#29) Pref:<V07/L7>
N043. V07(L7)
Use:<I26>(#30) *
Def:<V07/L7>(#31)
N045. IL_OFFSET INLRT @ 0x050[E-]
N047. CNS_INT 0
N049. LCL_ADDR V11 tmp1 [+0] NA
N051. STORE_BLK
Def:<T27>(#32)
Def:<T28>(#33)
Use:<T27>(#34) *
Use:<T28>(#35) *
N053. IL_OFFSET INL01 @ 0x000[E-] <- INLRT @ ???
N055. V01(L1)
N057. V11 MEM
Use:<V01/L1>(#36) *
N059. IL_OFFSET INL01 @ 0x007[E-] <- INLRT @ ???
N061. V02(L2)
N063. V11 MEM
Use:<V02/L2>(#37) *
N065. IL_OFFSET INLRT @ 0x057[--]
N067. V11 MEM
Def:<I29>(#38)
N069. V11 MEM
Def:<I30>(#39)
N071. FIELD_LIST
N073. V07(L7)
N075. HWINTRINSIC
Use:<I29>(#40) *
Use:<I30>(#41) *
Use:<V07/L7>(#42) *
Def:<I31>(#43) Pref:<V05/L5>
N077. V05(L5)
Use:<I31>(#44) *
Def:<V05/L5>(#45)
N079. IL_OFFSET INLRT @ 0x093[E-]
N081. V04(L4)
N083. CNS_VEC <0x08040201, 0x80402010, 0x08040201, 0x80402010>
Def:<T32>(#46)
Use:<T32>(#47) *
Def:<I33>(#48)
N085. HWINTRINSIC
Use:<I33>(#49) *
Use:<V04/L4>(#50) *
Def:<I34>(#51) Pref:<V06/L6>
N087. V06(L6)
Use:<I34>(#52) *
Def:<V06/L6>(#53)
N089. IL_OFFSET INLRT @ 0x0AD[E-]
N091. V05(L5)
N093. V06(L6)
N095. HWINTRINSIC
Use:<V05/L5>(#54) *
Use:<V06/L6>(#55)
Def:<I35>(#56)
N097. V06(L6)
N099. HWINTRINSIC
Use:<I35>(#57) *
Use:<V06/L6>(#58) *
Def:<I36>(#59)
N101. RETURN
Use:<I36>(#61) Fixed:d0(#60) *
Linear scan intervals after buildIntervals:
Interval 0: (V00) simd16 RefPositions {#0@0 #9@13 #14@23} physReg:d0 Preferences=[d0]
Interval 1: (V01) simd16 RefPositions {#1@0 #36@57} physReg:d1 Preferences=[d1]
Interval 2: (V02) simd16 RefPositions {#2@0 #37@63} physReg:d2 Preferences=[d2]
Interval 3: (V03) simd16 RefPositions {#13@16 #28@41} physReg:NA Preferences=[allFloat]
Interval 4: (V04) simd16 RefPositions {#20@30 #24@37 #50@85} physReg:NA Preferences=[allFloat]
Interval 5: (V05) simd16 RefPositions {#45@78 #54@95} physReg:NA Preferences=[allFloat]
Interval 6: (V06) simd16 RefPositions {#53@88 #55@95 #58@99} physReg:NA Preferences=[allFloat]
Interval 7: (V07) simd16 RefPositions {#31@44 #42@75} physReg:NA Preferences=[allFloat]
Interval 8: (V13) simd16 RefPositions {#8@10 #10@13 #17@27} physReg:NA Preferences=[allFloat]
Interval 9: (U00) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V00/L0>
Interval 10: (U01) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V01/L1>
Interval 11: (U02) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V02/L2>
Interval 12: (U04) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V04/L4>
Interval 13: (U06) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V06/L6>
Interval 14: (U13) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V13/L8>
Interval 15: (U03) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V03/L3>
Interval 16: (U05) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V05/L5>
Interval 17: (U07) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V07/L7>
Interval 18: int (INTERNAL) RefPositions {#4@7 #5@7} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 19: simd16 (constant) RefPositions {#6@8 #7@9} physReg:NA Preferences=[allFloat] RelatedInterval <V13/L8>
Interval 20: simd16 RefPositions {#11@14 #12@15} physReg:NA Preferences=[allFloat] RelatedInterval <V03/L3>
Interval 21: simd16 RefPositions {#15@24 #16@27} physReg:NA Preferences=[allFloat]
Interval 22: simd16 RefPositions {#18@28 #19@29} physReg:NA Preferences=[allFloat] RelatedInterval <V04/L4>
Interval 23: int (INTERNAL) RefPositions {#21@35 #22@35} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 24: simd16 (constant) RefPositions {#23@36 #25@37} physReg:NA Preferences=[allFloat]
Interval 25: simd16 RefPositions {#26@38 #27@41} physReg:NA Preferences=[allFloat]
Interval 26: simd16 RefPositions {#29@42 #30@43} physReg:NA Preferences=[allFloat] RelatedInterval <V07/L7>
Interval 27: int (INTERNAL) RefPositions {#32@51 #34@51} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 28: float (INTERNAL) RefPositions {#33@51 #35@51} physReg:NA Preferences=[allFloat]
Interval 29: simd16 RefPositions {#38@68 #40@75} physReg:NA Preferences=[allFloat]
Interval 30: simd16 RefPositions {#39@70 #41@75} physReg:NA Preferences=[allFloat]
Interval 31: simd16 RefPositions {#43@76 #44@77} physReg:NA Preferences=[allFloat] RelatedInterval <V05/L5>
Interval 32: int (INTERNAL) RefPositions {#46@83 #47@83} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 33: simd16 (constant) RefPositions {#48@84 #49@85} physReg:NA Preferences=[allFloat]
Interval 34: simd16 RefPositions {#51@86 #52@87} physReg:NA Preferences=[allFloat] RelatedInterval <V06/L6>
Interval 35: simd16 RefPositions {#56@96 #57@99} physReg:NA Preferences=[allFloat]
Interval 36: simd16 RefPositions {#59@100 #61@101} physReg:NA Preferences=[d0]
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: (V00) simd16 RefPositions {#0@0 #9@13 #14@23} physReg:d0 Preferences=[d0]
Interval 1: (V01) simd16 RefPositions {#1@0 #36@57} physReg:d1 Preferences=[d1]
Interval 2: (V02) simd16 RefPositions {#2@0 #37@63} physReg:d2 Preferences=[d2]
Interval 3: (V03) simd16 RefPositions {#13@16 #28@41} physReg:NA Preferences=[allFloat]
Interval 4: (V04) simd16 RefPositions {#20@30 #24@37 #50@85} physReg:NA Preferences=[allFloat]
Interval 5: (V05) simd16 RefPositions {#45@78 #54@95} physReg:NA Preferences=[allFloat]
Interval 6: (V06) simd16 RefPositions {#53@88 #55@95 #58@99} physReg:NA Preferences=[allFloat]
Interval 7: (V07) simd16 RefPositions {#31@44 #42@75} physReg:NA Preferences=[allFloat]
Interval 8: (V13) simd16 RefPositions {#8@10 #10@13 #17@27} physReg:NA Preferences=[allFloat]
Interval 9: (U00) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V00/L0>
Interval 10: (U01) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V01/L1>
Interval 11: (U02) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V02/L2>
Interval 12: (U04) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V04/L4>
Interval 13: (U06) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V06/L6>
Interval 14: (U13) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V13/L8>
Interval 15: (U03) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V03/L3>
Interval 16: (U05) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V05/L5>
Interval 17: (U07) double RefPositions {} physReg:NA Preferences=[allFloat] RelatedInterval <V07/L7>
Interval 18: int (INTERNAL) RefPositions {#4@7 #5@7} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 19: simd16 (constant) RefPositions {#6@8 #7@9} physReg:NA Preferences=[allFloat] RelatedInterval <V13/L8>
Interval 20: simd16 RefPositions {#11@14 #12@15} physReg:NA Preferences=[allFloat] RelatedInterval <V03/L3>
Interval 21: simd16 RefPositions {#15@24 #16@27} physReg:NA Preferences=[allFloat]
Interval 22: simd16 RefPositions {#18@28 #19@29} physReg:NA Preferences=[allFloat] RelatedInterval <V04/L4>
Interval 23: int (INTERNAL) RefPositions {#21@35 #22@35} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 24: simd16 (constant) RefPositions {#23@36 #25@37} physReg:NA Preferences=[allFloat]
Interval 25: simd16 RefPositions {#26@38 #27@41} physReg:NA Preferences=[allFloat]
Interval 26: simd16 RefPositions {#29@42 #30@43} physReg:NA Preferences=[allFloat] RelatedInterval <V07/L7>
Interval 27: int (INTERNAL) RefPositions {#32@51 #34@51} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 28: float (INTERNAL) RefPositions {#33@51 #35@51} physReg:NA Preferences=[allFloat]
Interval 29: simd16 RefPositions {#38@68 #40@75} physReg:NA Preferences=[allFloat]
Interval 30: simd16 RefPositions {#39@70 #41@75} physReg:NA Preferences=[allFloat]
Interval 31: simd16 RefPositions {#43@76 #44@77} physReg:NA Preferences=[allFloat] RelatedInterval <V05/L5>
Interval 32: int (INTERNAL) RefPositions {#46@83 #47@83} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 33: simd16 (constant) RefPositions {#48@84 #49@85} physReg:NA Preferences=[allFloat]
Interval 34: simd16 RefPositions {#51@86 #52@87} physReg:NA Preferences=[allFloat] RelatedInterval <V06/L6>
Interval 35: simd16 RefPositions {#56@96 #57@99} physReg:NA Preferences=[allFloat]
Interval 36: simd16 RefPositions {#59@100 #61@101} physReg:NA Preferences=[d0]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[d0] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[d1] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[d2] minReg=1 fixed regOptional wt=100.00>
<RefPosition #3 @1 RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #4 @7 RefTypeDef <Ivl:18 internal> CNS_VEC BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #5 @7 RefTypeUse <Ivl:18 internal> CNS_VEC BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00>
<RefPosition #6 @8 RefTypeDef <Ivl:19> CNS_VEC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #7 @9 RefTypeUse <Ivl:19> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #8 @10 RefTypeDef <Ivl:8 V13> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #9 @13 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #10 @13 RefTypeUse <Ivl:8 V13> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #11 @14 RefTypeDef <Ivl:20> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #12 @15 RefTypeUse <Ivl:20> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #13 @16 RefTypeDef <Ivl:3 V03> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=200.00>
<RefPosition #14 @23 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=400.00>
<RefPosition #15 @24 RefTypeDef <Ivl:21> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #16 @27 RefTypeUse <Ivl:21> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #17 @27 RefTypeUse <Ivl:8 V13> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
<RefPosition #18 @28 RefTypeDef <Ivl:22> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #19 @29 RefTypeUse <Ivl:22> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #20 @30 RefTypeDef <Ivl:4 V04> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #21 @35 RefTypeDef <Ivl:23 internal> CNS_VEC BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #22 @35 RefTypeUse <Ivl:23 internal> CNS_VEC BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00>
<RefPosition #23 @36 RefTypeDef <Ivl:24> CNS_VEC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #24 @37 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #25 @37 RefTypeUse <Ivl:24> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #26 @38 RefTypeDef <Ivl:25> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #27 @41 RefTypeUse <Ivl:25> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #28 @41 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=200.00>
<RefPosition #29 @42 RefTypeDef <Ivl:26> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #30 @43 RefTypeUse <Ivl:26> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #31 @44 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=200.00>
<RefPosition #32 @51 RefTypeDef <Ivl:27 internal> STORE_BLK BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #33 @51 RefTypeDef <Ivl:28 internal> STORE_BLK BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #34 @51 RefTypeUse <Ivl:27 internal> STORE_BLK BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00>
<RefPosition #35 @51 RefTypeUse <Ivl:28 internal> STORE_BLK BB01 regmask=[allFloat] minReg=1 last wt=400.00>
<RefPosition #36 @57 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
<RefPosition #37 @63 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
<RefPosition #38 @68 RefTypeDef <Ivl:29> LCL_FLD BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #39 @70 RefTypeDef <Ivl:30> LCL_FLD BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #40 @75 RefTypeUse <Ivl:29> BB01 regmask=[allFloat] minReg=2 last wt=100.00>
<RefPosition #41 @75 RefTypeUse <Ivl:30> BB01 regmask=[allFloat] minReg=2 last wt=100.00>
<RefPosition #42 @75 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=200.00>
<RefPosition #43 @76 RefTypeDef <Ivl:31> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #44 @77 RefTypeUse <Ivl:31> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #45 @78 RefTypeDef <Ivl:5 V05> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=200.00>
<RefPosition #46 @83 RefTypeDef <Ivl:32 internal> CNS_VEC BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #47 @83 RefTypeUse <Ivl:32 internal> CNS_VEC BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00>
<RefPosition #48 @84 RefTypeDef <Ivl:33> CNS_VEC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #49 @85 RefTypeUse <Ivl:33> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #50 @85 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
<RefPosition #51 @86 RefTypeDef <Ivl:34> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #52 @87 RefTypeUse <Ivl:34> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #53 @88 RefTypeDef <Ivl:6 V06> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #54 @95 RefTypeUse <Ivl:5 V05> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=200.00>
<RefPosition #55 @95 RefTypeUse <Ivl:6 V06> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #56 @96 RefTypeDef <Ivl:35> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #57 @99 RefTypeUse <Ivl:35> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #58 @99 RefTypeUse <Ivl:6 V06> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
<RefPosition #59 @100 RefTypeDef <Ivl:36> HWINTRINSIC BB01 regmask=[d0] minReg=1 wt=400.00>
<RefPosition #60 @101 RefTypeFixedReg <Reg:d0 > BB01 regmask=[d0] minReg=1 wt=100.00>
<RefPosition #61 @101 RefTypeUse <Ivl:36> BB01 regmask=[d0] minReg=1 last fixed wt=100.00>
VAR REFPOSITIONS BEFORE ALLOCATION
--- V00 (Interval 0)
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[d0] minReg=1 fixed regOptional wt=100.00>
<RefPosition #9 @13 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #14 @23 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=400.00>
--- V01 (Interval 1)
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[d1] minReg=1 fixed regOptional wt=100.00>
<RefPosition #36 @57 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
--- V02 (Interval 2)
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[d2] minReg=1 fixed regOptional wt=100.00>
<RefPosition #37 @63 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
--- V03 (Interval 3)
<RefPosition #13 @16 RefTypeDef <Ivl:3 V03> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=200.00>
<RefPosition #28 @41 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=200.00>
--- V04 (Interval 4)
<RefPosition #20 @30 RefTypeDef <Ivl:4 V04> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #24 @37 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #50 @85 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
--- V05 (Interval 5)
<RefPosition #45 @78 RefTypeDef <Ivl:5 V05> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=200.00>
<RefPosition #54 @95 RefTypeUse <Ivl:5 V05> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=200.00>
--- V06 (Interval 6)
<RefPosition #53 @88 RefTypeDef <Ivl:6 V06> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #55 @95 RefTypeUse <Ivl:6 V06> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #58 @99 RefTypeUse <Ivl:6 V06> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
--- V07 (Interval 7)
<RefPosition #31 @44 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=200.00>
<RefPosition #42 @75 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=200.00>
--- V08
--- V09
--- V10
--- V11
--- V12
--- V13 (Interval 8)
<RefPosition #8 @10 RefTypeDef <Ivl:8 V13> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #10 @13 RefTypeUse <Ivl:8 V13> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #17 @27 RefTypeUse <Ivl:8 V13> LCL_VAR BB01 regmask=[allFloat] minReg=1 last wt=300.00>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The columns are: (1) Loc: LSRA location, (2) RP#: RefPosition number, (3) Name, (4) Type (e.g. Def, Use,
Fixd, Parm, DDef (Dummy Def), ExpU (Exposed Use), Kill) followed by a '*' if it is a last use, and a 'D'
if it is delayRegFree, (5) Action taken during allocation. Some actions include (a) Alloc a new register,
(b) Keep an existing register, (c) Spill a register, (d) ReLod (Reload) a register. If an ALL-CAPS name
such as COVRS is displayed, it is a score name from lsra_score.h, with a trailing '(A)' indicating alloc,
'(C)' indicating copy, and '(R)' indicating re-use. See dumpLsraAllocationEvent() for details.
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, 'p' if it is a large vector that has been partially spilled, and 'i' if it is inactive.
Columns are only printed up to the last modified register, which may increase during allocation,
in which case additional columns will appear. Registers which are not marked modified have ---- in
their column.
-------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 |d0 |d1 |d2 |d8 |d9 |
-------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
| | | | | | | | | | |V0 a|V1 a|V2 a| | |
0.#0 V0 Parm Keep d0 | | | | | | | | | | |V0 a|V1 a|V2 a| | |
0.#1 V1 Parm Keep d1 | | | | | | | | | | |V0 a|V1 a|V2 a| | |
0.#2 V2 Parm Keep d2 | | | | | | | | | | |V0 a|V1 a|V2 a| | |
1.#3 BB1 PredBB0 | | | | | | | | | | |V0 a|V1 a|V2 a| | |
[000002] 7.#4 I18 Def ORDER(A) x0 |I18a| | | | | | | | | |V0 a|V1 a|V2 a| | |
7.#5 I18 Use * Keep x0 |I18a| | | | | | | | | |V0 a|V1 a|V2 a| | |
-------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 |d0 |d1 |d2 |d8 |d9 |d16 |
-------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
8.#6 C19 Def ORDER(A) d16 | | | | | | | | | | |V0 a|V1 a|V2 a| | |C19a|
[000065] 9.#7 C19 Use * Keep d16 | | | | | | | | | | |V0 a|V1 a|V2 a| | |C19a|
10.#8 V13 Def COVRS(A) d16 | | | | | | | | | | |V0 a|V1 a|V2 a| | |V13a|
[000003] 13.#9 V0 Use Keep d0 | | | | | | | | | | |V0 a|V1 a|V2 a| | |V13a|
13.#10 V13 Use Keep d16 | | | | | | | | | | |V0 a|V1 a|V2 a| | |V13a|
-------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 |d0 |d1 |d2 |d8 |d9 |d16 |d17 |
-------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
14.#11 I20 Def ORDER(A) d17 | | | | | | | | | | |V0 a|V1 a|V2 a| | |V13a|I20a|
[000004] 15.#12 I20 Use * Keep d17 | | | | | | | | | | |V0 a|V1 a|V2 a| | |V13a|I20a|
16.#13 V3 Def COVRS(A) d17 | | | | | | | | | | |V0 a|V1 a|V2 a| | |V13a|V3 a|
[000007] 23.#14 V0 Use * Keep d0 | | | | | | | | | | |V0 a|V1 a|V2 a| | |V13a|V3 a|
24.#15 I21 Def BSFIT(A) d0 | | | | | | | | | | |I21a|V1 a|V2 a| | |V13a|V3 a|
[000010] 27.#16 I21 Use * Keep d0 | | | | | | | | | | |I21a|V1 a|V2 a| | |V13a|V3 a|
27.#17 V13 Use * Keep d16 | | | | | | | | | | |I21a|V1 a|V2 a| | |V13a|V3 a|
28.#18 I22 Def BSFIT(A) d0 | | | | | | | | | | |I22a|V1 a|V2 a| | | |V3 a|
[000011] 29.#19 I22 Use * Keep d0 | | | | | | | | | | |I22a|V1 a|V2 a| | | |V3 a|
30.#20 V4 Def COVRS(A) d0 | | | | | | | | | | |V4 a|V1 a|V2 a| | | |V3 a|
[000017] 35.#21 I23 Def ORDER(A) x0 |I23a| | | | | | | | | |V4 a|V1 a|V2 a| | | |V3 a|
35.#22 I23 Use * Keep x0 |I23a| | | | | | | | | |V4 a|V1 a|V2 a| | | |V3 a|
36.#23 C24 Def ORDER(A) d16 | | | | | | | | | | |V4 a|V1 a|V2 a| | |C24a|V3 a|
[000018] 37.#24 V4 Use Keep d0 | | | | | | | | | | |V4 a|V1 a|V2 a| | |C24a|V3 a|
37.#25 C24 Use * Keep d16 | | | | | | | | | | |V4 a|V1 a|V2 a| | |C24a|V3 a|
38.#26 I25 Def ORDER(A) d16 | | | | | | | | | | |V4 a|V1 a|V2 a| | |I25a|V3 a|
[000020] 41.#27 I25 Use * Keep d16 | | | | | | | | | | |V4 a|V1 a|V2 a| | |I25a|V3 a|
41.#28 V3 Use * Keep d17 | | | | | | | | | | |V4 a|V1 a|V2 a| | |I25a|V3 a|
42.#29 I26 Def ORDER(A) d16 | | | | | | | | | | |V4 a|V1 a|V2 a| | |I26a| |
[000021] 43.#30 I26 Use * Keep d16 | | | | | | | | | | |V4 a|V1 a|V2 a| | |I26a| |
44.#31 V7 Def COVRS(A) d16 | | | | | | | | | | |V4 a|V1 a|V2 a| | |V7 a| |
[000025] 51.#32 I27 Def ORDER(A) x0 |I27a| | | | | | | | | |V4 a|V1 a|V2 a| | |V7 a| |
51.#33 I28 Def ORDER(A) d17 |I27a| | | | | | | | | |V4 a|V1 a|V2 a| | |V7 a|I28a|
51.#34 I27 Use * Keep x0 |I27a| | | | | | | | | |V4 a|V1 a|V2 a| | |V7 a|I28a|
51.#35 I28 Use * Keep d17 |I27a| | | | | | | | | |V4 a|V1 a|V2 a| | |V7 a|I28a|
[000049] 57.#36 V1 Use * Keep d1 | | | | | | | | | | |V4 a|V1 a|V2 a| | |V7 a| |
[000052] 63.#37 V2 Use * Keep d2 | | | | | | | | | | |V4 a| |V2 a| | |V7 a| |
[000031] 68.#38 I29 Def ORDER(A) d17 | | | | | | | | | | |V4 a| | | | |V7 a|I29a|
-------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 |d0 |d1 |d2 |d8 |d9 |d16 |d17 |d18 |
-------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
[000032] 70.#39 I30 Def ORDER(A) d18 | | | | | | | | | | |V4 a| | | | |V7 a|I29a|I30a|
[000033] 75.#40 I29 Use * Keep d17 | | | | | | | | | | |V4 a| | | | |V7 a|I29a|I30a|
75.#41 I30 Use * Keep d18 | | | | | | | | | | |V4 a| | | | |V7 a|I29a|I30a|
75.#42 V7 Use * Keep d16 | | | | | | | | | | |V4 a| | | | |V7 a|I29a|I30a|
76.#43 I31 Def ORDER(A) d16 | | | | | | | | | | |V4 a| | | | |I31a| | |
[000034] 77.#44 I31 Use * Keep d16 | | | | | | | | | | |V4 a| | | | |I31a| | |
78.#45 V5 Def COVRS(A) d16 | | | | | | | | | | |V4 a| | | | |V5 a| | |
[000060] 83.#46 I32 Def ORDER(A) x0 |I32a| | | | | | | | | |V4 a| | | | |V5 a| | |
83.#47 I32 Use * Keep x0 |I32a| | | | | | | | | |V4 a| | | | |V5 a| | |
84.#48 C33 Def ORDER(A) d17 | | | | | | | | | | |V4 a| | | | |V5 a|C33a| |
[000061] 85.#49 C33 Use * Keep d17 | | | | | | | | | | |V4 a| | | | |V5 a|C33a| |
85.#50 V4 Use * Keep d0 | | | | | | | | | | |V4 a| | | | |V5 a|C33a| |
86.#51 I34 Def BSFIT(A) d0 | | | | | | | | | | |I34a| | | | |V5 a|C33i| |
[000040] 87.#52 I34 Use * Keep d0 | | | | | | | | | | |I34a| | | | |V5 a|C33i| |
88.#53 V6 Def COVRS(A) d0 | | | | | | | | | | |V6 a| | | | |V5 a|C33i| |
[000043] 95.#54 V5 Use * Keep d16 | | | | | | | | | | |V6 a| | | | |V5 a|C33i| |
95.#55 V6 Use Keep d0 | | | | | | | | | | |V6 a| | | | |V5 a|C33i| |
96.#56 I35 Def ORDER(A) d16 | | | | | | | | | | |V6 a| | | | |I35a|C33i| |
[000045] 99.#57 I35 Use * Keep d16 | | | | | | | | | | |V6 a| | | | |I35a|C33i| |
99.#58 V6 Use * Keep d0 | | | | | | | | | | |V6 a| | | | |I35a|C33i| |
100.#59 I36 Def Alloc d0 | | | | | | | | | | |I36a| | | | | |C33i| |
[000046] 101.#60 d0 Fixd Keep d0 | | | | | | | | | | |I36a| | | | | |C33i| |
101.#61 I36 Use * Keep d0 | | | | | | | | | | | | | | | | |C33i| |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[d0] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[d1] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[d2] minReg=1 fixed regOptional wt=100.00>
<RefPosition #3 @1 RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #4 @7 RefTypeDef <Ivl:18 internal> CNS_VEC BB01 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #5 @7 RefTypeUse <Ivl:18 internal> CNS_VEC BB01 regmask=[x0] minReg=1 last wt=400.00>
<RefPosition #6 @8 RefTypeDef <Ivl:19> CNS_VEC BB01 regmask=[d16] minReg=1 wt=400.00>
<RefPosition #7 @9 RefTypeUse <Ivl:19> BB01 regmask=[d16] minReg=1 last wt=100.00>
<RefPosition #8 @10 RefTypeDef <Ivl:8 V13> STORE_LCL_VAR BB01 regmask=[d16] minReg=1 wt=300.00>
<RefPosition #9 @13 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[d0] minReg=1 wt=400.00>
<RefPosition #10 @13 RefTypeUse <Ivl:8 V13> LCL_VAR BB01 regmask=[d16] minReg=1 wt=300.00>
<RefPosition #11 @14 RefTypeDef <Ivl:20> HWINTRINSIC BB01 regmask=[d17] minReg=1 wt=400.00>
<RefPosition #12 @15 RefTypeUse <Ivl:20> BB01 regmask=[d17] minReg=1 last wt=100.00>
<RefPosition #13 @16 RefTypeDef <Ivl:3 V03> STORE_LCL_VAR BB01 regmask=[d17] minReg=1 wt=200.00>
<RefPosition #14 @23 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[d0] minReg=1 last wt=400.00>
<RefPosition #15 @24 RefTypeDef <Ivl:21> HWINTRINSIC BB01 regmask=[d0] minReg=1 wt=400.00>
<RefPosition #16 @27 RefTypeUse <Ivl:21> BB01 regmask=[d0] minReg=1 last wt=100.00>
<RefPosition #17 @27 RefTypeUse <Ivl:8 V13> LCL_VAR BB01 regmask=[d16] minReg=1 last wt=300.00>
<RefPosition #18 @28 RefTypeDef <Ivl:22> HWINTRINSIC BB01 regmask=[d0] minReg=1 wt=400.00>
<RefPosition #19 @29 RefTypeUse <Ivl:22> BB01 regmask=[d0] minReg=1 last wt=100.00>
<RefPosition #20 @30 RefTypeDef <Ivl:4 V04> STORE_LCL_VAR BB01 regmask=[d0] minReg=1 wt=300.00>
<RefPosition #21 @35 RefTypeDef <Ivl:23 internal> CNS_VEC BB01 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #22 @35 RefTypeUse <Ivl:23 internal> CNS_VEC BB01 regmask=[x0] minReg=1 last wt=400.00>
<RefPosition #23 @36 RefTypeDef <Ivl:24> CNS_VEC BB01 regmask=[d16] minReg=1 wt=400.00>
<RefPosition #24 @37 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[d0] minReg=1 wt=300.00>
<RefPosition #25 @37 RefTypeUse <Ivl:24> BB01 regmask=[d16] minReg=1 last wt=100.00>
<RefPosition #26 @38 RefTypeDef <Ivl:25> HWINTRINSIC BB01 regmask=[d16] minReg=1 wt=400.00>
<RefPosition #27 @41 RefTypeUse <Ivl:25> BB01 regmask=[d16] minReg=1 last wt=100.00>
<RefPosition #28 @41 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[d17] minReg=1 last wt=200.00>
<RefPosition #29 @42 RefTypeDef <Ivl:26> HWINTRINSIC BB01 regmask=[d16] minReg=1 wt=400.00>
<RefPosition #30 @43 RefTypeUse <Ivl:26> BB01 regmask=[d16] minReg=1 last wt=100.00>
<RefPosition #31 @44 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[d16] minReg=1 wt=200.00>
<RefPosition #32 @51 RefTypeDef <Ivl:27 internal> STORE_BLK BB01 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #33 @51 RefTypeDef <Ivl:28 internal> STORE_BLK BB01 regmask=[d17] minReg=1 wt=400.00>
<RefPosition #34 @51 RefTypeUse <Ivl:27 internal> STORE_BLK BB01 regmask=[x0] minReg=1 last wt=400.00>
<RefPosition #35 @51 RefTypeUse <Ivl:28 internal> STORE_BLK BB01 regmask=[d17] minReg=1 last wt=400.00>
<RefPosition #36 @57 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[d1] minReg=1 last wt=300.00>
<RefPosition #37 @63 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[d2] minReg=1 last wt=300.00>
<RefPosition #38 @68 RefTypeDef <Ivl:29> LCL_FLD BB01 regmask=[d17] minReg=1 wt=400.00>
<RefPosition #39 @70 RefTypeDef <Ivl:30> LCL_FLD BB01 regmask=[d18] minReg=1 wt=400.00>
<RefPosition #40 @75 RefTypeUse <Ivl:29> BB01 regmask=[d17] minReg=2 last wt=100.00>
<RefPosition #41 @75 RefTypeUse <Ivl:30> BB01 regmask=[d18] minReg=2 last wt=100.00>
<RefPosition #42 @75 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[d16] minReg=1 last wt=200.00>
<RefPosition #43 @76 RefTypeDef <Ivl:31> HWINTRINSIC BB01 regmask=[d16] minReg=1 wt=400.00>
<RefPosition #44 @77 RefTypeUse <Ivl:31> BB01 regmask=[d16] minReg=1 last wt=100.00>
<RefPosition #45 @78 RefTypeDef <Ivl:5 V05> STORE_LCL_VAR BB01 regmask=[d16] minReg=1 wt=200.00>
<RefPosition #46 @83 RefTypeDef <Ivl:32 internal> CNS_VEC BB01 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #47 @83 RefTypeUse <Ivl:32 internal> CNS_VEC BB01 regmask=[x0] minReg=1 last wt=400.00>
<RefPosition #48 @84 RefTypeDef <Ivl:33> CNS_VEC BB01 regmask=[d17] minReg=1 wt=400.00>
<RefPosition #49 @85 RefTypeUse <Ivl:33> BB01 regmask=[d17] minReg=1 last wt=100.00>
<RefPosition #50 @85 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[d0] minReg=1 last wt=300.00>
<RefPosition #51 @86 RefTypeDef <Ivl:34> HWINTRINSIC BB01 regmask=[d0] minReg=1 wt=400.00>
<RefPosition #52 @87 RefTypeUse <Ivl:34> BB01 regmask=[d0] minReg=1 last wt=100.00>
<RefPosition #53 @88 RefTypeDef <Ivl:6 V06> STORE_LCL_VAR BB01 regmask=[d0] minReg=1 wt=300.00>
<RefPosition #54 @95 RefTypeUse <Ivl:5 V05> LCL_VAR BB01 regmask=[d16] minReg=1 last wt=200.00>
<RefPosition #55 @95 RefTypeUse <Ivl:6 V06> LCL_VAR BB01 regmask=[d0] minReg=1 wt=300.00>
<RefPosition #56 @96 RefTypeDef <Ivl:35> HWINTRINSIC BB01 regmask=[d16] minReg=1 wt=400.00>
<RefPosition #57 @99 RefTypeUse <Ivl:35> BB01 regmask=[d16] minReg=1 last wt=100.00>
<RefPosition #58 @99 RefTypeUse <Ivl:6 V06> LCL_VAR BB01 regmask=[d0] minReg=1 last wt=300.00>
<RefPosition #59 @100 RefTypeDef <Ivl:36> HWINTRINSIC BB01 regmask=[d0] minReg=1 wt=400.00>
<RefPosition #60 @101 RefTypeFixedReg <Reg:d0 > BB01 regmask=[d0] minReg=1 wt=100.00>
<RefPosition #61 @101 RefTypeUse <Ivl:36> BB01 regmask=[d0] minReg=1 last fixed wt=100.00>
VAR REFPOSITIONS AFTER ALLOCATION
--- V00 (Interval 0)
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[d0] minReg=1 fixed regOptional wt=100.00>
<RefPosition #9 @13 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[d0] minReg=1 wt=400.00>
<RefPosition #14 @23 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[d0] minReg=1 last wt=400.00>
--- V01 (Interval 1)
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[d1] minReg=1 fixed regOptional wt=100.00>
<RefPosition #36 @57 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[d1] minReg=1 last wt=300.00>
--- V02 (Interval 2)
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[d2] minReg=1 fixed regOptional wt=100.00>
<RefPosition #37 @63 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[d2] minReg=1 last wt=300.00>
--- V03 (Interval 3)
<RefPosition #13 @16 RefTypeDef <Ivl:3 V03> STORE_LCL_VAR BB01 regmask=[d17] minReg=1 wt=200.00>
<RefPosition #28 @41 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[d17] minReg=1 last wt=200.00>
--- V04 (Interval 4)
<RefPosition #20 @30 RefTypeDef <Ivl:4 V04> STORE_LCL_VAR BB01 regmask=[d0] minReg=1 wt=300.00>
<RefPosition #24 @37 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[d0] minReg=1 wt=300.00>
<RefPosition #50 @85 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[d0] minReg=1 last wt=300.00>
--- V05 (Interval 5)
<RefPosition #45 @78 RefTypeDef <Ivl:5 V05> STORE_LCL_VAR BB01 regmask=[d16] minReg=1 wt=200.00>
<RefPosition #54 @95 RefTypeUse <Ivl:5 V05> LCL_VAR BB01 regmask=[d16] minReg=1 last wt=200.00>
--- V06 (Interval 6)
<RefPosition #53 @88 RefTypeDef <Ivl:6 V06> STORE_LCL_VAR BB01 regmask=[d0] minReg=1 wt=300.00>
<RefPosition #55 @95 RefTypeUse <Ivl:6 V06> LCL_VAR BB01 regmask=[d0] minReg=1 wt=300.00>
<RefPosition #58 @99 RefTypeUse <Ivl:6 V06> LCL_VAR BB01 regmask=[d0] minReg=1 last wt=300.00>
--- V07 (Interval 7)
<RefPosition #31 @44 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[d16] minReg=1 wt=200.00>
<RefPosition #42 @75 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[d16] minReg=1 last wt=200.00>
--- V08
--- V09
--- V10
--- V11
--- V12
--- V13 (Interval 8)
<RefPosition #8 @10 RefTypeDef <Ivl:8 V13> STORE_LCL_VAR BB01 regmask=[d16] minReg=1 wt=300.00>
<RefPosition #10 @13 RefTypeUse <Ivl:8 V13> LCL_VAR BB01 regmask=[d16] minReg=1 wt=300.00>
<RefPosition #17 @27 RefTypeUse <Ivl:8 V13> LCL_VAR BB01 regmask=[d16] minReg=1 last wt=300.00>
Active intervals at end of allocation:
-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Resolution Candidates: {V00 V01 V02}
Has No Critical Edges
Prior to Resolution
BB01
use: {V00 V01 V02}
def: {V03 V04 V05 V06 V07 V11 V13}
in: {V00 V01 V02}
out: {}
Var=Reg beg of BB01: V00=d0 V01=d1 V02=d2
Var=Reg end of BB01: none
RESOLVING EDGES
Set V00 argument initial register to d0
Set V01 argument initial register to d1
Set V02 argument initial register to d2
Trees after linear scan register allocator (LSRA)
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..0BB) (return), preds={} succs={}
N003 (???,???) [000069] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N005 ( 1, 1) [000000] ----------- t0 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 d0 REG d0 $80
N007 ( 3, 2) [000002] ----------- t2 = CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> REG d16 $140
/--* t2 simd16
N009 ( 3, 3) [000065] DA--------- * STORE_LCL_VAR simd16 V13 cse0 d:1 d16 REG d16 $VN.Void
N011 ( 1, 1) [000066] ----------- t66 = LCL_VAR simd16 V13 cse0 u:1 d16 REG d16 $140
/--* t0 simd16
+--* t66 simd16
N013 ( 6, 6) [000003] ----------- t3 = * HWINTRINSIC simd16 ubyte And REG d17 $1c0
/--* t3 simd16
N015 ( 10, 9) [000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 d:2 d17 REG d17 $VN.Void
N017 (???,???) [000070] ----------- IL_OFFSET void INLRT @ 0x00E[E-] REG NA
N019 ( 1, 1) [000005] ----------- t5 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 d0 (last use) REG d0 $80
N021 ( 1, 2) [000006] -c-----N--- t6 = CNS_INT int 4 REG NA $44
/--* t5 simd16
+--* t6 int
N023 ( 3, 4) [000007] ----------- t7 = * HWINTRINSIC simd16 int ShiftRightLogical REG d0 $1c1
N025 ( 1, 1) [000068] ----------- t68 = LCL_VAR simd16 V13 cse0 u:1 d16 (last use) REG d16 $140
/--* t7 simd16
+--* t68 simd16
N027 ( 5, 6) [000010] ----------- t10 = * HWINTRINSIC simd16 ubyte And REG d0 $1c2
/--* t10 simd16
N029 ( 5, 6) [000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 d:2 d0 REG d0 $VN.Void
N031 (???,???) [000071] ----------- IL_OFFSET void INLRT @ 0x033[E-] REG NA
N033 ( 1, 1) [000015] ----------- t15 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 d0 REG d0 $1c2
N035 ( 3, 2) [000017] ----------- t17 = CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808> REG d16 $143
/--* t15 simd16
+--* t17 simd16
N037 ( 5, 4) [000018] ----------- t18 = * HWINTRINSIC simd16 ubyte And REG d16 $1c3
N039 ( 3, 2) [000019] ----------- t19 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 u:2 d17 (last use) REG d17 $1c0
/--* t18 simd16
+--* t19 simd16
N041 ( 9, 7) [000020] ----------- t20 = * HWINTRINSIC simd16 ubyte Or REG d16 $1c4
/--* t20 simd16
N043 ( 13, 10) [000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 d:2 d16 REG d16 $VN.Void
N045 (???,???) [000072] ----------- IL_OFFSET void INLRT @ 0x050[E-] REG NA
N047 ( 1, 2) [000024] -c--------- t24 = CNS_INT int 0 REG NA $40
N049 (???,???) [000078] Dc--------- t78 = LCL_ADDR byref V11 tmp1 [+0] NA REG NA
/--* t78 byref
+--* t24 int
N051 ( 11, 9) [000025] sA--------- * STORE_BLK struct<System.ValueTuple`2, 32> (init) (Unroll) REG NA
N053 (???,???) [000073] ----------- IL_OFFSET void INL01 @ 0x000[E-] <- INLRT @ ??? REG NA
N055 ( 1, 1) [000022] ----------- t22 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1 u:1 d1 (last use) REG d1 $81
/--* t22 simd16
N057 ( 5, 6) [000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:2->3[+0] NA REG NA $VN.Void
N059 (???,???) [000074] ----------- IL_OFFSET void INL01 @ 0x007[E-] <- INLRT @ ??? REG NA
N061 ( 1, 1) [000023] ----------- t23 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2 u:1 d2 (last use) REG d2 $82
/--* t23 simd16
N063 ( 5, 6) [000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:3->4[+16] NA REG NA $VN.Void
N065 (???,???) [000075] ----------- IL_OFFSET void INLRT @ 0x057[--] REG NA
N067 ( 3, 4) [000031] ----------- t31 = LCL_FLD simd16 V11 tmp1 u:4[+0] d17 REG d17 $81
N069 ( 3, 4) [000032] ----------- t32 = LCL_FLD simd16 V11 tmp1 u:4[+16] d18 (last use) REG d18 $82
/--* t31 simd16
+--* t32 simd16
N071 ( 6, 8) [000030] -c--------- t30 = * FIELD_LIST struct REG NA $c2
N073 ( 3, 2) [000029] ----------- t29 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 u:2 d16 (last use) REG d16 $1c4
/--* t30 struct
+--* t29 simd16
N075 ( 10, 11) [000033] ----------- t33 = * HWINTRINSIC simd16 ubyte VectorTableLookup REG d16 $1c5
/--* t33 simd16
N077 ( 14, 14) [000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 d:2 d16 REG d16 $VN.Void
N079 (???,???) [000076] ----------- IL_OFFSET void INLRT @ 0x093[E-] REG NA
N081 ( 1, 1) [000037] ----------- t37 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 d0 (last use) REG d0 $1c2
N083 ( 3, 2) [000060] ----------- t60 = CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010> REG d17 $144
/--* t60 simd16
+--* t37 simd16
N085 ( 5, 4) [000061] ----------- t61 = * HWINTRINSIC simd16 ubyte VectorTableLookup REG d0 $1c6
/--* t61 simd16
N087 ( 5, 4) [000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 d:2 d0 REG d0 $VN.Void
N089 (???,???) [000077] ----------- IL_OFFSET void INLRT @ 0x0AD[E-] REG NA
N091 ( 3, 2) [000041] ----------- t41 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 u:2 d16 (last use) REG d16 $1c5
N093 ( 1, 1) [000042] ----------- t42 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 d0 REG d0 $1c6
/--* t41 simd16
+--* t42 simd16
N095 ( 5, 4) [000043] ----------- t43 = * HWINTRINSIC simd16 ubyte And REG d16 $1c7
N097 ( 1, 1) [000044] ----------- t44 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 d0 (last use) REG d0 $1c6
/--* t43 simd16
+--* t44 simd16
N099 ( 7, 6) [000045] ----------- t45 = * HWINTRINSIC simd16 ubyte CompareEqual REG d0 $1c8
/--* t45 simd16
N101 ( 8, 7) [000046] ----------- * RETURN simd16 REG NA $VN.Void
-------------------------------------------------------------------------------------------------------------------
Final allocation
-------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 |d0 |d1 |d2 |d8 |d9 |d16 |d17 |d18 |
-------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0.#0 V0 Parm Alloc d0 | | | | | | | | | | |V0 a| | | | | | | |
0.#1 V1 Parm Alloc d1 | | | | | | | | | | |V0 a|V1 a| | | | | | |
0.#2 V2 Parm Alloc d2 | | | | | | | | | | |V0 a|V1 a|V2 a| | | | | |
1.#3 BB1 PredBB0 | | | | | | | | | | |V0 a|V1 a|V2 a| | | | | |
[000002] 7.#4 I18 Def Alloc x0 |I18a| | | | | | | | | |V0 a|V1 a|V2 a| | | | | |
7.#5 I18 Use * Keep x0 |I18i| | | | | | | | | |V0 a|V1 a|V2 a| | | | | |
8.#6 C19 Def Alloc d16 | | | | | | | | | | |V0 a|V1 a|V2 a| | |C19a| | |
[000065] 9.#7 C19 Use * Keep d16 | | | | | | | | | | |V0 a|V1 a|V2 a| | |C19i| | |
10.#8 V13 Def Alloc d16 | | | | | | | | | | |V0 a|V1 a|V2 a| | |V13a| | |
[000003] 13.#9 V0 Use Keep d0 | | | | | | | | | | |V0 a|V1 a|V2 a| | |V13a| | |
13.#10 V13 Use Keep d16 | | | | | | | | | | |V0 a|V1 a|V2 a| | |V13a| | |
14.#11 I20 Def Alloc d17 | | | | | | | | | | |V0 a|V1 a|V2 a| | |V13a|I20a| |
[000004] 15.#12 I20 Use * Keep d17 | | | | | | | | | | |V0 a|V1 a|V2 a| | |V13a|I20i| |
16.#13 V3 Def Alloc d17 | | | | | | | | | | |V0 a|V1 a|V2 a| | |V13a|V3 a| |
[000007] 23.#14 V0 Use * Keep d0 | | | | | | | | | | |V0 i|V1 a|V2 a| | |V13a|V3 a| |
24.#15 I21 Def Alloc d0 | | | | | | | | | | |I21a|V1 a|V2 a| | |V13a|V3 a| |
[000010] 27.#16 I21 Use * Keep d0 | | | | | | | | | | |I21i|V1 a|V2 a| | |V13a|V3 a| |
27.#17 V13 Use * Keep d16 | | | | | | | | | | | |V1 a|V2 a| | |V13i|V3 a| |
28.#18 I22 Def Alloc d0 | | | | | | | | | | |I22a|V1 a|V2 a| | | |V3 a| |
[000011] 29.#19 I22 Use * Keep d0 | | | | | | | | | | |I22i|V1 a|V2 a| | | |V3 a| |
30.#20 V4 Def Alloc d0 | | | | | | | | | | |V4 a|V1 a|V2 a| | | |V3 a| |
[000017] 35.#21 I23 Def Alloc x0 |I23a| | | | | | | | | |V4 a|V1 a|V2 a| | | |V3 a| |
35.#22 I23 Use * Keep x0 |I23i| | | | | | | | | |V4 a|V1 a|V2 a| | | |V3 a| |
36.#23 C24 Def Alloc d16 | | | | | | | | | | |V4 a|V1 a|V2 a| | |C24a|V3 a| |
[000018] 37.#24 V4 Use Keep d0 | | | | | | | | | | |V4 a|V1 a|V2 a| | |C24a|V3 a| |
37.#25 C24 Use * Keep d16 | | | | | | | | | | |V4 a|V1 a|V2 a| | |C24i|V3 a| |
38.#26 I25 Def Alloc d16 | | | | | | | | | | |V4 a|V1 a|V2 a| | |I25a|V3 a| |
[000020] 41.#27 I25 Use * Keep d16 | | | | | | | | | | |V4 a|V1 a|V2 a| | |I25i|V3 a| |
41.#28 V3 Use * Keep d17 | | | | | | | | | | |V4 a|V1 a|V2 a| | | |V3 i| |
42.#29 I26 Def Alloc d16 | | | | | | | | | | |V4 a|V1 a|V2 a| | |I26a| | |
[000021] 43.#30 I26 Use * Keep d16 | | | | | | | | | | |V4 a|V1 a|V2 a| | |I26i| | |
44.#31 V7 Def Alloc d16 | | | | | | | | | | |V4 a|V1 a|V2 a| | |V7 a| | |
[000025] 51.#32 I27 Def Alloc x0 |I27a| | | | | | | | | |V4 a|V1 a|V2 a| | |V7 a| | |
51.#33 I28 Def Alloc d17 |I27a| | | | | | | | | |V4 a|V1 a|V2 a| | |V7 a|I28a| |
51.#34 I27 Use * Keep x0 |I27i| | | | | | | | | |V4 a|V1 a|V2 a| | |V7 a|I28a| |
51.#35 I28 Use * Keep d17 | | | | | | | | | | |V4 a|V1 a|V2 a| | |V7 a|I28i| |
[000049] 57.#36 V1 Use * Keep d1 | | | | | | | | | | |V4 a|V1 i|V2 a| | |V7 a| | |
[000052] 63.#37 V2 Use * Keep d2 | | | | | | | | | | |V4 a| |V2 i| | |V7 a| | |
[000031] 68.#38 I29 Def Alloc d17 | | | | | | | | | | |V4 a| | | | |V7 a|I29a| |
[000032] 70.#39 I30 Def Alloc d18 | | | | | | | | | | |V4 a| | | | |V7 a|I29a|I30a|
[000033] 75.#40 I29 Use * Keep d17 | | | | | | | | | | |V4 a| | | | |V7 a|I29i|I30a|
75.#41 I30 Use * Keep d18 | | | | | | | | | | |V4 a| | | | |V7 a| |I30i|
75.#42 V7 Use * Keep d16 | | | | | | | | | | |V4 a| | | | |V7 i| | |
76.#43 I31 Def Alloc d16 | | | | | | | | | | |V4 a| | | | |I31a| | |
[000034] 77.#44 I31 Use * Keep d16 | | | | | | | | | | |V4 a| | | | |I31i| | |
78.#45 V5 Def Alloc d16 | | | | | | | | | | |V4 a| | | | |V5 a| | |
[000060] 83.#46 I32 Def Alloc x0 |I32a| | | | | | | | | |V4 a| | | | |V5 a| | |
83.#47 I32 Use * Keep x0 |I32i| | | | | | | | | |V4 a| | | | |V5 a| | |
84.#48 C33 Def Alloc d17 | | | | | | | | | | |V4 a| | | | |V5 a|C33a| |
[000061] 85.#49 C33 Use * Keep d17 | | | | | | | | | | |V4 a| | | | |V5 a|C33i| |
85.#50 V4 Use * Keep d0 | | | | | | | | | | |V4 i| | | | |V5 a| | |
86.#51 I34 Def Alloc d0 | | | | | | | | | | |I34a| | | | |V5 a| | |
[000040] 87.#52 I34 Use * Keep d0 | | | | | | | | | | |I34i| | | | |V5 a| | |
88.#53 V6 Def Alloc d0 | | | | | | | | | | |V6 a| | | | |V5 a| | |
[000043] 95.#54 V5 Use * Keep d16 | | | | | | | | | | |V6 a| | | | |V5 i| | |
95.#55 V6 Use Keep d0 | | | | | | | | | | |V6 a| | | | | | | |
96.#56 I35 Def Alloc d16 | | | | | | | | | | |V6 a| | | | |I35a| | |
[000045] 99.#57 I35 Use * Keep d16 | | | | | | | | | | |V6 a| | | | |I35i| | |
99.#58 V6 Use * Keep d0 | | | | | | | | | | |V6 i| | | | | | | |
100.#59 I36 Def Alloc d0 | | | | | | | | | | |I36a| | | | | | | |
[000046] 101.#60 d0 Fixd Keep d0 | | | | | | | | | | |I36a| | | | | | | |
101.#61 I36 Use * Keep d0 | | | | | | | | | | |I36i| | | | | | | |
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
Register selection order: ABCDEFGHIJKLMNOPQ
Total Tracked Vars: 10
Total Reg Cand Vars: 9
Total number of Intervals: 36
Total number of RefPositions: 61
Total Number of spill temps created: 0
..........
BB01 [ 100.00]: COVERS = 6, BEST_FIT = 3, REG_ORDER = 15
..........
Total SpillCount : 0 Weighted: 0.000000
Total CopyReg : 0 Weighted: 0.000000
Total ResolutionMovs : 0 Weighted: 0.000000
Total SplitEdges : 0 Weighted: 0.000000
..........
Total COVERS [# 4] : 6 Weighted: 600.000000
Total BEST_FIT [#11] : 3 Weighted: 300.000000
Total REG_ORDER [#13] : 15 Weighted: 1500.000000
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters: V00(d0) V01(d1) V02(d2)
BB01 [000..0BB) (return), preds={} succs={}
=====
N003. IL_OFFSET INLRT @ 0x000[E-]
N005. V00(d0)
N007. d16 = CNS_VEC <0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f>
* N009. V13(d16); d16
N011. V13(d16)
N013. d17 = HWINTRINSIC; d0,d16
* N015. V03(d17); d17
N017. IL_OFFSET INLRT @ 0x00E[E-]
N019. V00(d0*)
N021. CNS_INT 4
N023. d0 = HWINTRINSIC; d0*
N025. V13(d16*)
N027. d0 = HWINTRINSIC; d0,d16*
* N029. V04(d0); d0
N031. IL_OFFSET INLRT @ 0x033[E-]
N033. V04(d0)
N035. d16 = CNS_VEC <0x08080808, 0x08080808, 0x08080808, 0x08080808>
N037. d16 = HWINTRINSIC; d0,d16
N039. V03(d17*)
N041. d16 = HWINTRINSIC; d16,d17*
* N043. V07(d16); d16
N045. IL_OFFSET INLRT @ 0x050[E-]
N047. CNS_INT 0
N049. LCL_ADDR V11 tmp1 [+0] NA
N051. STORE_BLK
N053. IL_OFFSET INL01 @ 0x000[E-] <- INLRT @ ???
N055. V01(d1*)
N057. V11 MEM; d1*
N059. IL_OFFSET INL01 @ 0x007[E-] <- INLRT @ ???
N061. V02(d2*)
N063. V11 MEM; d2*
N065. IL_OFFSET INLRT @ 0x057[--]
N067. d17 = V11 MEM
N069. d18 = V11 MEM
N071. STK = FIELD_LIST; d17,d18
N073. V07(d16*)
N075. d16 = HWINTRINSIC; STK,d16*
* N077. V05(d16); d16
N079. IL_OFFSET INLRT @ 0x093[E-]
N081. V04(d0*)
N083. d17 = CNS_VEC <0x08040201, 0x80402010, 0x08040201, 0x80402010>
N085. d0 = HWINTRINSIC; d17,d0*
* N087. V06(d0); d0
N089. IL_OFFSET INLRT @ 0x0AD[E-]
N091. V05(d16*)
N093. V06(d0)
N095. d16 = HWINTRINSIC; d16*,d0
N097. V06(d0*)
N099. d0 = HWINTRINSIC; d16,d0*
N101. RETURN ; d0
Var=Reg end of BB01: none
*************** Finishing PHASE Linear scan register alloc
Trees after Linear scan register alloc
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..0BB) (return), preds={} succs={}
N003 (???,???) [000069] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N005 ( 1, 1) [000000] ----------- t0 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 d0 REG d0 $80
N007 ( 3, 2) [000002] ----------- t2 = CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> REG d16 $140
/--* t2 simd16
N009 ( 3, 3) [000065] DA--------- * STORE_LCL_VAR simd16 V13 cse0 d:1 d16 REG d16 $VN.Void
N011 ( 1, 1) [000066] ----------- t66 = LCL_VAR simd16 V13 cse0 u:1 d16 REG d16 $140
/--* t0 simd16
+--* t66 simd16
N013 ( 6, 6) [000003] ----------- t3 = * HWINTRINSIC simd16 ubyte And REG d17 $1c0
/--* t3 simd16
N015 ( 10, 9) [000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 d:2 d17 REG d17 $VN.Void
N017 (???,???) [000070] ----------- IL_OFFSET void INLRT @ 0x00E[E-] REG NA
N019 ( 1, 1) [000005] ----------- t5 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 d0 (last use) REG d0 $80
N021 ( 1, 2) [000006] -c-----N--- t6 = CNS_INT int 4 REG NA $44
/--* t5 simd16
+--* t6 int
N023 ( 3, 4) [000007] ----------- t7 = * HWINTRINSIC simd16 int ShiftRightLogical REG d0 $1c1
N025 ( 1, 1) [000068] ----------- t68 = LCL_VAR simd16 V13 cse0 u:1 d16 (last use) REG d16 $140
/--* t7 simd16
+--* t68 simd16
N027 ( 5, 6) [000010] ----------- t10 = * HWINTRINSIC simd16 ubyte And REG d0 $1c2
/--* t10 simd16
N029 ( 5, 6) [000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 d:2 d0 REG d0 $VN.Void
N031 (???,???) [000071] ----------- IL_OFFSET void INLRT @ 0x033[E-] REG NA
N033 ( 1, 1) [000015] ----------- t15 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 d0 REG d0 $1c2
N035 ( 3, 2) [000017] ----------- t17 = CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808> REG d16 $143
/--* t15 simd16
+--* t17 simd16
N037 ( 5, 4) [000018] ----------- t18 = * HWINTRINSIC simd16 ubyte And REG d16 $1c3
N039 ( 3, 2) [000019] ----------- t19 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 u:2 d17 (last use) REG d17 $1c0
/--* t18 simd16
+--* t19 simd16
N041 ( 9, 7) [000020] ----------- t20 = * HWINTRINSIC simd16 ubyte Or REG d16 $1c4
/--* t20 simd16
N043 ( 13, 10) [000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 d:2 d16 REG d16 $VN.Void
N045 (???,???) [000072] ----------- IL_OFFSET void INLRT @ 0x050[E-] REG NA
N047 ( 1, 2) [000024] -c--------- t24 = CNS_INT int 0 REG NA $40
N049 (???,???) [000078] Dc--------- t78 = LCL_ADDR byref V11 tmp1 [+0] NA REG NA
/--* t78 byref
+--* t24 int
N051 ( 11, 9) [000025] sA--------- * STORE_BLK struct<System.ValueTuple`2, 32> (init) (Unroll) REG NA
N053 (???,???) [000073] ----------- IL_OFFSET void INL01 @ 0x000[E-] <- INLRT @ ??? REG NA
N055 ( 1, 1) [000022] ----------- t22 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1 u:1 d1 (last use) REG d1 $81
/--* t22 simd16
N057 ( 5, 6) [000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:2->3[+0] NA REG NA $VN.Void
N059 (???,???) [000074] ----------- IL_OFFSET void INL01 @ 0x007[E-] <- INLRT @ ??? REG NA
N061 ( 1, 1) [000023] ----------- t23 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2 u:1 d2 (last use) REG d2 $82
/--* t23 simd16
N063 ( 5, 6) [000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:3->4[+16] NA REG NA $VN.Void
N065 (???,???) [000075] ----------- IL_OFFSET void INLRT @ 0x057[--] REG NA
N067 ( 3, 4) [000031] ----------- t31 = LCL_FLD simd16 V11 tmp1 u:4[+0] d17 REG d17 $81
N069 ( 3, 4) [000032] ----------- t32 = LCL_FLD simd16 V11 tmp1 u:4[+16] d18 (last use) REG d18 $82
/--* t31 simd16
+--* t32 simd16
N071 ( 6, 8) [000030] -c--------- t30 = * FIELD_LIST struct REG NA $c2
N073 ( 3, 2) [000029] ----------- t29 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 u:2 d16 (last use) REG d16 $1c4
/--* t30 struct
+--* t29 simd16
N075 ( 10, 11) [000033] ----------- t33 = * HWINTRINSIC simd16 ubyte VectorTableLookup REG d16 $1c5
/--* t33 simd16
N077 ( 14, 14) [000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 d:2 d16 REG d16 $VN.Void
N079 (???,???) [000076] ----------- IL_OFFSET void INLRT @ 0x093[E-] REG NA
N081 ( 1, 1) [000037] ----------- t37 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 d0 (last use) REG d0 $1c2
N083 ( 3, 2) [000060] ----------- t60 = CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010> REG d17 $144
/--* t60 simd16
+--* t37 simd16
N085 ( 5, 4) [000061] ----------- t61 = * HWINTRINSIC simd16 ubyte VectorTableLookup REG d0 $1c6
/--* t61 simd16
N087 ( 5, 4) [000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 d:2 d0 REG d0 $VN.Void
N089 (???,???) [000077] ----------- IL_OFFSET void INLRT @ 0x0AD[E-] REG NA
N091 ( 3, 2) [000041] ----------- t41 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 u:2 d16 (last use) REG d16 $1c5
N093 ( 1, 1) [000042] ----------- t42 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 d0 REG d0 $1c6
/--* t41 simd16
+--* t42 simd16
N095 ( 5, 4) [000043] ----------- t43 = * HWINTRINSIC simd16 ubyte And REG d16 $1c7
N097 ( 1, 1) [000044] ----------- t44 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 d0 (last use) REG d0 $1c6
/--* t43 simd16
+--* t44 simd16
N099 ( 7, 6) [000045] ----------- t45 = * HWINTRINSIC simd16 ubyte CompareEqual REG d0 $1c8
/--* t45 simd16
N101 ( 8, 7) [000046] ----------- * RETURN simd16 REG NA $VN.Void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid
*************** Starting PHASE Place 'align' instructions
*************** Finishing PHASE Place 'align' instructions [no changes]
*************** In genGenerateCode()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i IBC LIR
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
V00(d0) V01(d1) V02(d2)
Modified regs: [x0 d0-d2 d16-d18]
Callee-saved registers pushed: 2 [fp lr]
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Setting genSaveFpLrWithAllCalleeSavedRegisters to false
Assign V11 tmp1, size=32, stkOffs=-0x20
--- delta bump 48 for FP frame
--- virtual stack offset to actual stack offset delta is 48
-- V10 was 0, now 48
-- V11 was -32, now 16
; Final local variable assignments
;
; V00 arg0 [V00,T01] ( 4, 4 ) simd16 -> d0 HFA(simd16) single-def
; V01 arg1 [V01,T02] ( 3, 3 ) simd16 -> d1 HFA(simd16) single-def
; V02 arg2 [V02,T03] ( 3, 3 ) simd16 -> d2 HFA(simd16) single-def
; V03 loc0 [V03,T07] ( 2, 2 ) simd16 -> d17 HFA(simd16)
; V04 loc1 [V04,T04] ( 3, 3 ) simd16 -> d0 HFA(simd16)
; V05 loc2 [V05,T08] ( 2, 2 ) simd16 -> d16 HFA(simd16)
; V06 loc3 [V06,T05] ( 3, 3 ) simd16 -> d0 HFA(simd16)
; V07 loc4 [V07,T09] ( 2, 2 ) simd16 -> d16 HFA(simd16)
;* V08 loc5 [V08 ] ( 0, 0 ) simd16 -> zero-ref HFA(simd16)
;* V09 loc6 [V09 ] ( 0, 0 ) simd16 -> zero-ref HFA(simd16)
;# V10 OutArgs [V10 ] ( 1, 1 ) struct ( 0) [sp+00H] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
; V11 tmp1 [V11,T00] ( 5, 10 ) struct (32) [fp+10H] HFA(simd16) do-not-enreg[SF] ld-addr-op "NewObj constructor temp"
;* V12 tmp2 [V12 ] ( 0, 0 ) simd16 -> zero-ref HFA(simd16) "Inline return value spill temp"
; V13 cse0 [V13,T06] ( 3, 3 ) simd16 -> d16 "CSE - aggressive"
;
; Lcl frame size = 32
Created:
G_M8077_IG02: ; offs=000000H, size=0000H, bbWeight=1, gcrefRegs=0000 {}
Mark labels for codegen
BB01 : first block
*************** After genMarkLabelsForCodegen()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 100 [000..0BB) (return) i label IBC LIR
-----------------------------------------------------------------------------------------------------------------------------------------
Setting stack level from -572662307 to 0
=============== Generating BB01 [000..0BB) (return), preds={} succs={} flags=0x00000000.40020011: i label IBC LIR
BB01 IN (3)={V00 V01 V02}
OUT(0)={ }
Recording Var Locations at start of BB01
V00(d0) V01(d1) V02(d2)
Change life 0000000000000000 {} -> 000000000000000E {V00 V01 V02}
V00 in reg d0 is becoming live [------]
Live regs: 0000 {} => 0000 {d0}
New debug range: first
V01 in reg d1 is becoming live [------]
Live regs: 0000 {d0} => 0000 {d0 d1}
New debug range: first
V02 in reg d2 is becoming live [------]
Live regs: 0000 {d0 d1} => 0000 {d0 d1 d2}
New debug range: first
Live regs: (unchanged) 0000 {d0 d1 d2}
GC regs: (unchanged) 0000 {}
Byref regs: (unchanged) 0000 {}
L_M8077_BB01:
Label: G_M8077_IG02, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
Scope info: begin block BB01, IL range [000..0BB)
Added IP mapping: 0x0000 STACK_EMPTY (G_M8077_IG02,ins#0,ofs#0) label
Generating: N003 (???,???) [000069] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
Generating: N005 ( 1, 1) [000000] ----------- t0 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 d0 REG d0 $80
Generating: N007 ( 3, 2) [000002] ----------- t2 = CNS_VEC simd16<0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f> REG d16 $140
Increasing data section alignment from 4 to 16 for type simd16
Mapped BB01 to G_M8077_IG02
IN0001: ldr q16, (LARGELDC)[@RWD00]
/--* t2 simd16
Generating: N009 ( 3, 3) [000065] DA--------- * STORE_LCL_VAR simd16 V13 cse0 d:1 d16 REG d16 $VN.Void
V13 in reg d16 is becoming live [000065]
Live regs: 0000 {d0 d1 d2} => 0000 {d0 d1 d2 d16}
Live vars after [000065]: {V00 V01 V02} => {V00 V01 V02 V13}
Generating: N011 ( 1, 1) [000066] ----------- t66 = LCL_VAR simd16 V13 cse0 u:1 d16 REG d16 $140
/--* t0 simd16
+--* t66 simd16
Generating: N013 ( 6, 6) [000003] ----------- t3 = * HWINTRINSIC simd16 ubyte And REG d17 $1c0
IN0002: and v17.16b, v0.16b, v16.16b
/--* t3 simd16
Generating: N015 ( 10, 9) [000004] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 d:2 d17 REG d17 $VN.Void
V03 in reg d17 is becoming live [000004]
Live regs: 0000 {d0 d1 d2 d16} => 0000 {d0 d1 d2 d16 d17}
New debug range: first
Live vars after [000004]: {V00 V01 V02 V13} => {V00 V01 V02 V03 V13}
Added IP mapping: 0x000E STACK_EMPTY (G_M8077_IG02,ins#2,ofs#16)
Generating: N017 (???,???) [000070] ----------- IL_OFFSET void INLRT @ 0x00E[E-] REG NA
Generating: N019 ( 1, 1) [000005] ----------- t5 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V00 arg0 u:1 d0 (last use) REG d0 $80
Generating: N021 ( 1, 2) [000006] -c-----N--- t6 = CNS_INT int 4 REG NA $44
/--* t5 simd16
+--* t6 int
Generating: N023 ( 3, 4) [000007] ----------- t7 = * HWINTRINSIC simd16 int ShiftRightLogical REG d0 $1c1
V00 in reg d0 is becoming dead [000005]
Live regs: 0000 {d0 d1 d2 d16 d17} => 0000 {d1 d2 d16 d17}
Closing debug range.
Live vars after [000005]: {V00 V01 V02 V03 V13} => {V01 V02 V03 V13}
IN0003: ushr v0.4s, v0.4s, #4
Generating: N025 ( 1, 1) [000068] ----------- t68 = LCL_VAR simd16 V13 cse0 u:1 d16 (last use) REG d16 $140
/--* t7 simd16
+--* t68 simd16
Generating: N027 ( 5, 6) [000010] ----------- t10 = * HWINTRINSIC simd16 ubyte And REG d0 $1c2
V13 in reg d16 is becoming dead [000068]
Live regs: 0000 {d1 d2 d16 d17} => 0000 {d1 d2 d17}
Live vars after [000068]: {V01 V02 V03 V13} => {V01 V02 V03}
IN0004: and v0.16b, v0.16b, v16.16b
/--* t10 simd16
Generating: N029 ( 5, 6) [000011] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 d:2 d0 REG d0 $VN.Void
V04 in reg d0 is becoming live [000011]
Live regs: 0000 {d1 d2 d17} => 0000 {d0 d1 d2 d17}
New debug range: first
Live vars after [000011]: {V01 V02 V03} => {V01 V02 V03 V04}
Added IP mapping: 0x0033 STACK_EMPTY (G_M8077_IG02,ins#4,ofs#24)
Generating: N031 (???,???) [000071] ----------- IL_OFFSET void INLRT @ 0x033[E-] REG NA
Generating: N033 ( 1, 1) [000015] ----------- t15 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 d0 REG d0 $1c2
Generating: N035 ( 3, 2) [000017] ----------- t17 = CNS_VEC simd16<0x08080808, 0x08080808, 0x08080808, 0x08080808> REG d16 $143
IN0005: ldr q16, (LARGELDC)[@RWD16]
/--* t15 simd16
+--* t17 simd16
Generating: N037 ( 5, 4) [000018] ----------- t18 = * HWINTRINSIC simd16 ubyte And REG d16 $1c3
IN0006: and v16.16b, v0.16b, v16.16b
Generating: N039 ( 3, 2) [000019] ----------- t19 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 loc0 u:2 d17 (last use) REG d17 $1c0
/--* t18 simd16
+--* t19 simd16
Generating: N041 ( 9, 7) [000020] ----------- t20 = * HWINTRINSIC simd16 ubyte Or REG d16 $1c4
V03 in reg d17 is becoming dead [000019]
Live regs: 0000 {d0 d1 d2 d17} => 0000 {d0 d1 d2}
Closing debug range.
Live vars after [000019]: {V01 V02 V03 V04} => {V01 V02 V04}
IN0007: orr v16.16b, v16.16b, v17.16b
/--* t20 simd16
Generating: N043 ( 13, 10) [000021] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 d:2 d16 REG d16 $VN.Void
V07 in reg d16 is becoming live [000021]
Live regs: 0000 {d0 d1 d2} => 0000 {d0 d1 d2 d16}
New debug range: first
Live vars after [000021]: {V01 V02 V04} => {V01 V02 V04 V07}
Added IP mapping: 0x0050 STACK_EMPTY (G_M8077_IG02,ins#7,ofs#44)
Generating: N045 (???,???) [000072] ----------- IL_OFFSET void INLRT @ 0x050[E-] REG NA
Generating: N047 ( 1, 2) [000024] -c--------- t24 = CNS_INT int 0 REG NA $40
Generating: N049 (???,???) [000078] Dc--------- t78 = LCL_ADDR byref V11 tmp1 [+0] NA REG NA
/--* t78 byref
+--* t24 int
Generating: N051 ( 11, 9) [000025] sA--------- * STORE_BLK struct<System.ValueTuple`2, 32> (init) (Unroll) REG NA
IN0008: stp xzr, xzr, [fp, #0x10]
IN0009: stp xzr, xzr, [fp, #0x20]
Generating: N053 (???,???) [000073] ----------- IL_OFFSET void INL01 @ 0x000[E-] <- INLRT @ ??? REG NA
Generating: N055 ( 1, 1) [000022] ----------- t22 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V01 arg1 u:1 d1 (last use) REG d1 $81
/--* t22 simd16
Generating: N057 ( 5, 6) [000049] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:2->3[+0] NA REG NA $VN.Void
V01 in reg d1 is becoming dead [000022]
Live regs: 0000 {d0 d1 d2 d16} => 0000 {d0 d2 d16}
Closing debug range.
Live vars after [000022]: {V01 V02 V04 V07} => {V02 V04 V07}
IN000a: str q1, [fp, #0x10] // [V11 tmp1]
Generating: N059 (???,???) [000074] ----------- IL_OFFSET void INL01 @ 0x007[E-] <- INLRT @ ??? REG NA
Generating: N061 ( 1, 1) [000023] ----------- t23 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 arg2 u:1 d2 (last use) REG d2 $82
/--* t23 simd16
Generating: N063 ( 5, 6) [000052] UA--------- * STORE_LCL_FLD simd16 V11 tmp1 ud:3->4[+16] NA REG NA $VN.Void
V02 in reg d2 is becoming dead [000023]
Live regs: 0000 {d0 d2 d16} => 0000 {d0 d16}
Closing debug range.
Live vars after [000023]: {V02 V04 V07} => {V04 V07}
Removing saved instruction in current IG G_M8077_IG02:
> IN000a: str q1, [fp, #0x10] // [V11 tmp1]
IN000a: stp q1, q2, [fp, #0x10] // [V11 tmp1], [V11 tmp1+0x10]
Added IP mapping: 0x0057 (G_M8077_IG02,ins#10,ofs#56)
Generating: N065 (???,???) [000075] ----------- IL_OFFSET void INLRT @ 0x057[--] REG NA
Generating: N067 ( 3, 4) [000031] ----------- t31 = LCL_FLD simd16 V11 tmp1 u:4[+0] d17 REG d17 $81
IN000b: ldr q17, [fp, #0x10] // [V11 tmp1]
Generating: N069 ( 3, 4) [000032] ----------- t32 = LCL_FLD simd16 V11 tmp1 u:4[+16] d18 (last use) REG d18 $82
Removing saved instruction in current IG G_M8077_IG02:
> IN000b: ldr q17, [fp, #0x10] // [V11 tmp1]
IN000b: ldp q17, q18, [fp, #0x10] // [V11 tmp1], [V11 tmp1+0x10]
/--* t31 simd16
+--* t32 simd16
Generating: N071 ( 6, 8) [000030] -c--------- t30 = * FIELD_LIST struct REG NA $c2
Generating: N073 ( 3, 2) [000029] ----------- t29 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V07 loc4 u:2 d16 (last use) REG d16 $1c4
/--* t30 struct
+--* t29 simd16
Generating: N075 ( 10, 11) [000033] ----------- t33 = * HWINTRINSIC simd16 ubyte VectorTableLookup REG d16 $1c5
V07 in reg d16 is becoming dead [000029]
Live regs: 0000 {d0 d16} => 0000 {d0}
Closing debug range.
Live vars after [000029]: {V04 V07} => {V04}
IN000c: tbl v16.16b, {v17.16b, v18.16b}, v16.16b
/--* t33 simd16
Generating: N077 ( 14, 14) [000034] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 d:2 d16 REG d16 $VN.Void
V05 in reg d16 is becoming live [000034]
Live regs: 0000 {d0} => 0000 {d0 d16}
New debug range: first
Live vars after [000034]: {V04} => {V04 V05}
Added IP mapping: 0x0093 STACK_EMPTY (G_M8077_IG02,ins#12,ofs#64)
Generating: N079 (???,???) [000076] ----------- IL_OFFSET void INLRT @ 0x093[E-] REG NA
Generating: N081 ( 1, 1) [000037] ----------- t37 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V04 loc1 u:2 d0 (last use) REG d0 $1c2
Generating: N083 ( 3, 2) [000060] ----------- t60 = CNS_VEC simd16<0x08040201, 0x80402010, 0x08040201, 0x80402010> REG d17 $144
IN000d: ldr q17, (LARGELDC)[@RWD32]
/--* t60 simd16
+--* t37 simd16
Generating: N085 ( 5, 4) [000061] ----------- t61 = * HWINTRINSIC simd16 ubyte VectorTableLookup REG d0 $1c6
V04 in reg d0 is becoming dead [000037]
Live regs: 0000 {d0 d16} => 0000 {d16}
Closing debug range.
Live vars after [000037]: {V04 V05} => {V05}
IN000e: tbl v0.16b, {v17.16b}, v0.16b
/--* t61 simd16
Generating: N087 ( 5, 4) [000040] DA--------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 d:2 d0 REG d0 $VN.Void
V06 in reg d0 is becoming live [000040]
Live regs: 0000 {d16} => 0000 {d0 d16}
New debug range: first
Live vars after [000040]: {V05} => {V05 V06}
Added IP mapping: 0x00AD STACK_EMPTY (G_M8077_IG02,ins#14,ofs#80)
Generating: N089 (???,???) [000077] ----------- IL_OFFSET void INLRT @ 0x0AD[E-] REG NA
Generating: N091 ( 3, 2) [000041] ----------- t41 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V05 loc2 u:2 d16 (last use) REG d16 $1c5
Generating: N093 ( 1, 1) [000042] ----------- t42 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 d0 REG d0 $1c6
/--* t41 simd16
+--* t42 simd16
Generating: N095 ( 5, 4) [000043] ----------- t43 = * HWINTRINSIC simd16 ubyte And REG d16 $1c7
V05 in reg d16 is becoming dead [000041]
Live regs: 0000 {d0 d16} => 0000 {d0}
Closing debug range.
Live vars after [000041]: {V05 V06} => {V06}
IN000f: and v16.16b, v16.16b, v0.16b
Generating: N097 ( 1, 1) [000044] ----------- t44 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V06 loc3 u:2 d0 (last use) REG d0 $1c6
/--* t43 simd16
+--* t44 simd16
Generating: N099 ( 7, 6) [000045] ----------- t45 = * HWINTRINSIC simd16 ubyte CompareEqual REG d0 $1c8
V06 in reg d0 is becoming dead [000044]
Live regs: 0000 {d0} => 0000 {}
Closing debug range.
Live vars after [000044]: {V06} => {}
IN0010: cmeq v0.16b, v16.16b, v0.16b
/--* t45 simd16
Generating: N101 ( 8, 7) [000046] ----------- * RETURN simd16 REG NA $VN.Void
Added IP mapping: EPILOG (G_M8077_IG02,ins#16,ofs#88) label
Reserving epilog IG for block BB01
Saved:
G_M8077_IG02: ; offs=000000H, size=0058H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
Created:
G_M8077_IG03: ; offs=000058H, size=0000H, bbWeight=1, gcrefRegs=0000 {}
*************** After placeholder IG creation
G_M8077_IG01: ; func=00, offs=000000H, size=0000H, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG
G_M8077_IG02: ; offs=000000H, size=0058H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
G_M8077_IG03: ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {}
Variable Live Range History Dump for BB01
V00 arg0: d0 [(G_M8077_IG02,ins#0,ofs#0), (G_M8077_IG02,ins#2,ofs#16)]
V01 arg1: d1 [(G_M8077_IG02,ins#0,ofs#0), (G_M8077_IG02,ins#9,ofs#52)]
V02 arg2: d2 [(G_M8077_IG02,ins#0,ofs#0), (G_M8077_IG02,ins#10,ofs#56)]
V03 loc0: d17 [(G_M8077_IG02,ins#2,ofs#16), (G_M8077_IG02,ins#6,ofs#40)]
V04 loc1: d0 [(G_M8077_IG02,ins#4,ofs#24), (G_M8077_IG02,ins#13,ofs#76)]
V05 loc2: d16 [(G_M8077_IG02,ins#12,ofs#64), (G_M8077_IG02,ins#14,ofs#80)]
V06 loc3: d0 [(G_M8077_IG02,ins#14,ofs#80), (G_M8077_IG02,ins#15,ofs#84)]
V07 loc4: d16 [(G_M8077_IG02,ins#7,ofs#44), (G_M8077_IG02,ins#11,ofs#60)]
Liveness not changing: 0000000000000000 {}
# compCycleEstimate = 76, compSizeEstimate = 71 System.Text.Tests.Demo:IndexOfAnyLookupCombined(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]
; Final local variable assignments
;
; V00 arg0 [V00,T01] ( 4, 4 ) simd16 -> d0 HFA(simd16) single-def
; V01 arg1 [V01,T02] ( 3, 3 ) simd16 -> d1 HFA(simd16) single-def
; V02 arg2 [V02,T03] ( 3, 3 ) simd16 -> d2 HFA(simd16) single-def
; V03 loc0 [V03,T07] ( 2, 2 ) simd16 -> d17 HFA(simd16)
; V04 loc1 [V04,T04] ( 3, 3 ) simd16 -> d0 HFA(simd16)
; V05 loc2 [V05,T08] ( 2, 2 ) simd16 -> d16 HFA(simd16)
; V06 loc3 [V06,T05] ( 3, 3 ) simd16 -> d0 HFA(simd16)
; V07 loc4 [V07,T09] ( 2, 2 ) simd16 -> d16 HFA(simd16)
;* V08 loc5 [V08 ] ( 0, 0 ) simd16 -> zero-ref HFA(simd16)
;* V09 loc6 [V09 ] ( 0, 0 ) simd16 -> zero-ref HFA(simd16)
;# V10 OutArgs [V10 ] ( 1, 1 ) struct ( 0) [sp+00H] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
; V11 tmp1 [V11,T00] ( 5, 10 ) struct (32) [fp+10H] HFA(simd16) do-not-enreg[SF] ld-addr-op "NewObj constructor temp"
;* V12 tmp2 [V12 ] ( 0, 0 ) simd16 -> zero-ref HFA(simd16) "Inline return value spill temp"
; V13 cse0 [V13,T06] ( 3, 3 ) simd16 -> d16 "CSE - aggressive"
;
; Lcl frame size = 32
*************** Before prolog / epilog generation
G_M8077_IG01: ; func=00, offs=000000H, size=0000H, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG
G_M8077_IG02: ; offs=000000H, size=0058H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
G_M8077_IG03: ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {}
Recording Var Locations at start of BB01
V00(d0) V01(d1) V02(d2)
*************** In genFnProlog()
Added IP mapping to front: PROLOG (G_M8077_IG01,ins#0,ofs#0) label
__prolog:
New debug range: first
New debug range: first
New debug range: first
Save float regs: []
Save int regs: [fp lr]
Frame type 1. #outsz=0; #framesz=48; LclFrameSize=32
IN0011: stp fp, lr, [sp, #-0x30]!
offset=48, calleeSaveSpDelta=0
offsetSpToSavedFp=0
IN0012: mov fp, sp
*************** In genFnPrologCalleeRegArgs() for float regs
*************** In genEnregisterIncomingStackArgs()
Closing debug range.
Closing debug range.
Closing debug range.
Saved:
G_M8077_IG01: ; offs=000000H, size=0008H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=0000 {}, gcRegByrefSetCur=0000 {}
Frame type 1. #outsz=0; #framesz=48; localloc? false
calleeSaveSpOffset=48, calleeSaveSpDelta=0
IN0013: ldp fp, lr, [sp], #0x30
IN0014: ret lr
Saved:
G_M8077_IG03: ; offs=000058H, size=0008H, bbWeight=1, epilog, nogc, extend
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M8077_IG01: ; func=00, offs=000000H, size=0008H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
G_M8077_IG02: ; offs=000008H, size=0058H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
G_M8077_IG03: ; offs=000060H, size=0008H, bbWeight=1, epilog, nogc, extend
*************** In emitJumpDistBind()
Emitter Jump List:
IG02 IN0001 ldr[12]
IG02 IN0005 ldr[12]
IG02 IN000d ldr[12]
total jump count: 3
Shrinking jump [D1FFAB1E/001]
Shrinking jump [D1FFAB1E/005]
Shrinking jump [D1FFAB1E/013]
Adjusted offset of BB03 from 0060 to 0048
Total shrinkage = 24, min extra jump size = 4294967295
*************** Finishing PHASE Generate code
*************** Starting PHASE Emit code
Hot code size = 0x50 bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=false, isColdCode=false, unwindSize=0xc)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)
***************************************************************************
Instructions as they come out of the scheduler
G_M8077_IG01: ; offs=000000H, size=0008H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
IN0011: 000000 stp fp, lr, [sp, #-0x30]!
IN0012: 000004 mov fp, sp
;; size=8 bbWeight=1 PerfScore 1.50
G_M8077_IG02: ; offs=000008H, size=0040H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref, isz
IN0001: 000008 ldr q16, [@RWD00]
IN0002: 00000C and v17.16b, v0.16b, v16.16b
IN0003: 000010 ushr v0.4s, v0.4s, #4
IN0004: 000014 and v0.16b, v0.16b, v16.16b
IN0005: 000018 ldr q16, [@RWD16]
IN0006: 00001C and v16.16b, v0.16b, v16.16b
IN0007: 000020 orr v16.16b, v16.16b, v17.16b
IN0008: 000024 stp xzr, xzr, [fp, #0x10]
IN0009: 000028 stp xzr, xzr, [fp, #0x20]
IN000a: 00002C stp q1, q2, [fp, #0x10] // [V11 tmp1], [V11 tmp1+0x10]
IN000b: 000030 ldp q17, q18, [fp, #0x10] // [V11 tmp1], [V11 tmp1+0x10]
IN000c: 000034 tbl v16.16b, {v17.16b, v18.16b}, v16.16b
IN000d: 000038 ldr q17, [@RWD32]
IN000e: 00003C tbl v0.16b, {v17.16b}, v0.16b
IN000f: 000040 and v16.16b, v16.16b, v0.16b
IN0010: 000044 cmeq v0.16b, v16.16b, v0.16b
;; size=64 bbWeight=1 PerfScore 17.00
G_M8077_IG03: ; offs=000048H, size=0008H, bbWeight=1, epilog, nogc, extend
IN0013: 000048 ldp fp, lr, [sp], #0x30
IN0014: 00004C ret lr
;; size=8 bbWeight=1 PerfScore 2.00
Emitting data sections: 48 total bytes
section 0, size 16, RWD 0: 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f
section 1, size 16, RWD16: 08 08 08 08 08 08 08 08 08 08 08 08 08 08 08 08
section 2, size 16, RWD32: 01 02 04 08 10 20 40 80 01 02 04 08 10 20 40 80
Allocated method code size = 80 , actual size = 80, unused size = 0
; Total bytes of code 80, prolog size 8, PerfScore 28.50, instruction count 20, allocated bytes for code 80 (MethodHash=2430e072) for method System.Text.Tests.Demo:IndexOfAnyLookupCombined(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]
; ============================================================
*************** After end code gen, before unwindEmit()
G_M8077_IG01: ; func=00, offs=000000H, size=0008H, bbWeight=1, PerfScore 1.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
IN0011: 000000 stp fp, lr, [sp, #-0x30]!
IN0012: 000004 mov fp, sp
G_M8077_IG02: ; offs=000008H, size=0040H, bbWeight=1, PerfScore 17.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref, isz
IN0001: 000008 ldr q16, [@RWD00]
IN0002: 00000C and v17.16b, v0.16b, v16.16b
IN0003: 000010 ushr v0.4s, v0.4s, #4
IN0004: 000014 and v0.16b, v0.16b, v16.16b
IN0005: 000018 ldr q16, [@RWD16]
IN0006: 00001C and v16.16b, v0.16b, v16.16b
IN0007: 000020 orr v16.16b, v16.16b, v17.16b
IN0008: 000024 stp xzr, xzr, [fp, #0x10]
IN0009: 000028 stp xzr, xzr, [fp, #0x20]
IN000a: 00002C stp q1, q2, [fp, #0x10] // [V11 tmp1], [V11 tmp1+0x10]
IN000b: 000030 ldp q17, q18, [fp, #0x10] // [V11 tmp1], [V11 tmp1+0x10]
IN000c: 000034 tbl v16.16b, {v17.16b, v18.16b}, v16.16b
IN000d: 000038 ldr q17, [@RWD32]
IN000e: 00003C tbl v0.16b, {v17.16b}, v0.16b
IN000f: 000040 and v16.16b, v16.16b, v0.16b
IN0010: 000044 cmeq v0.16b, v16.16b, v0.16b
G_M8077_IG03: ; offs=000048H, size=0008H, bbWeight=1, PerfScore 2.00, epilog, nogc, extend
IN0013: 000048 ldp fp, lr, [sp], #0x30
IN0014: 00004C ret lr
*************** Finishing PHASE Emit code
*************** Starting PHASE Emit GC+EH tables
Unwind Info:
>> Start offset : 0x000000 (not in unwind data)
>> End offset : 0xd1ffab1e (not in unwind data)
Code Words : 1
Epilog Count : 1
E bit : 0
X bit : 0
Vers : 0
Function Length : 20 (0x00014) Actual length = 80 (0x000050)
---- Epilog scopes ----
---- Scope 0
Epilog Start Offset : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e)
Epilog Start Index : 1 (0x01)
---- Unwind codes ----
E1 set_fp; mov fp, sp
---- Epilog start at index 1 ----
85 save_fplr_x #5 (0x05); stp fp, lr, [sp, #-48]!
E4 end
E4 end
allocUnwindInfo(pHotCode=0x0xd1ffab1e, pColdCode=0x(nil), startOffset=0x0, endOffset=0x50, unwindSize=0xc, pUnwindBlock=0x0xd1ffab1e, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 9
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000008 ( STACK_EMPTY )
IL offs 0x000E : 0x00000010 ( STACK_EMPTY )
IL offs 0x0033 : 0x00000018 ( STACK_EMPTY )
IL offs 0x0050 : 0x00000024 ( STACK_EMPTY )
IL offs 0x0057 : 0x00000030
IL offs 0x0093 : 0x00000038 ( STACK_EMPTY )
IL offs 0x00AD : 0x00000040 ( STACK_EMPTY )
IL offs EPILOG : 0x00000048 ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 11
; Variable debug info: 11 live ranges, 8 vars for method System.Text.Tests.Demo:IndexOfAnyLookupCombined(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]
(V00 arg0) : From 00000000h to 00000008h, in d0
(V00 arg0) : From 00000008h to 00000010h, in d0
(V01 arg1) : From 00000000h to 00000008h, in d1
(V01 arg1) : From 00000008h to 0000002Ch, in d1
(V02 arg2) : From 00000000h to 00000008h, in d2
(V02 arg2) : From 00000008h to 00000030h, in d2
(V03 loc0) : From 00000010h to 00000020h, in d17
(V04 loc1) : From 00000018h to 0000003Ch, in d0
(V05 loc2) : From 00000038h to 00000040h, in d16
(V06 loc3) : From 00000040h to 00000044h, in d0
(V07 loc4) : From 00000024h to 00000034h, in d16
*************** In gcInfoBlockHdrSave()
Set code length to 80.
Set ReturnKind to Scalar.
Set stack base register to fp.
Set Outgoing stack arg area size to 0.
Defining 0 call sites:
*************** Finishing PHASE Emit GC+EH tables
Method code size: 80
Allocations for System.Text.Tests.Demo:IndexOfAnyLookupCombined(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte] (MethodHash=2430e072)
count: 1173, size: 114662, max = 5880
allocateMemory: 131072, nraUsed: 119912
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
AssertionProp | 6604 | 5.76%
ASTNode | 10816 | 9.43%
InstDesc | 7032 | 6.13%
ImpStack | 384 | 0.33%
BasicBlock | 3608 | 3.15%
CallArgs | 360 | 0.31%
FlowEdge | 528 | 0.46%
TreeStatementList | 64 | 0.06%
SiScope | 0 | 0.00%
DominatorMemory | 96 | 0.08%
LSRA | 7828 | 6.83%
LSRA_Interval | 2960 | 2.58%
LSRA_RefPosition | 4960 | 4.33%
Reachability | 40 | 0.03%
SSA | 1208 | 1.05%
ValueNumber | 10602 | 9.25%
LvaTable | 2028 | 1.77%
UnwindInfo | 32 | 0.03%
hashBv | 40 | 0.03%
bitset | 576 | 0.50%
FixedBitVect | 96 | 0.08%
Generic | 1400 | 1.22%
LocalAddressVisitor | 0 | 0.00%
FieldSeqStore | 0 | 0.00%
MemorySsaMap | 40 | 0.03%
MemoryPhiArg | 0 | 0.00%
CSE | 2624 | 2.29%
GC | 1232 | 1.07%
CorTailCallInfo | 0 | 0.00%
Inlining | 2216 | 1.93%
ArrayStack | 0 | 0.00%
DebugInfo | 832 | 0.73%
DebugOnly | 40078 | 34.95%
Codegen | 1088 | 0.95%
LoopOpt | 0 | 0.00%
LoopClone | 0 | 0.00%
LoopHoist | 0 | 0.00%
Unknown | 154 | 0.13%
RangeCheck | 0 | 0.00%
CopyProp | 1840 | 1.60%
Promotion | 0 | 0.00%
SideEffects | 0 | 0.00%
ObjectAllocator | 0 | 0.00%
VariableLiveRanges | 2272 | 1.98%
ClassLayout | 176 | 0.15%
TailMergeThrows | 0 | 0.00%
EarlyProp | 0 | 0.00%
ZeroInit | 568 | 0.50%
Pgo | 280 | 0.24%
****** DONE compiling System.Text.Tests.Demo:IndexOfAnyLookupCombined(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte]
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