aarch64_less_args_no_debug_asm_dump.txt

; Assembly listing for method System.Text.ASCIIUtility:NarrowUtf16ToAscii_Intrinsified(long,long,long):long
; Emitting BLENDED_CODE for generic ARM64 CPU - Unix
; Tier-1 compilation
; optimized code
; fp based frame
; fully interruptible
; No PGO data
; 0 inlinees with PGO data; 0 single block inlinees; 8 inlinees without PGO data
; Final local variable assignments
;
;  V00 arg0         [V00,T06] (  3,  3   )    long  ->   x0         single-def
;  V01 arg1         [V01,T05] (  5,  3.50)    long  ->   x1         single-def
;  V02 arg2         [V02,T07] (  3,  2.50)    long  ->   x2         single-def
;* V03 loc0         [V03,T12] (  0,  0   )     int  ->  zero-ref
;* V04 loc1         [V04,T13] (  0,  0   )    long  ->  zero-ref
;  V05 loc2         [V05,T01] (  5, 10.50)   byref  ->   x0         single-def
;  V06 loc3         [V06,T14] ( 14, 19   )  simd16  ->  d16         HFA(simd16)
;  V07 loc4         [V07,T03] (  5,  6   )   byref  ->   x3         single-def
;  V08 loc5         [V08,T17] (  8, 11   )  simd16  ->  d16         HFA(simd16)
;  V09 loc6         [V09,T00] ( 11, 26.50)    long  ->   x4
;  V10 loc7         [V10,T08] (  2,  4.50)    long  ->   x1
;  V11 loc8         [V11,T15] (  3, 12   )  simd16  ->  d18         HFA(simd16)
;  V12 loc9         [V12,T16] (  3, 12   )  simd16  ->  d19         HFA(simd16)
;# V13 OutArgs      [V13    ] (  1,  1   )  lclBlk ( 0) [sp+00H]   "OutgoingArgSpace"
;* V14 tmp1         [V14,T09] (  0,  0   )    bool  ->  zero-ref    "Inline return value spill temp"
;* V15 tmp2         [V15    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inlining Arg"
;* V16 tmp3         [V16    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp"
;* V17 tmp4         [V17    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inlining Arg"
;* V18 tmp5         [V18,T10] (  0,  0   )    bool  ->  zero-ref    "Inline return value spill temp"
;* V19 tmp6         [V19    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inlining Arg"
;* V20 tmp7         [V20    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp"
;* V21 tmp8         [V21    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inlining Arg"
;* V22 tmp9         [V22,T04] (  0,  0   )    bool  ->  zero-ref    "Inline return value spill temp"
;* V23 tmp10        [V23    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inlining Arg"
;* V24 tmp11        [V24    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp"
;* V25 tmp12        [V25    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inlining Arg"
;* V26 tmp13        [V26    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inlining Arg"
;* V27 tmp14        [V27,T11] (  0,  0   )    bool  ->  zero-ref    "Inline return value spill temp"
;* V28 tmp15        [V28    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inlining Arg"
;* V29 tmp16        [V29    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp"
;* V30 tmp17        [V30    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inlining Arg"
;  V31 cse0         [V31,T02] (  3,  8.50)    long  ->   x2         "CSE - moderate"
;  V32 cse1         [V32,T18] (  4,  2   )  simd16  ->  d17         HFA(simd16)  "CSE - moderate"
;
; Lcl frame size = 0

G_M37634_IG01:
            stp     fp, lr, [sp,#-16]!
            mov     fp, sp
						;; size=8 bbWeight=1    PerfScore 1.50
G_M37634_IG02:
            ld1     {v16.8h}, [x0]
            umaxp   v17.8h, v16.8h, v16.8h
            umov    x3, v17.d[0]
            tst     x3, #0xd1ffab1e
            bne     G_M37634_IG04
						;; size=20 bbWeight=1    PerfScore 6.50
G_M37634_IG03:
            mov     x3, x1
            ldr     q17, [@RWD00]
            tbl     v16.16b, {v16.16b}, v17.16b
            st1     {v16.8b}, [x3]
            mov     x4, #8
            tbnz    w1, #3, G_M37634_IG06
            add     x5, x0, #16
            ld1     {v16.8h}, [x5]
            umaxp   v18.8h, v16.8h, v16.8h
            umov    x5, v18.d[0]
            tst     x5, #0xd1ffab1e
            bne     G_M37634_IG08
            tbl     v16.16b, {v16.16b}, v17.16b
            add     x4, x3, #8
            st1     {v16.8b}, [x4]
            b       G_M37634_IG06
            align   [4 bytes for IG07]
            align   [4 bytes]
            align   [0 bytes]
            align   [0 bytes]
						;; size=72 bbWeight=0.50 PerfScore 7.75
G_M37634_IG04:
            mov     x0, xzr
						;; size=4 bbWeight=0.50 PerfScore 0.25
G_M37634_IG05:
            ldp     fp, lr, [sp],#16
            ret     lr
						;; size=8 bbWeight=0.50 PerfScore 1.00
G_M37634_IG06:
            and     x1, x1, #15
            mov     x4, #16
            sub     x4, x4, x1
            sub     x1, x2, #16
						;; size=16 bbWeight=0.50 PerfScore 1.00
G_M37634_IG07:
            lsl     x2, x4, #1
            ldr     q16, [x0, x2]
            add     x2, x4, #8
            lsl     x5, x2, #1
            ldr     q18, [x0, x5]
            orr     v19.8h, v16.8h, v18.8h
            umaxp   v19.8h, v19.8h, v19.8h
            umov    x5, v19.d[0]
            tst     x5, #0xd1ffab1e
            bne     G_M37634_IG10
            uzp1    v16.16b, v16.16b, v18.16b
            add     x2, x3, x4
            st1     {v16.16b}, [x2]
            add     x4, x4, #16
            cmp     x4, x1
            bls     G_M37634_IG07
						;; size=64 bbWeight=4    PerfScore 68.00
G_M37634_IG08:
            mov     x0, x4
						;; size=4 bbWeight=0.50 PerfScore 0.25
G_M37634_IG09:
            ldp     fp, lr, [sp],#16
            ret     lr
						;; size=8 bbWeight=0.50 PerfScore 1.00
G_M37634_IG10:
            umaxp   v18.8h, v16.8h, v16.8h
            umov    x0, v18.d[0]
            tst     x0, #0xd1ffab1e
            bne     G_M37634_IG08
            tbl     v16.16b, {v16.16b}, v17.16b
            add     x4, x3, x4
            st1     {v16.8b}, [x4]
            mov     x4, x2
            b       G_M37634_IG08
						;; size=36 bbWeight=0.50 PerfScore 3.50
RWD00  	dq	0E0C0A0806040200h, 0E0C0A0806040200h