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Some notes I typed a while ago on my phone trying to kind-of reverse engineer (guess) and understand the public (but blurry as heck) GlobalFoundries 180 nanometer standard cell layout images. See the comment below.
https://gf180mcu-pdk.readthedocs.io/en/latest/digital/standard_cells/gf180mcu_fd_sc_mcu9t5v0/cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_1.html
nand A B
0 0 1 (+) | O | (+) (OR, eithr side 0)
0 1 1 | |
1 0 1 | |
1 1 0 (--) | | O (AND, both 1
to cross = Out (-))
nor B A
0 0 1 (+) | | O (AND, both 1 to
0 1 0 | | cross = Out (+))
1 0 0 | |
1 1 0 (--) | O | (--) (OR, eithr side 0)
invert A
0 1 O | (+) (toggles on wh A=0)
1 0 |
|
O | (--) (toggles on wh A=1)
com_nand=nand(a, b)
remaind=invert(com_nand)
sum=invert(block(com_nand, nor(a, b)))
block=invert the nand, and use as gate to set the nor 1 1 0 to 1 1 1 so we get xnor
https://gf180mcu-pdk.readthedocs.io/en/latest/digital/standard_cells/gf180mcu_fd_sc_mcu9t5v0/cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_1.html
b a1 a2 zh
0 0 0 1 it needs at least one zero
0 0 1 1 from a1 or a2, and b being
0 1 0 1 always zero to output 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
(inv(a1) OR inv(a2)) AND inv(b)
@Swyter

Swyter commented Jun 12, 2026

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Here are some notes I typed a while ago on my phone trying to kind-of reverse engineer (well, guess) and intuitively understand those public (but blurry as heck) GlobalFoundries 180 nanometer standard cell layout images in a visual way without any math crap.

The idea was to go backwards, to understand the mess of wires in a half-adder logic cell (see at the bottom of the notes) starting from the inverter, which seems like the simplest CMOS transistor but it doesn't intuitively make sense until you visualize it with a diagram, then from that the NAND and NOR gates, which are the main blocks a physical adder has. I think I kind of understand CMOS logic now, and why it's like that. I'm no teacher or expert, but it more or less clicks for me like this:

CMOS is complementary because the same transistor (here represented as a vertical line that blocks or interrupts any horizontal wires it crosses over) being on or off has the opposite effect in the top and the bottom halves. If a transistor line is off it acts as a barrier in the bottom half while still flowing/going across in the top part, and vice versa; if the transistor line is on it more or less instantly blocks current flow from the top half and lifts the barrier so that electricity at the same time it's blocking it flows on the bottom half.

The logic is set up so that the electric flow to the output O always comes from either the top (+) (i.e. +5V) or bottom (-) (i.e. ground) part in any given combination, but it never flows from both at the same time (an electric short).

There's an O for each top or bottom half, all outputs Os are technically tied together, so there can't be any electricity flowing from a top and a bottom O at the same time or it goes kaboom. If 0 isn't connected to anything (here it should always be (-) or (+)) then its output is in a hi-Z/undefined/unconnected/floating state, this is more for analog circuits where there's pull ups, pull down resistors, buffers, muxes and that kind of thing. Here we're technically aiming for digital outcomes, even if we're faking it in an analog world and we don't want undefined results. So electricity must flow up or down so that we always get concrete (and complementary) results. If it's not good it always needs to be explicitly bad for the rest of the logic to work.

All in all, I find the CMOS stuff pretty elegant and compact. Because as you turn off a faucet or tap it turns on a parallel/linked one at the same speed and to the opposite degree, so it's proportional electrically and gapless.

Hope someone else finds the diagrams interesting, and hope it helps.

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