Last active
December 22, 2017 12:07
-
-
Save TheStrix/2d59a1607d20cf2c92abc6220f4f1639 to your computer and use it in GitHub Desktop.
SAGIT (Qualcomm Technologies, Inc. MSM 8998 v2.1 MTP) from stock oreo 7.12.19
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
/dts-v1/; | |
/ { | |
#address-cells = <0x2>; | |
#size-cells = <0x2>; | |
model = "Qualcomm Technologies, Inc. MSM 8998 v2.1 MTP"; | |
compatible = "qcom,msm8998-mtp", "qcom,msm8998", "qcom,mtp"; | |
qcom,msm-id = <0x124 0x20001>; | |
interrupt-parent = <0x1>; | |
qcom,board-id = <0x1e 0x0>; | |
cpus { | |
#address-cells = <0x2>; | |
#size-cells = <0x0>; | |
cpu@0 { | |
device_type = "cpu"; | |
compatible = "arm,armv8"; | |
reg = <0x0 0x0>; | |
qcom,limits-info = <0x2>; | |
qcom,lmh-dcvs = <0x3>; | |
enable-method = "psci"; | |
efficiency = <0x400>; | |
next-level-cache = <0x4>; | |
qcom,ea = <0x5>; | |
linux,phandle = <0x16>; | |
phandle = <0x16>; | |
l2-cache { | |
compatible = "arm,arch-cache"; | |
cache-level = <0x2>; | |
qcom,dump-size = <0x0>; | |
linux,phandle = <0x4>; | |
phandle = <0x4>; | |
}; | |
l1-icache { | |
compatible = "arm,arch-cache"; | |
qcom,dump-size = <0x9040>; | |
linux,phandle = <0xa9>; | |
phandle = <0xa9>; | |
}; | |
l1-dcache { | |
compatible = "arm,arch-cache"; | |
qcom,dump-size = <0x9040>; | |
linux,phandle = <0xb1>; | |
phandle = <0xb1>; | |
}; | |
l1-tlb { | |
qcom,dump-size = <0x2000>; | |
linux,phandle = <0xb9>; | |
phandle = <0xb9>; | |
}; | |
}; | |
cpu@1 { | |
device_type = "cpu"; | |
compatible = "arm,armv8"; | |
reg = <0x0 0x1>; | |
qcom,limits-info = <0x6>; | |
qcom,lmh-dcvs = <0x3>; | |
enable-method = "psci"; | |
efficiency = <0x400>; | |
next-level-cache = <0x4>; | |
qcom,ea = <0x7>; | |
linux,phandle = <0x17>; | |
phandle = <0x17>; | |
l1-icache { | |
compatible = "arm,arch-cache"; | |
qcom,dump-size = <0x9040>; | |
linux,phandle = <0xaa>; | |
phandle = <0xaa>; | |
}; | |
l1-dcache { | |
compatible = "arm,arch-cache"; | |
qcom,dump-size = <0x9040>; | |
linux,phandle = <0xb2>; | |
phandle = <0xb2>; | |
}; | |
l1-tlb { | |
qcom,dump-size = <0x2000>; | |
linux,phandle = <0xba>; | |
phandle = <0xba>; | |
}; | |
}; | |
cpu@2 { | |
device_type = "cpu"; | |
compatible = "arm,armv8"; | |
reg = <0x0 0x2>; | |
qcom,limits-info = <0x8>; | |
qcom,lmh-dcvs = <0x3>; | |
enable-method = "psci"; | |
efficiency = <0x400>; | |
next-level-cache = <0x4>; | |
qcom,ea = <0x9>; | |
linux,phandle = <0x18>; | |
phandle = <0x18>; | |
l1-icache { | |
compatible = "arm,arch-cache"; | |
qcom,dump-size = <0x9040>; | |
linux,phandle = <0xab>; | |
phandle = <0xab>; | |
}; | |
l1-dcache { | |
compatible = "arm,arch-cache"; | |
qcom,dump-size = <0x9040>; | |
linux,phandle = <0xb3>; | |
phandle = <0xb3>; | |
}; | |
l1-tlb { | |
qcom,dump-size = <0x2000>; | |
linux,phandle = <0xbb>; | |
phandle = <0xbb>; | |
}; | |
}; | |
cpu@3 { | |
device_type = "cpu"; | |
compatible = "arm,armv8"; | |
reg = <0x0 0x3>; | |
qcom,limits-info = <0xa>; | |
qcom,lmh-dcvs = <0x3>; | |
enable-method = "psci"; | |
efficiency = <0x400>; | |
next-level-cache = <0x4>; | |
qcom,ea = <0xb>; | |
linux,phandle = <0x19>; | |
phandle = <0x19>; | |
l1-icache { | |
compatible = "arm,arch-cache"; | |
qcom,dump-size = <0x9040>; | |
linux,phandle = <0xac>; | |
phandle = <0xac>; | |
}; | |
l1-dcache { | |
compatible = "arm,arch-cache"; | |
qcom,dump-size = <0x9040>; | |
linux,phandle = <0xb4>; | |
phandle = <0xb4>; | |
}; | |
l1-tlb { | |
qcom,dump-size = <0x2000>; | |
linux,phandle = <0xbc>; | |
phandle = <0xbc>; | |
}; | |
}; | |
cpu@100 { | |
device_type = "cpu"; | |
compatible = "arm,armv8"; | |
reg = <0x0 0x100>; | |
qcom,limits-info = <0xc>; | |
qcom,lmh-dcvs = <0xd>; | |
enable-method = "psci"; | |
efficiency = <0x600>; | |
next-level-cache = <0xe>; | |
qcom,ea = <0xf>; | |
linux,phandle = <0x1a>; | |
phandle = <0x1a>; | |
l2-cache { | |
compatible = "arm,arch-cache"; | |
cache-level = <0x2>; | |
linux,phandle = <0xe>; | |
phandle = <0xe>; | |
}; | |
l1-icache { | |
compatible = "arm,arch-cache"; | |
qcom,dump-size = <0x12000>; | |
linux,phandle = <0xad>; | |
phandle = <0xad>; | |
}; | |
l1-dcache { | |
compatible = "arm,arch-cache"; | |
qcom,dump-size = <0x12000>; | |
linux,phandle = <0xb5>; | |
phandle = <0xb5>; | |
}; | |
l1-tlb { | |
qcom,dump-size = <0x4800>; | |
linux,phandle = <0xbd>; | |
phandle = <0xbd>; | |
}; | |
}; | |
cpu@101 { | |
device_type = "cpu"; | |
compatible = "arm,armv8"; | |
reg = <0x0 0x101>; | |
qcom,limits-info = <0x10>; | |
qcom,lmh-dcvs = <0xd>; | |
enable-method = "psci"; | |
efficiency = <0x600>; | |
next-level-cache = <0xe>; | |
qcom,ea = <0x11>; | |
linux,phandle = <0x1b>; | |
phandle = <0x1b>; | |
l1-icache { | |
compatible = "arm,arch-cache"; | |
qcom,dump-size = <0x12000>; | |
linux,phandle = <0xae>; | |
phandle = <0xae>; | |
}; | |
l1-dcache { | |
compatible = "arm,arch-cache"; | |
qcom,dump-size = <0x12000>; | |
linux,phandle = <0xb6>; | |
phandle = <0xb6>; | |
}; | |
l1-tlb { | |
qcom,dump-size = <0x4800>; | |
linux,phandle = <0xbe>; | |
phandle = <0xbe>; | |
}; | |
}; | |
cpu@102 { | |
device_type = "cpu"; | |
compatible = "arm,armv8"; | |
reg = <0x0 0x102>; | |
qcom,limits-info = <0x12>; | |
qcom,lmh-dcvs = <0xd>; | |
enable-method = "psci"; | |
efficiency = <0x600>; | |
next-level-cache = <0xe>; | |
qcom,ea = <0x13>; | |
linux,phandle = <0x1c>; | |
phandle = <0x1c>; | |
l1-icache { | |
compatible = "arm,arch-cache"; | |
qcom,dump-size = <0x12000>; | |
linux,phandle = <0xaf>; | |
phandle = <0xaf>; | |
}; | |
l1-dcache { | |
compatible = "arm,arch-cache"; | |
qcom,dump-size = <0x12000>; | |
linux,phandle = <0xb7>; | |
phandle = <0xb7>; | |
}; | |
l1-tlb { | |
qcom,dump-size = <0x4800>; | |
linux,phandle = <0xbf>; | |
phandle = <0xbf>; | |
}; | |
}; | |
cpu@103 { | |
device_type = "cpu"; | |
compatible = "arm,armv8"; | |
reg = <0x0 0x103>; | |
qcom,limits-info = <0x14>; | |
qcom,lmh-dcvs = <0xd>; | |
enable-method = "psci"; | |
efficiency = <0x600>; | |
next-level-cache = <0xe>; | |
qcom,ea = <0x15>; | |
linux,phandle = <0x1d>; | |
phandle = <0x1d>; | |
l1-icache { | |
compatible = "arm,arch-cache"; | |
qcom,dump-size = <0x12000>; | |
linux,phandle = <0xb0>; | |
phandle = <0xb0>; | |
}; | |
l1-dcache { | |
compatible = "arm,arch-cache"; | |
qcom,dump-size = <0x12000>; | |
linux,phandle = <0xb8>; | |
phandle = <0xb8>; | |
}; | |
l1-tlb { | |
qcom,dump-size = <0x4800>; | |
linux,phandle = <0xc0>; | |
phandle = <0xc0>; | |
}; | |
}; | |
cpu-map { | |
cluster0 { | |
core0 { | |
cpu = <0x16>; | |
}; | |
core1 { | |
cpu = <0x17>; | |
}; | |
core2 { | |
cpu = <0x18>; | |
}; | |
core3 { | |
cpu = <0x19>; | |
}; | |
}; | |
cluster1 { | |
core0 { | |
cpu = <0x1a>; | |
}; | |
core1 { | |
cpu = <0x1b>; | |
}; | |
core2 { | |
cpu = <0x1c>; | |
}; | |
core3 { | |
cpu = <0x1d>; | |
}; | |
}; | |
}; | |
}; | |
soc { | |
#address-cells = <0x1>; | |
#size-cells = <0x1>; | |
ranges = <0x0 0x0 0x0 0xffffffff>; | |
compatible = "simple-bus"; | |
qcom,smp2p-modem@17911008 { | |
compatible = "qcom,smp2p"; | |
reg = <0x17911008 0x4>; | |
qcom,remote-pid = <0x1>; | |
qcom,irq-bitmask = <0x4000>; | |
interrupts = <0x0 0x1c3 0x1>; | |
}; | |
qcom,smp2p-adsp@17911008 { | |
compatible = "qcom,smp2p"; | |
reg = <0x17911008 0x4>; | |
qcom,remote-pid = <0x2>; | |
qcom,irq-bitmask = <0x400>; | |
interrupts = <0x0 0x9e 0x1>; | |
}; | |
qcom,smp2p-dsps@17911008 { | |
compatible = "qcom,smp2p"; | |
reg = <0x17911008 0x4>; | |
qcom,remote-pid = <0x3>; | |
qcom,irq-bitmask = <0x4000000>; | |
interrupts = <0x0 0xb2 0x1>; | |
}; | |
qcom,smp2pgpio-smp2p-15-in { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "smp2p"; | |
qcom,remote-pid = <0xf>; | |
qcom,is-inbound; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0x1e>; | |
phandle = <0x1e>; | |
}; | |
qcom,smp2pgpio_test_smp2p_15_in { | |
compatible = "qcom,smp2pgpio_test_smp2p_15_in"; | |
gpios = <0x1e 0x0 0x0>; | |
}; | |
qcom,smp2pgpio-smp2p-15-out { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "smp2p"; | |
qcom,remote-pid = <0xf>; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0x1f>; | |
phandle = <0x1f>; | |
}; | |
qcom,smp2pgpio_test_smp2p_15_out { | |
compatible = "qcom,smp2pgpio_test_smp2p_15_out"; | |
gpios = <0x1f 0x0 0x0>; | |
}; | |
qcom,smp2pgpio-smp2p-1-in { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "smp2p"; | |
qcom,remote-pid = <0x1>; | |
qcom,is-inbound; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0x20>; | |
phandle = <0x20>; | |
}; | |
qcom,smp2pgpio_test_smp2p_1_in { | |
compatible = "qcom,smp2pgpio_test_smp2p_1_in"; | |
gpios = <0x20 0x0 0x0>; | |
}; | |
qcom,smp2pgpio-smp2p-1-out { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "smp2p"; | |
qcom,remote-pid = <0x1>; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0x21>; | |
phandle = <0x21>; | |
}; | |
qcom,smp2pgpio_test_smp2p_1_out { | |
compatible = "qcom,smp2pgpio_test_smp2p_1_out"; | |
gpios = <0x21 0x0 0x0>; | |
}; | |
qcom,smp2pgpio-smp2p-2-in { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "smp2p"; | |
qcom,remote-pid = <0x2>; | |
qcom,is-inbound; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0x22>; | |
phandle = <0x22>; | |
}; | |
qcom,smp2pgpio_test_smp2p_2_in { | |
compatible = "qcom,smp2pgpio_test_smp2p_2_in"; | |
gpios = <0x22 0x0 0x0>; | |
}; | |
qcom,smp2pgpio-smp2p-2-out { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "smp2p"; | |
qcom,remote-pid = <0x2>; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0x23>; | |
phandle = <0x23>; | |
}; | |
qcom,smp2pgpio_test_smp2p_2_out { | |
compatible = "qcom,smp2pgpio_test_smp2p_2_out"; | |
gpios = <0x23 0x0 0x0>; | |
}; | |
qcom,smp2pgpio-smp2p-3-in { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "smp2p"; | |
qcom,remote-pid = <0x3>; | |
qcom,is-inbound; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0x24>; | |
phandle = <0x24>; | |
}; | |
qcom,smp2pgpio_test_smp2p_3_in { | |
compatible = "qcom,smp2pgpio_test_smp2p_3_in"; | |
gpios = <0x24 0x0 0x0>; | |
}; | |
qcom,smp2pgpio-smp2p-3-out { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "smp2p"; | |
qcom,remote-pid = <0x3>; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0x25>; | |
phandle = <0x25>; | |
}; | |
qcom,smp2pgpio-ssr-smp2p-1-in { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "slave-kernel"; | |
qcom,remote-pid = <0x1>; | |
qcom,is-inbound; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0x8c>; | |
phandle = <0x8c>; | |
}; | |
qcom,smp2pgpio-ssr-smp2p-1-out { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "master-kernel"; | |
qcom,remote-pid = <0x1>; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0x8d>; | |
phandle = <0x8d>; | |
}; | |
qcom,smp2pgpio-ssr-smp2p-2-in { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "slave-kernel"; | |
qcom,remote-pid = <0x2>; | |
qcom,is-inbound; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0x89>; | |
phandle = <0x89>; | |
}; | |
qcom,smp2pgpio-ssr-smp2p-2-out { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "master-kernel"; | |
qcom,remote-pid = <0x2>; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0x8a>; | |
phandle = <0x8a>; | |
}; | |
qcom,smp2pgpio-ssr-smp2p-3-in { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "slave-kernel"; | |
qcom,remote-pid = <0x3>; | |
qcom,is-inbound; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0xa4>; | |
phandle = <0xa4>; | |
}; | |
qcom,smp2pgpio-ssr-smp2p-3-out { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "master-kernel"; | |
qcom,remote-pid = <0x3>; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0xa5>; | |
phandle = <0xa5>; | |
}; | |
qcom,smp2pgpio_test_smp2p_3_out { | |
compatible = "qcom,smp2pgpio_test_smp2p_3_out"; | |
gpios = <0x25 0x0 0x0>; | |
}; | |
qcom,smp2pgpio-sleepstate-gpio-3-out { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "sleepstate"; | |
qcom,remote-pid = <0x3>; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0x26>; | |
phandle = <0x26>; | |
}; | |
qcom,smp2pgpio-sleepstate-3-out { | |
compatible = "qcom,smp2pgpio_sleepstate_3_out"; | |
gpios = <0x26 0x0 0x0>; | |
}; | |
qcom,smp2pgpio-ipa-1-out { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "ipa"; | |
qcom,remote-pid = <0x1>; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0x61>; | |
phandle = <0x61>; | |
}; | |
qcom,smp2pgpio-ipa-1-in { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "ipa"; | |
qcom,remote-pid = <0x1>; | |
qcom,is-inbound; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0x62>; | |
phandle = <0x62>; | |
}; | |
qcom,gdsc@10f004 { | |
compatible = "qcom,gdsc"; | |
regulator-name = "gdsc_usb30"; | |
reg = <0x10f004 0x4>; | |
status = "ok"; | |
linux,phandle = <0x84>; | |
phandle = <0x84>; | |
}; | |
qcom,gdsc@16b004 { | |
compatible = "qcom,gdsc"; | |
regulator-name = "gdsc_pcie_0"; | |
reg = <0x16b004 0x4>; | |
status = "ok"; | |
linux,phandle = <0x9e>; | |
phandle = <0x9e>; | |
}; | |
qcom,gdsc@175004 { | |
compatible = "qcom,gdsc"; | |
regulator-name = "gdsc_ufs"; | |
reg = <0x175004 0x4>; | |
status = "ok"; | |
linux,phandle = <0x7e>; | |
phandle = <0x7e>; | |
}; | |
qcom,gdsc@17d034 { | |
compatible = "qcom,gdsc"; | |
regulator-name = "gdsc_hlos1_vote_lpass_adsp"; | |
reg = <0x17d034 0x4>; | |
qcom,no-status-check-on-disable; | |
qcom,gds-timeout = <0x1f4>; | |
status = "ok"; | |
linux,phandle = <0xd2>; | |
phandle = <0xd2>; | |
}; | |
qcom,gdsc@17d038 { | |
compatible = "qcom,gdsc"; | |
regulator-name = "gdsc_hlos1_vote_lpass_core"; | |
reg = <0x17d038 0x4>; | |
qcom,no-status-check-on-disable; | |
qcom,gds-timeout = <0x1f4>; | |
status = "ok"; | |
}; | |
qcom,gdsc@c8ce020 { | |
compatible = "qcom,gdsc"; | |
regulator-name = "gdsc_bimc_smmu"; | |
reg = <0xc8ce020 0x4 0xc8ce024 0x4>; | |
reg-names = "base", "hw_ctrl_addr"; | |
qcom,no-status-check-on-disable; | |
qcom,gds-timeout = <0x1f4>; | |
status = "ok"; | |
clock-names = "bus_clk"; | |
clocks = <0x27 0xc365ac39>; | |
proxy-supply = <0x28>; | |
qcom,proxy-consumer-enable; | |
linux,phandle = <0x28>; | |
phandle = <0x28>; | |
}; | |
qcom,gdsc@c8c1024 { | |
compatible = "qcom,gdsc"; | |
regulator-name = "gdsc_venus"; | |
reg = <0xc8c1024 0x4>; | |
status = "ok"; | |
clock-names = "bus_clk", "maxi_clk", "core_clk"; | |
clocks = <0x27 0xf3178ba5 0x27 0x1785ef88 0x27 0x78f14c85>; | |
linux,phandle = <0xa6>; | |
phandle = <0xa6>; | |
}; | |
qcom,gdsc@c8c1040 { | |
compatible = "qcom,gdsc"; | |
regulator-name = "gdsc_venus_core0"; | |
reg = <0xc8c1040 0x4>; | |
status = "ok"; | |
clock-names = "core0_clk"; | |
clocks = <0x27 0x23fae359>; | |
qcom,support-hw-trigger; | |
linux,phandle = <0xf8>; | |
phandle = <0xf8>; | |
}; | |
qcom,gdsc@c8c1044 { | |
compatible = "qcom,gdsc"; | |
regulator-name = "gdsc_venus_core1"; | |
reg = <0xc8c1044 0x4>; | |
status = "ok"; | |
clock-names = "core1_clk"; | |
clocks = <0x27 0x5213a0c7>; | |
qcom,support-hw-trigger; | |
linux,phandle = <0xf9>; | |
phandle = <0xf9>; | |
}; | |
qcom,gdsc@c8c34a0 { | |
compatible = "qcom,gdsc"; | |
regulator-name = "gdsc_camss_top"; | |
reg = <0xc8c34a0 0x4>; | |
status = "ok"; | |
ock-names = "bus_clk", "vfe_axi"; | |
clocks = <0x27 0xd84e390b 0x27 0xe626d8a1>; | |
linux,phandle = <0x29>; | |
phandle = <0x29>; | |
}; | |
qcom,gdsc@c8c3664 { | |
compatible = "qcom,gdsc"; | |
regulator-name = "gdsc_vfe0"; | |
reg = <0xc8c3664 0x4>; | |
status = "ok"; | |
clock-names = "core0_clk", "core0_stream_clk"; | |
clocks = <0x27 0xead28288 0x27 0xa0428287>; | |
parent-supply = <0x29>; | |
linux,phandle = <0xd9>; | |
phandle = <0xd9>; | |
}; | |
qcom,gdsc@c8c3674 { | |
compatible = "qcom,gdsc"; | |
regulator-name = "gdsc_vfe1"; | |
reg = <0xc8c3674 0x4>; | |
status = "ok"; | |
clock-names = "core1_clk", "core1_stream_clk"; | |
clocks = <0x27 0xc216b14d 0x27 0x745af3b6>; | |
parent-supply = <0x29>; | |
linux,phandle = <0xda>; | |
phandle = <0xda>; | |
}; | |
qcom,gdsc@c8c36d4 { | |
compatible = "qcom,gdsc"; | |
regulator-name = "gdsc_cpp"; | |
reg = <0xc8c36d4 0x4>; | |
status = "ok"; | |
clock-names = "core_clk"; | |
clocks = <0x27 0x8e99ef57>; | |
parent-supply = <0x29>; | |
qcom,support-hw-trigger; | |
linux,phandle = <0xd8>; | |
phandle = <0xd8>; | |
}; | |
qcom,gdsc@c8c2304 { | |
compatible = "qcom,gdsc"; | |
regulator-name = "gdsc_mdss"; | |
reg = <0xc8c2304 0x4>; | |
status = "ok"; | |
proxy-supply = <0x2a>; | |
qcom,proxy-consumer-enable; | |
linux,phandle = <0x2a>; | |
phandle = <0x2a>; | |
}; | |
qcom,gdsc@5066004 { | |
compatible = "qcom,gdsc"; | |
regulator-name = "gdsc_gpu_cx"; | |
reg = <0x5066004 0x4 0x5066008 0x4>; | |
reg-names = "base", "hw_ctrl_addr"; | |
qcom,no-status-check-on-disable; | |
qcom,gds-timeout = <0x1f4>; | |
status = "ok"; | |
linux,phandle = <0xd3>; | |
phandle = <0xd3>; | |
}; | |
qcom,gdsc@5066094 { | |
compatible = "qcom,gdsc"; | |
regulator-name = "gdsc_gpu_gx"; | |
reg = <0x5066094 0x4 0x5065130 0x4 0x5066090 0x4>; | |
reg-names = "base", "domain_addr", "sw_reset"; | |
qcom,retain-periph; | |
qcom,reset-aon-logic; | |
status = "ok"; | |
clock-names = "core_root_clk"; | |
clocks = <0x2b 0x917f76ef>; | |
qcom,force-enable-root-clk; | |
parent-supply = <0x2c>; | |
linux,phandle = <0x1a7>; | |
phandle = <0x1a7>; | |
}; | |
interrupt-controller@17a00000 { | |
compatible = "arm,gic-v3"; | |
reg = <0x17a00000 0x10000 0x17b00000 0x100000>; | |
#interrupt-cells = <0x3>; | |
#address-cells = <0x1>; | |
#size-cells = <0x1>; | |
ranges; | |
interrupt-controller; | |
#redistributor-regions = <0x1>; | |
redistributor-stride = <0x0 0x20000>; | |
interrupts = <0x1 0x9 0x4>; | |
linux,phandle = <0x1>; | |
phandle = <0x1>; | |
gic-its@0x17a20000 { | |
compatible = "arm,gic-v3-its"; | |
msi-contoller; | |
reg = <0x17a20000 0x20000>; | |
}; | |
}; | |
timer { | |
compatible = "arm,armv8-timer"; | |
interrupts = <0x1 0x1 0xf08 0x1 0x2 0xf08 0x1 0x3 0xf08 0x1 0x0 0xf08>; | |
clock-frequency = <0x124f800>; | |
}; | |
restart@10ac000 { | |
compatible = "qcom,pshold"; | |
reg = <0x10ac000 0x4 0x1fd3000 0x4>; | |
reg-names = "pshold-base", "tcsr-boot-misc-detect"; | |
}; | |
qcom,spmi@800f000 { | |
compatible = "qcom,spmi-pmic-arb"; | |
reg = <0x800f000 0x1000 0x8400000 0x1000000 0x9400000 0x1000000 0xa400000 0x220000 0x800a000 0x3000>; | |
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; | |
interrupt-names = "periph_irq"; | |
interrupts = <0x0 0x146 0x0>; | |
qcom,ee = <0x0>; | |
qcom,channel = <0x0>; | |
qcom,reserved-chan = <0x1ff>; | |
#address-cells = <0x2>; | |
#size-cells = <0x0>; | |
interrupt-controller; | |
#interrupt-cells = <0x4>; | |
cell-index = <0x0>; | |
linux,phandle = <0x1f8>; | |
phandle = <0x1f8>; | |
qcom,pm8998@0 { | |
compatible = "qcom,spmi-pmic"; | |
reg = <0x0 0x0>; | |
#address-cells = <0x2>; | |
#size-cells = <0x0>; | |
qcom,revid@100 { | |
compatible = "qcom,qpnp-revid"; | |
reg = <0x100 0x100>; | |
}; | |
qcom,power-on@800 { | |
compatible = "qcom,qpnp-power-on"; | |
reg = <0x800 0x100>; | |
interrupts = <0x0 0x8 0x0 0x0 0x0 0x8 0x1 0x0 0x0 0x8 0x4 0x0 0x0 0x8 0x5 0x0>; | |
interrupt-names = "kpdpwr", "resin", "resin-bark", "kpdpwr-resin-bark"; | |
qcom,pon-dbc-delay = <0x3d09>; | |
qcom,kpdpwr-sw-debounce; | |
qcom,system-reset; | |
qcom,store-hard-reset-reason; | |
qcom,pon_1 { | |
qcom,pon-type = <0x0>; | |
qcom,pull-up = <0x1>; | |
linux,code = <0x74>; | |
qcom,support-reset = <0x1>; | |
qcom,s1-timer = <0x1180>; | |
qcom,s2-timer = <0x7d0>; | |
qcom,s2-type = <0x7>; | |
}; | |
qcom,pon_2 { | |
qcom,pon-type = <0x1>; | |
qcom,pull-up = <0x1>; | |
linux,code = <0x72>; | |
}; | |
qcom,pon_3 { | |
qcom,pon-type = <0x3>; | |
qcom,support-reset = <0x1>; | |
qcom,pull-up = <0x1>; | |
qcom,s1-timer = <0xc00>; | |
qcom,s2-timer = <0x7d0>; | |
qcom,s2-type = <0x1>; | |
qcom,use-bark; | |
}; | |
}; | |
qcom,temp-alarm@2400 { | |
compatible = "qcom,qpnp-temp-alarm"; | |
reg = <0x2400 0x100>; | |
interrupts = <0x0 0x24 0x0 0x1>; | |
label = "pm8998_tz"; | |
qcom,channel-num = <0x6>; | |
qcom,temp_alarm-vadc = <0x2d>; | |
}; | |
gpios { | |
compatible = "qcom,qpnp-pin"; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
#address-cells = <0x1>; | |
#size-cells = <0x1>; | |
label = "pm8998-gpio"; | |
linux,phandle = <0x8f>; | |
phandle = <0x8f>; | |
gpio@c000 { | |
reg = <0xc000 0x100>; | |
qcom,pin-num = <0x1>; | |
status = "disabled"; | |
}; | |
gpio@c100 { | |
reg = <0xc100 0x100>; | |
qcom,pin-num = <0x2>; | |
status = "disabled"; | |
}; | |
gpio@c200 { | |
reg = <0xc200 0x100>; | |
qcom,pin-num = <0x3>; | |
status = "disabled"; | |
}; | |
gpio@c300 { | |
reg = <0xc300 0x100>; | |
qcom,pin-num = <0x4>; | |
status = "disabled"; | |
}; | |
gpio@c400 { | |
reg = <0xc400 0x100>; | |
qcom,pin-num = <0x5>; | |
status = "disabled"; | |
}; | |
gpio@c500 { | |
reg = <0xc500 0x100>; | |
qcom,pin-num = <0x6>; | |
status = "okay"; | |
qcom,mode = <0x0>; | |
qcom,pull = <0x0>; | |
qcom,vin-sel = <0x0>; | |
qcom,src-sel = <0x0>; | |
qcom,out-strength = <0x1>; | |
}; | |
gpio@c600 { | |
reg = <0xc600 0x100>; | |
qcom,pin-num = <0x7>; | |
status = "okay"; | |
qcom,mode = <0x0>; | |
qcom,pull = <0x0>; | |
qcom,vin-sel = <0x0>; | |
qcom,src-sel = <0x0>; | |
qcom,out-strength = <0x1>; | |
}; | |
gpio@c700 { | |
reg = <0xc700 0x100>; | |
qcom,pin-num = <0x8>; | |
status = "okay"; | |
qcom,mode = <0x0>; | |
qcom,pull = <0x0>; | |
qcom,vin-sel = <0x0>; | |
qcom,src-sel = <0x0>; | |
qcom,out-strength = <0x1>; | |
}; | |
gpio@c800 { | |
reg = <0xc800 0x100>; | |
qcom,pin-num = <0x9>; | |
status = "ok"; | |
qcom,mode = <0x1>; | |
qcom,pull = <0x5>; | |
qcom,vin-sel = <0x0>; | |
qcom,src-sel = <0x0>; | |
qcom,invert = <0x0>; | |
qcom,master-en = <0x1>; | |
}; | |
gpio@c900 { | |
reg = <0xc900 0x100>; | |
qcom,pin-num = <0xa>; | |
status = "disabled"; | |
}; | |
gpio@ca00 { | |
reg = <0xca00 0x100>; | |
qcom,pin-num = <0xb>; | |
status = "disabled"; | |
}; | |
gpio@cb00 { | |
reg = <0xcb00 0x100>; | |
qcom,pin-num = <0xc>; | |
status = "disabled"; | |
}; | |
gpio@cc00 { | |
reg = <0xcc00 0x100>; | |
qcom,pin-num = <0xd>; | |
status = "okay"; | |
qcom,mode = <0x1>; | |
qcom,output-type = <0x0>; | |
qcom,pull = <0x5>; | |
qcom,vin-sel = <0x0>; | |
qcom,out-strength = <0x1>; | |
qcom,src-sel = <0x3>; | |
qcom,master-en = <0x1>; | |
}; | |
gpio@cd00 { | |
reg = <0xcd00 0x100>; | |
qcom,pin-num = <0xe>; | |
status = "disabled"; | |
}; | |
gpio@ce00 { | |
reg = <0xce00 0x100>; | |
qcom,pin-num = <0xf>; | |
status = "disabled"; | |
}; | |
gpio@cf00 { | |
reg = <0xcf00 0x100>; | |
qcom,pin-num = <0x10>; | |
status = "disabled"; | |
}; | |
gpio@d000 { | |
reg = <0xd000 0x100>; | |
qcom,pin-num = <0x11>; | |
status = "disabled"; | |
}; | |
gpio@d100 { | |
reg = <0xd100 0x100>; | |
qcom,pin-num = <0x12>; | |
status = "okay"; | |
qcom,mode = <0x0>; | |
qcom,pull = <0x0>; | |
qcom,vin-sel = <0x0>; | |
qcom,src-sel = <0x0>; | |
qcom,master-en = <0x1>; | |
}; | |
gpio@d200 { | |
reg = <0xd200 0x100>; | |
qcom,pin-num = <0x13>; | |
status = "disabled"; | |
}; | |
gpio@d300 { | |
reg = <0xd300 0x100>; | |
qcom,pin-num = <0x14>; | |
status = "ok"; | |
qcom,mode = <0x1>; | |
qcom,pull = <0x5>; | |
qcom,vin-sel = <0x1>; | |
qcom,src-sel = <0x0>; | |
qcom,invert = <0x0>; | |
qcom,master-en = <0x1>; | |
}; | |
gpio@d400 { | |
reg = <0xd400 0x100>; | |
qcom,pin-num = <0x15>; | |
status = "okay"; | |
qcom,mode = <0x0>; | |
qcom,vin-sel = <0x1>; | |
qcom,src-sel = <0x0>; | |
qcom,master-en = <0x1>; | |
}; | |
gpio@d500 { | |
reg = <0xd500 0x100>; | |
qcom,pin-num = <0x16>; | |
status = "disabled"; | |
}; | |
gpio@d600 { | |
reg = <0xd600 0x100>; | |
qcom,pin-num = <0x17>; | |
status = "disabled"; | |
}; | |
gpio@d700 { | |
reg = <0xd700 0x100>; | |
qcom,pin-num = <0x18>; | |
status = "disabled"; | |
}; | |
gpio@d800 { | |
reg = <0xd800 0x100>; | |
qcom,pin-num = <0x19>; | |
status = "disabled"; | |
}; | |
gpio@d900 { | |
reg = <0xd900 0x100>; | |
qcom,pin-num = <0x1a>; | |
status = "disabled"; | |
}; | |
}; | |
qcom,coincell@2800 { | |
compatible = "qcom,qpnp-coincell"; | |
reg = <0x2800 0x100>; | |
}; | |
qcom,pm8998_rtc { | |
compatible = "qcom,qpnp-rtc"; | |
#address-cells = <0x1>; | |
#size-cells = <0x1>; | |
qcom,qpnp-rtc-write = <0x0>; | |
qcom,qpnp-rtc-alarm-pwrup = <0x0>; | |
qcom,pm8998_rtc_rw@6000 { | |
reg = <0x6000 0x100>; | |
}; | |
qcom,pm8998_rtc_alarm@6100 { | |
reg = <0x6100 0x100>; | |
interrupts = <0x0 0x61 0x1 0x0>; | |
}; | |
}; | |
vadc@3100 { | |
compatible = "qcom,qpnp-vadc-hc"; | |
reg = <0x3100 0x100>; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
interrupts = <0x0 0x31 0x0 0x1>; | |
interrupt-names = "eoc-int-en-set"; | |
qcom,adc-bit-resolution = <0xf>; | |
qcom,adc-vdd-reference = <0x753>; | |
linux,phandle = <0x2d>; | |
phandle = <0x2d>; | |
chan@6 { | |
label = "die_temp"; | |
reg = <0x6>; | |
qcom,decimation = <0x2>; | |
qcom,pre-div-channel-scaling = <0x0>; | |
qcom,calibration-type = "absolute"; | |
qcom,scale-function = <0x3>; | |
qcom,hw-settle-time = <0x0>; | |
qcom,fast-avg-setup = <0x0>; | |
qcom,cal-val = <0x0>; | |
}; | |
chan@0 { | |
label = "ref_gnd"; | |
reg = <0x0>; | |
qcom,decimation = <0x2>; | |
qcom,pre-div-channel-scaling = <0x0>; | |
qcom,calibration-type = "absolute"; | |
qcom,scale-function = <0x0>; | |
qcom,hw-settle-time = <0x0>; | |
qcom,fast-avg-setup = <0x0>; | |
qcom,cal-val = <0x0>; | |
}; | |
chan@1 { | |
label = "ref_1250v"; | |
reg = <0x1>; | |
qcom,decimation = <0x2>; | |
qcom,pre-div-channel-scaling = <0x0>; | |
qcom,calibration-type = "absolute"; | |
qcom,scale-function = <0x0>; | |
qcom,hw-settle-time = <0x0>; | |
qcom,fast-avg-setup = <0x0>; | |
qcom,cal-val = <0x0>; | |
}; | |
chan@83 { | |
label = "vph_pwr"; | |
reg = <0x83>; | |
qcom,decimation = <0x2>; | |
qcom,pre-div-channel-scaling = <0x1>; | |
qcom,calibration-type = "absolute"; | |
qcom,scale-function = <0x0>; | |
qcom,hw-settle-time = <0x0>; | |
qcom,fast-avg-setup = <0x0>; | |
}; | |
chan@85 { | |
label = "vcoin"; | |
reg = <0x85>; | |
qcom,decimation = <0x2>; | |
qcom,pre-div-channel-scaling = <0x1>; | |
qcom,calibration-type = "absolute"; | |
qcom,scale-function = <0x0>; | |
qcom,hw-settle-time = <0x0>; | |
qcom,fast-avg-setup = <0x0>; | |
}; | |
chan@4c { | |
label = "xo_therm"; | |
reg = <0x4c>; | |
qcom,decimation = <0x2>; | |
qcom,pre-div-channel-scaling = <0x0>; | |
qcom,calibration-type = "ratiometric"; | |
qcom,scale-function = <0x4>; | |
qcom,hw-settle-time = <0x2>; | |
qcom,fast-avg-setup = <0x0>; | |
}; | |
chan@4d { | |
label = "msm_therm"; | |
reg = <0x4d>; | |
qcom,decimation = <0x2>; | |
qcom,pre-div-channel-scaling = <0x0>; | |
qcom,calibration-type = "ratiometric"; | |
qcom,scale-function = <0x2>; | |
qcom,hw-settle-time = <0x2>; | |
qcom,fast-avg-setup = <0x0>; | |
}; | |
chan@4e { | |
label = "emmc_therm"; | |
reg = <0x4e>; | |
qcom,decimation = <0x2>; | |
qcom,pre-div-channel-scaling = <0x0>; | |
qcom,calibration-type = "ratiometric"; | |
qcom,scale-function = <0x2>; | |
qcom,hw-settle-time = <0x2>; | |
qcom,fast-avg-setup = <0x0>; | |
}; | |
chan@4f { | |
label = "pa_therm0"; | |
reg = <0x4f>; | |
qcom,decimation = <0x2>; | |
qcom,pre-div-channel-scaling = <0x0>; | |
qcom,calibration-type = "ratiometric"; | |
qcom,scale-function = <0x2>; | |
qcom,hw-settle-time = <0x2>; | |
qcom,fast-avg-setup = <0x0>; | |
}; | |
chan@50 { | |
label = "pa_therm1"; | |
reg = <0x50>; | |
qcom,decimation = <0x2>; | |
qcom,pre-div-channel-scaling = <0x0>; | |
qcom,calibration-type = "ratiometric"; | |
qcom,scale-function = <0x2>; | |
qcom,hw-settle-time = <0x2>; | |
qcom,fast-avg-setup = <0x0>; | |
}; | |
chan@51 { | |
label = "quiet_therm"; | |
reg = <0x51>; | |
qcom,decimation = <0x2>; | |
qcom,pre-div-channel-scaling = <0x0>; | |
qcom,calibration-type = "ratiometric"; | |
qcom,scale-function = <0x2>; | |
qcom,hw-settle-time = <0x2>; | |
qcom,fast-avg-setup = <0x0>; | |
}; | |
}; | |
vadc@3400 { | |
compatible = "qcom,qpnp-adc-tm-hc"; | |
reg = <0x3400 0x100>; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
interrupts = <0x0 0x34 0x0 0x1>; | |
interrupt-names = "eoc-int-en-set"; | |
qcom,adc-bit-resolution = <0xf>; | |
qcom,adc-vdd-reference = <0x753>; | |
qcom,adc_tm-vadc = <0x2d>; | |
qcom,decimation = <0x0>; | |
qcom,fast-avg-setup = <0x0>; | |
linux,phandle = <0xc5>; | |
phandle = <0xc5>; | |
chan@83 { | |
label = "vph_pwr"; | |
reg = <0x83>; | |
qcom,pre-div-channel-scaling = <0x1>; | |
qcom,calibration-type = "absolute"; | |
qcom,scale-function = <0x0>; | |
qcom,hw-settle-time = <0x0>; | |
qcom,btm-channel-number = <0x60>; | |
}; | |
chan@4d { | |
label = "msm_therm"; | |
reg = <0x4d>; | |
qcom,pre-div-channel-scaling = <0x0>; | |
qcom,calibration-type = "ratiometric"; | |
qcom,scale-function = <0x2>; | |
qcom,hw-settle-time = <0x2>; | |
qcom,btm-channel-number = <0x68>; | |
qcom,thermal-node; | |
}; | |
chan@4e { | |
label = "emmc_therm"; | |
reg = <0x4e>; | |
qcom,pre-div-channel-scaling = <0x0>; | |
qcom,calibration-type = "ratiometric"; | |
qcom,scale-function = <0x2>; | |
qcom,hw-settle-time = <0x2>; | |
qcom,btm-channel-number = <0x80>; | |
qcom,thermal-node; | |
}; | |
chan@4f { | |
label = "pa_therm0"; | |
reg = <0x4f>; | |
qcom,pre-div-channel-scaling = <0x0>; | |
qcom,calibration-type = "ratiometric"; | |
qcom,scale-function = <0x2>; | |
qcom,hw-settle-time = <0x2>; | |
qcom,btm-channel-number = <0x88>; | |
qcom,thermal-node; | |
}; | |
chan@50 { | |
label = "pa_therm1"; | |
reg = <0x50>; | |
qcom,pre-div-channel-scaling = <0x0>; | |
qcom,calibration-type = "ratiometric"; | |
qcom,scale-function = <0x2>; | |
qcom,hw-settle-time = <0x2>; | |
qcom,btm-channel-number = <0x90>; | |
qcom,thermal-node; | |
}; | |
chan@51 { | |
label = "quiet_therm"; | |
reg = <0x51>; | |
qcom,pre-div-channel-scaling = <0x0>; | |
qcom,calibration-type = "ratiometric"; | |
qcom,scale-function = <0x2>; | |
qcom,hw-settle-time = <0x2>; | |
qcom,btm-channel-number = <0x70>; | |
qcom,thermal-node; | |
}; | |
chan@4c { | |
label = "xo_therm"; | |
reg = <0x4c>; | |
qcom,pre-div-channel-scaling = <0x0>; | |
qcom,calibration-type = "ratiometric"; | |
qcom,scale-function = <0x4>; | |
qcom,hw-settle-time = <0x2>; | |
qcom,btm-channel-number = <0x78>; | |
qcom,thermal-node; | |
}; | |
}; | |
}; | |
qcom,pm8998@1 { | |
compatible = "qcom,spmi-pmic"; | |
reg = <0x1 0x0>; | |
#address-cells = <0x2>; | |
#size-cells = <0x0>; | |
regulator@2f00 { | |
compatible = "qcom,qpnp-regulator"; | |
reg = <0x2f00 0x100>; | |
regulator-name = "pm8998_s10"; | |
regulator-min-microvolt = <0x8aac0>; | |
regulator-max-microvolt = <0x101d00>; | |
qcom,enable-time = <0x1f4>; | |
regulator-always-on; | |
linux,phandle = <0xcc>; | |
phandle = <0xcc>; | |
}; | |
regulator@3800 { | |
compatible = "qcom,qpnp-regulator"; | |
reg = <0x3800 0x100>; | |
regulator-name = "pm8998_s13"; | |
regulator-min-microvolt = <0x8aac0>; | |
regulator-max-microvolt = <0x115580>; | |
qcom,enable-time = <0x1f4>; | |
regulator-always-on; | |
linux,phandle = <0xcd>; | |
phandle = <0xcd>; | |
}; | |
}; | |
qcom,pmi8998@2 { | |
compatible = "qcom,spmi-pmic"; | |
reg = <0x2 0x0>; | |
#address-cells = <0x2>; | |
#size-cells = <0x0>; | |
qcom,revid@100 { | |
compatible = "qcom,qpnp-revid"; | |
reg = <0x100 0x100>; | |
qcom,fab-id-valid; | |
linux,phandle = <0x2e>; | |
phandle = <0x2e>; | |
}; | |
qcom,power-on@800 { | |
compatible = "qcom,qpnp-power-on"; | |
reg = <0x800 0x100>; | |
}; | |
qcom,misc@900 { | |
compatible = "qcom,qpnp-misc"; | |
reg = <0x900 0x100>; | |
linux,phandle = <0x37>; | |
phandle = <0x37>; | |
}; | |
qcom,temp-alarm@2400 { | |
compatible = "qcom,qpnp-temp-alarm"; | |
reg = <0x2400 0x100>; | |
interrupts = <0x2 0x24 0x0 0x1>; | |
label = "pmi8998_tz"; | |
}; | |
gpios { | |
compatible = "qcom,qpnp-pin"; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
#address-cells = <0x1>; | |
#size-cells = <0x1>; | |
label = "pmi8998-gpio"; | |
linux,phandle = <0x27a>; | |
phandle = <0x27a>; | |
gpio@c000 { | |
reg = <0xc000 0x100>; | |
qcom,pin-num = <0x1>; | |
status = "disabled"; | |
}; | |
gpio@c100 { | |
reg = <0xc100 0x100>; | |
qcom,pin-num = <0x2>; | |
status = "disabled"; | |
}; | |
gpio@c200 { | |
reg = <0xc200 0x100>; | |
qcom,pin-num = <0x3>; | |
status = "okay"; | |
qcom,mode = <0x1>; | |
qcom,pull = <0x5>; | |
qcom,vin-sel = <0x1>; | |
qcom,src-sel = <0x0>; | |
qcom,out-strength = <0x1>; | |
qcom,master-en = <0x1>; | |
}; | |
gpio@c300 { | |
reg = <0xc300 0x100>; | |
qcom,pin-num = <0x4>; | |
status = "disabled"; | |
}; | |
gpio@c400 { | |
reg = <0xc400 0x100>; | |
qcom,pin-num = <0x5>; | |
status = "okay"; | |
qcom,mode = <0x1>; | |
qcom,pull = <0x4>; | |
qcom,src-sel = <0x2>; | |
qcom,master-en = <0x1>; | |
qcom,out-strength = <0x2>; | |
}; | |
gpio@c500 { | |
reg = <0xc500 0x100>; | |
qcom,pin-num = <0x6>; | |
status = "okay"; | |
qcom,mode = <0x1>; | |
qcom,pull = <0x5>; | |
qcom,vin-sel = <0x0>; | |
qcom,src-sel = <0x2>; | |
qcom,out-strength = <0x1>; | |
qcom,master-en = <0x1>; | |
}; | |
gpio@c600 { | |
reg = <0xc600 0x100>; | |
qcom,pin-num = <0x7>; | |
status = "disabled"; | |
}; | |
gpio@c700 { | |
reg = <0xc700 0x100>; | |
qcom,pin-num = <0x8>; | |
status = "disabled"; | |
}; | |
gpio@c800 { | |
reg = <0xc800 0x100>; | |
qcom,pin-num = <0x9>; | |
status = "disabled"; | |
}; | |
gpio@c900 { | |
reg = <0xc900 0x100>; | |
qcom,pin-num = <0xa>; | |
status = "disabled"; | |
}; | |
gpio@ca00 { | |
reg = <0xca00 0x100>; | |
qcom,pin-num = <0xb>; | |
status = "disabled"; | |
}; | |
gpio@cb00 { | |
reg = <0xcb00 0x100>; | |
qcom,pin-num = <0xc>; | |
status = "disabled"; | |
}; | |
gpio@cc00 { | |
reg = <0xcc00 0x100>; | |
qcom,pin-num = <0xd>; | |
status = "disabled"; | |
}; | |
gpio@cd00 { | |
reg = <0xcd00 0x100>; | |
qcom,pin-num = <0xe>; | |
status = "disabled"; | |
}; | |
}; | |
qcom,qpnp-qnovo@1500 { | |
compatible = "qcom,qpnp-qnovo"; | |
reg = <0x1500 0x100>; | |
interrupts = <0x2 0x15 0x0 0x0>; | |
interrupt-names = "ptrain-done"; | |
qcom,pmic-revid = <0x2e>; | |
}; | |
qcom,qpnp-smb2 { | |
compatible = "qcom,qpnp-smb2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x1>; | |
qcom,pmic-revid = <0x2e>; | |
io-channels = <0x2f 0x8 0x2f 0xa 0x2f 0x3 0x2f 0x4>; | |
io-channel-names = "charger_temp", "charger_temp_max", "usbin_i", "usbin_v"; | |
qcom,boost-threshold-ua = <0x186a0>; | |
qcom,wipower-max-uw = <0x4c4b40>; | |
dpdm-supply = <0x30>; | |
qcom,thermal-mitigation = <0x1b7740 0x186a00 0x155cc0 0x124f80 0xf4240 0xf4240 0xf4240>; | |
qcom,usb-icl-ua = <0x2dc6c0>; | |
qcom,fcc-max-ua = <0x30d400>; | |
qcom,fcc-low-temp-delta = <0x2bde78>; | |
qcom,fcc-hot-temp-delta = <0x186a00>; | |
qcom,fcc-cool-temp-delta = <0x21f368>; | |
qcom,auto-recharge-soc; | |
qcom,thermal-mitigation-dcp = <0x1b7740 0x186a00 0x155cc0 0x124f80 0xf4240 0xf4240 0xf4240>; | |
qcom,thermal-mitigation-qc3 = <0x2dc6c0 0x2500a8 0x206cc8 0x1bd8e8 0x174508 0x12b128 0xb71b0>; | |
qcom,thermal-mitigation-qc2 = <0x186a00 0x155cc0 0x124f80 0xf4240 0xdbba0 0xdbba0 0x86470>; | |
qcom,chgr@1000 { | |
reg = <0x1000 0x100>; | |
interrupts = <0x2 0x10 0x0 0x1 0x2 0x10 0x1 0x1 0x2 0x10 0x2 0x1 0x2 0x10 0x3 0x1 0x2 0x10 0x4 0x1>; | |
interrupt-names = "chg-error", "chg-state-change", "step-chg-state-change", "step-chg-soc-update-fail", "step-chg-soc-update-request"; | |
}; | |
qcom,otg@1100 { | |
reg = <0x1100 0x100>; | |
interrupts = <0x2 0x11 0x0 0x3 0x2 0x11 0x1 0x3 0x2 0x11 0x2 0x3 0x2 0x11 0x3 0x3>; | |
interrupt-names = "otg-fail", "otg-overcurrent", "otg-oc-dis-sw-sts", "testmode-change-detect"; | |
}; | |
qcom,bat-if@1200 { | |
reg = <0x1200 0x100>; | |
interrupts = <0x2 0x12 0x0 0x1 0x2 0x12 0x1 0x3 0x2 0x12 0x2 0x3 0x2 0x12 0x3 0x3 0x2 0x12 0x4 0x3 0x2 0x12 0x5 0x3>; | |
interrupt-names = "bat-temp", "bat-ocp", "bat-ov", "bat-low", "bat-therm-or-id-missing", "bat-terminal-missing"; | |
}; | |
qcom,usb-chgpth@1300 { | |
reg = <0x1300 0x100>; | |
interrupts = <0x2 0x13 0x0 0x3 0x2 0x13 0x1 0x3 0x2 0x13 0x2 0x3 0x2 0x13 0x3 0x3 0x2 0x13 0x4 0x3 0x2 0x13 0x5 0x1 0x2 0x13 0x6 0x1 0x2 0x13 0x7 0x1>; | |
interrupt-names = "usbin-collapse", "usbin-lt-3p6v", "usbin-uv", "usbin-ov", "usbin-plugin", "usbin-src-change", "usbin-icl-change", "type-c-change"; | |
}; | |
qcom,dc-chgpth@1400 { | |
reg = <0x1400 0x100>; | |
interrupts = <0x2 0x14 0x0 0x3 0x2 0x14 0x1 0x3 0x2 0x14 0x2 0x3 0x2 0x14 0x3 0x3 0x2 0x14 0x4 0x3 0x2 0x14 0x5 0x3 0x2 0x14 0x6 0x1>; | |
interrupt-names = "dcin-collapse", "dcin-lt-3p6v", "dcin-uv", "dcin-ov", "dcin-plugin", "div2-en-dg", "dcin-icl-change"; | |
}; | |
qcom,chgr-misc@1600 { | |
reg = <0x1600 0x100>; | |
interrupts = <0x2 0x16 0x0 0x1 0x2 0x16 0x1 0x1 0x2 0x16 0x2 0x3 0x2 0x16 0x3 0x3 0x2 0x16 0x4 0x3 0x2 0x16 0x5 0x3 0x2 0x16 0x6 0x2 0x2 0x16 0x7 0x3>; | |
interrupt-names = "wdog-snarl", "wdog-bark", "aicl-fail", "aicl-done", "high-duty-cycle", "input-current-limiting", "temperature-change", "switcher-power-ok"; | |
}; | |
qcom,smb2-vbus { | |
regulator-name = "smb2-vbus"; | |
linux,phandle = <0x32>; | |
phandle = <0x32>; | |
}; | |
qcom,smb2-vconn { | |
regulator-name = "smb2-vconn"; | |
linux,phandle = <0x33>; | |
phandle = <0x33>; | |
}; | |
}; | |
qcom,usb-pdphy@1700 { | |
compatible = "qcom,qpnp-pdphy"; | |
reg = <0x1700 0x100>; | |
vdd-pdphy-supply = <0x31>; | |
vbus-supply = <0x32>; | |
vconn-supply = <0x33>; | |
interrupts = <0x2 0x17 0x0 0x1 0x2 0x17 0x1 0x1 0x2 0x17 0x2 0x1 0x2 0x17 0x3 0x1 0x2 0x17 0x4 0x1 0x2 0x17 0x5 0x1 0x2 0x17 0x6 0x1>; | |
interrupt-names = "sig-tx", "sig-rx", "msg-tx", "msg-rx", "msg-tx-failed", "msg-tx-discarded", "msg-rx-discarded"; | |
qcom,default-sink-caps = <0x1388 0xbb8 0x2328 0xbb8 0x2ee0 0x8ca>; | |
linux,phandle = <0x86>; | |
phandle = <0x86>; | |
}; | |
bcl@4200 { | |
compatible = "qcom,msm-bcl-lmh"; | |
reg = <0x4200 0xff 0x4300 0xff>; | |
reg-names = "fg_user_adc", "fg_lmh"; | |
interrupts = <0x2 0x42 0x0 0x0 0x2 0x42 0x2 0x0>; | |
interrupt-names = "bcl-high-ibat-int", "bcl-low-vbat-int"; | |
qcom,vbat-polling-delay-ms = <0x64>; | |
qcom,ibat-polling-delay-ms = <0x64>; | |
}; | |
rradc@4500 { | |
compatible = "qcom,rradc"; | |
reg = <0x4500 0x100>; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
#io-channel-cells = <0x1>; | |
qcom,pmic-revid = <0x2e>; | |
linux,phandle = <0x2f>; | |
phandle = <0x2f>; | |
}; | |
qpnp,fg { | |
compatible = "qcom,fg-gen3"; | |
#address-cells = <0x1>; | |
#size-cells = <0x1>; | |
qcom,pmic-revid = <0x2e>; | |
io-channels = <0x2f 0x0>; | |
io-channel-names = "rradc_batt_id"; | |
qcom,rradc-base = <0x4500>; | |
qcom,fg-esr-timer-awake = <0x60 0x60>; | |
qcom,fg-esr-timer-asleep = <0x100 0x100>; | |
qcom,fg-esr-timer-charging = <0x0 0x60>; | |
qcom,cycle-counter-en; | |
status = "okay"; | |
qcom,fg-force-load-profile; | |
qcom,fg-sys-term-current = <0xfffffed4>; | |
qcom,fg-chg-term-current = <0xc8>; | |
qcom,fg-auto-recharge-soc; | |
qcom,fg-recharge-soc-thr = <0x63>; | |
qcom,fg-cutoff-voltage = <0xd48>; | |
qcom,fg-empty-voltage = <0xc1c>; | |
qcom,fg-jeita-hyst-temp = <0x0>; | |
qcom,fg-jeita-thresholds = <0x0 0xf 0x2d 0x3a>; | |
qcom,fg-esr-clamp-mohms = <0x3c>; | |
qcom,fg-batt-temp-delta = <0x6>; | |
qcom,fg-batt-soc@4000 { | |
status = "okay"; | |
reg = <0x4000 0x100>; | |
interrupts = <0x2 0x40 0x0 0x3 0x2 0x40 0x1 0x3 0x2 0x40 0x2 0x1 0x2 0x40 0x3 0x1 0x2 0x40 0x4 0x3 0x2 0x40 0x5 0x1 0x2 0x40 0x6 0x3 0x2 0x40 0x7 0x3>; | |
interrupt-names = "soc-update", "soc-ready", "bsoc-delta", "msoc-delta", "msoc-low", "msoc-empty", "msoc-high", "msoc-full"; | |
}; | |
qcom,fg-batt-info@4100 { | |
status = "okay"; | |
reg = <0x4100 0x100>; | |
interrupts = <0x2 0x41 0x0 0x3 0x2 0x41 0x1 0x3 0x2 0x41 0x2 0x3 0x2 0x41 0x3 0x3 0x2 0x41 0x6 0x3>; | |
interrupt-names = "vbatt-pred-delta", "vbatt-low", "esr-delta", "batt-missing", "batt-temp-delta"; | |
}; | |
qcom,fg-memif@4400 { | |
status = "okay"; | |
reg = <0x4400 0x100>; | |
interrupts = <0x2 0x44 0x1 0x3 0x2 0x44 0x2 0x3>; | |
interrupt-names = "mem-xcp", "dma-grant"; | |
}; | |
}; | |
}; | |
qcom,pmi8998@3 { | |
compatible = "qcom,spmi-pmic"; | |
reg = <0x3 0x0>; | |
#address-cells = <0x2>; | |
#size-cells = <0x0>; | |
pwm@b100 { | |
compatible = "qcom,qpnp-pwm"; | |
reg = <0xb100 0x100 0xb042 0x7e>; | |
reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; | |
qcom,lpg-lut-size = <0x7e>; | |
qcom,channel-id = <0x1>; | |
qcom,supported-sizes = <0x6 0x9>; | |
qcom,ramp-index = <0x0>; | |
#pwm-cells = <0x2>; | |
status = "disabled"; | |
}; | |
pwm@b200 { | |
compatible = "qcom,qpnp-pwm"; | |
reg = <0xb200 0x100 0xb042 0x7e>; | |
reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; | |
qcom,lpg-lut-size = <0x7e>; | |
qcom,channel-id = <0x2>; | |
qcom,supported-sizes = <0x6 0x9>; | |
qcom,ramp-index = <0x1>; | |
#pwm-cells = <0x2>; | |
status = "disabled"; | |
}; | |
pwm@b300 { | |
compatible = "qcom,qpnp-pwm"; | |
reg = <0xb300 0x100 0xb042 0x7e>; | |
reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; | |
qcom,lpg-lut-size = <0x7e>; | |
qcom,channel-id = <0x3>; | |
qcom,supported-sizes = <0x6 0x9>; | |
qcom,ramp-index = <0x2>; | |
#pwm-cells = <0x2>; | |
linux,phandle = <0x36>; | |
phandle = <0x36>; | |
}; | |
pwm@b400 { | |
compatible = "qcom,qpnp-pwm"; | |
reg = <0xb400 0x100 0xb042 0x7e>; | |
reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; | |
qcom,lpg-lut-size = <0x7e>; | |
qcom,channel-id = <0x4>; | |
qcom,supported-sizes = <0x6 0x9>; | |
qcom,ramp-index = <0x3>; | |
#pwm-cells = <0x2>; | |
linux,phandle = <0x35>; | |
phandle = <0x35>; | |
}; | |
pwm@b500 { | |
compatible = "qcom,qpnp-pwm"; | |
reg = <0xb500 0x100 0xb042 0x7e>; | |
reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; | |
qcom,lpg-lut-size = <0x7e>; | |
qcom,channel-id = <0x5>; | |
qcom,supported-sizes = <0x6 0x9>; | |
qcom,ramp-index = <0x4>; | |
#pwm-cells = <0x2>; | |
linux,phandle = <0x34>; | |
phandle = <0x34>; | |
}; | |
pwm@b600 { | |
compatible = "qcom,qpnp-pwm"; | |
reg = <0xb600 0x100 0xb042 0x7e>; | |
reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; | |
qcom,lpg-lut-size = <0x7e>; | |
qcom,channel-id = <0x6>; | |
qcom,supported-sizes = <0x6 0x9>; | |
qcom,ramp-index = <0x5>; | |
#pwm-cells = <0x2>; | |
status = "disabled"; | |
}; | |
qcom,leds@d000 { | |
compatible = "qcom,leds-qpnp"; | |
reg = <0xd000 0x100>; | |
label = "rgb"; | |
status = "okay"; | |
qcom,rgb_0 { | |
label = "rgb"; | |
qcom,id = <0x3>; | |
qcom,mode = "pwm"; | |
pwms = <0x34 0x0 0x0>; | |
qcom,pwm-us = <0x3e8>; | |
qcom,max-current = <0xc>; | |
qcom,default-state = "off"; | |
linux,name = "white"; | |
qcom,start-idx = <0x1>; | |
qcom,idx-len = <0x14>; | |
qcom,duty-pcts = <0x61020 0x3244545e 0x6464645e 0x54443220 0x10060000>; | |
qcom,lut-flags = <0x3>; | |
qcom,pause-lo = <0x0>; | |
qcom,pause-hi = <0x0>; | |
qcom,ramp-step-ms = <0x80>; | |
qcom,use-blink; | |
}; | |
qcom,rgb_1 { | |
label = "rgb"; | |
qcom,id = <0x4>; | |
qcom,mode = "pwm"; | |
pwms = <0x35 0x0 0x0>; | |
qcom,pwm-us = <0x3e8>; | |
qcom,max-current = <0xc>; | |
qcom,default-state = "off"; | |
linux,name = "button-backlight1"; | |
}; | |
qcom,rgb_2 { | |
label = "rgb"; | |
qcom,id = <0x5>; | |
qcom,mode = "pwm"; | |
pwms = <0x36 0x0 0x0>; | |
qcom,pwm-us = <0x3e8>; | |
qcom,max-current = <0xc>; | |
qcom,default-state = "off"; | |
linux,name = "button-backlight"; | |
}; | |
}; | |
qpnp-labibb-regulator { | |
compatible = "qcom,qpnp-labibb-regulator"; | |
#address-cells = <0x1>; | |
#size-cells = <0x1>; | |
qcom,pmic-revid = <0x2e>; | |
status = "ok"; | |
qcom,qpnp-labibb-mode = "lcd"; | |
qcom,ibb@dc00 { | |
reg = <0xdc00 0x100>; | |
reg-names = "ibb_reg"; | |
regulator-name = "ibb_reg"; | |
regulator-min-microvolt = <0x4630c0>; | |
regulator-max-microvolt = <0x5b8d80>; | |
interrupts = <0x3 0xdc 0x2 0x1>; | |
interrupt-names = "ibb-sc-err"; | |
qcom,qpnp-ibb-min-voltage = <0x155cc0>; | |
qcom,qpnp-ibb-step-size = <0x186a0>; | |
qcom,qpnp-ibb-slew-rate = <0x1e8480>; | |
qcom,qpnp-ibb-use-default-voltage; | |
qcom,qpnp-ibb-init-voltage = <0x53ec60>; | |
qcom,qpnp-ibb-init-amoled-voltage = <0x3d0900>; | |
qcom,qpnp-ibb-init-lcd-voltage = <0x53ec60>; | |
qcom,qpnp-ibb-soft-start = <0x3e8>; | |
qcom,qpnp-ibb-lab-pwrup-delay = <0x1f40>; | |
qcom,qpnp-ibb-lab-pwrdn-delay = <0x1f40>; | |
qcom,qpnp-ibb-en-discharge; | |
qcom,qpnp-ibb-full-pull-down; | |
qcom,qpnp-ibb-pull-down-enable; | |
qcom,qpnp-ibb-switching-clock-frequency = <0x5c8>; | |
qcom,qpnp-ibb-limit-maximum-current = <0x60e>; | |
qcom,qpnp-ibb-debounce-cycle = <0x10>; | |
qcom,qpnp-ibb-limit-max-current-enable; | |
qcom,qpnp-ibb-ps-enable; | |
linux,phandle = <0x1c5>; | |
phandle = <0x1c5>; | |
}; | |
qcom,lab@de00 { | |
reg = <0xde00 0x100>; | |
reg-names = "lab"; | |
regulator-name = "lab_reg"; | |
regulator-min-microvolt = <0x4630c0>; | |
regulator-max-microvolt = <0x5b8d80>; | |
interrupts = <0x3 0xde 0x0 0x1 0x3 0xde 0x1 0x1>; | |
interrupt-names = "lab-vreg-ok", "lab-sc-err"; | |
qcom,qpnp-lab-min-voltage = <0x4630c0>; | |
qcom,qpnp-lab-step-size = <0x186a0>; | |
qcom,qpnp-lab-slew-rate = <0x1388>; | |
qcom,qpnp-lab-use-default-voltage; | |
qcom,qpnp-lab-init-voltage = <0x53ec60>; | |
qcom,qpnp-lab-init-amoled-voltage = <0x4630c0>; | |
qcom,qpnp-lab-init-lcd-voltage = <0x53ec60>; | |
qcom,qpnp-lab-soft-start = <0x320>; | |
qcom,qpnp-lab-full-pull-down; | |
qcom,qpnp-lab-pull-down-enable; | |
qcom,qpnp-lab-switching-clock-frequency = <0x640>; | |
qcom,qpnp-lab-limit-maximum-current = <0x640>; | |
qcom,qpnp-lab-limit-max-current-enable; | |
qcom,qpnp-lab-ps-threshold = <0x14>; | |
qcom,qpnp-lab-ps-enable; | |
qcom,qpnp-lab-nfet-size = <0x64>; | |
qcom,qpnp-lab-pfet-size = <0x64>; | |
qcom,qpnp-lab-max-precharge-time = <0x1f4>; | |
linux,phandle = <0x1c4>; | |
phandle = <0x1c4>; | |
}; | |
}; | |
qcom,leds@d800 { | |
compatible = "qcom,qpnp-wled"; | |
reg = <0xd800 0x100 0xd900 0x100>; | |
reg-names = "qpnp-wled-ctrl-base", "qpnp-wled-sink-base"; | |
interrupts = <0x3 0xd8 0x1 0x1 0x3 0xd8 0x2 0x1>; | |
interrupt-names = "ovp-irq", "sc-irq"; | |
linux,name = "wled"; | |
linux,default-trigger = "bkl-trigger"; | |
qcom,fdbk-output = "auto"; | |
qcom,vref-uv = <0x1f20c>; | |
qcom,switch-freq-khz = <0x258>; | |
qcom,ovp-mv = <0x73a0>; | |
qcom,ilim-ma = <0x3ca>; | |
qcom,boost-duty-ns = <0x1a>; | |
qcom,mod-freq-khz = <0x2580>; | |
qcom,dim-mode = "hybrid"; | |
qcom,hyb-thres = <0x271>; | |
qcom,sync-dly-us = <0x320>; | |
qcom,fs-curr-ua = <0x4e20>; | |
qcom,cons-sync-write-delay-us = <0x3e8>; | |
qcom,led-strings-list = [00 01]; | |
qcom,en-ext-pfet-sc-pro; | |
qcom,pmic-revid = <0x2e>; | |
qcom,loop-auto-gm-en; | |
qcom,auto-calibration-enable; | |
status = "okay"; | |
qcom,en-cabc; | |
}; | |
qcom,haptic@c000 { | |
status = "okay"; | |
compatible = "qcom,qpnp-haptic"; | |
reg = <0xc000 0x100>; | |
interrupts = <0x3 0xc0 0x0 0x3 0x3 0xc0 0x1 0x3>; | |
interrupt-names = "sc-irq", "play-irq"; | |
qcom,pmic-revid = <0x2e>; | |
qcom,pmic-misc = <0x37>; | |
qcom,misc-clk-trim-error-reg = <0xf3>; | |
qcom,actuator-type = "lra"; | |
qcom,play-mode = "direct"; | |
qcom,vmax-mv = <0xb0e>; | |
qcom,ilim-ma = <0x320>; | |
qcom,wave-shape = "sine"; | |
qcom,wave-play-rate-us = <0x1388>; | |
qcom,int-pwm-freq-khz = <0x1f9>; | |
qcom,sc-deb-cycles = <0x8>; | |
qcom,en-brake; | |
qcom,brake-pattern = <0x3020000>; | |
qcom,lra-high-z = "opt1"; | |
qcom,lra-auto-res-mode = "qwd"; | |
qcom,lra-res-cal-period = <0x4>; | |
qcom,correct-lra-drive-freq; | |
qcom,misc-trim-error-rc19p2-clk-reg-present; | |
}; | |
qcom,leds@d300 { | |
compatible = "qcom,qpnp-flash-led-v2"; | |
status = "okay"; | |
reg = <0xd300 0x100>; | |
label = "flash"; | |
interrupts = <0x3 0xd3 0x0 0x1 0x3 0xd3 0x3 0x1 0x3 0xd3 0x4 0x1>; | |
interrupt-names = "led-fault-irq", "all-ramp-down-done-irq", "all-ramp-up-done-irq"; | |
qcom,hdrm-auto-mode; | |
qcom,short-circuit-det; | |
qcom,open-circuit-det; | |
qcom,vph-droop-det; | |
qcom,thermal-derate-en; | |
qcom,thermal-derate-current = <0xc8 0x1f4 0x3e8>; | |
qcom,isc-delay = <0xc0>; | |
qcom,pmic-revid = <0x2e>; | |
qcom,flash_0 { | |
label = "flash"; | |
qcom,led-name = "led:flash_0"; | |
qcom,max-current = <0x5dc>; | |
qcom,default-led-trigger = "flash0_trigger"; | |
qcom,id = <0x0>; | |
qcom,current-ma = <0x3e8>; | |
qcom,duration-ms = <0x500>; | |
qcom,ires-ua = <0x32c8>; | |
qcom,hdrm-voltage-mv = <0x145>; | |
qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
linux,phandle = <0x295>; | |
phandle = <0x295>; | |
}; | |
qcom,flash_1 { | |
label = "flash"; | |
qcom,led-name = "led:flash_1"; | |
qcom,max-current = <0x5dc>; | |
qcom,default-led-trigger = "flash1_trigger"; | |
qcom,id = <0x1>; | |
qcom,current-ma = <0x3e8>; | |
qcom,duration-ms = <0x500>; | |
qcom,ires-ua = <0x32c8>; | |
qcom,hdrm-voltage-mv = <0x145>; | |
qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
linux,phandle = <0x296>; | |
phandle = <0x296>; | |
}; | |
qcom,flash_2 { | |
label = "flash"; | |
qcom,led-name = "led:flash_2"; | |
qcom,max-current = <0x2ee>; | |
qcom,default-led-trigger = "flash2_trigger"; | |
qcom,id = <0x2>; | |
qcom,current-ma = <0x1f4>; | |
qcom,duration-ms = <0x500>; | |
qcom,ires-ua = <0x30d4>; | |
qcom,hdrm-voltage-mv = <0x145>; | |
qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
linux,phandle = <0x29a>; | |
phandle = <0x29a>; | |
}; | |
qcom,torch_0 { | |
label = "torch"; | |
qcom,led-name = "led:torch_0"; | |
qcom,max-current = <0xc8>; | |
qcom,default-led-trigger = "torch0_trigger"; | |
qcom,id = <0x0>; | |
qcom,current-ma = <0x4b>; | |
qcom,ires-ua = <0x32c8>; | |
qcom,hdrm-voltage-mv = <0x145>; | |
qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
linux,phandle = <0x297>; | |
phandle = <0x297>; | |
}; | |
qcom,torch_1 { | |
label = "torch"; | |
qcom,led-name = "led:torch_1"; | |
qcom,max-current = <0xc8>; | |
qcom,default-led-trigger = "torch1_trigger"; | |
qcom,id = <0x1>; | |
qcom,current-ma = <0x4b>; | |
qcom,ires-ua = <0x32c8>; | |
qcom,hdrm-voltage-mv = <0x145>; | |
qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
linux,phandle = <0x298>; | |
phandle = <0x298>; | |
}; | |
qcom,torch_2 { | |
label = "torch"; | |
qcom,led-name = "led:torch_2"; | |
qcom,max-current = <0x1f4>; | |
qcom,default-led-trigger = "torch2_trigger"; | |
qcom,id = <0x2>; | |
qcom,current-ma = <0x12c>; | |
qcom,ires-ua = <0x30d4>; | |
qcom,hdrm-voltage-mv = <0x145>; | |
qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
linux,phandle = <0x29b>; | |
phandle = <0x29b>; | |
}; | |
qcom,led_switch_0 { | |
label = "switch"; | |
qcom,led-name = "led:switch_0"; | |
qcom,led-mask = <0x3>; | |
qcom,default-led-trigger = "switch0_trigger"; | |
linux,phandle = <0x299>; | |
phandle = <0x299>; | |
}; | |
qcom,led_switch_1 { | |
label = "switch"; | |
qcom,led-name = "led:switch_1"; | |
qcom,led-mask = <0x4>; | |
qcom,default-led-trigger = "switch1_trigger"; | |
linux,phandle = <0x29c>; | |
phandle = <0x29c>; | |
}; | |
}; | |
}; | |
qcom,pm8005@4 { | |
compatible = "qcom,spmi-pmic"; | |
reg = <0x4 0x0>; | |
#address-cells = <0x2>; | |
#size-cells = <0x0>; | |
qcom,revid@100 { | |
compatible = "qcom,qpnp-revid"; | |
reg = <0x100 0x100>; | |
}; | |
qcom,temp-alarm@2400 { | |
compatible = "qcom,qpnp-temp-alarm"; | |
reg = <0x2400 0x100>; | |
interrupts = <0x4 0x24 0x0 0x1>; | |
label = "pm8005_tz"; | |
}; | |
gpios { | |
compatible = "qcom,qpnp-pin"; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
#address-cells = <0x1>; | |
#size-cells = <0x1>; | |
label = "pm8005-gpio"; | |
gpio@c000 { | |
reg = <0xc000 0x100>; | |
qcom,pin-num = <0x1>; | |
status = "disabled"; | |
}; | |
gpio@c100 { | |
reg = <0xc100 0x100>; | |
qcom,pin-num = <0x2>; | |
status = "disabled"; | |
}; | |
gpio@c200 { | |
reg = <0xc200 0x100>; | |
qcom,pin-num = <0x3>; | |
status = "disabled"; | |
}; | |
gpio@c300 { | |
reg = <0xc300 0x100>; | |
qcom,pin-num = <0x4>; | |
status = "disabled"; | |
}; | |
}; | |
}; | |
qcom,pm8005@5 { | |
compatible = "qcom,spmi-pmic"; | |
reg = <0x5 0x0>; | |
#address-cells = <0x2>; | |
#size-cells = <0x0>; | |
regulator@1400 { | |
compatible = "qcom,qpnp-regulator"; | |
reg = <0x1400 0x100>; | |
regulator-name = "pm8005_s1"; | |
status = "okay"; | |
regulator-min-microvolt = <0x7dfa0>; | |
regulator-max-microvolt = <0x109a00>; | |
qcom,enable-time = <0x1f4>; | |
linux,phandle = <0xce>; | |
phandle = <0xce>; | |
}; | |
regulator@1700 { | |
compatible = "qcom,qpnp-regulator"; | |
reg = <0x1700 0x100>; | |
regulator-name = "pm8005_s2"; | |
status = "disabled"; | |
}; | |
regulator@1a00 { | |
compatible = "qcom,qpnp-regulator"; | |
reg = <0x1a00 0x100>; | |
regulator-name = "pm8005_s3"; | |
status = "disabled"; | |
}; | |
regulator@1d00 { | |
compatible = "qcom,qpnp-regulator"; | |
reg = <0x1d00 0x100>; | |
regulator-name = "pm8005_s4"; | |
status = "disabled"; | |
}; | |
}; | |
}; | |
qcom,sps { | |
compatible = "qcom,msm_sps_4k"; | |
qcom,device-type = <0x3>; | |
qcom,pipe-attr-ee; | |
}; | |
serial@0c170000 { | |
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
reg = <0xc170000 0x1000>; | |
interrupts = <0x0 0x6c 0x0>; | |
status = "disabled"; | |
clocks = <0x38 0xf8a61c96 0x38 0x8caa5b4f>; | |
clock-names = "core", "iface"; | |
}; | |
serial@0c1b0000 { | |
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
reg = <0xc1b0000 0x1000>; | |
interrupts = <0x0 0x72 0x0>; | |
status = "ok"; | |
clocks = <0x38 0x1e1965a3 0x38 0x8f283c1d>; | |
clock-names = "core", "iface"; | |
pinctrl-names = "default"; | |
pinctrl-0 = <0x39>; | |
}; | |
slim@171c0000 { | |
cell-index = <0x1>; | |
compatible = "qcom,slim-ngd"; | |
reg = <0x171c0000 0x2c000 0x17184000 0x32000>; | |
reg-names = "slimbus_physical", "slimbus_bam_physical"; | |
interrupts = <0x0 0xa3 0x0 0x0 0xa4 0x0>; | |
interrupt-names = "slimbus_irq", "slimbus_bam_irq"; | |
qcom,apps-ch-pipes = <0x1f80>; | |
qcom,ea-pc = <0x210>; | |
tasha_codec { | |
compatible = "qcom,tasha-slim-pgd"; | |
elemental-addr = [00 01 a0 01 17 02]; | |
interrupt-parent = <0x3a>; | |
interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e>; | |
qcom,wcd-rst-gpio-node = <0x3b>; | |
clock-names = "wcd_clk", "wcd_native_clk"; | |
clocks = <0x3c 0xcbfe416d 0x3c 0x454d1e91>; | |
cdc-vdd-buck-supply = <0x3d>; | |
qcom,cdc-vdd-buck-voltage = <0x1b7740 0x1b7740>; | |
qcom,cdc-vdd-buck-current = <0x9eb10>; | |
cdc-buck-sido-supply = <0x3d>; | |
qcom,cdc-buck-sido-voltage = <0x1b7740 0x1b7740>; | |
qcom,cdc-buck-sido-current = <0x3d090>; | |
cdc-vdd-tx-h-supply = <0x3d>; | |
qcom,cdc-vdd-tx-h-voltage = <0x1b7740 0x1b7740>; | |
qcom,cdc-vdd-tx-h-current = <0x61a8>; | |
cdc-vdd-rx-h-supply = <0x3d>; | |
qcom,cdc-vdd-rx-h-voltage = <0x1b7740 0x1b7740>; | |
qcom,cdc-vdd-rx-h-current = <0x61a8>; | |
cdc-vddpx-1-supply = <0x3d>; | |
qcom,cdc-vddpx-1-voltage = <0x1b7740 0x1b7740>; | |
qcom,cdc-vddpx-1-current = <0x2710>; | |
qcom,cdc-static-supplies = "cdc-vdd-buck", "cdc-buck-sido", "cdc-vdd-tx-h", "cdc-vdd-rx-h", "cdc-vddpx-1"; | |
qcom,cdc-micbias1-mv = <0xabe>; | |
qcom,cdc-micbias2-mv = <0x708>; | |
qcom,cdc-micbias3-mv = <0x708>; | |
qcom,cdc-micbias4-mv = <0xabe>; | |
qcom,cdc-mclk-clk-rate = <0x927c00>; | |
qcom,cdc-slim-ifd = "tasha-slim-ifd"; | |
qcom,cdc-slim-ifd-elemental-addr = [00 00 a0 01 17 02]; | |
qcom,cdc-dmic-sample-rate = <0x493e00>; | |
qcom,cdc-mad-dmic-rate = <0x927c0>; | |
qcom,cdc-ecpp-dmic-rate = <0x124f80>; | |
msm_cdc_pinctrll { | |
compatible = "qcom,msm-cdc-pinctrl"; | |
pinctrl-names = "aud_active", "aud_sleep"; | |
pinctrl-0 = <0x3e>; | |
pinctrl-1 = <0x3f>; | |
linux,phandle = <0x42>; | |
phandle = <0x42>; | |
}; | |
msm_cdc_pinctrlr { | |
compatible = "qcom,msm-cdc-pinctrl"; | |
pinctrl-names = "aud_active", "aud_sleep"; | |
pinctrl-0 = <0x40>; | |
pinctrl-1 = <0x41>; | |
linux,phandle = <0x43>; | |
phandle = <0x43>; | |
}; | |
swr_master { | |
compatible = "qcom,swr-wcd"; | |
#address-cells = <0x2>; | |
#size-cells = <0x0>; | |
wsa881x@20170211 { | |
compatible = "qcom,wsa881x"; | |
reg = <0x0 0x20170211>; | |
qcom,spkr-sd-n-node = <0x42>; | |
linux,phandle = <0x275>; | |
phandle = <0x275>; | |
}; | |
wsa881x@20170212 { | |
compatible = "qcom,wsa881x"; | |
reg = <0x0 0x20170212>; | |
qcom,spkr-sd-n-node = <0x43>; | |
linux,phandle = <0x276>; | |
phandle = <0x276>; | |
}; | |
wsa881x@21170213 { | |
compatible = "qcom,wsa881x"; | |
reg = <0x0 0x21170213>; | |
qcom,spkr-sd-n-node = <0x42>; | |
linux,phandle = <0x277>; | |
phandle = <0x277>; | |
}; | |
wsa881x@21170214 { | |
compatible = "qcom,wsa881x"; | |
reg = <0x0 0x21170214>; | |
qcom,spkr-sd-n-node = <0x43>; | |
linux,phandle = <0x278>; | |
phandle = <0x278>; | |
}; | |
}; | |
}; | |
tavil_codec { | |
compatible = "qcom,tavil-slim-pgd"; | |
elemental-addr = [00 01 50 02 17 02]; | |
interrupt-parent = <0x3a>; | |
interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f>; | |
qcom,wcd-rst-gpio-node = <0x3b>; | |
clock-names = "wcd_clk"; | |
clocks = <0x44 0x57312343>; | |
cdc-vdd-buck-supply = <0x3d>; | |
qcom,cdc-vdd-buck-voltage = <0x1b7740 0x1b7740>; | |
qcom,cdc-vdd-buck-current = <0x9eb10>; | |
cdc-buck-sido-supply = <0x3d>; | |
qcom,cdc-buck-sido-voltage = <0x1b7740 0x1b7740>; | |
qcom,cdc-buck-sido-current = <0x3d090>; | |
cdc-vdd-tx-h-supply = <0x3d>; | |
qcom,cdc-vdd-tx-h-voltage = <0x1b7740 0x1b7740>; | |
qcom,cdc-vdd-tx-h-current = <0x61a8>; | |
cdc-vdd-rx-h-supply = <0x3d>; | |
qcom,cdc-vdd-rx-h-voltage = <0x1b7740 0x1b7740>; | |
qcom,cdc-vdd-rx-h-current = <0x61a8>; | |
cdc-vddpx-1-supply = <0x3d>; | |
qcom,cdc-vddpx-1-voltage = <0x1b7740 0x1b7740>; | |
qcom,cdc-vddpx-1-current = <0x2710>; | |
qcom,cdc-static-supplies = "cdc-vdd-buck", "cdc-buck-sido", "cdc-vdd-tx-h", "cdc-vdd-rx-h", "cdc-vddpx-1"; | |
qcom,cdc-micbias1-mv = <0x708>; | |
qcom,cdc-micbias2-mv = <0x708>; | |
qcom,cdc-micbias3-mv = <0x708>; | |
qcom,cdc-micbias4-mv = <0x708>; | |
qcom,cdc-mclk-clk-rate = <0x927c00>; | |
qcom,cdc-slim-ifd = "tavil-slim-ifd"; | |
qcom,cdc-slim-ifd-elemental-addr = [00 00 50 02 17 02]; | |
qcom,cdc-dmic-sample-rate = <0x493e00>; | |
qcom,cdc-mad-dmic-rate = <0x927c0>; | |
qcom,wdsp-cmpnt-dev-name = "tavil_codec"; | |
linux,phandle = <0x287>; | |
phandle = <0x287>; | |
wcd_pinctrl@5 { | |
compatible = "qcom,wcd-pinctrl"; | |
qcom,num-gpios = <0x5>; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
us_euro_sw_wcd_active { | |
linux,phandle = <0x49>; | |
phandle = <0x49>; | |
mux { | |
pins = "gpio1"; | |
}; | |
config { | |
pins = "gpio1"; | |
output-high; | |
}; | |
}; | |
us_euro_sw_wcd_sleep { | |
linux,phandle = <0x4a>; | |
phandle = <0x4a>; | |
mux { | |
pins = "gpio1"; | |
}; | |
config { | |
pins = "gpio1"; | |
output-low; | |
}; | |
}; | |
spkr_1_wcd_en_active { | |
linux,phandle = <0x45>; | |
phandle = <0x45>; | |
mux { | |
pins = "gpio2"; | |
}; | |
config { | |
pins = "gpio2"; | |
output-high; | |
}; | |
}; | |
spkr_1_wcd_en_sleep { | |
linux,phandle = <0x46>; | |
phandle = <0x46>; | |
mux { | |
pins = "gpio2"; | |
}; | |
config { | |
pins = "gpio2"; | |
input-enable; | |
}; | |
}; | |
spkr_2_sd_n_active { | |
linux,phandle = <0x47>; | |
phandle = <0x47>; | |
mux { | |
pins = "gpio3"; | |
}; | |
config { | |
pins = "gpio3"; | |
output-high; | |
}; | |
}; | |
spkr_2_sd_n_sleep { | |
linux,phandle = <0x48>; | |
phandle = <0x48>; | |
mux { | |
pins = "gpio3"; | |
}; | |
config { | |
pins = "gpio3"; | |
input-enable; | |
}; | |
}; | |
hph_en0_wcd_active { | |
linux,phandle = <0x4b>; | |
phandle = <0x4b>; | |
mux { | |
pins = "gpio4"; | |
}; | |
config { | |
pins = "gpio4"; | |
output-high; | |
}; | |
}; | |
hph_en0_wcd_sleep { | |
linux,phandle = <0x4c>; | |
phandle = <0x4c>; | |
mux { | |
pins = "gpio4"; | |
}; | |
config { | |
pins = "gpio4"; | |
output-low; | |
}; | |
}; | |
hph_en1_wcd_active { | |
linux,phandle = <0x4d>; | |
phandle = <0x4d>; | |
mux { | |
pins = "gpio5"; | |
}; | |
config { | |
pins = "gpio5"; | |
output-high; | |
}; | |
}; | |
hph_en1_wcd_sleep { | |
linux,phandle = <0x4e>; | |
phandle = <0x4e>; | |
mux { | |
pins = "gpio5"; | |
}; | |
config { | |
pins = "gpio5"; | |
output-low; | |
}; | |
}; | |
}; | |
msm_cdc_pinctrll { | |
compatible = "qcom,msm-cdc-pinctrl"; | |
pinctrl-names = "aud_active", "aud_sleep"; | |
pinctrl-0 = <0x45>; | |
pinctrl-1 = <0x46>; | |
linux,phandle = <0x4f>; | |
phandle = <0x4f>; | |
}; | |
msm_cdc_pinctrlr { | |
compatible = "qcom,msm-cdc-pinctrl"; | |
pinctrl-names = "aud_active", "aud_sleep"; | |
pinctrl-0 = <0x47>; | |
pinctrl-1 = <0x48>; | |
linux,phandle = <0x50>; | |
phandle = <0x50>; | |
}; | |
msm_cdc_pinctrl_us_euro_sw { | |
compatible = "qcom,msm-cdc-pinctrl"; | |
pinctrl-names = "aud_active", "aud_sleep"; | |
pinctrl-0 = <0x49>; | |
pinctrl-1 = <0x4a>; | |
linux,phandle = <0x280>; | |
phandle = <0x280>; | |
}; | |
msm_cdc_pinctrl_hph_en0 { | |
compatible = "qcom,msm-cdc-pinctrl"; | |
pinctrl-names = "aud_active", "aud_sleep"; | |
pinctrl-0 = <0x4b>; | |
pinctrl-1 = <0x4c>; | |
linux,phandle = <0x281>; | |
phandle = <0x281>; | |
}; | |
msm_cdc_pinctrl_hph_en1 { | |
compatible = "qcom,msm-cdc-pinctrl"; | |
pinctrl-names = "aud_active", "aud_sleep"; | |
pinctrl-0 = <0x4d>; | |
pinctrl-1 = <0x4e>; | |
linux,phandle = <0x282>; | |
phandle = <0x282>; | |
}; | |
swr_master { | |
compatible = "qcom,swr-wcd"; | |
#address-cells = <0x2>; | |
#size-cells = <0x0>; | |
wsa881x@20170211 { | |
compatible = "qcom,wsa881x"; | |
reg = <0x0 0x20170211>; | |
qcom,spkr-sd-n-node = <0x4f>; | |
linux,phandle = <0x283>; | |
phandle = <0x283>; | |
}; | |
wsa881x@20170212 { | |
compatible = "qcom,wsa881x"; | |
reg = <0x0 0x20170212>; | |
qcom,spkr-sd-n-node = <0x50>; | |
linux,phandle = <0x284>; | |
phandle = <0x284>; | |
}; | |
wsa881x@21170213 { | |
compatible = "qcom,wsa881x"; | |
reg = <0x0 0x21170213>; | |
qcom,spkr-sd-n-node = <0x4f>; | |
linux,phandle = <0x285>; | |
phandle = <0x285>; | |
}; | |
wsa881x@21170214 { | |
compatible = "qcom,wsa881x"; | |
reg = <0x0 0x21170214>; | |
qcom,spkr-sd-n-node = <0x50>; | |
linux,phandle = <0x286>; | |
phandle = <0x286>; | |
}; | |
}; | |
wcd_spi { | |
compatible = "qcom,wcd-spi-v2"; | |
qcom,master-bus-num = <0xa>; | |
qcom,chip-select = <0x0>; | |
qcom,max-frequency = <0x16e3600>; | |
qcom,mem-base-addr = <0x100000>; | |
linux,phandle = <0x288>; | |
phandle = <0x288>; | |
}; | |
}; | |
msm_dai_slim { | |
compatible = "qcom,msm-dai-slim"; | |
elemental-addr = [ff ff ff fe 17 02]; | |
}; | |
}; | |
slim@17240000 { | |
status = "ok"; | |
cell-index = <0x3>; | |
compatible = "qcom,slim-ngd"; | |
reg = <0x17240000 0x2c000 0x17204000 0x26000>; | |
reg-names = "slimbus_physical", "slimbus_bam_physical"; | |
interrupts = <0x0 0x123 0x0 0x0 0x124 0x0>; | |
interrupt-names = "slimbus_irq", "slimbus_bam_irq"; | |
wcn3990 { | |
compatible = "qcom,btfmslim_slave"; | |
elemental-addr = [00 01 20 02 17 02]; | |
qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; | |
qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; | |
}; | |
}; | |
timer@17920000 { | |
#address-cells = <0x1>; | |
#size-cells = <0x1>; | |
ranges; | |
compatible = "arm,armv7-timer-mem"; | |
reg = <0x17920000 0x1000>; | |
clock-frequency = <0x124f800>; | |
frame@17921000 { | |
frame-number = <0x0>; | |
interrupts = <0x0 0x8 0x4 0x0 0x7 0x4>; | |
reg = <0x17921000 0x1000 0x17922000 0x1000>; | |
}; | |
frame@17923000 { | |
frame-number = <0x1>; | |
interrupts = <0x0 0x9 0x4>; | |
reg = <0x17923000 0x1000>; | |
status = "disabled"; | |
}; | |
frame@17924000 { | |
frame-number = <0x2>; | |
interrupts = <0x0 0xa 0x4>; | |
reg = <0x17924000 0x1000>; | |
status = "disabled"; | |
}; | |
frame@17925000 { | |
frame-number = <0x3>; | |
interrupts = <0x0 0xb 0x4>; | |
reg = <0x17925000 0x1000>; | |
status = "disabled"; | |
}; | |
frame@17926000 { | |
frame-number = <0x4>; | |
interrupts = <0x0 0xc 0x4>; | |
reg = <0x17926000 0x1000>; | |
status = "disabled"; | |
}; | |
frame@17927000 { | |
frame-number = <0x5>; | |
interrupts = <0x0 0xd 0x4>; | |
reg = <0x17927000 0x1000>; | |
status = "disabled"; | |
}; | |
frame@17928000 { | |
frame-number = <0x6>; | |
interrupts = <0x0 0xe 0x4>; | |
reg = <0x17928000 0x1000>; | |
status = "disabled"; | |
}; | |
}; | |
qcom,cpubw { | |
compatible = "qcom,devbw"; | |
governor = "performance"; | |
qcom,src-dst-ports = <0x1 0x200>; | |
qcom,active-only; | |
qcom,bw-tbl = <0x2fa 0x478 0x5f5 0x8f0 0xc47 0x104d 0x144b 0x16e3 0x1e4f 0x269f 0x2e57 0x35c3>; | |
linux,phandle = <0x51>; | |
phandle = <0x51>; | |
}; | |
qcom,cpu-bwmon { | |
compatible = "qcom,bimc-bwmon4"; | |
reg = <0x1008000 0x300 0x1001000 0x200>; | |
reg-names = "base", "global_base"; | |
interrupts = <0x0 0xb7 0x4>; | |
qcom,mport = <0x0>; | |
qcom,target-dev = <0x51>; | |
qcom,hw-timer-hz = <0x124f800>; | |
}; | |
qcom,mincpubw { | |
compatible = "qcom,devbw"; | |
governor = "powersave"; | |
qcom,src-dst-ports = <0x1 0x200>; | |
qcom,active-only; | |
qcom,bw-tbl = <0x2fa 0x478 0x5f5 0x8f0 0xc47 0x104d 0x144b 0x16e3 0x1e4f 0x269f 0x2e57 0x35c3>; | |
linux,phandle = <0x54>; | |
phandle = <0x54>; | |
}; | |
qcom,memlat-cpu0 { | |
compatible = "qcom,devbw"; | |
governor = "powersave"; | |
qcom,src-dst-ports = <0x1 0x200>; | |
qcom,active-only; | |
qcom,bw-tbl = <0x2fa 0x478 0x5f5 0x8f0 0xc47 0x104d 0x144b 0x16e3 0x1e4f 0x269f 0x2e57 0x35c3>; | |
linux,phandle = <0x52>; | |
phandle = <0x52>; | |
}; | |
qcom,memlat-cpu4 { | |
compatible = "qcom,devbw"; | |
governor = "powersave"; | |
qcom,src-dst-ports = <0x1 0x200>; | |
qcom,active-only; | |
status = "ok"; | |
qcom,bw-tbl = <0x2fa 0x478 0x5f5 0x8f0 0xc47 0x104d 0x144b 0x16e3 0x1e4f 0x269f 0x2e57 0x35c3>; | |
linux,phandle = <0x53>; | |
phandle = <0x53>; | |
}; | |
qcom,arm-memlat-mon-0 { | |
compatible = "qcom,arm-memlat-mon"; | |
qcom,cpulist = <0x16 0x17 0x18 0x19>; | |
qcom,target-dev = <0x52>; | |
qcom,core-dev-table = <0x493e0 0x5f5 0x91500 0xc47 0x143700 0x104d 0x17bb00 0x16e3 0x1aa900 0x16e3 0x1d0100 0x1e4f>; | |
}; | |
qcom,arm-memlat-mon-4 { | |
compatible = "qcom,arm-memlat-mon"; | |
qcom,cpulist = <0x1a 0x1b 0x1c 0x1d>; | |
qcom,target-dev = <0x53>; | |
qcom,core-dev-table = <0x8ca00 0xc47 0x114900 0x104d 0x148200 0x16e3 0x1a5e00 0x1e4f 0x1de200 0x2e57 0x21b100 0x35c3>; | |
}; | |
devfreq-cpufreq { | |
mincpubw-cpufreq { | |
target-dev = <0x54>; | |
cpu-to-dev-map-0 = <0x1d0100 0x5f5>; | |
cpu-to-dev-map-4 = <0x203a00 0x5f5 0x261600 0x144b>; | |
}; | |
}; | |
qcom,msm-cpufreq { | |
compatible = "qcom,msm-cpufreq"; | |
clock-names = "cpu0_clk", "cpu1_clk", "cpu2_clk", "cpu3_clk", "cpu4_clk", "cpu5_clk", "cpu6_clk", "cpu7_clk"; | |
clocks = <0x55 0xc554130e 0x55 0xc554130e 0x55 0xc554130e 0x55 0xc554130e 0x55 0x58869997 0x55 0x58869997 0x55 0x58869997 0x55 0x58869997>; | |
qcom,governor-per-policy; | |
qcom,cpufreq-table-0 = <0x493e0 0x59100 0x6bd00 0x7e900 0x91500 0xa4100 0xb6d00 0xc9900 0xd7a00 0xea600 0xfd200 0x10b300 0x11df00 0x130b00 0x143700 0x156300 0x168f00 0x17bb00 0x197d00 0x1aa900 0x1bd500 0x1d0100>; | |
qcom,cpufreq-table-4 = <0x493e0 0x54600 0x67200 0x79e00 0x8ca00 0x9f600 0xb2200 0xc4e00 0xdc500 0xef100 0x101d00 0x114900 0x122a00 0x135600 0x148200 0x15ae00 0x16da00 0x180600 0x193200 0x1a5e00 0x1b8a00 0x1cb600 0x1de200 0x1f0e00 0x203a00 0x21b100 0x229200 0x232800 0x237300 0x23be00 0x240900 0x24ea00 0x258000 0x25cb00 0x261600 0x278d00>; | |
}; | |
arm64-cpu-erp { | |
compatible = "arm,arm64-cpu-erp"; | |
interrupts = <0x0 0x2b 0x4 0x0 0x2c 0x4 0x0 0x29 0x4 0x0 0x2a 0x4>; | |
interrupt-names = "pri-dbe-irq", "sec-dbe-irq", "pri-ext-irq", "sec-ext-irq"; | |
poll-delay-ms = <0x1388>; | |
}; | |
qcom,gcc@100000 { | |
compatible = "qcom,gcc-8998-v2"; | |
reg = <0x100000 0xb0000>; | |
reg-names = "cc_base"; | |
vdd_dig-supply = <0x56>; | |
vdd_dig_ao-supply = <0x57>; | |
#clock-cells = <0x1>; | |
#reset-cells = <0x1>; | |
linux,phandle = <0x38>; | |
phandle = <0x38>; | |
}; | |
qcom,mmsscc@c8c0000 { | |
compatible = "qcom,mmsscc-8998-v2"; | |
reg = <0xc8c0000 0x40000>; | |
reg-names = "cc_base"; | |
vdd_dig-supply = <0x56>; | |
vdd_mmsscc_mx-supply = <0x58>; | |
clock-names = "xo", "gpll0", "gpll0_div", "pclk0_src", "pclk1_src", "byte0_src", "byte1_src", "dp_link_src", "dp_vco_div", "extpclk_src"; | |
clocks = <0x38 0x79e95308 0x38 0x8050f008 0x38 0xdd06848d 0x59 0x6c9da335 0x5a 0x4c0518b5 0x59 0xecf2c434 0x5a 0x14e2f38f 0x5b 0xcfe3f5dd 0x5b 0x3f8197c2 0x5c 0xbb7dc20d>; | |
#clock-cells = <0x1>; | |
#reset-cells = <0x1>; | |
linux,phandle = <0x27>; | |
phandle = <0x27>; | |
}; | |
qcom,gpucc@5065000 { | |
compatible = "qcom,gpucc-8998-v2"; | |
reg = <0x5065000 0x9000>; | |
reg-names = "cc_base"; | |
vdd_dig-supply = <0x56>; | |
clock-names = "xo_ao", "gpll0"; | |
clocks = <0x38 0x64eb6004 0x38 0xdad7a7a4>; | |
#clock-cells = <0x1>; | |
linux,phandle = <0x60>; | |
phandle = <0x60>; | |
}; | |
qcom,gfxcc@5065000 { | |
compatible = "qcom,gfxcc-8998-v2"; | |
reg = <0x5065000 0x9000>; | |
reg-names = "cc_base"; | |
vdd_gpucc-supply = <0x2c>; | |
vdd_mx-supply = <0x58>; | |
vdd_gpu_mx-supply = <0x58>; | |
qcom,gfx3d_clk_src-opp-handle = <0x5d>; | |
qcom,gfxfreq-speedbin0 = <0x0 0x0 0x0 0xaba9500 0x1 0x80 0xf518240 0x2 0x80 0x14628180 0x3 0x80 0x18ad2380 0x4 0x80 0x1eb246c0 0x5 0x100 0x23863d00 0x6 0x100 0x27ef6380 0x7 0x180 0x2a51bd80 0x8 0x180>; | |
qcom,gfxfreq-mx-speedbin0 = <0x0 0x0 0xaba9500 0x80 0xf518240 0x80 0x14628180 0x80 0x18ad2380 0x80 0x1eb246c0 0x100 0x23863d00 0x100 0x27ef6380 0x180 0x2a51bd80 0x180>; | |
#clock-cells = <0x1>; | |
linux,phandle = <0x2b>; | |
phandle = <0x2b>; | |
}; | |
qcom,cpu-clock-8998@179c0000 { | |
compatible = "qcom,cpu-clock-osm-msm8998-v2"; | |
reg = <0x179c0000 0x4000 0x17916000 0x1000 0x17816000 0x1000 0x179d1000 0x1000 0x17914800 0x800 0x17814800 0x800 0x784130 0x8 0x1791101c 0x8>; | |
reg-names = "osm", "pwrcl_pll", "perfcl_pll", "apcs_common", "pwrcl_acd", "perfcl_acd", "perfcl_efuse", "debug"; | |
vdd-pwrcl-supply = <0x5e>; | |
vdd-perfcl-supply = <0x5f>; | |
interrupts = <0x0 0x23 0x1 0x0 0x24 0x1>; | |
interrupt-names = "pwrcl-irq", "perfcl-irq"; | |
qcom,pwrcl-speedbin0-v0 = <0x11e1a300 0x4000f 0x1200020 0x1 0x1 0x15be6800 0x5040013 0x1200020 0x1 0x2 0x1a524800 0x5040017 0x2200020 0x1 0x3 0x1ee62800 0x504001b 0x2200020 0x1 0x4 0x237a0800 0x504001f 0x2200020 0x1 0x5 0x280de800 0x5040023 0x3200020 0x1 0x6 0x2ca1c800 0x5040027 0x3200020 0x1 0x7 0x3135a800 0x404002b 0x3220022 0x1 0x8 0x34a49000 0x404002e 0x4250025 0x1 0x9 0x39387000 0x4040032 0x4280028 0x1 0xa 0x3dcc5000 0x4040036 0x42b002b 0x1 0xb 0x413b3800 0x4040039 0x52e002e 0x2 0xc 0x45cf1800 0x404003d 0x5310031 0x2 0xd 0x4a62f800 0x4040041 0x5340034 0x2 0xe 0x4ef6d800 0x4040045 0x6370037 0x2 0xf 0x538ab800 0x4040049 0x63a003a 0x2 0x10 0x581e9800 0x404004d 0x73e003e 0x2 0x11 0x5cb27800 0x4040051 0x7410041 0x2 0x12 0x63904800 0x4040057 0x8460046 0x2 0x13 0x68242800 0x404005b 0x8490049 0x2 0x14 0x6cb80800 0x404005f 0x84c004c 0x3 0x15 0x714be800 0x4040063 0x94f004f 0x3 0x16>; | |
qcom,perfcl-speedbin0-v0 = <0x11e1a300 0x4000f 0x1200020 0x1 0x1 0x14997000 0x5040012 0x1200020 0x1 0x2 0x192d5000 0x5040016 0x2200020 0x1 0x3 0x1dc13000 0x504001a 0x2200020 0x1 0x4 0x22551000 0x504001e 0x2200020 0x1 0x5 0x26e8f000 0x5040022 0x3200020 0x1 0x6 0x2b7cd000 0x5040026 0x3200020 0x1 0x7 0x3010b000 0x504002a 0x3220022 0x1 0x8 0x35c98800 0x404002f 0x4260026 0x1 0x9 0x3a5d6800 0x4040033 0x4290029 0x1 0xa 0x3ef14800 0x4040037 0x52c002c 0x1 0xb 0x43852800 0x404003b 0x52f002f 0x1 0xc 0x46f41000 0x404003e 0x5320032 0x2 0xd 0x4b87f000 0x4040042 0x6350035 0x2 0xe 0x501bd000 0x4040046 0x6380038 0x2 0xf 0x54afb000 0x404004a 0x63b003b 0x2 0x10 0x59439000 0x404004e 0x73e003e 0x2 0x11 0x5dd77000 0x4040052 0x7420042 0x2 0x12 0x626b5000 0x4040056 0x7450045 0x2 0x13 0x66ff3000 0x404005a 0x8480048 0x2 0x14 0x6b931000 0x404005e 0x84b004b 0x2 0x15 0x7026f000 0x4040062 0x94e004e 0x2 0x16 0x74bad000 0x4040066 0x9520052 0x2 0x17 0x794eb000 0x404006a 0x9550055 0x3 0x18 0x7de29000 0x404006e 0xa580058 0x3 0x19 0x839b6800 0x4040073 0xa5c005c 0x3 0x1a 0x870a5000 0x4010076 0xa5e005e 0x3 0x1a 0x870a5000 0x4040076 0xa5e005e 0x3 0x1b 0x8b9e3000 0x401007a 0xa620062 0x3 0x1b 0x8b9e3000 0x404007a 0xa620062 0x3 0x1c 0x90321000 0x401007e 0xa650065 0x3 0x1c 0x90321000 0x404007e 0xa650065 0x3 0x1d 0x94c5f000 0x4010082 0xa680068 0x3 0x1d 0x927c0000 0x4040080 0xa660066 0x3 0x1e 0x9834d800 0x4010085 0xa6a006a 0x3 0x1e 0x93a0f800 0x4040081 0xa670067 0x3 0x1f 0x9959d000 0x4010086 0xa6b006b 0x3 0x1f 0x94c5f000 0x4040082 0xa680068 0x3 0x20 0x9a7ec800 0x4010087 0xa6c006c 0x3 0x20>; | |
qcom,up-timer = <0x3e8 0x3e8>; | |
qcom,down-timer = <0x3e8 0x3e8>; | |
qcom,pc-override-index = <0x0 0x0>; | |
qcom,set-ret-inactive; | |
qcom,enable-llm-freq-vote; | |
qcom,llm-freq-up-timer = <0x4fffb 0x4fffb>; | |
qcom,llm-freq-down-timer = <0x4fffb 0x4fffb>; | |
qcom,enable-llm-volt-vote; | |
qcom,llm-volt-up-timer = <0x4fffb 0x4fffb>; | |
qcom,llm-volt-down-timer = <0x4fffb 0x4fffb>; | |
qcom,cc-reads = <0xa>; | |
qcom,cc-delay = <0x5>; | |
qcom,cc-factor = <0x64>; | |
qcom,osm-clk-rate = <0xbebc200>; | |
qcom,xo-clk-rate = <0x124f800>; | |
qcom,l-val-base = <0x17916004 0x17816004>; | |
qcom,apcs-itm-present = <0x179d143c 0x179d143c>; | |
qcom,apcs-pll-user-ctl = <0x1791600c 0x1781600c>; | |
qcom,apcs-cfg-rcgr = <0x17911054 0x17811054>; | |
qcom,apcs-cmd-rcgr = <0x17911050 0x17811050>; | |
qcom,apm-mode-ctl = <0x179d0004 0x179d0010>; | |
qcom,apm-ctrl-status = <0x179d000c 0x179d0018>; | |
qcom,apm-threshold-voltage = <0xc3500>; | |
qcom,boost-fsm-en; | |
qcom,safe-fsm-en; | |
qcom,ps-fsm-en; | |
qcom,droop-fsm-en; | |
qcom,wfx-fsm-en; | |
qcom,pc-fsm-en; | |
qcom,pwrcl-apcs-mem-acc-cfg = <0x179d1360 0x179d1364 0x179d1364>; | |
qcom,perfcl-apcs-mem-acc-cfg = <0x179d1368 0x179d136c 0x179d1370>; | |
qcom,pwrcl-apcs-mem-acc-val = <0x0 0x80000000 0x80000000 0x0 0x0 0x0 0x0 0x1 0x1>; | |
qcom,perfcl-apcs-mem-acc-val = <0x0 0x0 0x80000000 0x0 0x0 0x0 0x0 0x0 0x1>; | |
clock-names = "aux_clk", "xo_ao"; | |
clocks = <0x38 0x17eb05d0 0x38 0x64eb6004>; | |
#clock-cells = <0x1>; | |
qcom,acdtd-val = <0x9611 0x9611>; | |
qcom,acdcr-val = <0x2b5ffd 0x2b5ffd>; | |
qcom,acdsscr-val = <0x501 0x501>; | |
qcom,acdextint0-val = <0x2cf9ae8 0x2cf9ae8>; | |
qcom,acdextint1-val = <0x2cf9afe 0x2cf9afe>; | |
qcom,acdautoxfer-val = <0x15 0x15>; | |
qcom,pwrcl-apcs-mem-acc-threshold-voltage = <0xd0020>; | |
qcom,perfcl-apcs-mem-acc-threshold-voltage = <0xd0020>; | |
qcom,perfcl-speedbin1-v0 = <0x11e1a300 0x4000f 0x1200020 0x1 0x1 0x14997000 0x5040012 0x1200020 0x1 0x2 0x192d5000 0x5040016 0x2200020 0x1 0x3 0x1dc13000 0x504001a 0x2200020 0x1 0x4 0x22551000 0x504001e 0x2200020 0x1 0x5 0x26e8f000 0x5040022 0x3200020 0x1 0x6 0x2b7cd000 0x5040026 0x3200020 0x1 0x7 0x3010b000 0x504002a 0x3220022 0x1 0x8 0x35c98800 0x404002f 0x4260026 0x1 0x9 0x3a5d6800 0x4040033 0x4290029 0x1 0xa 0x3ef14800 0x4040037 0x52c002c 0x1 0xb 0x43852800 0x404003b 0x52f002f 0x1 0xc 0x46f41000 0x404003e 0x5320032 0x2 0xd 0x4b87f000 0x4040042 0x6350035 0x2 0xe 0x501bd000 0x4040046 0x6380038 0x2 0xf 0x54afb000 0x404004a 0x63b003b 0x2 0x10 0x59439000 0x404004e 0x73e003e 0x2 0x11 0x5dd77000 0x4040052 0x7420042 0x2 0x12 0x626b5000 0x4040056 0x7450045 0x2 0x13 0x66ff3000 0x404005a 0x8480048 0x2 0x14 0x6b931000 0x404005e 0x84b004b 0x2 0x15 0x7026f000 0x4040062 0x94e004e 0x2 0x16 0x74bad000 0x4040066 0x9520052 0x2 0x17 0x794eb000 0x404006a 0x9550055 0x3 0x18 0x7de29000 0x404006e 0xa580058 0x3 0x19 0x839b6800 0x4040073 0xa5c005c 0x3 0x1a 0x89544000 0x4010078 0xa600060 0x3 0x1a>; | |
qcom,perfcl-speedbin2-v0 = <0x11e1a300 0x4000f 0x1200020 0x1 0x1 0x14997000 0x5040012 0x1200020 0x1 0x2 0x192d5000 0x5040016 0x2200020 0x1 0x3 0x1dc13000 0x504001a 0x2200020 0x1 0x4 0x22551000 0x504001e 0x2200020 0x1 0x5 0x26e8f000 0x5040022 0x3200020 0x1 0x6 0x2b7cd000 0x5040026 0x3200020 0x1 0x7 0x3010b000 0x504002a 0x3220022 0x1 0x8 0x35c98800 0x404002f 0x4260026 0x1 0x9 0x3a5d6800 0x4040033 0x4290029 0x1 0xa 0x3ef14800 0x4040037 0x52c002c 0x1 0xb 0x43852800 0x404003b 0x52f002f 0x1 0xc 0x46f41000 0x404003e 0x5320032 0x2 0xd 0x4b87f000 0x4040042 0x6350035 0x2 0xe 0x501bd000 0x4040046 0x6380038 0x2 0xf 0x54afb000 0x404004a 0x63b003b 0x2 0x10 0x59439000 0x404004e 0x73e003e 0x2 0x11 0x5dd77000 0x4040052 0x7420042 0x2 0x12 0x626b5000 0x4040056 0x7450045 0x2 0x13 0x66ff3000 0x404005a 0x8480048 0x2 0x14 0x6b931000 0x404005e 0x84b004b 0x2 0x15 0x7026f000 0x4040062 0x94e004e 0x2 0x16 0x74bad000 0x4040066 0x9520052 0x2 0x17 0x794eb000 0x404006a 0x9550055 0x3 0x18 0x7de29000 0x404006e 0xa580058 0x3 0x19 0x839b6800 0x4040073 0xa5c005c 0x3 0x1a 0x870a5000 0x4010076 0xa5e005e 0x3 0x1a 0x870a5000 0x4040076 0xa5e005e 0x3 0x1b 0x8b9e3000 0x401007a 0xa620062 0x3 0x1b 0x8a793800 0x4040079 0xa610061 0x3 0x1c 0x90321000 0x401007e 0xa650065 0x3 0x1c 0x8b9e3000 0x404007a 0xa620062 0x3 0x1d 0x91570800 0x401007f 0xa660066 0x3 0x1d 0x8cc32800 0x404007b 0xa620062 0x3 0x1e 0x927c0000 0x4010080 0xa660066 0x3 0x1e>; | |
qcom,perfcl-speedbin3-v0 = <0x11e1a300 0x4000f 0x1200020 0x1 0x1 0x14997000 0x5040012 0x1200020 0x1 0x2 0x192d5000 0x5040016 0x2200020 0x1 0x3 0x1dc13000 0x504001a 0x2200020 0x1 0x4 0x22551000 0x504001e 0x2200020 0x1 0x5 0x26e8f000 0x5040022 0x3200020 0x1 0x6 0x2b7cd000 0x5040026 0x3200020 0x1 0x7 0x3010b000 0x504002a 0x3220022 0x1 0x8 0x35c98800 0x404002f 0x4260026 0x1 0x9 0x3a5d6800 0x4040033 0x4290029 0x1 0xa 0x3ef14800 0x4040037 0x52c002c 0x1 0xb 0x43852800 0x404003b 0x52f002f 0x1 0xc 0x46f41000 0x404003e 0x5320032 0x2 0xd 0x4b87f000 0x4040042 0x6350035 0x2 0xe 0x501bd000 0x4040046 0x6380038 0x2 0xf 0x54afb000 0x404004a 0x63b003b 0x2 0x10 0x59439000 0x404004e 0x73e003e 0x2 0x11 0x5dd77000 0x4040052 0x7420042 0x2 0x12 0x626b5000 0x4040056 0x7450045 0x2 0x13 0x66ff3000 0x404005a 0x8480048 0x2 0x14 0x6b931000 0x404005e 0x84b004b 0x2 0x15 0x7026f000 0x4040062 0x94e004e 0x2 0x16 0x74bad000 0x4040066 0x9520052 0x2 0x17 0x794eb000 0x404006a 0x9550055 0x3 0x18 0x7de29000 0x404006e 0xa580058 0x3 0x19 0x839b6800 0x4040073 0xa5c005c 0x3 0x1a 0x870a5000 0x4010076 0xa5e005e 0x3 0x1a 0x870a5000 0x4040076 0xa5e005e 0x3 0x1b 0x8b9e3000 0x401007a 0xa620062 0x3 0x1b 0x8a793800 0x4040079 0xa610061 0x3 0x1c 0x90321000 0x401007e 0xa650065 0x3 0x1c 0x8b9e3000 0x404007a 0xa620062 0x3 0x1d 0x91570800 0x401007f 0xa660066 0x3 0x1d 0x8cc32800 0x404007b 0xa620062 0x3 0x1e 0x927c0000 0x4010080 0xa660066 0x3 0x1e>; | |
linux,phandle = <0x55>; | |
phandle = <0x55>; | |
qcom,limits-dcvs@0 { | |
compatible = "qcom,msm-hw-limits"; | |
interrupts = <0x0 0x25 0x4>; | |
linux,phandle = <0x3>; | |
phandle = <0x3>; | |
}; | |
qcom,limits-dcvs@1 { | |
compatible = "qcom,msm-hw-limits"; | |
interrupts = <0x0 0x26 0x4>; | |
linux,phandle = <0xd>; | |
phandle = <0xd>; | |
}; | |
}; | |
qcom,debugcc@162000 { | |
compatible = "qcom,cc-debug-8998"; | |
reg = <0x162000 0x4>; | |
reg-names = "cc_base"; | |
clock-names = "debug_gpu_clk", "debug_gfx_clk", "debug_mmss_clk", "debug_cpu_clk"; | |
clocks = <0x60 0x9ae8cd3c 0x2b 0x3ed47625 0x27 0xe646ffda 0x55 0x3ae8bcb2>; | |
#clock-cells = <0x1>; | |
}; | |
qcom,rmtfs_sharedmem@0 { | |
compatible = "qcom,sharedmem-uio"; | |
reg = <0x0 0x200000>; | |
reg-names = "rmtfs"; | |
qcom,client-id = <0x1>; | |
}; | |
qcom,msm_gsi { | |
compatible = "qcom,msm_gsi"; | |
}; | |
qcom,rmnet-ipa { | |
compatible = "qcom,rmnet-ipa3"; | |
qcom,rmnet-ipa-ssr; | |
qcom,ipa-loaduC; | |
qcom,ipa-advertise-sg-support; | |
}; | |
qcom,ipa@01e00000 { | |
compatible = "qcom,ipa"; | |
reg = <0x1e00000 0x34000 0x1e84000 0x31fff 0x1e04000 0x2c000>; | |
reg-names = "ipa-base", "bam-base", "gsi-base"; | |
interrupts = <0x0 0x14d 0x0 0x0 0x1b0 0x0 0x0 0x1b0 0x0>; | |
interrupt-names = "ipa-irq", "bam-irq", "gsi-irq"; | |
qcom,ipa-hw-ver = <0xb>; | |
qcom,ipa-hw-mode = <0x0>; | |
qcom,ee = <0x0>; | |
qcom,use-gsi; | |
qcom,use-ipa-tethering-bridge; | |
qcom,modem-cfg-emb-pipe-flt; | |
qcom,do-not-use-ch-gsi-20; | |
qcom,ipa-wdi2; | |
qcom,use-64-bit-dma-mask; | |
clocks = <0x38 0xfa685cda>; | |
clock-names = "core_clk"; | |
qcom,arm-smmu; | |
qcom,smmu-disable-htw; | |
qcom,smmu-s1-bypass; | |
qcom,msm-bus,name = "ipa"; | |
qcom,msm-bus,num-cases = <0x4>; | |
qcom,msm-bus,num-paths = <0x4>; | |
qcom,msm-bus,vectors-KBps = <0x5a 0x200 0x0 0x0 0x5a 0x249 0x0 0x0 0x1 0x2a4 0x0 0x0 0x51 0x2751 0x0 0x0 0x5a 0x200 0x13880 0x9c400 0x5a 0x249 0x13880 0x9c400 0x1 0x2a4 0x13880 0x13880 0x51 0x2751 0x0 0x3e80 0x5a 0x200 0x324b0 0xea600 0x5a 0x249 0x324b0 0xea600 0x1 0x2a4 0x324b0 0x27100 0x51 0x2751 0x0 0x3e80 0x5a 0x200 0x324b0 0x36ee80 0x5a 0x249 0x324b0 0x36ee80 0x1 0x2a4 0x324b0 0x493e0 0x51 0x2751 0x0 0x3e80>; | |
qcom,bus-vector-names = "MIN", "SVS", "NOMINAL", "TURBO"; | |
qcom,ipa-ram-mmap = <0x280 0x0 0x0 0x288 0x78 0x4000 0x308 0x78 0x4000 0x388 0x78 0x4000 0x408 0x78 0x4000 0xf 0x0 0x7 0x8 0xe 0x488 0x78 0x4000 0x508 0x78 0x4000 0xf 0x0 0x7 0x8 0xe 0x588 0x78 0x4000 0x608 0x78 0x4000 0x688 0x140 0x7c8 0x0 0x800 0x7d0 0x200 0x9d0 0x200 0x0 0x0 0x0 0xbd8 0x1424 0x1ffc 0x0 0x1ffc 0x0 0x1ffc 0x0 0x1ffc 0x0 0x80 0x200 0x2000 0x1ffc 0x0 0x1ffc 0x0 0x1ffc 0x0 0x1ffc 0x0>; | |
qcom,smp2pgpio_map_ipa_1_out { | |
compatible = "qcom,smp2pgpio-map-ipa-1-out"; | |
gpios = <0x61 0x0 0x0>; | |
}; | |
qcom,smp2pgpio_map_ipa_1_in { | |
compatible = "qcom,smp2pgpio-map-ipa-1-in"; | |
gpios = <0x62 0x0 0x0>; | |
}; | |
ipa_smmu_ap { | |
compatible = "qcom,ipa-smmu-ap-cb"; | |
iommus = <0x63 0x18e0>; | |
qcom,iova-mapping = <0x10000000 0x40000000>; | |
}; | |
ipa_smmu_wlan { | |
compatible = "qcom,ipa-smmu-wlan-cb"; | |
iommus = <0x63 0x18e1>; | |
}; | |
ipa_smmu_uc { | |
compatible = "qcom,ipa-smmu-uc-cb"; | |
iommus = <0x63 0x18e2>; | |
qcom,iova-mapping = <0x40000000 0x20000000>; | |
}; | |
}; | |
qcom,ipa_fws@1e08000 { | |
compatible = "qcom,pil-tz-generic"; | |
qcom,pas-id = <0xf>; | |
qcom,firmware-name = "ipa_fws"; | |
}; | |
qcom,chd_silver { | |
compatible = "qcom,core-hang-detect"; | |
label = "silver"; | |
qcom,threshold-arr = <0x179880b0 0x179980b0 0x179a80b0 0x179b80b0>; | |
qcom,config-arr = <0x179880b8 0x179980b8 0x179a80b8 0x179b80b8>; | |
}; | |
qcom,chd_gold { | |
compatible = "qcom,core-hang-detect"; | |
label = "gold"; | |
qcom,threshold-arr = <0x178880b0 0x178980b0 0x178a80b0 0x178b80b0>; | |
qcom,config-arr = <0x178880b8 0x178980b8 0x178a80b8 0x178b80b8>; | |
}; | |
qcom,ipc-spinlock@1f40000 { | |
compatible = "qcom,ipc-spinlock-sfpb"; | |
reg = <0x1f40000 0x8000>; | |
qcom,num-locks = <0x8>; | |
}; | |
qcom,ghd { | |
compatible = "qcom,gladiator-hang-detect"; | |
qcom,threshold-arr = <0x179d141c 0x179d1420 0x179d1424 0x179d1428 0x179d142c 0x179d1430>; | |
qcom,config-reg = <0x179d1434>; | |
}; | |
qcom,msm-gladiator-v2@17900000 { | |
compatible = "qcom,msm-gladiator-v2"; | |
reg = <0x17900000 0xe000>; | |
reg-names = "gladiator_base"; | |
interrupts = <0x0 0x16 0x0>; | |
clock-names = "atb_clk"; | |
clocks = <0x38 0x1492202a>; | |
}; | |
qcom,smem@86000000 { | |
compatible = "qcom,smem"; | |
reg = <0x86000000 0x200000 0x17911008 0x4 0x778000 0x7000 0x1fd4000 0x8>; | |
reg-names = "smem", "irq-reg-base", "aux-mem1", "smem_targ_info_reg"; | |
qcom,mpu-enabled; | |
}; | |
qcom,msm-adsprpc-mem { | |
compatible = "qcom,msm-adsprpc-mem-region"; | |
memory-region = <0x64>; | |
}; | |
qcom,msm_fastrpc { | |
compatible = "qcom,msm-fastrpc-adsp"; | |
qcom,fastrpc-glink; | |
qcom,msm_fastrpc_cpz_cb1 { | |
compatible = "qcom,msm-fastrpc-compute-cb"; | |
label = "adsprpc-smd"; | |
iommus = <0x65 0x2>; | |
qcom,secure-context-bank; | |
dma-coherent; | |
}; | |
qcom,msm_fastrpc_compute_cb1 { | |
compatible = "qcom,msm-fastrpc-compute-cb"; | |
label = "adsprpc-smd"; | |
iommus = <0x65 0x8>; | |
dma-coherent; | |
}; | |
qcom,msm_fastrpc_compute_cb2 { | |
compatible = "qcom,msm-fastrpc-compute-cb"; | |
label = "adsprpc-smd"; | |
iommus = <0x65 0x9>; | |
dma-coherent; | |
}; | |
qcom,msm_fastrpc_compute_cb3 { | |
compatible = "qcom,msm-fastrpc-compute-cb"; | |
label = "adsprpc-smd"; | |
iommus = <0x65 0xa>; | |
dma-coherent; | |
}; | |
qcom,msm_fastrpc_compute_cb4 { | |
compatible = "qcom,msm-fastrpc-compute-cb"; | |
label = "adsprpc-smd"; | |
iommus = <0x65 0xb>; | |
dma-coherent; | |
}; | |
qcom,msm_fastrpc_compute_cb6 { | |
compatible = "qcom,msm-fastrpc-compute-cb"; | |
label = "adsprpc-smd"; | |
iommus = <0x65 0x5>; | |
dma-coherent; | |
}; | |
qcom,msm_fastrpc_compute_cb7 { | |
compatible = "qcom,msm-fastrpc-compute-cb"; | |
label = "adsprpc-smd"; | |
iommus = <0x65 0x6>; | |
dma-coherent; | |
}; | |
qcom,msm_fastrpc_compute_cb8 { | |
compatible = "qcom,msm-fastrpc-compute-cb"; | |
label = "adsprpc-smd"; | |
iommus = <0x65 0x7>; | |
dma-coherent; | |
}; | |
}; | |
qcom,rpm-smd { | |
compatible = "qcom,rpm-glink"; | |
qcom,glink-edge = "rpm"; | |
rpm-channel-name = "rpm_requests"; | |
rpm-regulator-smpa1 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "rwcx"; | |
qcom,resource-id = <0x0>; | |
qcom,regulator-type = <0x1>; | |
status = "okay"; | |
regulator-s1 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_s1"; | |
qcom,set = <0x3>; | |
status = "disabled"; | |
}; | |
regulator-s1-level { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_s1_level"; | |
qcom,set = <0x3>; | |
regulator-min-microvolt = <0x10>; | |
regulator-max-microvolt = <0x180>; | |
qcom,use-voltage-level; | |
linux,phandle = <0x56>; | |
phandle = <0x56>; | |
}; | |
regulator-s1-floor-level { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_s1_floor_level"; | |
qcom,set = <0x3>; | |
regulator-min-microvolt = <0x10>; | |
regulator-max-microvolt = <0x180>; | |
qcom,use-voltage-floor-level; | |
qcom,always-send-voltage; | |
linux,phandle = <0x98>; | |
phandle = <0x98>; | |
}; | |
regulator-s1-level-ao { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_s1_level_ao"; | |
qcom,set = <0x1>; | |
regulator-min-microvolt = <0x10>; | |
regulator-max-microvolt = <0x180>; | |
qcom,use-voltage-level; | |
linux,phandle = <0x57>; | |
phandle = <0x57>; | |
}; | |
}; | |
rpm-regulator-smpa2 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "smpa"; | |
qcom,resource-id = <0x2>; | |
qcom,regulator-type = <0x1>; | |
status = "okay"; | |
regulator-s2 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_s2"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x113640>; | |
regulator-max-microvolt = <0x113640>; | |
}; | |
}; | |
rpm-regulator-smpa3 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "smpa"; | |
qcom,resource-id = <0x3>; | |
qcom,regulator-type = <0x1>; | |
status = "okay"; | |
regulator-s3 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_s3"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x14a140>; | |
regulator-max-microvolt = <0x14a140>; | |
linux,phandle = <0x2ab>; | |
phandle = <0x2ab>; | |
}; | |
}; | |
rpm-regulator-smpa4 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "smpa"; | |
qcom,resource-id = <0x4>; | |
qcom,regulator-type = <0x1>; | |
status = "okay"; | |
regulator-s4 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_s4"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x1b7740>; | |
regulator-max-microvolt = <0x1b7740>; | |
linux,phandle = <0x3d>; | |
phandle = <0x3d>; | |
}; | |
}; | |
rpm-regulator-smpa5 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "smpa"; | |
qcom,resource-id = <0x5>; | |
qcom,regulator-type = <0x1>; | |
status = "okay"; | |
regulator-s5 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_s5"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x1d0d80>; | |
regulator-max-microvolt = <0x1f20c0>; | |
qcom,init-pin-ctrl-mode = <0x8>; | |
qcom,send-defaults; | |
linux,phandle = <0xcb>; | |
phandle = <0xcb>; | |
}; | |
}; | |
rpm-regulator-smpa7 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "smpa"; | |
qcom,resource-id = <0x7>; | |
qcom,regulator-type = <0x1>; | |
status = "okay"; | |
regulator-s7 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_s7"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0xdbba0>; | |
regulator-max-microvolt = <0xfafa0>; | |
qcom,init-pin-ctrl-mode = <0x8>; | |
qcom,send-defaults; | |
linux,phandle = <0xca>; | |
phandle = <0xca>; | |
}; | |
}; | |
rpm-regulator-smpa8 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "smpa"; | |
qcom,resource-id = <0x8>; | |
qcom,regulator-type = <0x1>; | |
status = "okay"; | |
regulator-s8 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_s8"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0xc3500>; | |
regulator-max-microvolt = <0xc3500>; | |
}; | |
}; | |
rpm-regulator-smpa9 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "rwmx"; | |
qcom,resource-id = <0x0>; | |
qcom,regulator-type = <0x1>; | |
status = "okay"; | |
regulator-s9 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_s9"; | |
qcom,set = <0x3>; | |
status = "disabled"; | |
}; | |
regulator-s9-level { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_s9_level"; | |
qcom,set = <0x3>; | |
regulator-min-microvolt = <0x10>; | |
regulator-max-microvolt = <0x180>; | |
qcom,use-voltage-level; | |
linux,phandle = <0x58>; | |
phandle = <0x58>; | |
}; | |
regulator-s9-floor-level { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_s9_floor_level"; | |
qcom,set = <0x3>; | |
regulator-min-microvolt = <0x10>; | |
regulator-max-microvolt = <0x180>; | |
qcom,use-voltage-floor-level; | |
qcom,always-send-voltage; | |
}; | |
regulator-s9-level-ao { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_s9_level_ao"; | |
qcom,set = <0x1>; | |
regulator-min-microvolt = <0x10>; | |
regulator-max-microvolt = <0x180>; | |
qcom,use-voltage-level; | |
}; | |
}; | |
rpm-regulator-ldoa1 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0x1>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l1 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l1"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0xd6d80>; | |
regulator-max-microvolt = <0xd6d80>; | |
proxy-supply = <0x66>; | |
qcom,proxy-consumer-enable; | |
qcom,proxy-consumer-current = <0x11eb8>; | |
linux,phandle = <0x66>; | |
phandle = <0x66>; | |
}; | |
}; | |
rpm-regulator-ldoa2 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0x2>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l2 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l2"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x124f80>; | |
regulator-max-microvolt = <0x124f80>; | |
proxy-supply = <0x67>; | |
qcom,proxy-consumer-enable; | |
qcom,proxy-consumer-current = <0x3110>; | |
linux,phandle = <0x67>; | |
phandle = <0x67>; | |
}; | |
}; | |
rpm-regulator-ldoa3 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0x3>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l3 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l3"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0xf4240>; | |
regulator-max-microvolt = <0xf4240>; | |
}; | |
}; | |
rpm-regulator-ldoa4 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "rwsm"; | |
qcom,resource-id = <0x0>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l4 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l4"; | |
qcom,set = <0x3>; | |
status = "disabled"; | |
}; | |
regulator-l4-level { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l4_level"; | |
qcom,set = <0x3>; | |
regulator-min-microvolt = <0x10>; | |
regulator-max-microvolt = <0x180>; | |
qcom,use-voltage-level; | |
}; | |
regulator-l4-floor-level { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l4_floor_level"; | |
qcom,set = <0x3>; | |
regulator-min-microvolt = <0x10>; | |
regulator-max-microvolt = <0x180>; | |
qcom,use-voltage-floor-level; | |
qcom,always-send-voltage; | |
}; | |
}; | |
rpm-regulator-ldoa5 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0x5>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l5 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l5"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0xc3500>; | |
regulator-max-microvolt = <0xc3500>; | |
qcom,init-pin-ctrl-mode = <0x1>; | |
linux,phandle = <0xc1>; | |
phandle = <0xc1>; | |
}; | |
}; | |
rpm-regulator-ldoa6 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0x6>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l6 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l6"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x1b7740>; | |
regulator-max-microvolt = <0x1b7740>; | |
linux,phandle = <0x1ea>; | |
phandle = <0x1ea>; | |
}; | |
}; | |
rpm-regulator-ldoa7 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0x7>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l7 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l7"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x1b7740>; | |
regulator-max-microvolt = <0x1b7740>; | |
linux,phandle = <0x2ac>; | |
phandle = <0x2ac>; | |
}; | |
regulator-l7-pin-ctrl { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l7_pin_ctrl"; | |
qcom,set = <0x3>; | |
regulator-min-microvolt = <0x1b7740>; | |
regulator-max-microvolt = <0x1b7740>; | |
qcom,init-pin-ctrl-mode = <0x4>; | |
qcom,enable-with-pin-ctrl = <0x0 0x4>; | |
linux,phandle = <0xc2>; | |
phandle = <0xc2>; | |
}; | |
}; | |
rpm-regulator-ldoa8 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0x8>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l8 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l8"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x124f80>; | |
regulator-max-microvolt = <0x124f80>; | |
}; | |
}; | |
rpm-regulator-ldoa9 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0x9>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l9 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l9"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x1b9680>; | |
regulator-max-microvolt = <0x2d2a80>; | |
}; | |
}; | |
rpm-regulator-ldoa10 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0xa>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l10 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l10"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x1b9680>; | |
regulator-max-microvolt = <0x2d2a80>; | |
}; | |
}; | |
rpm-regulator-ldoa11 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0xb>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l11 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l11"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0xf4240>; | |
regulator-max-microvolt = <0xf4240>; | |
}; | |
}; | |
rpm-regulator-ldoa12 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0xc>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l12 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l12"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x1b7740>; | |
regulator-max-microvolt = <0x1b7740>; | |
linux,phandle = <0x69>; | |
phandle = <0x69>; | |
}; | |
}; | |
rpm-regulator-ldoa13 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0xd>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l13 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l13"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x1b9680>; | |
regulator-max-microvolt = <0x2d2a80>; | |
linux,phandle = <0x73>; | |
phandle = <0x73>; | |
}; | |
}; | |
rpm-regulator-ldoa14 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0xe>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l14 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l14"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x1b7740>; | |
regulator-max-microvolt = <0x1b7740>; | |
proxy-supply = <0x68>; | |
qcom,proxy-consumer-enable; | |
qcom,proxy-consumer-current = <0x7d00>; | |
linux,phandle = <0x68>; | |
phandle = <0x68>; | |
}; | |
}; | |
rpm-regulator-ldoa15 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0xf>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l15 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l15"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x1b7740>; | |
regulator-max-microvolt = <0x1b7740>; | |
}; | |
}; | |
rpm-regulator-ldoa16 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0x10>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l16 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l16"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x294280>; | |
regulator-max-microvolt = <0x294280>; | |
}; | |
}; | |
rpm-regulator-ldoa17 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0x11>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l17 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l17"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x13e5c0>; | |
regulator-max-microvolt = <0x13e5c0>; | |
linux,phandle = <0x2ad>; | |
phandle = <0x2ad>; | |
}; | |
regulator-l17-pin-ctrl { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l17_pin_ctrl"; | |
qcom,set = <0x3>; | |
regulator-min-microvolt = <0x13e5c0>; | |
regulator-max-microvolt = <0x13e5c0>; | |
qcom,init-pin-ctrl-mode = <0x4>; | |
qcom,enable-with-pin-ctrl = <0x0 0x4>; | |
linux,phandle = <0xc3>; | |
phandle = <0xc3>; | |
}; | |
}; | |
rpm-regulator-ldoa18 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0x12>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l18 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l18"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x294280>; | |
regulator-max-microvolt = <0x294280>; | |
}; | |
}; | |
rpm-regulator-ldoa19 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0x13>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l19 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l19"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x2de600>; | |
regulator-max-microvolt = <0x2de600>; | |
}; | |
}; | |
rpm-regulator-ldoa20 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0x14>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l20 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l20"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x2d2a80>; | |
regulator-max-microvolt = <0x2d2a80>; | |
linux,phandle = <0x83>; | |
phandle = <0x83>; | |
}; | |
}; | |
rpm-regulator-ldoa21 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0x15>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l21 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l21"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x2d2a80>; | |
regulator-max-microvolt = <0x2d2a80>; | |
linux,phandle = <0x72>; | |
phandle = <0x72>; | |
}; | |
}; | |
rpm-regulator-ldoa22 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0x16>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l22 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l22"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x2bb380>; | |
regulator-max-microvolt = <0x2bb380>; | |
linux,phandle = <0xe7>; | |
phandle = <0xe7>; | |
}; | |
}; | |
rpm-regulator-ldoa23 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0x17>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l23 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l23"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x328980>; | |
regulator-max-microvolt = <0x328980>; | |
}; | |
}; | |
rpm-regulator-ldoa24 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0x18>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l24 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l24"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x1c32c0>; | |
regulator-max-microvolt = <0x2f1e80>; | |
parent-supply = <0x69>; | |
linux,phandle = <0x31>; | |
phandle = <0x31>; | |
}; | |
}; | |
rpm-regulator-ldoa25 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0x19>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l25 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l25"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x2f5d00>; | |
regulator-max-microvolt = <0x328980>; | |
linux,phandle = <0x2ae>; | |
phandle = <0x2ae>; | |
}; | |
regulator-l25-pin-ctrl { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l25_pin_ctrl"; | |
qcom,set = <0x3>; | |
regulator-min-microvolt = <0x2f5d00>; | |
regulator-max-microvolt = <0x328980>; | |
qcom,init-pin-ctrl-mode = <0x4>; | |
qcom,enable-with-pin-ctrl = <0x0 0x4>; | |
linux,phandle = <0xc4>; | |
phandle = <0xc4>; | |
}; | |
}; | |
rpm-regulator-ldoa26 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0x1a>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l26 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l26"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x124f80>; | |
regulator-max-microvolt = <0x124f80>; | |
linux,phandle = <0x7d>; | |
phandle = <0x7d>; | |
}; | |
}; | |
rpm-regulator-ldoa27 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "rwsc"; | |
qcom,resource-id = <0x0>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l27 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l27"; | |
qcom,set = <0x3>; | |
status = "disabled"; | |
}; | |
regulator-l27-level { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l27_level"; | |
qcom,set = <0x3>; | |
regulator-min-microvolt = <0x10>; | |
regulator-max-microvolt = <0x180>; | |
qcom,use-voltage-level; | |
linux,phandle = <0xa1>; | |
phandle = <0xa1>; | |
}; | |
regulator-l27-floor-level { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l27_floor_level"; | |
qcom,set = <0x3>; | |
regulator-min-microvolt = <0x10>; | |
regulator-max-microvolt = <0x180>; | |
qcom,use-voltage-floor-level; | |
qcom,always-send-voltage; | |
}; | |
}; | |
rpm-regulator-ldoa28 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "ldoa"; | |
qcom,resource-id = <0x1c>; | |
qcom,regulator-type = <0x0>; | |
status = "okay"; | |
regulator-l28 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_l28"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x2de600>; | |
regulator-max-microvolt = <0x2de600>; | |
}; | |
}; | |
rpm-regulator-vsa1 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "vsa"; | |
qcom,resource-id = <0x1>; | |
qcom,regulator-type = <0x2>; | |
status = "okay"; | |
regulator-lvs1 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_lvs1"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
linux,phandle = <0xdf>; | |
phandle = <0xdf>; | |
}; | |
}; | |
rpm-regulator-vsa2 { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "vsa"; | |
qcom,resource-id = <0x2>; | |
qcom,regulator-type = <0x2>; | |
status = "okay"; | |
regulator-lvs2 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_lvs2"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
linux,phandle = <0xa2>; | |
phandle = <0xa2>; | |
}; | |
}; | |
rpm-regulator-bobb { | |
compatible = "qcom,rpm-smd-regulator-resource"; | |
qcom,resource-name = "bobb"; | |
qcom,resource-id = <0x1>; | |
qcom,regulator-type = <0x4>; | |
status = "okay"; | |
regulator-bob { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_bob"; | |
qcom,set = <0x3>; | |
status = "okay"; | |
regulator-min-microvolt = <0x328980>; | |
regulator-max-microvolt = <0x39fbc0>; | |
qcom,pwm-threshold-current = <0x1e8480>; | |
qcom,init-bob-mode = <0x2>; | |
qcom,bob-pwm-threshold-current = <0x1e8480>; | |
}; | |
regulator-bob-pin1 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_bob_pin1"; | |
qcom,set = <0x3>; | |
regulator-min-microvolt = <0x328980>; | |
regulator-max-microvolt = <0x39fbc0>; | |
qcom,pwm-threshold-current = <0x1e8480>; | |
qcom,init-bob-mode = <0x2>; | |
qcom,use-pin-ctrl-voltage1; | |
qcom,bob-pwm-threshold-current = <0x1e8480>; | |
linux,phandle = <0x2af>; | |
phandle = <0x2af>; | |
}; | |
regulator-bob-pin2 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_bob_pin2"; | |
qcom,set = <0x3>; | |
regulator-min-microvolt = <0x328980>; | |
regulator-max-microvolt = <0x39fbc0>; | |
qcom,pwm-threshold-current = <0x1e8480>; | |
qcom,init-bob-mode = <0x2>; | |
qcom,use-pin-ctrl-voltage2; | |
qcom,bob-pwm-threshold-current = <0x1e8480>; | |
}; | |
regulator-bob-pin3 { | |
compatible = "qcom,rpm-smd-regulator"; | |
regulator-name = "pm8998_bob_pin3"; | |
qcom,set = <0x3>; | |
regulator-min-microvolt = <0x328980>; | |
regulator-max-microvolt = <0x39fbc0>; | |
qcom,pwm-threshold-current = <0x1e8480>; | |
qcom,init-bob-mode = <0x2>; | |
qcom,use-pin-ctrl-voltage3; | |
qcom,bob-pwm-threshold-current = <0x1e8480>; | |
}; | |
}; | |
}; | |
qcom,glink-ssr-modem { | |
compatible = "qcom,glink_ssr"; | |
label = "modem"; | |
qcom,edge = "mpss"; | |
qcom,notify-edges = <0x6a 0x6b 0x6c>; | |
qcom,xprt = "smem"; | |
linux,phandle = <0x6d>; | |
phandle = <0x6d>; | |
}; | |
qcom,glink-ssr-adsp { | |
compatible = "qcom,glink_ssr"; | |
label = "adsp"; | |
qcom,edge = "lpass"; | |
qcom,notify-edges = <0x6d 0x6b 0x6c>; | |
qcom,xprt = "smem"; | |
linux,phandle = <0x6a>; | |
phandle = <0x6a>; | |
}; | |
qcom,glink-ssr-dsps { | |
compatible = "qcom,glink_ssr"; | |
label = "slpi"; | |
qcom,edge = "dsps"; | |
qcom,notify-edges = <0x6d 0x6a 0x6c>; | |
qcom,xprt = "smem"; | |
linux,phandle = <0x6b>; | |
phandle = <0x6b>; | |
}; | |
qcom,glink-ssr-rpm { | |
compatible = "qcom,glink_ssr"; | |
label = "rpm"; | |
qcom,edge = "rpm"; | |
qcom,notify-edges = <0x6a 0x6d 0x6b 0x6e>; | |
qcom,xprt = "smem"; | |
linux,phandle = <0x6c>; | |
phandle = <0x6c>; | |
}; | |
qcom,glink-ssr-spss { | |
compatible = "qcom,glink_ssr"; | |
label = "spss"; | |
qcom,edge = "spss"; | |
qcom,notify-edges = <0x6d 0x6a 0x6b 0x6c>; | |
qcom,xprt = "mailbox"; | |
linux,phandle = <0x6e>; | |
phandle = <0x6e>; | |
}; | |
qcom,glink-smem-native-xprt-modem@86000000 { | |
compatible = "qcom,glink-smem-native-xprt"; | |
reg = <0x86000000 0x200000 0x17911008 0x4>; | |
reg-names = "smem", "irq-reg-base"; | |
qcom,irq-mask = <0x8000>; | |
interrupts = <0x0 0x1c4 0x1>; | |
label = "mpss"; | |
}; | |
qcom,glink-smem-native-xprt-adsp@86000000 { | |
compatible = "qcom,glink-smem-native-xprt"; | |
reg = <0x86000000 0x200000 0x17911008 0x4>; | |
reg-names = "smem", "irq-reg-base"; | |
qcom,irq-mask = <0x200>; | |
interrupts = <0x0 0x9d 0x1>; | |
label = "lpass"; | |
qcom,qos-config = <0x6f>; | |
qcom,ramp-time = <0xaf>; | |
}; | |
qcom,glink-qos-config-adsp { | |
compatible = "qcom,glink-qos-config"; | |
qcom,flow-info = <0x3c 0x0 0x3c 0x0 0x3c 0x0 0x3c 0x0>; | |
qcom,mtu-size = <0x800>; | |
qcom,tput-stats-cycle = <0xa>; | |
linux,phandle = <0x6f>; | |
phandle = <0x6f>; | |
}; | |
qcom,glink-smem-native-xprt-dsps@86000000 { | |
compatible = "qcom,glink-smem-native-xprt"; | |
reg = <0x86000000 0x200000 0x17911008 0x4>; | |
reg-names = "smem", "irq-reg-base"; | |
qcom,irq-mask = <0x8000000>; | |
interrupts = <0x0 0xb3 0x1>; | |
label = "dsps"; | |
}; | |
qcom,glink-smem-native-xprt-rpm@778000 { | |
compatible = "qcom,glink-rpm-native-xprt"; | |
reg = <0x778000 0x7000 0x17911008 0x4>; | |
reg-names = "msgram", "irq-reg-base"; | |
qcom,irq-mask = <0x1>; | |
interrupts = <0x0 0xa8 0x1>; | |
label = "rpm"; | |
}; | |
qcom,glink-mailbox-xprt-spss@1d05008 { | |
compatible = "qcom,glink-mailbox-xprt"; | |
reg = <0x1d05008 0x8 0x1d05010 0x4 0x1d0501c 0x4 0x1d06008 0x4>; | |
reg-names = "mbox-loc-addr", "mbox-loc-size", "irq-reg-base", "irq-rx-reset"; | |
qcom,irq-mask = <0x1>; | |
interrupts = <0x0 0x15c 0x4>; | |
label = "spss"; | |
qcom,tx-ring-size = <0x800>; | |
qcom,rx-ring-size = <0x800>; | |
}; | |
qcom,glink-spi-xprt-wdsp { | |
compatible = "qcom,glink-spi-xprt"; | |
label = "wdsp"; | |
qcom,remote-fifo-config = <0x70>; | |
qcom,qos-config = <0x71>; | |
qcom,ramp-time = <0x10 0x20 0x30 0x40>; | |
linux,phandle = <0x289>; | |
phandle = <0x289>; | |
}; | |
qcom,glink-fifo-config-wdsp { | |
compatible = "qcom,glink-fifo-config"; | |
qcom,out-read-idx-reg = <0x12000>; | |
qcom,out-write-idx-reg = <0x12004>; | |
qcom,in-read-idx-reg = <0x1200c>; | |
qcom,in-write-idx-reg = <0x12010>; | |
linux,phandle = <0x70>; | |
phandle = <0x70>; | |
}; | |
qcom,glink-qos-config-wdsp { | |
compatible = "qcom,glink-qos-config"; | |
qcom,flow-info = <0x80 0x0 0x70 0x1 0x60 0x2 0x50 0x3>; | |
qcom,mtu-size = <0x800>; | |
qcom,tput-stats-cycle = <0xa>; | |
linux,phandle = <0x71>; | |
phandle = <0x71>; | |
}; | |
qcom,glink_pkt { | |
compatible = "qcom,glinkpkt"; | |
qcom,glinkpkt-at-mdm0 { | |
qcom,glinkpkt-transport = "smem"; | |
qcom,glinkpkt-edge = "mpss"; | |
qcom,glinkpkt-ch-name = "DS"; | |
qcom,glinkpkt-dev-name = "at_mdm0"; | |
}; | |
qcom,glinkpkt-loopback_cntl { | |
qcom,glinkpkt-transport = "lloop"; | |
qcom,glinkpkt-edge = "local"; | |
qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT"; | |
qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl"; | |
}; | |
qcom,glinkpkt-loopback_data { | |
qcom,glinkpkt-transport = "lloop"; | |
qcom,glinkpkt-edge = "local"; | |
qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT"; | |
qcom,glinkpkt-dev-name = "glink_pkt_loopback"; | |
}; | |
qcom,glinkpkt-apr-apps2 { | |
qcom,glinkpkt-transport = "smem"; | |
qcom,glinkpkt-edge = "adsp"; | |
qcom,glinkpkt-ch-name = "apr_apps2"; | |
qcom,glinkpkt-dev-name = "apr_apps2"; | |
}; | |
qcom,glinkpkt-data40-cntl { | |
qcom,glinkpkt-transport = "smem"; | |
qcom,glinkpkt-edge = "mpss"; | |
qcom,glinkpkt-ch-name = "DATA40_CNTL"; | |
qcom,glinkpkt-dev-name = "smdcntl8"; | |
}; | |
qcom,glinkpkt-data1 { | |
qcom,glinkpkt-transport = "smem"; | |
qcom,glinkpkt-edge = "mpss"; | |
qcom,glinkpkt-ch-name = "DATA1"; | |
qcom,glinkpkt-dev-name = "smd7"; | |
}; | |
qcom,glinkpkt-data4 { | |
qcom,glinkpkt-transport = "smem"; | |
qcom,glinkpkt-edge = "mpss"; | |
qcom,glinkpkt-ch-name = "DATA4"; | |
qcom,glinkpkt-dev-name = "smd8"; | |
}; | |
qcom,glinkpkt-data11 { | |
qcom,glinkpkt-transport = "smem"; | |
qcom,glinkpkt-edge = "mpss"; | |
qcom,glinkpkt-ch-name = "DATA11"; | |
qcom,glinkpkt-dev-name = "smd11"; | |
}; | |
}; | |
qcom,ipc_router { | |
compatible = "qcom,ipc_router"; | |
qcom,node-id = <0x1>; | |
}; | |
qcom,ipc_router_modem_xprt { | |
compatible = "qcom,ipc_router_glink_xprt"; | |
qcom,ch-name = "IPCRTR"; | |
qcom,xprt-remote = "mpss"; | |
qcom,glink-xprt = "smem"; | |
qcom,xprt-linkid = <0x1>; | |
qcom,xprt-version = <0x1>; | |
qcom,fragmented-data; | |
}; | |
qcom,ipc_router_q6_xprt { | |
compatible = "qcom,ipc_router_glink_xprt"; | |
qcom,ch-name = "IPCRTR"; | |
qcom,xprt-remote = "lpass"; | |
qcom,glink-xprt = "smem"; | |
qcom,xprt-linkid = <0x1>; | |
qcom,xprt-version = <0x1>; | |
qcom,fragmented-data; | |
}; | |
qcom,ipc_router_dsps_xprt { | |
compatible = "qcom,ipc_router_glink_xprt"; | |
qcom,ch-name = "IPCRTR"; | |
qcom,xprt-remote = "dsps"; | |
qcom,glink-xprt = "smem"; | |
qcom,xprt-linkid = <0x1>; | |
qcom,xprt-version = <0x1>; | |
qcom,fragmented-data; | |
qcom,dynamic-wakeup-source; | |
}; | |
qcom,spcom { | |
compatible = "qcom,spcom"; | |
qcom,spcom-ch-names = "sp_kernel", "sp_ssr"; | |
status = "ok"; | |
}; | |
qcom,spss_utils { | |
compatible = "qcom,spss-utils"; | |
qcom,spss-fuse1-addr = <0x7841c4>; | |
qcom,spss-fuse1-bit = <0x1b>; | |
qcom,spss-fuse2-addr = <0x78413c>; | |
qcom,spss-fuse2-bit = <0x1f>; | |
qcom,spss-test-firmware-name = "spss2t"; | |
qcom,spss-prod-firmware-name = "spss2p"; | |
qcom,spss-hybr-firmware-name = "spss2h"; | |
qcom,spss-debug-reg-addr = <0x1d06020>; | |
status = "ok"; | |
}; | |
sdhci@c0a4900 { | |
compatible = "qcom,sdhci-msm"; | |
reg = <0xc0a4900 0x314 0xc0a4000 0x800>; | |
reg-names = "hc_mem", "core_mem"; | |
interrupts = <0x0 0x7d 0x0 0x0 0xdd 0x0>; | |
interrupt-names = "hc_irq", "pwr_irq"; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x23d5727f 0x38 0x861b20ac>; | |
qcom,large-address-bus; | |
qcom,bus-width = <0x4>; | |
qcom,cpu-dma-latency-us = <0x2bd>; | |
qcom,devfreq,freq-table = <0x3197500 0xbebc200>; | |
qcom,msm-bus,name = "sdhc2"; | |
qcom,msm-bus,num-cases = <0x8>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x51 0x200 0x0 0x0 0x51 0x200 0x640 0xc80 0x51 0x200 0x13880 0x27100 0x51 0x200 0x186a0 0x30d40 0x51 0x200 0x30d40 0x61a80 0x51 0x200 0x61a80 0xc3500 0x51 0x200 0xc3500 0xc3500 0x51 0x200 0x1f4000 0x3e8000>; | |
qcom,bus-bw-vectors-bps = <0x0 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>; | |
qcom,sdr104-wa; | |
status = "ok"; | |
vdd-supply = <0x72>; | |
qcom,vdd-voltage-level = <0x2d0370 0x2d2a80>; | |
qcom,vdd-current-level = <0xc8 0xc3500>; | |
vdd-io-supply = <0x73>; | |
qcom,vdd-io-voltage-level = <0x1b9680 0x2d2a80>; | |
qcom,vdd-io-current-level = <0xc8 0x55f0>; | |
pinctrl-names = "active", "sleep"; | |
pinctrl-0 = <0x74 0x75 0x76 0x77>; | |
pinctrl-1 = <0x78 0x79 0x7a 0x7b>; | |
qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200>; | |
qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; | |
cd-gpios = <0x7c 0x5f 0x1>; | |
}; | |
ufsphy@1da7000 { | |
compatible = "qcom,ufs-phy-qmp-v3"; | |
reg = <0x1da7000 0xda8>; | |
reg-names = "phy_mem"; | |
#phy-cells = <0x0>; | |
clock-names = "ref_clk_src", "ref_clk", "ref_aux_clk"; | |
clocks = <0x38 0xb867b147 0x38 0x92aa126f 0x38 0x7dbdb2e2>; | |
status = "ok"; | |
vdda-phy-supply = <0x66>; | |
vdda-pll-supply = <0x67>; | |
vddp-ref-clk-supply = <0x7d>; | |
vdda-phy-max-microamp = <0xc8c8>; | |
vdda-pll-max-microamp = <0x3908>; | |
vddp-ref-clk-max-microamp = <0x64>; | |
vddp-ref-clk-always-on; | |
linux,phandle = <0x7f>; | |
phandle = <0x7f>; | |
}; | |
ufsice@1db0000 { | |
compatible = "qcom,ice"; | |
reg = <0x1db0000 0x8000>; | |
qcom,enable-ice-clk; | |
clock-names = "ufs_core_clk", "bus_clk", "iface_clk", "ice_core_clk"; | |
clocks = <0x38 0x47c743a7 0x38 0x873459d8 0x38 0x1914bb84 0x38 0x310b0710>; | |
qcom,op-freq-hz = <0x0 0x0 0x0 0x11e1a300>; | |
vdd-hba-supply = <0x7e>; | |
qcom,msm-bus,name = "ufs_ice_noc"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x1 0x28a 0x0 0x0 0x1 0x28a 0x3e8 0x0>; | |
qcom,bus-vector-names = "MIN", "MAX"; | |
qcom,instance-type = "ufs"; | |
status = "ok"; | |
linux,phandle = <0x80>; | |
phandle = <0x80>; | |
}; | |
ufshc@1da4000 { | |
compatible = "qcom,ufshc"; | |
reg = <0x1da4000 0x2500>; | |
interrupts = <0x0 0x109 0x0>; | |
phys = <0x7f>; | |
phy-names = "ufsphy"; | |
ufs-qcom-crypto = <0x80>; | |
clock-names = "core_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro", "core_clk_ice", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", "rx_lane1_sync_clk"; | |
clocks = <0x38 0x69385b45 0x38 0x873459d8 0x38 0x1914bb84 0x38 0x4a4e0f3d 0x38 0x84e15a5b 0x38 0xb867b147 0x38 0x6a9f747a 0x38 0x7f43251c 0x38 0x3182fde>; | |
freq-table-hz = <0x2faf080 0xbebc200 0x0 0x0 0x0 0x0 0x23c3460 0x8f0d180 0x47868c0 0x11e1a300 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; | |
lanes-per-direction = <0x2>; | |
qcom,msm-bus,name = "ufs1"; | |
qcom,msm-bus,num-cases = <0x16>; | |
qcom,msm-bus,num-paths = <0x2>; | |
qcom,msm-bus,vectors-KBps = <0x5f 0x200 0x0 0x0 0x1 0x28a 0x0 0x0 0x5f 0x200 0x39a 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x734 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0xe68 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x1cd0 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x734 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0xe68 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x1cd0 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x39a0 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x1f334 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x3e667 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x200000 0x0 0x1 0x28a 0x19000 0x0 0x5f 0x200 0x3e667 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x7cccd 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x400000 0x0 0x1 0x28a 0x32000 0x0 0x5f 0x200 0x247ae 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x48ccd 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x200000 0x0 0x1 0x28a 0x19000 0x0 0x5f 0x200 0x48ccd 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x9199a 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x400000 0x0 0x1 0x28a 0x32000 0x0 0x5f 0x200 0x74a000 0x0 0x1 0x28a 0x4b000 0x0>; | |
qcom,bus-vector-names = "MIN", "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "MAX"; | |
qcom,pm-qos-cpu-groups = <0xf 0xf0>; | |
qcom,pm-qos-cpu-group-latency-us = <0x46 0x46>; | |
qcom,pm-qos-default-cpu = <0x0>; | |
pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; | |
pinctrl-0 = <0x81>; | |
pinctrl-1 = <0x82>; | |
resets = <0x38 0x6>; | |
reset-names = "core_reset"; | |
status = "ok"; | |
vdd-hba-supply = <0x7e>; | |
vdd-hba-fixed-regulator; | |
vcc-supply = <0x83>; | |
vccq-supply = <0x7d>; | |
vccq2-supply = <0x3d>; | |
vcc-max-microamp = <0xb71b0>; | |
vccq-max-microamp = <0x88b80>; | |
vccq2-max-microamp = <0xb71b0>; | |
}; | |
ssusb@a800000 { | |
compatible = "qcom,dwc-usb3-msm"; | |
reg = <0xa800000 0xf8c00 0xc016000 0x400>; | |
reg-names = "core_base", "ahb2phy_base"; | |
#address-cells = <0x1>; | |
#size-cells = <0x1>; | |
ranges; | |
interrupts = <0x0 0x15b 0x0 0x0 0xf3 0x0 0x0 0xb4 0x0>; | |
interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq"; | |
USB3_GDSC-supply = <0x84>; | |
qcom,usb-dbm = <0x85>; | |
qcom,msm-bus,name = "usb3"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x3d 0x200 0x0 0x0 0x3d 0x200 0x3a980 0xc3500>; | |
qcom,dwc-usb3-msm-tx-fifo-size = <0x5328>; | |
extcon = <0x86>; | |
clocks = <0x38 0xb3b4e2cb 0x38 0x9ea4c2d9 0x38 0xc5c3fbe8 0x38 0xa800b65a 0x38 0xd0b65c92 0x38 0xf79c19f6>; | |
clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk", "sleep_clk", "xo"; | |
qcom,core-clk-rate = <0x7270e00>; | |
qcom,core-clk-rate-hs = <0x3938700>; | |
resets = <0x38 0x7>; | |
reset-names = "core_reset"; | |
dwc3@a800000 { | |
compatible = "snps,dwc3"; | |
reg = <0xa800000 0xcd00>; | |
interrupt-parent = <0x1>; | |
interrupts = <0x0 0x83 0x0>; | |
usb-phy = <0x30 0x87>; | |
tx-fifo-resize; | |
snps,nominal-elastic-buffer; | |
snps,disable-clk-gating; | |
snps,has-lpm-erratum; | |
snps,hird-threshold = [10]; | |
snps,num-gsi-evt-buffs = <0x3>; | |
maximum-speed = "high-speed"; | |
}; | |
qcom,usbbam@a904000 { | |
compatible = "qcom,usb-bam-msm"; | |
reg = <0xa904000 0x17000>; | |
interrupt-parent = <0x1>; | |
interrupts = <0x0 0x84 0x0>; | |
qcom,bam-type = <0x0>; | |
qcom,usb-bam-fifo-baseaddr = <0x146bb000>; | |
qcom,usb-bam-num-pipes = <0x8>; | |
qcom,ignore-core-reset-ack; | |
qcom,disable-clk-gating; | |
qcom,usb-bam-override-threshold = <0x4001>; | |
qcom,usb-bam-max-mbps-highspeed = <0x190>; | |
qcom,usb-bam-max-mbps-superspeed = <0xe10>; | |
qcom,reset-bam-on-connect; | |
qcom,pipe0 { | |
label = "ssusb-qdss-in-0"; | |
qcom,usb-bam-mem-type = <0x2>; | |
qcom,dir = <0x1>; | |
qcom,pipe-num = <0x0>; | |
qcom,peer-bam = <0x0>; | |
qcom,peer-bam-physical-address = <0x6064000>; | |
qcom,src-bam-pipe-index = <0x0>; | |
qcom,dst-bam-pipe-index = <0x0>; | |
qcom,data-fifo-offset = <0x0>; | |
qcom,data-fifo-size = <0x1800>; | |
qcom,descriptor-fifo-offset = <0x1800>; | |
qcom,descriptor-fifo-size = <0x800>; | |
}; | |
}; | |
}; | |
qusb@c012000 { | |
compatible = "qcom,qusb2phy-v2"; | |
reg = <0xc012000 0x2a8 0x1fcb24c 0x4>; | |
reg-names = "qusb_phy_base", "tcsr_clamp_dig_n_1p8"; | |
vdd-supply = <0x66>; | |
vdda12-supply = <0x67>; | |
vdda18-supply = <0x69>; | |
vdda33-supply = <0x31>; | |
qcom,vdd-voltage-level = <0x0 0xd6d80 0xd6d80>; | |
qcom,vdda33-voltage-level = <0x249f00 0x2f1e80 0x2f1e80>; | |
qcom,qusb-phy-init-seq = <0x80 0x0 0x13 0x4 0x7c 0x18c 0x80 0x2c 0xa 0x184 0xf0 0x23c 0xf 0x240>; | |
phy_type = "utmi"; | |
clocks = <0x38 0xb867b147 0x38 0x53351d25>; | |
clock-names = "ref_clk_src", "ref_clk"; | |
resets = <0x38 0x0>; | |
reset-names = "phy_reset"; | |
qcom,efuse-bit-pos = <0x10>; | |
qcom,efuse-num-bits = <0x4>; | |
linux,phandle = <0x30>; | |
phandle = <0x30>; | |
}; | |
ssphy@c010000 { | |
compatible = "qcom,usb-ssphy-qmp-v2"; | |
reg = <0xc010000 0xe0c 0x1fcb244 0x4 0x1fcb248 0x4>; | |
reg-names = "qmp_phy_base", "vls_clamp_reg", "tcsr_usb3_dp_phymode"; | |
vdd-supply = <0x66>; | |
core-supply = <0x67>; | |
qcom,vdd-voltage-level = <0x0 0xd6d80 0xd6d80>; | |
qcom,vbus-valid-override; | |
qcom,qmp-phy-init-seq = <0x138 0x30 0x0 0x34 0x4 0x1 0x80 0x14 0x0 0x3c 0x6 0x0 0x8c 0x8 0x0 0x15c 0x6 0x0 0x164 0x1 0x0 0x13c 0x80 0x0 0xb0 0x82 0x0 0xb8 0xab 0x0 0xbc 0xea 0x0 0xc0 0x2 0x0 0x60 0x6 0x0 0x68 0x16 0x0 0x70 0x36 0x0 0xdc 0x0 0x0 0xd8 0x3f 0x0 0xf8 0x1 0x0 0xf4 0xc9 0x0 0x148 0xa 0x0 0xa0 0x0 0x0 0x9c 0x34 0x0 0x98 0x15 0x0 0x90 0x4 0x0 0x154 0x0 0x0 0x94 0x0 0x0 0xf0 0x0 0x0 0xc 0xa 0x0 0x48 0x7 0x0 0xd0 0x80 0x0 0x184 0x1 0x0 0x10 0x1 0x0 0x1c 0x31 0x0 0x20 0x1 0x0 0x14 0x0 0x0 0x18 0x0 0x0 0x24 0x85 0x0 0x28 0x7 0x0 0x430 0xb 0x0 0x4d4 0xf 0x0 0x4d8 0x4e 0x0 0x4dc 0x18 0x0 0x4f8 0x7 0x0 0x4fc 0x80 0x0 0x504 0x43 0x0 0x50c 0x1c 0x0 0x434 0x75 0x0 0x43c 0x0 0x0 0x440 0x0 0x0 0x444 0x80 0x0 0x408 0xa 0x0 0x414 0x6 0x0 0x500 0x0 0x0 0x4c0 0x3 0x0 0x564 0x5 0x0 0x830 0xb 0x0 0x8d4 0xf 0x0 0x8d8 0x4e 0x0 0x8dc 0x18 0x0 0x8f8 0x7 0x0 0x8fc 0x80 0x0 0x904 0x43 0x0 0x90c 0x1c 0x0 0x834 0x75 0x0 0x83c 0x0 0x0 0x840 0x0 0x0 0x844 0x80 0x0 0x808 0xa 0x0 0x814 0x6 0x0 0x900 0x0 0x0 0x8c0 0x3 0x0 0x964 0x5 0x0 0x260 0x10 0x0 0x2a4 0x12 0x0 0x28c 0x16 0x0 0x244 0x0 0x0 0x660 0x10 0x0 0x6a4 0x12 0x0 0x68c 0x16 0x0 0x644 0x0 0x0 0xcc8 0x83 0x0 0xccc 0x9 0x0 0xcd0 0xa2 0x0 0xcd4 0x40 0x0 0xcc4 0x2 0x0 0xc80 0xd1 0x0 0xc84 0x1f 0x0 0xc88 0x47 0x0 0xc64 0x1b 0x0 0xc0c 0x9f 0x0 0xc10 0x9f 0x0 0xc14 0xb7 0x0 0xc18 0x4e 0x0 0xc1c 0x65 0x0 0xc20 0x6b 0x0 0xc24 0x15 0x0 0xc28 0xd 0x0 0xc2c 0x15 0x0 0xc30 0xd 0x0 0xc34 0x15 0x0 0xc38 0xd 0x0 0xc3c 0x15 0x0 0xc40 0xd 0x0 0xc44 0x15 0x0 0xc48 0xd 0x0 0xc4c 0x15 0x0 0xc50 0xd 0x0 0xc5c 0x2 0x0 0xca0 0x4 0x0 0xc8c 0x44 0x0 0xc70 0xe7 0x0 0xc74 0x3 0x0 0xc78 0x40 0x0 0xc7c 0x0 0x0 0xdd8 0x8a 0x0 0xcb8 0x75 0x0 0xcb0 0x86 0x0 0xcbc 0x13 0x0 0xffffffff 0xffffffff 0x0>; | |
qcom,qmp-phy-reg-offset = <0xd74 0xcd8 0xcdc 0xc04 0xc00 0xc08 0xa00>; | |
clocks = <0x38 0xd9a36e0 0x38 0xf279aff2 0x38 0xb867b147 0x38 0xb6cc8f00>; | |
clock-names = "aux_clk", "pipe_clk", "ref_clk_src", "ref_clk"; | |
resets = <0x38 0x8 0x38 0x9>; | |
reset-names = "phy_reset", "phy_phy_reset"; | |
linux,phandle = <0x87>; | |
phandle = <0x87>; | |
}; | |
usb_audio_qmi_dev { | |
compatible = "qcom,usb-audio-qmi-dev"; | |
iommus = <0x65 0xc>; | |
qcom,usb-audio-stream-id = <0xc>; | |
qcom,usb-audio-intr-num = <0x2>; | |
}; | |
dbm@a8f8000 { | |
compatible = "qcom,usb-dbm-1p5"; | |
reg = <0xa8f8000 0x300>; | |
qcom,reset-ep-after-lpm-resume; | |
linux,phandle = <0x85>; | |
phandle = <0x85>; | |
}; | |
usb_nop_phy { | |
compatible = "usb-nop-xceiv"; | |
}; | |
qcom,lpass@17300000 { | |
compatible = "qcom,pil-tz-generic"; | |
reg = <0x17300000 0x100>; | |
interrupts = <0x0 0xa2 0x1>; | |
vdd_cx-supply = <0x56>; | |
qcom,proxy-reg-names = "vdd_cx"; | |
qcom,vdd_cx-uV-uA = <0x180 0x186a0>; | |
clocks = <0x38 0xe17f0ff6>; | |
clock-names = "xo"; | |
qcom,proxy-clock-names = "xo"; | |
qcom,pas-id = <0x1>; | |
qcom,proxy-timeout-ms = <0x2710>; | |
qcom,smem-id = <0x1a7>; | |
qcom,sysmon-id = <0x1>; | |
status = "ok"; | |
qcom,ssctl-instance-id = <0x14>; | |
qcom,firmware-name = "adsp"; | |
memory-region = <0x88>; | |
qcom,gpio-err-fatal = <0x89 0x0 0x0>; | |
qcom,gpio-proxy-unvote = <0x89 0x2 0x0>; | |
qcom,gpio-err-ready = <0x89 0x1 0x0>; | |
qcom,gpio-stop-ack = <0x89 0x3 0x0>; | |
qcom,gpio-force-stop = <0x8a 0x0 0x0>; | |
}; | |
qcom,memshare { | |
compatible = "qcom,memshare"; | |
qcom,client_1 { | |
compatible = "qcom,memshare-peripheral"; | |
qcom,peripheral-size = <0x200000>; | |
qcom,client-id = <0x0>; | |
qcom,allocate-boot-time; | |
label = "modem"; | |
}; | |
qcom,client_2 { | |
compatible = "qcom,memshare-peripheral"; | |
qcom,peripheral-size = <0x300000>; | |
qcom,client-id = <0x2>; | |
label = "modem"; | |
}; | |
qcom,client_3 { | |
compatible = "qcom,memshare-peripheral"; | |
qcom,peripheral-size = <0x500000>; | |
qcom,client-id = <0x1>; | |
label = "modem"; | |
}; | |
}; | |
qcom,mss@4080000 { | |
compatible = "qcom,pil-q6v55-mss"; | |
reg = <0x4080000 0x100 0x1f63000 0x8 0x1f65000 0x8 0x1f64000 0x8 0x4180000 0x20 0x179000 0x4>; | |
reg-names = "qdsp6_base", "halt_q6", "halt_modem", "halt_nc", "rmb_base", "restart_reg"; | |
clocks = <0x38 0x79e95308 0x38 0x111cde81 0x38 0x7437988f 0x38 0xde2adeb1 0x38 0x7d794829 0x38 0xe71de85 0x38 0xf665d03f 0x38 0x1492202a>; | |
clock-names = "xo", "iface_clk", "bus_clk", "mem_clk", "gpll0_mss_clk", "snoc_axi_clk", "mnoc_axi_clk", "qdss_clk"; | |
qcom,proxy-clock-names = "xo", "qdss_clk", "mem_clk"; | |
qcom,active-clock-names = "iface_clk", "bus_clk", "gpll0_mss_clk", "snoc_axi_clk", "mnoc_axi_clk"; | |
interrupts = <0x0 0x1c0 0x1>; | |
vdd_cx-supply = <0x56>; | |
vdd_cx-voltage = <0x180>; | |
vdd_mx-supply = <0x58>; | |
vdd_mx-uV = <0x180>; | |
qcom,firmware-name = "modem"; | |
qcom,pil-self-auth; | |
qcom,sysmon-id = <0x0>; | |
qcom,ssctl-instance-id = <0x12>; | |
qcom,qdsp6v62-1-2; | |
status = "ok"; | |
memory-region = <0x8b>; | |
qcom,mem-protect-id = <0xf>; | |
qcom,gpio-err-fatal = <0x8c 0x0 0x0>; | |
qcom,gpio-err-ready = <0x8c 0x1 0x0>; | |
qcom,gpio-proxy-unvote = <0x8c 0x2 0x0>; | |
qcom,gpio-stop-ack = <0x8c 0x3 0x0>; | |
qcom,gpio-shutdown-ack = <0x8c 0x7 0x0>; | |
qcom,gpio-force-stop = <0x8d 0x0 0x0>; | |
qcom,mba-mem@0 { | |
compatible = "qcom,pil-mba-mem"; | |
memory-region = <0x8e>; | |
}; | |
}; | |
tsens@10aa000 { | |
compatible = "qcom,msm8998-tsens"; | |
reg = <0x10aa000 0x2000>; | |
reg-names = "tsens_physical"; | |
interrupts = <0x0 0x1ca 0x0 0x0 0x1bd 0x0>; | |
interrupt-names = "tsens-upper-lower", "tsens-critical"; | |
qcom,client-id = <0x0 0x1 0x2 0x3 0x4 0x7 0x8 0x9 0xa 0xb 0xc 0xd>; | |
qcom,sensor-id = <0x0 0x1 0x2 0x3 0x4 0x7 0x8 0x9 0xa 0xb 0xc 0xd>; | |
qcom,sensors = <0xc>; | |
}; | |
tsens@10ad000 { | |
compatible = "qcom,msm8998-tsens"; | |
reg = <0x10ad000 0x2000>; | |
reg-names = "tsens_physical"; | |
interrupts = <0x0 0xb8 0x0 0x0 0x1ae 0x0>; | |
interrupt-names = "tsens-upper-lower", "tsens-critical"; | |
qcom,client-id = <0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15>; | |
qcom,sensor-id = <0x0 0x1 0x3 0x4 0x5 0x6 0x7 0x2>; | |
qcom,sensors = <0x8>; | |
}; | |
qcom,qbt1000 { | |
compatible = "qcom,qbt1000"; | |
clock-names = "core", "iface"; | |
clocks = <0x38 0xfe1bd34a 0x38 0x8f283c1d>; | |
clock-frequency = <0xe4e1c0>; | |
qcom,ipc-gpio = <0x7c 0x79 0x0>; | |
qcom,finger-detect-gpio = <0x8f 0x2 0x0>; | |
}; | |
qcom,sensor-information { | |
compatible = "qcom,sensor-information"; | |
qcom,sensor-information-0 { | |
qcom,sensor-type = "tsens"; | |
qcom,sensor-name = "tsens_tz_sensor0"; | |
qcom,scaling-factor = <0xa>; | |
}; | |
qcom,sensor-information-1 { | |
qcom,sensor-type = "tsens"; | |
qcom,sensor-name = "tsens_tz_sensor1"; | |
qcom,scaling-factor = <0xa>; | |
linux,phandle = <0x90>; | |
phandle = <0x90>; | |
}; | |
qcom,sensor-information-2 { | |
qcom,sensor-type = "tsens"; | |
qcom,sensor-name = "tsens_tz_sensor2"; | |
qcom,scaling-factor = <0xa>; | |
linux,phandle = <0x91>; | |
phandle = <0x91>; | |
}; | |
qcom,sensor-information-3 { | |
qcom,sensor-type = "tsens"; | |
qcom,sensor-name = "tsens_tz_sensor3"; | |
qcom,scaling-factor = <0xa>; | |
linux,phandle = <0x92>; | |
phandle = <0x92>; | |
}; | |
qcom,sensor-information-4 { | |
qcom,sensor-type = "tsens"; | |
qcom,sensor-name = "tsens_tz_sensor4"; | |
qcom,scaling-factor = <0xa>; | |
linux,phandle = <0x93>; | |
phandle = <0x93>; | |
}; | |
qcom,sensor-information-7 { | |
qcom,sensor-type = "tsens"; | |
qcom,sensor-name = "tsens_tz_sensor7"; | |
qcom,scaling-factor = <0xa>; | |
linux,phandle = <0x94>; | |
phandle = <0x94>; | |
}; | |
qcom,sensor-information-8 { | |
qcom,sensor-type = "tsens"; | |
qcom,sensor-name = "tsens_tz_sensor8"; | |
qcom,scaling-factor = <0xa>; | |
linux,phandle = <0x95>; | |
phandle = <0x95>; | |
}; | |
qcom,sensor-information-9 { | |
qcom,sensor-type = "tsens"; | |
qcom,sensor-name = "tsens_tz_sensor9"; | |
qcom,scaling-factor = <0xa>; | |
linux,phandle = <0x96>; | |
phandle = <0x96>; | |
}; | |
qcom,sensor-information-10 { | |
qcom,sensor-type = "tsens"; | |
qcom,sensor-name = "tsens_tz_sensor10"; | |
qcom,scaling-factor = <0xa>; | |
linux,phandle = <0x97>; | |
phandle = <0x97>; | |
}; | |
qcom,sensor-information-11 { | |
qcom,sensor-type = "tsens"; | |
qcom,sensor-name = "tsens_tz_sensor11"; | |
qcom,scaling-factor = <0xa>; | |
}; | |
qcom,sensor-information-12 { | |
qcom,sensor-type = "tsens"; | |
qcom,sensor-name = "tsens_tz_sensor12"; | |
qcom,scaling-factor = <0xa>; | |
qcom,alias-name = "gpu_1"; | |
}; | |
qcom,sensor-information-13 { | |
qcom,sensor-type = "tsens"; | |
qcom,sensor-name = "tsens_tz_sensor13"; | |
qcom,scaling-factor = <0xa>; | |
qcom,alias-name = "gpu"; | |
}; | |
qcom,sensor-information-14 { | |
qcom,sensor-type = "tsens"; | |
qcom,sensor-name = "tsens_tz_sensor14"; | |
qcom,scaling-factor = <0xa>; | |
}; | |
qcom,sensor-information-15 { | |
qcom,sensor-type = "tsens"; | |
qcom,sensor-name = "tsens_tz_sensor15"; | |
qcom,scaling-factor = <0xa>; | |
qcom,alias-name = "modem_dsp"; | |
}; | |
qcom,sensor-information-16 { | |
qcom,sensor-type = "tsens"; | |
qcom,sensor-name = "tsens_tz_sensor16"; | |
qcom,scaling-factor = <0xa>; | |
}; | |
qcom,sensor-information-17 { | |
qcom,sensor-type = "tsens"; | |
qcom,sensor-name = "tsens_tz_sensor17"; | |
qcom,scaling-factor = <0xa>; | |
qcom,alias-name = "hvx"; | |
}; | |
qcom,sensor-information-18 { | |
qcom,sensor-type = "tsens"; | |
qcom,sensor-name = "tsens_tz_sensor18"; | |
qcom,scaling-factor = <0xa>; | |
qcom,alias-name = "camera"; | |
}; | |
qcom,sensor-information-19 { | |
qcom,sensor-type = "tsens"; | |
qcom,sensor-name = "tsens_tz_sensor19"; | |
qcom,scaling-factor = <0xa>; | |
qcom,alias-name = "multi_media_ss"; | |
}; | |
qcom,sensor-information-20 { | |
qcom,sensor-type = "tsens"; | |
qcom,sensor-name = "tsens_tz_sensor20"; | |
qcom,scaling-factor = <0xa>; | |
qcom,alias-name = "modem"; | |
}; | |
qcom,sensor-information-21 { | |
qcom,sensor-type = "tsens"; | |
qcom,sensor-name = "tsens_tz_sensor21"; | |
qcom,scaling-factor = <0xa>; | |
qcom,alias-name = "pop_mem"; | |
}; | |
qcom,sensor-information-22 { | |
qcom,sensor-type = "alarm"; | |
qcom,sensor-name = "pm8998_tz"; | |
qcom,scaling-factor = <0x3e8>; | |
}; | |
qcom,sensor-information-23 { | |
qcom,sensor-type = "adc"; | |
qcom,sensor-name = "msm_therm"; | |
}; | |
qcom,sensor-information-24 { | |
qcom,sensor-type = "adc"; | |
qcom,sensor-name = "emmc_therm"; | |
}; | |
qcom,sensor-information-25 { | |
qcom,sensor-type = "adc"; | |
qcom,sensor-name = "pa_therm0"; | |
}; | |
qcom,sensor-information-26 { | |
qcom,sensor-type = "adc"; | |
qcom,sensor-name = "pa_therm1"; | |
}; | |
qcom,sensor-information-27 { | |
qcom,sensor-type = "adc"; | |
qcom,sensor-name = "quiet_therm"; | |
}; | |
qcom,sensor-information-28 { | |
qcom,sensor-type = "adc"; | |
qcom,sensor-name = "xo_therm"; | |
}; | |
qcom,sensor-information-29 { | |
qcom,sensor-type = "llm"; | |
qcom,sensor-name = "limits_sensor-01"; | |
}; | |
qcom,sensor-information-30 { | |
qcom,sensor-type = "llm"; | |
qcom,sensor-name = "limits_sensor-02"; | |
}; | |
}; | |
qseecom@86600000 { | |
compatible = "qcom,qseecom"; | |
reg = <0x86600000 0x2200000>; | |
reg-names = "secapp-region"; | |
qcom,hlos-num-ce-hw-instances = <0x1>; | |
qcom,hlos-ce-hw-instance = <0x0>; | |
qcom,qsee-ce-hw-instance = <0x0>; | |
qcom,disk-encrypt-pipe-pair = <0x2>; | |
qcom,support-fde; | |
qcom,no-clock-support; | |
qcom,appsbl-qseecom-support; | |
qcom,fde-key-size; | |
qcom,commonlib64-loaded-by-uefi; | |
qcom,msm-bus,name = "qseecom-noc"; | |
qcom,msm-bus,num-cases = <0x4>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x37 0x200 0x0 0x0 0x37 0x200 0x0 0x0 0x37 0x200 0x1d4c0 0x124f80 0x37 0x200 0x60180 0x3c0f00>; | |
clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; | |
clocks = <0x38 0x42229c55 0x38 0xaa858373 0x38 0x2eb28c01 0x38 0xc174dfba>; | |
qcom,ce-opp-freq = <0xa37d070>; | |
qcom,qsee-reentrancy-support = <0x2>; | |
}; | |
tz-log@146BF720 { | |
compatible = "qcom,tz-log"; | |
reg = <0x146bf720 0x3000>; | |
qcom,hyplog-enabled; | |
hyplog-address-offset = <0x410>; | |
hyplog-size-offset = <0x414>; | |
}; | |
qcom,msm_hdcp { | |
compatible = "qcom,msm-hdcp"; | |
}; | |
qcrypto@1DE0000 { | |
compatible = "qcom,qcrypto"; | |
reg = <0x1de0000 0x20000 0x1dc4000 0x24000>; | |
reg-names = "crypto-base", "crypto-bam-base"; | |
interrupts = <0x0 0xce 0x0>; | |
qcom,bam-pipe-pair = <0x2>; | |
qcom,ce-hw-instance = <0x0>; | |
qcom,ce-device = <0x0>; | |
qcom,bam-ee = <0x0>; | |
qcom,ce-hw-shared; | |
qcom,clk-mgmt-sus-res; | |
qcom,msm-bus,name = "qcrypto-noc"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x37 0x200 0x0 0x0 0x37 0x200 0x3c0f00 0x60180>; | |
clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; | |
clocks = <0x38 0xa6ac14df 0x38 0xa6ac14df 0x38 0x2eb28c01 0x38 0xc174dfba>; | |
qcom,ce-opp-freq = <0xa37d070>; | |
qcom,use-sw-aes-cbc-ecb-ctr-algo; | |
qcom,use-sw-aes-xts-algo; | |
qcom,use-sw-aes-ccm-algo; | |
qcom,use-sw-ahash-algo; | |
qcom,use-sw-aead-algo; | |
qcom,use-sw-hmac-algo; | |
}; | |
qcedev@1DE0000 { | |
compatible = "qcom,qcedev"; | |
reg = <0x1de0000 0x20000 0x1dc4000 0x24000>; | |
reg-names = "crypto-base", "crypto-bam-base"; | |
interrupts = <0x0 0xce 0x0>; | |
qcom,bam-pipe-pair = <0x1>; | |
qcom,ce-hw-instance = <0x0>; | |
qcom,ce-device = <0x0>; | |
qcom,ce-hw-shared; | |
qcom,bam-ee = <0x0>; | |
qcom,msm-bus,name = "qcedev-noc"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x37 0x200 0x0 0x0 0x37 0x200 0x3c0f00 0x60180>; | |
clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; | |
clocks = <0x38 0x293f97b0 0x38 0x293f97b0 0x38 0x2eb28c01 0x38 0xc174dfba>; | |
qcom,ce-opp-freq = <0xa37d070>; | |
}; | |
qrng@793000 { | |
compatible = "qcom,msm-rng"; | |
reg = <0x793000 0x1000>; | |
qcom,msm-rng-iface-clk; | |
qcom,no-qrng-config; | |
qcom,msm-bus,name = "msm-rng-noc"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x1 0x26a 0x0 0x0 0x1 0x26a 0x0 0x320>; | |
clocks = <0x38 0x397e7eaa>; | |
clock-names = "iface_clk"; | |
}; | |
qcom,limit_info-0 { | |
qcom,temperature-sensor = <0x90>; | |
qcom,hotplug-mitigation-enable; | |
linux,phandle = <0x2>; | |
phandle = <0x2>; | |
}; | |
qcom,limit_info-1 { | |
qcom,temperature-sensor = <0x91>; | |
qcom,hotplug-mitigation-enable; | |
linux,phandle = <0x6>; | |
phandle = <0x6>; | |
}; | |
qcom,limit_info-2 { | |
qcom,temperature-sensor = <0x92>; | |
qcom,hotplug-mitigation-enable; | |
linux,phandle = <0x8>; | |
phandle = <0x8>; | |
}; | |
qcom,limit_info-3 { | |
qcom,temperature-sensor = <0x93>; | |
qcom,hotplug-mitigation-enable; | |
linux,phandle = <0xa>; | |
phandle = <0xa>; | |
}; | |
qcom,limit_info-4 { | |
qcom,temperature-sensor = <0x94>; | |
qcom,hotplug-mitigation-enable; | |
linux,phandle = <0xc>; | |
phandle = <0xc>; | |
}; | |
qcom,limit_info-5 { | |
qcom,temperature-sensor = <0x95>; | |
qcom,hotplug-mitigation-enable; | |
linux,phandle = <0x10>; | |
phandle = <0x10>; | |
}; | |
qcom,limit_info-6 { | |
qcom,temperature-sensor = <0x96>; | |
qcom,hotplug-mitigation-enable; | |
linux,phandle = <0x12>; | |
phandle = <0x12>; | |
}; | |
qcom,limit_info-7 { | |
qcom,temperature-sensor = <0x97>; | |
qcom,hotplug-mitigation-enable; | |
linux,phandle = <0x14>; | |
phandle = <0x14>; | |
}; | |
qcom,lmh { | |
compatible = "qcom,lmh_v1"; | |
interrupts = <0x0 0x86 0x4>; | |
}; | |
qcom,msm-thermal { | |
compatible = "qcom,msm-thermal"; | |
qcom,sensor-id = <0x1>; | |
qcom,poll-ms = <0x64>; | |
qcom,therm-reset-temp = <0x73>; | |
qcom,core-limit-temp = <0x46>; | |
qcom,core-temp-hysteresis = <0xa>; | |
qcom,hotplug-temp = <0x69>; | |
qcom,hotplug-temp-hysteresis = <0x14>; | |
qcom,online-hotplug-core; | |
qcom,synchronous-cluster-id = <0x0 0x1>; | |
qcom,synchronous-cluster-map = <0x0 0x4 0x16 0x17 0x18 0x19 0x1 0x4 0x1a 0x1b 0x1c 0x1d>; | |
clock-names = "osm"; | |
clocks = <0x55 0xc554130e>; | |
qcom,vdd-restriction-temp = <0x5>; | |
qcom,vdd-restriction-temp-hysteresis = <0xa>; | |
vdd-dig-supply = <0x98>; | |
vdd-gfx-supply = <0x2c>; | |
qcom,vdd-dig-rstr { | |
qcom,vdd-rstr-reg = "vdd-dig"; | |
qcom,levels = <0x100 0x180 0x180>; | |
qcom,min-level = <0x0>; | |
}; | |
qcom,vdd-gfx-rstr { | |
qcom,vdd-rstr-reg = "vdd-gfx"; | |
qcom,levels = <0x5 0x6 0x6>; | |
qcom,min-level = <0x1>; | |
}; | |
qcom,vdd-apps-rstr { | |
qcom,vdd-rstr-reg = "vdd-apps"; | |
qcom,levels = <0x130b00>; | |
qcom,freq-req; | |
linux,phandle = <0xa0>; | |
phandle = <0xa0>; | |
}; | |
}; | |
qcom,pcie@01c00000 { | |
compatible = "qcom,pci-msm"; | |
cell-index = <0x0>; | |
reg = <0x1c00000 0x2000 0x1c06000 0x1000 0x1b000000 0xf1d 0x1b000f20 0xa8 0x1b100000 0x100000 0x1b200000 0x100000 0x1b300000 0xd00000>; | |
reg-names = "parf", "phy", "dm_core", "elbi", "conf", "io", "bars"; | |
#address-cells = <0x3>; | |
#size-cells = <0x2>; | |
ranges = <0x1000000 0x0 0x1b200000 0x1b200000 0x0 0x100000 0x2000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; | |
interrupt-parent = <0x99>; | |
interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25>; | |
#interrupt-cells = <0x1>; | |
interrupt-map-mask = <0x0 0x0 0x0 0xffffffff>; | |
interrupt-map = <0x0 0x0 0x0 0x0 0x1 0x0 0x0 0x195 0x0 0x0 0x0 0x0 0x1 0x1 0x0 0x0 0x87 0x0 0x0 0x0 0x0 0x2 0x1 0x0 0x0 0x88 0x0 0x0 0x0 0x0 0x3 0x1 0x0 0x0 0x8a 0x0 0x0 0x0 0x0 0x4 0x1 0x0 0x0 0x8b 0x0 0x0 0x0 0x0 0x5 0x1 0x0 0x0 0x116 0x0 0x0 0x0 0x0 0x6 0x1 0x0 0x0 0x240 0x0 0x0 0x0 0x0 0x7 0x1 0x0 0x0 0x241 0x0 0x0 0x0 0x0 0x8 0x1 0x0 0x0 0x242 0x0 0x0 0x0 0x0 0x9 0x1 0x0 0x0 0x243 0x0 0x0 0x0 0x0 0xa 0x1 0x0 0x0 0x244 0x0 0x0 0x0 0x0 0xb 0x1 0x0 0x0 0x245 0x0 0x0 0x0 0x0 0xc 0x1 0x0 0x0 0x246 0x0 0x0 0x0 0x0 0xd 0x1 0x0 0x0 0x247 0x0 0x0 0x0 0x0 0xe 0x1 0x0 0x0 0x248 0x0 0x0 0x0 0x0 0xf 0x1 0x0 0x0 0x249 0x0 0x0 0x0 0x0 0x10 0x1 0x0 0x0 0x24a 0x0 0x0 0x0 0x0 0x11 0x1 0x0 0x0 0x24b 0x0 0x0 0x0 0x0 0x12 0x1 0x0 0x0 0x24c 0x0 0x0 0x0 0x0 0x13 0x1 0x0 0x0 0x24d 0x0 0x0 0x0 0x0 0x14 0x1 0x0 0x0 0x24e 0x0 0x0 0x0 0x0 0x15 0x1 0x0 0x0 0x24f 0x0 0x0 0x0 0x0 0x16 0x1 0x0 0x0 0x250 0x0 0x0 0x0 0x0 0x17 0x1 0x0 0x0 0x251 0x0 0x0 0x0 0x0 0x18 0x1 0x0 0x0 0x252 0x0 0x0 0x0 0x0 0x19 0x1 0x0 0x0 0x253 0x0 0x0 0x0 0x0 0x1a 0x1 0x0 0x0 0x254 0x0 0x0 0x0 0x0 0x1b 0x1 0x0 0x0 0x255 0x0 0x0 0x0 0x0 0x1c 0x1 0x0 0x0 0x256 0x0 0x0 0x0 0x0 0x1d 0x1 0x0 0x0 0x257 0x0 0x0 0x0 0x0 0x1e 0x1 0x0 0x0 0x258 0x0 0x0 0x0 0x0 0x1f 0x1 0x0 0x0 0x259 0x0 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x25a 0x0 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x25b 0x0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x25c 0x0 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x25d 0x0 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x25e 0x0 0x0 0x0 0x0 0x25 0x1 0x0 0x0 0x25f 0x0>; | |
interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d", "int_global_int", "msi_0", "msi_1", "msi_2", "msi_3", "msi_4", "msi_5", "msi_6", "msi_7", "msi_8", "msi_9", "msi_10", "msi_11", "msi_12", "msi_13", "msi_14", "msi_15", "msi_16", "msi_17", "msi_18", "msi_19", "msi_20", "msi_21", "msi_22", "msi_23", "msi_24", "msi_25", "msi_26", "msi_27", "msi_28", "msi_29", "msi_30", "msi_31"; | |
qcom,phy-sequence = <0x804 0x1 0x0 0x34 0x14 0x0 0x138 0x30 0x0 0x48 0xf 0x0 0x15c 0x6 0x0 0x90 0x1 0x0 0x88 0x20 0x0 0xf0 0x0 0x0 0xf8 0x1 0x0 0xf4 0xc9 0x0 0x11c 0xff 0x0 0x120 0x3f 0x0 0x164 0x1 0x0 0x154 0x0 0x0 0x148 0xa 0x0 0x5c 0x19 0x0 0x38 0x90 0x0 0xb0 0x82 0x0 0xc0 0x3 0x0 0xbc 0x55 0x0 0xb8 0x55 0x0 0xa0 0x0 0x0 0x9c 0xd 0x0 0x98 0x4 0x0 0x13c 0x0 0x0 0x60 0x8 0x0 0x68 0x16 0x0 0x70 0x34 0x0 0x15c 0x6 0x0 0x138 0x33 0x0 0x3c 0x2 0x0 0x40 0x7 0x0 0x80 0x4 0x0 0xdc 0x0 0x0 0xd8 0x3f 0x0 0xc 0x9 0x0 0x10 0x1 0x0 0x1c 0x40 0x0 0x20 0x1 0x0 0x14 0x2 0x0 0x18 0x0 0x0 0x24 0x7e 0x0 0x28 0x15 0x0 0x244 0x2 0x0 0x2a4 0x12 0x0 0x260 0x10 0x0 0x28c 0x6 0x0 0x504 0x3 0x0 0x500 0x1c 0x0 0x50c 0x14 0x0 0x4d4 0xa 0x0 0x4d8 0x4 0x0 0x4dc 0x1a 0x0 0x434 0x4b 0x0 0x414 0x4 0x0 0x40c 0x4 0x0 0x4f8 0x0 0x0 0x4fc 0x80 0x0 0x51c 0x40 0x0 0x444 0x71 0x0 0x43c 0x40 0x0 0x854 0x4 0x0 0x62c 0x52 0x0 0x9ac 0x0 0x0 0x8a0 0x1 0x0 0x9e0 0x0 0x0 0x9dc 0x20 0x0 0x9a8 0x0 0x0 0x8a4 0x1 0x0 0x8a8 0x73 0x0 0x9d8 0x99 0x0 0x9b0 0x3 0x0 0x804 0x3 0x0 0x800 0x0 0x0 0x808 0x3 0x0>; | |
pinctrl-names = "default", "sleep"; | |
pinctrl-0 = <0x9a 0x9b 0x9c>; | |
pinctrl-1 = <0x9a 0x9b 0x9d>; | |
perst-gpio = <0x7c 0x23 0x0>; | |
wake-gpio = <0x7c 0x25 0x0>; | |
gdsc-vdd-supply = <0x9e>; | |
vreg-1.8-supply = <0x67>; | |
vreg-0.9-supply = <0x66>; | |
vreg-cx-supply = <0x56>; | |
qcom,vreg-1.8-voltage-level = <0x124f80 0x124f80 0x5dc0>; | |
qcom,vreg-0.9-voltage-level = <0xd6d80 0xd6d80 0x5dc0>; | |
qcom,vreg-cx-voltage-level = <0x200 0x80 0x0>; | |
qcom,l1-supported; | |
qcom,l1ss-supported; | |
qcom,aux-clk-sync; | |
qcom,ep-latency = <0xa>; | |
qcom,boot-option = <0x1>; | |
linux,pci-domain = <0x0>; | |
qcom,msi-gicm-addr = <0x17a00040>; | |
qcom,msi-gicm-base = <0x260>; | |
qcom,pcie-phy-ver = <0x20>; | |
qcom,use-19p2mhz-aux-clk; | |
iommus = <0x9f>; | |
qcom,smmu-exist; | |
qcom,smmu-sid-base = <0x1480>; | |
qcom,msm-bus,name = "pcie0"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x2d 0x200 0x0 0x0 0x2d 0x200 0x1f4 0x320>; | |
clocks = <0x38 0x4f37621e 0x38 0xb867b147 0x38 0x3d2e3ece 0x38 0x4dd325c3 0x38 0x3f85285b 0x38 0xd69638a1 0x38 0xa2e247fa>; | |
clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", "pcie_0_ldo"; | |
max-clock-frequency-hz = <0x0 0x0 0x124f800 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; | |
resets = <0x38 0xb 0x38 0xa 0x38 0xa>; | |
reset-names = "pcie_phy_reset", "pcie_0_phy_reset", "pcie_0_phy_pipe_reset"; | |
status = "disabled"; | |
linux,phandle = <0x99>; | |
phandle = <0x99>; | |
}; | |
qcom,bcl { | |
compatible = "qcom,bcl"; | |
qcom,bcl-enable; | |
qcom,bcl-framework-interface; | |
qcom,bcl-freq-control-list = <0x1a 0x1b 0x1c 0x1d>; | |
qcom,bcl-hotplug-list = <0x1a 0x1b 0x1c 0x1d>; | |
qcom,bcl-soc-hotplug-list = <0x1a 0x1b 0x1c 0x1d>; | |
qcom,ibat-monitor { | |
qcom,low-threshold-uamp = <0x33e140>; | |
qcom,high-threshold-uamp = <0x401640>; | |
qcom,mitigation-freq-khz = <0x8ca00>; | |
qcom,vph-high-threshold-uv = <0x3567e0>; | |
qcom,vph-low-threshold-uv = <0x325aa0>; | |
qcom,soc-low-threshold = <0xa>; | |
qcom,thermal-handle = <0xa0>; | |
}; | |
}; | |
qcom,ssc@5c00000 { | |
compatible = "qcom,pil-tz-generic"; | |
reg = <0x5c00000 0x4000>; | |
interrupts = <0x0 0x186 0x1>; | |
vdd_cx-supply = <0xa1>; | |
vdd_px-supply = <0xa2>; | |
qcom,vdd_cx-uV-uA = <0x180 0x0>; | |
qcom,proxy-reg-names = "vdd_cx", "vdd_px"; | |
qcom,keep-proxy-regs-on; | |
clocks = <0x38 0x81832015 0x38 0xaa681404>; | |
clock-names = "xo", "aggre2"; | |
qcom,proxy-clock-names = "xo", "aggre2"; | |
qcom,pas-id = <0xc>; | |
qcom,proxy-timeout-ms = <0x2710>; | |
qcom,smem-id = <0x1a8>; | |
qcom,sysmon-id = <0x3>; | |
qcom,ssctl-instance-id = <0x16>; | |
qcom,firmware-name = "slpi"; | |
status = "ok"; | |
memory-region = <0xa3>; | |
qcom,gpio-err-fatal = <0xa4 0x0 0x0>; | |
qcom,gpio-proxy-unvote = <0xa4 0x2 0x0>; | |
qcom,gpio-err-ready = <0xa4 0x1 0x0>; | |
qcom,gpio-stop-ack = <0xa4 0x3 0x0>; | |
qcom,gpio-force-stop = <0xa5 0x0 0x0>; | |
}; | |
qcom,venus@cce0000 { | |
compatible = "qcom,pil-tz-generic"; | |
reg = <0xcce0000 0x4000>; | |
vdd-supply = <0xa6>; | |
qcom,proxy-reg-names = "vdd"; | |
clocks = <0x27 0x78f14c85 0x27 0x49a394f4 0x27 0x94334ae9 0x38 0xdb4b31e6 0x27 0xf3178ba5 0x27 0x1785ef88>; | |
clock-names = "core_clk", "mnoc_ahb_clk", "iface_clk", "noc_axi_clk", "bus_clk", "maxi_clk"; | |
qcom,proxy-clock-names = "core_clk", "mnoc_ahb_clk", "iface_clk", "noc_axi_clk", "bus_clk", "maxi_clk"; | |
qcom,pas-id = <0x9>; | |
qcom,msm-bus,name = "pil-venus"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x3f 0x200 0x0 0x0 0x3f 0x200 0x0 0x4a380>; | |
qcom,proxy-timeout-ms = <0x64>; | |
qcom,firmware-name = "venus"; | |
memory-region = <0xa7>; | |
status = "ok"; | |
}; | |
qcom,wdt@17817000 { | |
compatible = "qcom,msm-watchdog"; | |
reg = <0x17817000 0x1000>; | |
reg-names = "wdt-base"; | |
interrupts = <0x0 0x3 0x0 0x0 0x4 0x0>; | |
qcom,bark-time = <0x4e20>; | |
qcom,pet-time = <0x3a98>; | |
qcom,ipi-ping; | |
qcom,wakeup-enable; | |
qcom,scandump-size = <0x40000>; | |
}; | |
qcom,spss@1d00000 { | |
compatible = "qcom,pil-tz-generic"; | |
reg = <0x1d0101c 0x4 0x1d01024 0x4 0x1d01028 0x4 0x1d0103c 0x4 0x1d02030 0x4>; | |
reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2"; | |
interrupts = <0x0 0x160 0x1>; | |
vdd_cx-supply = <0x56>; | |
qcom,proxy-reg-names = "vdd_cx"; | |
qcom,vdd_cx-uV-uA = <0x180 0x186a0>; | |
clocks = <0x38 0x5cd71a61>; | |
clock-names = "xo"; | |
qcom,proxy-clock-names = "xo"; | |
qcom,pil-generic-irq-handler; | |
status = "ok"; | |
qcom,pas-id = <0xe>; | |
qcom,proxy-timeout-ms = <0x2710>; | |
qcom,firmware-name = "spss"; | |
memory-region = <0xa8>; | |
qcom,spss-scsr-bits = <0x18 0x19>; | |
}; | |
qcom,msm-rtb { | |
compatible = "qcom,msm-rtb"; | |
qcom,rtb-size = <0x100000>; | |
}; | |
qcom,mpm2-sleep-counter@10a3000 { | |
compatible = "qcom,mpm2-sleep-counter"; | |
reg = <0x10a3000 0x1000>; | |
clock-frequency = <0x8000>; | |
}; | |
qcom,msm-imem@146bf000 { | |
compatible = "qcom,msm-imem"; | |
reg = <0x146bf000 0x1000>; | |
ranges = <0x0 0x146bf000 0x1000>; | |
#address-cells = <0x1>; | |
#size-cells = <0x1>; | |
mem_dump_table@10 { | |
compatible = "qcom,msm-imem-mem_dump_table"; | |
reg = <0x10 0x8>; | |
}; | |
dload_type@18 { | |
compatible = "qcom,msm-imem-dload-type"; | |
reg = <0x18 0x4>; | |
}; | |
restart_reason@65c { | |
compatible = "qcom,msm-imem-restart_reason"; | |
reg = <0x65c 0x4>; | |
}; | |
boot_stats@6b0 { | |
compatible = "qcom,msm-imem-boot_stats"; | |
reg = <0x6b0 0x20>; | |
}; | |
kaslr_offset@6d0 { | |
compatible = "qcom,msm-imem-kaslr_offset"; | |
reg = <0x6d0 0xc>; | |
}; | |
pil@94c { | |
compatible = "qcom,msm-imem-pil"; | |
reg = <0x94c 0xc8>; | |
}; | |
diag_dload@c8 { | |
compatible = "qcom,msm-imem-diag-dload"; | |
reg = <0xc8 0xc8>; | |
}; | |
}; | |
cpu-pmu { | |
compatible = "arm,armv8-pmuv3"; | |
qcom,irq-is-percpu; | |
interrupts = <0x1 0x6 0x4>; | |
}; | |
cpuss_dump { | |
compatible = "qcom,cpuss-dump"; | |
qcom,l1_i_cache0 { | |
qcom,dump-node = <0xa9>; | |
qcom,dump-id = <0x60>; | |
}; | |
qcom,l1_i_cache1 { | |
qcom,dump-node = <0xaa>; | |
qcom,dump-id = <0x61>; | |
}; | |
qcom,l1_i_cache2 { | |
qcom,dump-node = <0xab>; | |
qcom,dump-id = <0x62>; | |
}; | |
qcom,l1_i_cache3 { | |
qcom,dump-node = <0xac>; | |
qcom,dump-id = <0x63>; | |
}; | |
qcom,l1_i_cache100 { | |
qcom,dump-node = <0xad>; | |
qcom,dump-id = <0x64>; | |
}; | |
qcom,l1_i_cache101 { | |
qcom,dump-node = <0xae>; | |
qcom,dump-id = <0x65>; | |
}; | |
qcom,l1_i_cache102 { | |
qcom,dump-node = <0xaf>; | |
qcom,dump-id = <0x66>; | |
}; | |
qcom,l1_i_cache103 { | |
qcom,dump-node = <0xb0>; | |
qcom,dump-id = <0x67>; | |
}; | |
qcom,l1_d_cache0 { | |
qcom,dump-node = <0xb1>; | |
qcom,dump-id = <0x80>; | |
}; | |
qcom,l1_d_cache1 { | |
qcom,dump-node = <0xb2>; | |
qcom,dump-id = <0x81>; | |
}; | |
qcom,l1_d_cache2 { | |
qcom,dump-node = <0xb3>; | |
qcom,dump-id = <0x82>; | |
}; | |
qcom,l1_d_cache3 { | |
qcom,dump-node = <0xb4>; | |
qcom,dump-id = <0x83>; | |
}; | |
qcom,l1_d_cache100 { | |
qcom,dump-node = <0xb5>; | |
qcom,dump-id = <0x84>; | |
}; | |
qcom,l1_d_cache101 { | |
qcom,dump-node = <0xb6>; | |
qcom,dump-id = <0x85>; | |
}; | |
qcom,l1_d_cache102 { | |
qcom,dump-node = <0xb7>; | |
qcom,dump-id = <0x86>; | |
}; | |
qcom,l1_d_cache103 { | |
qcom,dump-node = <0xb8>; | |
qcom,dump-id = <0x87>; | |
}; | |
qcom,l1_tlb_dump0 { | |
qcom,dump-node = <0xb9>; | |
qcom,dump-id = <0x20>; | |
}; | |
qcom,l1_tlb_dump1 { | |
qcom,dump-node = <0xba>; | |
qcom,dump-id = <0x21>; | |
}; | |
qcom,l1_tlb_dump2 { | |
qcom,dump-node = <0xbb>; | |
qcom,dump-id = <0x22>; | |
}; | |
qcom,l1_tlb_dump3 { | |
qcom,dump-node = <0xbc>; | |
qcom,dump-id = <0x23>; | |
}; | |
qcom,l1_tlb_dump100 { | |
qcom,dump-node = <0xbd>; | |
qcom,dump-id = <0x24>; | |
}; | |
qcom,l1_tlb_dump101 { | |
qcom,dump-node = <0xbe>; | |
qcom,dump-id = <0x25>; | |
}; | |
qcom,l1_tlb_dump102 { | |
qcom,dump-node = <0xbf>; | |
qcom,dump-id = <0x26>; | |
}; | |
qcom,l1_tlb_dump103 { | |
qcom,dump-node = <0xc0>; | |
qcom,dump-id = <0x27>; | |
}; | |
}; | |
qcom,msm-ssc-sensors { | |
compatible = "qcom,msm-ssc-sensors"; | |
status = "ok"; | |
qcom,firmware-name = "slpi_v2"; | |
}; | |
dcc@10b3000 { | |
compatible = "qcom,dcc"; | |
reg = <0x10b3000 0x1000 0x10b4000 0x2000>; | |
reg-names = "dcc-base", "dcc-ram-base"; | |
clocks = <0x38 0xfa14a88c>; | |
clock-names = "dcc_clk"; | |
}; | |
qcom,msm-core@780000 { | |
compatible = "qcom,apss-core-ea"; | |
reg = <0x780000 0x1000>; | |
qcom,low-hyst-temp = <0x64>; | |
qcom,high-hyst-temp = <0x64>; | |
qcom,polling-interval = <0x32>; | |
ea0 { | |
sensor = <0x90>; | |
linux,phandle = <0x5>; | |
phandle = <0x5>; | |
}; | |
ea1 { | |
sensor = <0x91>; | |
linux,phandle = <0x7>; | |
phandle = <0x7>; | |
}; | |
ea2 { | |
sensor = <0x92>; | |
linux,phandle = <0x9>; | |
phandle = <0x9>; | |
}; | |
ea3 { | |
sensor = <0x93>; | |
linux,phandle = <0xb>; | |
phandle = <0xb>; | |
}; | |
ea4 { | |
sensor = <0x94>; | |
linux,phandle = <0xf>; | |
phandle = <0xf>; | |
}; | |
ea5 { | |
sensor = <0x95>; | |
linux,phandle = <0x11>; | |
phandle = <0x11>; | |
}; | |
ea6 { | |
sensor = <0x96>; | |
linux,phandle = <0x13>; | |
phandle = <0x13>; | |
}; | |
ea7 { | |
sensor = <0x97>; | |
linux,phandle = <0x15>; | |
phandle = <0x15>; | |
}; | |
}; | |
qcom,msm_ath10k_wlan { | |
status = "disabled"; | |
compatible = "qcom,wcn3990-wifi"; | |
reg = <0x18800000 0x800000>; | |
reg-names = "membase"; | |
clocks = <0x38 0xa7c5602a>; | |
clock-names = "cxo_ref_clk_pin"; | |
interrupts = <0x0 0x19d 0x0 0x0 0x19e 0x0 0x0 0x19f 0x0 0x0 0x1a0 0x0 0x0 0x1a1 0x0 0x0 0x1a2 0x0 0x0 0x1a4 0x0 0x0 0x1a5 0x0 0x0 0x1a6 0x0 0x0 0x1a7 0x0 0x0 0x1a8 0x0 0x0 0x1a9 0x0>; | |
vdd-0.8-cx-mx-supply = <0xc1>; | |
vdd-1.8-xo-supply = <0xc2>; | |
vdd-1.3-rfa-supply = <0xc3>; | |
vdd-3.3-ch0-supply = <0xc4>; | |
qcom,vdd-0.8-cx-mx-config = <0xc3500 0xc3500>; | |
qcom,vdd-3.3-ch0-config = <0x2f5d00 0x328980>; | |
}; | |
qcom,icnss@18800000 { | |
compatible = "qcom,icnss"; | |
reg = <0x18800000 0x800000 0xa0000000 0x10000000 0xb0000000 0x10000>; | |
reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa"; | |
clocks = <0x38 0xa7c5602a>; | |
clock-names = "cxo_ref_clk_pin"; | |
iommus = <0x63 0x1900 0x63 0x1901>; | |
interrupts = <0x0 0x19d 0x0 0x0 0x19e 0x0 0x0 0x19f 0x0 0x0 0x1a0 0x0 0x0 0x1a1 0x0 0x0 0x1a2 0x0 0x0 0x1a4 0x0 0x0 0x1a5 0x0 0x0 0x1a6 0x0 0x0 0x1a7 0x0 0x0 0x1a8 0x0 0x0 0x1a9 0x0>; | |
qcom,wlan-msa-memory = <0x100000>; | |
vdd-0.8-cx-mx-supply = <0xc1>; | |
vdd-1.8-xo-supply = <0xc2>; | |
vdd-1.3-rfa-supply = <0xc3>; | |
vdd-3.3-ch0-supply = <0xc4>; | |
qcom,vdd-0.8-cx-mx-config = <0xc3500 0xc3500>; | |
qcom,vdd-3.3-ch0-config = <0x2f5d00 0x328980>; | |
qcom,icnss-vadc = <0x2d>; | |
qcom,icnss-adc_tm = <0xc5>; | |
}; | |
msm_tspp@0c1e7000 { | |
compatible = "qcom,msm_tspp"; | |
reg = <0xc1e7000 0x200 0xc1e8000 0x200 0xc1e9000 0x1000 0xc1c4000 0x23000>; | |
reg-names = "MSM_TSIF0_PHYS", "MSM_TSIF1_PHYS", "MSM_TSPP_PHYS", "MSM_TSPP_BAM_PHYS"; | |
interrupts = <0x0 0x79 0x0 0x0 0x77 0x0 0x0 0x78 0x0 0x0 0x7a 0x0>; | |
interrupt-names = "TSIF_TSPP_IRQ", "TSIF0_IRQ", "TSIF1_IRQ", "TSIF_BAM_IRQ"; | |
clock-names = "iface_clk", "ref_clk"; | |
clocks = <0x38 0x88d2822c 0x38 0x8f1ed2c2>; | |
qcom,msm-bus,name = "tsif"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x52 0x200 0x0 0x0 0x52 0x200 0x3000 0x6000>; | |
pinctrl-names = "disabled", "tsif0-mode1", "tsif0-mode2", "tsif1-mode1", "tsif1-mode2", "dual-tsif-mode1", "dual-tsif-mode2"; | |
pinctrl-0; | |
pinctrl-1 = <0xc6>; | |
pinctrl-2 = <0xc6 0xc7>; | |
pinctrl-3 = <0xc8>; | |
pinctrl-4 = <0xc8 0xc9>; | |
pinctrl-5 = <0xc6 0xc8>; | |
pinctrl-6 = <0xc6 0xc7 0xc8 0xc9>; | |
}; | |
qcom,wil6210 { | |
compatible = "qcom,wil6210"; | |
qcom,pcie-parent = <0x99>; | |
qcom,wigig-en = <0x7c 0x50 0x0>; | |
qcom,msm-bus,name = "wil6210"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x2d 0x200 0x0 0x0 0x2d 0x200 0x927c0 0xc3500>; | |
qcom,use-ext-supply; | |
vdd-supply = <0xca>; | |
vddio-supply = <0xcb>; | |
qcom,use-ext-clocks; | |
clocks = <0x38 0xb673936b 0x38 0x726f53f5>; | |
clock-names = "rf_clk3_clk", "rf_clk3_pin_clk"; | |
qcom,smmu-support; | |
qcom,smmu-s1-en; | |
qcom,smmu-fast-map; | |
qcom,smmu-coherent; | |
qcom,smmu-mapping = <0x20000000 0xe0000000>; | |
qcom,keep-radio-on-during-sleep; | |
status = "ok"; | |
}; | |
qcom,qsee_ipc_irq_bridge { | |
compatible = "qcom,qsee-ipc-irq-bridge"; | |
qcom,qsee-ipc-irq-spss { | |
qcom,rx-irq-clr = <0x1d08008 0x4>; | |
qcom,rx-irq-clr-mask = <0x1>; | |
qcom,dev-name = "qsee_ipc_irq_spss"; | |
interrupts = <0x0 0x15d 0x4>; | |
label = "spss"; | |
}; | |
}; | |
cprh-ctrl@179c8000 { | |
compatible = "qcom,cprh-msm8998-v2-kbss-regulator"; | |
reg = <0x179c8000 0x4000 0x784000 0x1000>; | |
reg-names = "cpr_ctrl", "fuse_base"; | |
clocks = <0x38 0x699183be>; | |
clock-names = "core_clk"; | |
qcom,cpr-ctrl-name = "apc0"; | |
qcom,cpr-controller-id = <0x0>; | |
qcom,cpr-sensor-time = <0x3e8>; | |
qcom,cpr-loop-time = <0x4c4b40>; | |
qcom,cpr-idle-cycles = <0xf>; | |
qcom,cpr-up-down-delay-time = <0xbb8>; | |
qcom,cpr-step-quot-init-min = <0xb>; | |
qcom,cpr-step-quot-init-max = <0xc>; | |
qcom,cpr-count-mode = <0x0>; | |
qcom,cpr-count-repeat = <0x1>; | |
qcom,cpr-down-error-step-limit = <0x1>; | |
qcom,cpr-up-error-step-limit = <0x1>; | |
qcom,cpr-corner-switch-delay-time = <0x412>; | |
qcom,cpr-voltage-settling-time = <0x6e0>; | |
qcom,apm-threshold-voltage = <0xc3500>; | |
qcom,apm-crossover-voltage = <0xd6d80>; | |
qcom,apm-hysteresis-voltage = <0x0>; | |
qcom,voltage-step = <0xfa0>; | |
qcom,voltage-base = <0x55f00>; | |
qcom,cpr-saw-use-unit-mV; | |
qcom,cpr-enable; | |
qcom,cpr-hw-closed-loop; | |
qcom,cpr-panic-reg-addr-list = <0x179cbaa4 0x17912c18>; | |
qcom,cpr-panic-reg-name-list = "PWR_CPRH_STATUS", "APCLUS0_L2_SAW4_PMIC_STS"; | |
qcom,cpr-aging-ref-voltage = <0x101d00>; | |
vdd-supply = <0xcc>; | |
qcom,mem-acc-threshold-voltage = <0xd0020>; | |
qcom,mem-acc-crossover-voltage = <0xd0020>; | |
thread@0 { | |
qcom,cpr-thread-id = <0x0>; | |
qcom,cpr-consecutive-up = <0x0>; | |
qcom,cpr-consecutive-down = <0x2>; | |
qcom,cpr-up-threshold = <0x2>; | |
qcom,cpr-down-threshold = <0x2>; | |
regulator { | |
regulator-name = "apc0_pwrcl_corner"; | |
regulator-min-microvolt = <0x1>; | |
regulator-max-microvolt = <0x17>; | |
qcom,cpr-fuse-corners = <0x4>; | |
qcom,cpr-fuse-combos = <0x20>; | |
qcom,cpr-corners = <0x16>; | |
qcom,cpr-corner-fmax-map = <0x8 0xb 0x12 0x16>; | |
qcom,cpr-voltage-ceiling = <0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xe86c0 0xe86c0 0x101d00 0x101d00>; | |
qcom,cpr-voltage-floor = <0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0xadd40 0xadd40 0xbc7a0 0xbc7a0>; | |
qcom,cpr-floor-to-ceiling-max-range = <0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x9c40 0x9c40 0x9c40 0x9c40>; | |
qcom,corner-frequencies = <0x11e1a300 0x15be6800 0x1a524800 0x1ee62800 0x237a0800 0x280de800 0x2ca1c800 0x3135a800 0x34a49000 0x39387000 0x3dcc5000 0x413b3800 0x45cf1800 0x4a62f800 0x4ef6d800 0x538ab800 0x581e9800 0x5cb27800 0x63904800 0x68242800 0x6cb80800 0x714be800>; | |
qcom,cpr-ro-scaling-factor = <0xa23 0xaea 0xa11 0xaca 0x9a7 0xa72 0x897 0x9f9 0xc75 0xcb7 0xc78 0xb92 0xbee 0xba6 0x7fa 0xb81 0xa23 0xaea 0xa11 0xaca 0x9a7 0xa72 0x897 0x9f9 0xc75 0xcb7 0xc78 0xb92 0xbee 0xba6 0x7fa 0xb81 0x957 0x9f6 0x9b3 0xa4e 0x94e 0xa04 0x8d3 0x9fb 0xace 0xbe1 0xbac 0xb77 0xb39 0xa80 0x7dd 0xae0 0x812 0x869 0x8fc 0x982 0x8ac 0x952 0x8f0 0x9a1 0x7ec 0x9cf 0x9b7 0xaae 0x9fa 0x845 0x764 0x949>; | |
qcom,cpr-open-loop-voltage-fuse-adjustment = <0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530 0x9c40 0x5dc0 0x2ee0 0x7530>; | |
qcom,cpr-closed-loop-voltage-fuse-adjustment = <0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530 0x4e20 0x6590 0x2ee0 0x7530>; | |
qcom,allow-voltage-interpolation; | |
qcom,allow-quotient-interpolation; | |
qcom,cpr-scaled-open-loop-voltage-as-ceiling; | |
qcom,cpr-aging-max-voltage-adjustment = <0x3a98>; | |
qcom,cpr-aging-ref-corner = <0x16>; | |
qcom,cpr-aging-ro-scaling-factor = <0x654>; | |
qcom,allow-aging-voltage-adjustment = <0x0>; | |
qcom,allow-aging-open-loop-voltage-adjustment = <0x1>; | |
qcom,cpr-speed-bins = <0x4>; | |
qcom,cpr-speed-bin-corners = <0x16 0x16 0x16 0x16>; | |
qcom,cpr-open-loop-voltage-adjustment = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xffffd120 0xffffd120 0xffffd120 0xffffd120 0xffffd120 0xffffc180 0xffffc180 0xffffb1e0 0xffffa240 0xffff92a0 0xffff92a0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xffffd120 0xffffd120 0xffffd120 0xffffd120 0xffffd120 0xffffc180 0xffffc180 0xffffb1e0 0xffffa240 0xffff92a0 0xffff92a0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xffffd120 0xffffd120 0xffffd120 0xffffd120 0xffffd120 0xffffc180 0xffffc180 0xffffb1e0 0xffffa240 0xffff92a0 0xffff92a0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xffffd120 0xffffd120 0xffffd120 0xffffd120 0xffffd120 0xffffc180 0xffffc180 0xffffb1e0 0xffffa240 0xffff92a0 0xffff92a0>; | |
qcom,cpr-closed-loop-voltage-adjustment = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xffffd8f0 0xffffd508 0xffffd120 0xffffcd38 0xffffc950 0xffffc950 0xffffc568 0xffffadf8 0xffffa240 0xffff9a70 0xffff92a0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xffffd8f0 0xffffd508 0xffffd120 0xffffcd38 0xffffc950 0xffffc950 0xffffc568 0xffffadf8 0xffffa240 0xffff9a70 0xffff92a0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xffffd8f0 0xffffd508 0xffffd120 0xffffcd38 0xffffc950 0xffffc950 0xffffc568 0xffffadf8 0xffffa240 0xffff9a70 0xffff92a0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xffffd8f0 0xffffd508 0xffffd120 0xffffcd38 0xffffc950 0xffffc950 0xffffc568 0xffffadf8 0xffffa240 0xffff9a70 0xffff92a0>; | |
linux,phandle = <0x5e>; | |
phandle = <0x5e>; | |
}; | |
}; | |
}; | |
cprh-ctrl@179c4000 { | |
compatible = "qcom,cprh-msm8998-v2-kbss-regulator"; | |
reg = <0x179c4000 0x4000 0x784000 0x1000>; | |
reg-names = "cpr_ctrl", "fuse_base"; | |
clocks = <0x38 0x699183be>; | |
clock-names = "core_clk"; | |
qcom,cpr-ctrl-name = "apc1"; | |
qcom,cpr-controller-id = <0x1>; | |
qcom,cpr-sensor-time = <0x3e8>; | |
qcom,cpr-loop-time = <0x4c4b40>; | |
qcom,cpr-idle-cycles = <0xf>; | |
qcom,cpr-up-down-delay-time = <0xbb8>; | |
qcom,cpr-step-quot-init-min = <0x9>; | |
qcom,cpr-step-quot-init-max = <0xe>; | |
qcom,cpr-count-mode = <0x0>; | |
qcom,cpr-count-repeat = <0x1>; | |
qcom,cpr-down-error-step-limit = <0x1>; | |
qcom,cpr-up-error-step-limit = <0x1>; | |
qcom,cpr-corner-switch-delay-time = <0x412>; | |
qcom,cpr-voltage-settling-time = <0x6e0>; | |
qcom,apm-threshold-voltage = <0xc3500>; | |
qcom,apm-crossover-voltage = <0xd6d80>; | |
qcom,apm-hysteresis-voltage = <0x0>; | |
qcom,voltage-step = <0xfa0>; | |
qcom,voltage-base = <0x55f00>; | |
qcom,cpr-saw-use-unit-mV; | |
qcom,cpr-enable; | |
qcom,cpr-hw-closed-loop; | |
qcom,cpr-panic-reg-addr-list = <0x179c7aa4 0x17812c18>; | |
qcom,cpr-panic-reg-name-list = "PERF_CPRH_STATUS", "APCLUS1_L2_SAW4_PMIC_STS"; | |
qcom,cpr-aging-ref-voltage = <0x115580>; | |
vdd-supply = <0xcd>; | |
qcom,mem-acc-threshold-voltage = <0xd0020>; | |
qcom,mem-acc-crossover-voltage = <0xd0020>; | |
thread@0 { | |
qcom,cpr-thread-id = <0x0>; | |
qcom,cpr-consecutive-up = <0x0>; | |
qcom,cpr-consecutive-down = <0x2>; | |
qcom,cpr-up-threshold = <0x2>; | |
qcom,cpr-down-threshold = <0x2>; | |
regulator { | |
regulator-name = "apc1_perfcl_corner"; | |
regulator-min-microvolt = <0x1>; | |
regulator-max-microvolt = <0x22>; | |
qcom,cpr-fuse-corners = <0x4>; | |
qcom,cpr-fuse-combos = <0x20>; | |
qcom,cpr-corners = <0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x1a 0x1a 0x1a 0x1a 0x1a 0x1a 0x1a 0x1a 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1f 0x1f 0x1f 0x1f 0x1f 0x1f 0x1f 0x1f>; | |
qcom,cpr-corner-fmax-map = <0x8 0xc 0x14 0x20 0x8 0xc 0x14 0x1a 0x8 0xc 0x14 0x1e 0x8 0xc 0x14 0x1f>; | |
qcom,cpr-voltage-ceiling = <0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xe86c0 0xe86c0 0xe86c0 0x115580 0x115580 0x115580 0x115580 0x115580 0x115580 0x115580 0x115580 0x115580 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xe86c0 0xe86c0 0xe86c0 0x115580 0x115580 0x115580 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xe86c0 0xe86c0 0xe86c0 0x115580 0x115580 0x115580 0x115580 0x115580 0x115580 0x115580 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xca260 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xdbba0 0xe86c0 0xe86c0 0xe86c0 0x115580 0x115580 0x115580 0x115580 0x115580 0x115580 0x115580 0x115580>; | |
qcom,cpr-voltage-floor = <0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0xadd40 0xadd40 0xadd40 0xbc7a0 0xbc7a0 0xbc7a0 0xbc7a0 0xbc7a0 0xbc7a0 0xbc7a0 0xbc7a0 0xbc7a0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0xadd40 0xadd40 0xadd40 0xbc7a0 0xbc7a0 0xbc7a0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0xadd40 0xadd40 0xadd40 0xbc7a0 0xbc7a0 0xbc7a0 0xbc7a0 0xbc7a0 0xbc7a0 0xbc7a0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0x9a4c0 0xadd40 0xadd40 0xadd40 0xbc7a0 0xbc7a0 0xbc7a0 0xbc7a0 0xbc7a0 0xbc7a0 0xbc7a0 0xbc7a0>; | |
qcom,cpr-floor-to-ceiling-max-range = <0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x7d00 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40>; | |
qcom,corner-frequencies = <0x11e1a300 0x14997000 0x192d5000 0x1dc13000 0x22551000 0x26e8f000 0x2b7cd000 0x3010b000 0x35c98800 0x3a5d6800 0x3ef14800 0x43852800 0x46f41000 0x4b87f000 0x501bd000 0x54afb000 0x59439000 0x5dd77000 0x626b5000 0x66ff3000 0x6b931000 0x7026f000 0x74bad000 0x794eb000 0x7de29000 0x839b6800 0x870a5000 0x8b9e3000 0x90321000 0x927c0000 0x93a0f800 0x94c5f000 0x11e1a300 0x14997000 0x192d5000 0x1dc13000 0x22551000 0x26e8f000 0x2b7cd000 0x3010b000 0x35c98800 0x3a5d6800 0x3ef14800 0x43852800 0x46f41000 0x4b87f000 0x501bd000 0x54afb000 0x59439000 0x5dd77000 0x626b5000 0x66ff3000 0x6b931000 0x7026f000 0x74bad000 0x794eb000 0x7de29000 0x839b6800 0x11e1a300 0x14997000 0x192d5000 0x1dc13000 0x22551000 0x26e8f000 0x2b7cd000 0x3010b000 0x35c98800 0x3a5d6800 0x3ef14800 0x43852800 0x46f41000 0x4b87f000 0x501bd000 0x54afb000 0x59439000 0x5dd77000 0x626b5000 0x66ff3000 0x6b931000 0x7026f000 0x74bad000 0x794eb000 0x7de29000 0x839b6800 0x870a5000 0x8a793800 0x8b9e3000 0x8cc32800 0x11e1a300 0x14997000 0x192d5000 0x1dc13000 0x22551000 0x26e8f000 0x2b7cd000 0x3010b000 0x35c98800 0x3a5d6800 0x3ef14800 0x43852800 0x46f41000 0x4b87f000 0x501bd000 0x54afb000 0x59439000 0x5dd77000 0x626b5000 0x66ff3000 0x6b931000 0x7026f000 0x74bad000 0x794eb000 0x7de29000 0x839b6800 0x870a5000 0x8a793800 0x8b9e3000 0x8cc32800 0x927c0000>; | |
qcom,cpr-ro-scaling-factor = <0xb29 0xbf1 0xb0c 0xb88 0xa8b 0xaee 0x98e 0xa47 0xa45 0xa12 0x8c4 0xd10 0xcd9 0xc41 0xc5c 0xa5f 0xb29 0xbf1 0xb0c 0xb88 0xa8b 0xaee 0x98e 0xa47 0xa45 0xa12 0x8c4 0xd10 0xcd9 0xc41 0xc5c 0xa5f 0xa2b 0xac3 0xa74 0xad9 0xa0d 0xa7d 0x9a1 0xa32 0x908 0x977 0x8c3 0xc20 0xbce 0xbdc 0xab4 0x8ff 0x76d 0x7e0 0x830 0x8b4 0x7f2 0x871 0x81d 0x88c 0x61d 0x74e 0x785 0x8bb 0x89d 0x96d 0x6e2 0x5c6>; | |
qcom,cpr-open-loop-voltage-fuse-adjustment = <0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20 0x1f40 0x0 0x2ee0 0xcb20>; | |
qcom,cpr-closed-loop-voltage-fuse-adjustment = <0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350 0x0 0x0 0x2ee0 0xc350>; | |
qcom,allow-voltage-interpolation; | |
qcom,allow-quotient-interpolation; | |
qcom,cpr-scaled-open-loop-voltage-as-ceiling; | |
qcom,cpr-aging-max-voltage-adjustment = <0x3a98>; | |
qcom,cpr-aging-ref-corner = <0x20 0x1a 0x1e 0x1f>; | |
qcom,cpr-aging-ro-scaling-factor = <0x6a4>; | |
qcom,allow-aging-voltage-adjustment = <0x0>; | |
qcom,allow-aging-open-loop-voltage-adjustment = <0x1>; | |
qcom,cpr-speed-bins = <0x4>; | |
qcom,cpr-speed-bin-corners = <0x20 0x1a 0x1e 0x1f>; | |
qcom,cpr-open-loop-voltage-adjustment = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xffffe0c0 0xffffd120 0xffffd120 0xffffd120 0xffffd120 0xffffd120 0xffffd120 0xffffc180 0xffffc180 0xffffb1e0 0xffffc180 0xffffc180 0xffffc180 0xffffd120 0xffff92a0 0xffff92a0 0xffff92a0 0xffff92a0 0xffff92a0 0xffff92a0 0xffff92a0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xffffe0c0 0xffffd120 0xffffd120 0xffffd120 0xffffd120 0xffffd120 0xffffd120 0xffffc180 0xffffc180 0xffffb1e0 0xffffc180 0xffffc180 0xffffc180 0xffffc180 0xffff92a0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xffffe0c0 0xffffd120 0xffffd120 0xffffd120 0xffffd120 0xffffd120 0xffffd120 0xffffc180 0xffffc180 0xffffb1e0 0xffffc180 0xffffc180 0xffffc180 0xffffd120 0xffff92a0 0xffff92a0 0xffff92a0 0xffff92a0 0xffff92a0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xffffe0c0 0xffffd120 0xffffd120 0xffffd120 0xffffd120 0xffffd120 0xffffd120 0xffffc180 0xffffc180 0xffffb1e0 0xffffc180 0xffffc180 0xffffc180 0xffffd120 0xffff92a0 0xffff92a0 0xffff92a0 0xffff92a0 0xffff92a0 0xffff92a0>; | |
qcom,cpr-closed-loop-voltage-adjustment = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xffffd8f0 0xffffd8f0 0xffffd508 0xffffd120 0xffffd120 0xffffcd38 0xffffc950 0xffffc950 0xffffc568 0xffffc180 0xffffc180 0xffffbd98 0xffffc568 0xffffcd38 0xffff9a70 0xffff9a70 0xffff9688 0xffff9688 0xffff92a0 0xffff92a0 0xffff92a0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xffffd8f0 0xffffd8f0 0xffffd508 0xffffd120 0xffffd120 0xffffcd38 0xffffc950 0xffffc950 0xffffc568 0xffffc180 0xffffc180 0xffffbd98 0xffffc180 0xffffc568 0xffff92a0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xffffd8f0 0xffffd8f0 0xffffd508 0xffffd120 0xffffd120 0xffffcd38 0xffffc950 0xffffc950 0xffffc568 0xffffc180 0xffffc180 0xffffbd98 0xffffc568 0xffffc950 0xffff9688 0xffff9688 0xffff92a0 0xffff92a0 0xffff92a0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xffffd8f0 0xffffd8f0 0xffffd508 0xffffd120 0xffffd120 0xffffcd38 0xffffc950 0xffffc950 0xffffc568 0xffffc180 0xffffc180 0xffffbd98 0xffffc568 0xffffc950 0xffff9a70 0xffff9688 0xffff9688 0xffff92a0 0xffff92a0 0xffff92a0>; | |
linux,phandle = <0x5f>; | |
phandle = <0x5f>; | |
}; | |
}; | |
}; | |
cpr4-ctrl@5061000 { | |
compatible = "qcom,cpr4-msm8998-v2-mmss-regulator"; | |
reg = <0x5061000 0x4000 0x784000 0x1000 0x5065204 0x4>; | |
reg-names = "cpr_ctrl", "fuse_base", "aging_allowed"; | |
clocks = <0x60 0x7bd750e8 0x38 0xd5ccb7f4>; | |
clock-names = "core_clk", "bus_clk"; | |
interrupts = <0x0 0x11d 0x1>; | |
interrupt-names = "cpr"; | |
qcom,cpr-ctrl-name = "gfx"; | |
qcom,cpr-sensor-time = <0x3e8>; | |
qcom,cpr-loop-time = <0x4c4b40>; | |
qcom,cpr-idle-cycles = <0xf>; | |
qcom,cpr-step-quot-init-min = <0x8>; | |
qcom,cpr-step-quot-init-max = <0xc>; | |
qcom,cpr-count-mode = <0x0>; | |
qcom,cpr-count-repeat = <0x1>; | |
vdd-supply = <0xce>; | |
qcom,voltage-step = <0xfa0>; | |
mem-acc-supply = <0xcf>; | |
qcom,cpr-aging-ref-voltage = <0x109a00>; | |
qcom,cpr-aging-allowed-reg-mask = <0x3>; | |
qcom,cpr-aging-allowed-reg-value = <0x3>; | |
qcom,cpr-enable; | |
thread@0 { | |
qcom,cpr-thread-id = <0x0>; | |
qcom,cpr-consecutive-up = <0x0>; | |
qcom,cpr-consecutive-down = <0x2>; | |
qcom,cpr-up-threshold = <0x0>; | |
qcom,cpr-down-threshold = <0x2>; | |
regulator { | |
regulator-name = "gfx_corner"; | |
regulator-min-microvolt = <0x1>; | |
regulator-max-microvolt = <0x8>; | |
qcom,cpr-fuse-corners = <0x4>; | |
qcom,cpr-fuse-combos = <0x8>; | |
qcom,cpr-corners = <0x8>; | |
qcom,cpr-corner-fmax-map = <0x1 0x3 0x5 0x8>; | |
qcom,cpr-voltage-ceiling = <0xaece0 0xaece0 0xbc7a0 0xd6d80 0xddae0 0xe7720 0xf80c0 0x109a00 0xb0c20 0xb0c20 0xbc7a0 0xcb200 0xdfa20 0xec540 0xfa000 0x109a00 0xb0c20 0xb0c20 0xbc7a0 0xcb200 0xdfa20 0xec540 0xfa000 0x109a00 0xb0c20 0xb0c20 0xbc7a0 0xcb200 0xdfa20 0xec540 0xfa000 0x109a00 0xb0c20 0xb0c20 0xbc7a0 0xcb200 0xdfa20 0xec540 0xfa000 0x109a00 0xb0c20 0xb0c20 0xbc7a0 0xcb200 0xdfa20 0xec540 0xfa000 0x109a00 0xb0c20 0xb0c20 0xbc7a0 0xcb200 0xdfa20 0xec540 0xfa000 0x109a00 0xb0c20 0xb0c20 0xbc7a0 0xcb200 0xdfa20 0xec540 0xfa000 0x109a00>; | |
qcom,cpr-voltage-floor = <0x7dfa0 0x7dfa0 0x81e20 0x8e940 0x9a4c0 0xa4100 0xadd40 0xb8920>; | |
qcom,mem-acc-voltage = <0x1 0x1 0x1 0x2 0x2 0x2 0x2 0x2>; | |
qcom,corner-frequencies = <0xaba9500 0xf518240 0x14628180 0x18ad2380 0x1eb246c0 0x23863d00 0x27ef6380 0x2a51bd80>; | |
qcom,cpr-target-quotients = <0x0 0x0 0x0 0x0 0x14b 0x165 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x73 0x0 0x0 0x0 0x0 0x0 0x1d3 0x1f4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xc7 0x0 0x0 0x0 0x0 0x0 0x274 0x299 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x122 0x0 0x0 0x0 0x0 0x0 0x2fa 0x325 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x18d 0x0 0x0 0x0 0x0 0x0 0x3c4 0x3f5 0x0 0x0 0x0 0x0 0x477 0x0 0x472 0x41f 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x51a 0x0 0x509 0x490 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x5bc 0x0 0x595 0x4e8 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x65b 0x0 0x62a 0x549 0x0 0x0>; | |
qcom,cpr-ro-scaling-factor = <0x0 0x0 0x0 0x0 0x949 0xa0b 0x0 0x0 0x0 0x0 0x878 0x0 0x8a1 0x739 0x7cd 0x0 0x0 0x0 0x0 0x0 0x949 0xa0b 0x0 0x0 0x0 0x0 0x878 0x0 0x8a1 0x739 0x7cd 0x0 0x0 0x0 0x0 0x0 0x949 0xa0b 0x0 0x0 0x0 0x0 0x878 0x0 0x8a1 0x739 0x7cd 0x0 0x0 0x0 0x0 0x0 0x949 0xa0b 0x0 0x0 0x0 0x0 0x878 0x0 0x8a1 0x739 0x7cd 0x0 0x0 0x0 0x0 0x0 0x949 0xa0b 0x0 0x0 0x0 0x0 0x878 0x0 0x8a1 0x739 0x7cd 0x0 0x0 0x0 0x0 0x0 0x949 0xa0b 0x0 0x0 0x0 0x0 0x878 0x0 0x8a1 0x739 0x7cd 0x0 0x0 0x0 0x0 0x0 0x949 0xa0b 0x0 0x0 0x0 0x0 0x878 0x0 0x8a1 0x739 0x7cd 0x0 0x0 0x0 0x0 0x0 0x949 0xa0b 0x0 0x0 0x0 0x0 0x878 0x0 0x8a1 0x739 0x7cd 0x0>; | |
qcom,cpr-open-loop-voltage-fuse-adjustment = <0xea60 0x0 0x0 0x0 0xea60 0x0 0x0 0x0 0xea60 0x0 0x0 0x0 0xea60 0x0 0x0 0x0 0xea60 0x0 0x0 0x0 0xea60 0x0 0x0 0x0 0xea60 0x0 0x0 0x0 0xea60 0x0 0x0 0x0>; | |
qcom,cpr-closed-loop-voltage-adjustment = <0x15f90 0x9470 0x6d60 0x1f40 0x0 0x7148 0x2af8 0x0 0x15f90 0x9470 0x6d60 0x1f40 0x0 0x7148 0x2af8 0x0 0x15f90 0x9470 0x6d60 0x1f40 0x0 0x7148 0x2af8 0x0 0x15f90 0x9470 0x6d60 0x1f40 0x0 0x7148 0x2af8 0x0 0x15f90 0x9470 0x6d60 0x1f40 0x0 0x7148 0x2af8 0x0 0x15f90 0x9470 0x6d60 0x1f40 0x0 0x7148 0x2af8 0x0 0x15f90 0x9470 0x6d60 0x1f40 0x0 0x7148 0x2af8 0x0 0x15f90 0x9470 0x6d60 0x1f40 0x0 0x7148 0x2af8 0x0>; | |
qcom,cpr-floor-to-ceiling-max-range = <0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0x9c40 0xc350 0xc350>; | |
qcom,cpr-fused-closed-loop-voltage-adjustment-map = <0x0 0x0 0x0 0x0 0x1 0x2 0x3 0x4>; | |
qcom,allow-voltage-interpolation; | |
qcom,cpr-scaled-open-loop-voltage-as-ceiling; | |
qcom,cpr-aging-max-voltage-adjustment = <0x3a98>; | |
qcom,cpr-aging-ref-corner = <0x8>; | |
qcom,cpr-aging-ro-scaling-factor = <0x654>; | |
qcom,allow-aging-voltage-adjustment = <0x0>; | |
qcom,allow-aging-open-loop-voltage-adjustment = <0x1>; | |
linux,phandle = <0x2c>; | |
phandle = <0x2c>; | |
}; | |
}; | |
}; | |
regulator@1fcf004 { | |
compatible = "qcom,mem-acc-regulator"; | |
reg = <0x1fcf004 0x4>; | |
reg-names = "acc-sel-l1"; | |
regulator-name = "gfx_mem_acc_corner"; | |
regulator-min-microvolt = <0x1>; | |
regulator-max-microvolt = <0x2>; | |
qcom,corner-acc-map = <0x1 0x0>; | |
qcom,acc-sel-l1-bit-pos = <0x0>; | |
qcom,acc-sel-l1-bit-size = <0x1>; | |
linux,phandle = <0xcf>; | |
phandle = <0xcf>; | |
}; | |
disp_vddts_vreg { | |
compatible = "regulator-fixed"; | |
regulator-name = "disp_vddts_vreg"; | |
startup-delay-us = <0xfa0>; | |
enable-active-high; | |
gpio = <0x7c 0x32 0x0>; | |
linux,phandle = <0x1eb>; | |
phandle = <0x1eb>; | |
}; | |
fp_vdd_vreg { | |
compatible = "regulator-fixed"; | |
regulator-name = "fp_vdd_vreg"; | |
startup-delay-us = <0xfa0>; | |
enable-active-high; | |
gpio = <0x7c 0x23 0x0>; | |
regulator-always-on; | |
linux,phandle = <0x2a5>; | |
phandle = <0x2a5>; | |
}; | |
fp_d5_vdd_vreg { | |
compatible = "regulator-fixed"; | |
regulator-name = "fp_d5_vdd_vreg"; | |
startup-delay-us = <0xfa0>; | |
enable-active-high; | |
gpio = <0x7c 0x4d 0x0>; | |
}; | |
qcom,spm@178120000 { | |
compatible = "qcom,spm-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x1>; | |
reg = <0x17812000 0x1000>; | |
qcom,name = "gold-l2"; | |
qcom,saw2-ver-reg = <0xfd0>; | |
qcom,cpu-vctl-list = <0x1a 0x1b 0x1c 0x1d>; | |
qcom,vctl-timeout-us = <0x1f4>; | |
qcom,vctl-port = <0x0>; | |
qcom,phase-port = <0x1>; | |
qcom,saw2-avs-ctl = <0x1010031>; | |
qcom,saw2-avs-limit = <0x4700470>; | |
qcom,pfm-port = <0x2>; | |
}; | |
qcom,spm@179120000 { | |
compatible = "qcom,spm-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x1>; | |
reg = <0x17912000 0x1000>; | |
qcom,name = "silver-l2"; | |
qcom,saw2-ver-reg = <0xfd0>; | |
qcom,cpu-vctl-list = <0x16 0x17 0x18 0x19>; | |
qcom,vctl-timeout-us = <0x1f4>; | |
qcom,vctl-port = <0x0>; | |
qcom,phase-port = <0x1>; | |
qcom,saw2-avs-ctl = <0x1010031>; | |
qcom,saw2-avs-limit = <0x4200420>; | |
qcom,pfm-port = <0x2>; | |
}; | |
qcom,lpm-levels { | |
compatible = "qcom,lpm-levels"; | |
qcom,use-psci; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
qcom,pm-cluster@0 { | |
reg = <0x0>; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
label = "system"; | |
qcom,spm-device-names = "cci"; | |
qcom,psci-mode-shift = <0x8>; | |
qcom,psci-mode-mask = <0xf>; | |
qcom,pm-cluster-level@0 { | |
reg = <0x0>; | |
label = "system-wfi"; | |
qcom,psci-mode = <0x0>; | |
qcom,latency-us = <0x64>; | |
qcom,ss-power = <0x2d5>; | |
qcom,energy-overhead = <0x14c08>; | |
qcom,time-overhead = <0x78>; | |
}; | |
qcom,pm-cluster-level@1 { | |
reg = <0x1>; | |
label = "system-pc"; | |
qcom,psci-mode = <0x3>; | |
qcom,latency-us = <0x159e>; | |
qcom,ss-power = <0x18f>; | |
qcom,energy-overhead = <0x32f7f9>; | |
qcom,time-overhead = <0x4168>; | |
qcom,min-child-idx = <0x3>; | |
qcom,is-reset; | |
qcom,notify-rpm; | |
}; | |
qcom,pm-cluster@0 { | |
reg = <0x0>; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
label = "pwr"; | |
qcom,spm-device-names = "l2"; | |
qcom,cpu = <0x16 0x17 0x18 0x19>; | |
qcom,psci-mode-shift = <0x4>; | |
qcom,psci-mode-mask = <0xf>; | |
qcom,pm-cluster-level@0 { | |
reg = <0x0>; | |
label = "pwr-l2-wfi"; | |
qcom,psci-mode = <0x1>; | |
qcom,latency-us = <0x33>; | |
qcom,ss-power = <0x1c4>; | |
qcom,energy-overhead = <0x10eeb>; | |
qcom,time-overhead = <0x63>; | |
}; | |
qcom,pm-cluster-level@1 { | |
reg = <0x1>; | |
label = "pwr-l2-dynret"; | |
qcom,psci-mode = <0x2>; | |
qcom,latency-us = <0x293>; | |
qcom,ss-power = <0x1b2>; | |
qcom,energy-overhead = <0x71b3d>; | |
qcom,time-overhead = <0x3d0>; | |
qcom,min-child-idx = <0x1>; | |
}; | |
qcom,pm-cluster-level@2 { | |
reg = <0x2>; | |
label = "pwr-l2-ret"; | |
qcom,psci-mode = <0x3>; | |
qcom,latency-us = <0x2e7>; | |
qcom,ss-power = <0x1a9>; | |
qcom,energy-overhead = <0x99cb0>; | |
qcom,time-overhead = <0x520>; | |
qcom,min-child-idx = <0x2>; | |
}; | |
qcom,pm-cluster-level@3 { | |
reg = <0x3>; | |
label = "pwr-l2-pc"; | |
qcom,psci-mode = <0x4>; | |
qcom,latency-us = <0x11d2>; | |
qcom,ss-power = <0x198>; | |
qcom,energy-overhead = <0x24f450>; | |
qcom,time-overhead = <0x1500>; | |
qcom,min-child-idx = <0x2>; | |
qcom,is-reset; | |
}; | |
qcom,pm-cpu { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
qcom,psci-mode-shift = <0x0>; | |
qcom,psci-mode-mask = <0xf>; | |
qcom,pm-cpu-level@0 { | |
reg = <0x0>; | |
qcom,spm-cpu-mode = "wfi"; | |
qcom,psci-cpu-mode = <0x1>; | |
qcom,latency-us = <0x2b>; | |
qcom,ss-power = <0x1c6>; | |
qcom,energy-overhead = <0x96ef>; | |
qcom,time-overhead = <0x53>; | |
}; | |
qcom,pm-cpu-level@1 { | |
reg = <0x1>; | |
qcom,psci-cpu-mode = <0x2>; | |
qcom,spm-cpu-mode = "ret"; | |
qcom,latency-us = <0x56>; | |
qcom,ss-power = <0x1c1>; | |
qcom,energy-overhead = <0x13278>; | |
qcom,time-overhead = <0xa7>; | |
}; | |
qcom,pm-cpu-level@2 { | |
reg = <0x2>; | |
qcom,spm-cpu-mode = "pc"; | |
qcom,psci-cpu-mode = <0x3>; | |
qcom,latency-us = <0x264>; | |
qcom,ss-power = <0x1b4>; | |
qcom,energy-overhead = <0x661b1>; | |
qcom,time-overhead = <0x375>; | |
qcom,is-reset; | |
}; | |
}; | |
}; | |
qcom,pm-cluster@1 { | |
reg = <0x1>; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
label = "perf"; | |
qcom,spm-device-names = "l2"; | |
qcom,cpu = <0x1a 0x1b 0x1c 0x1d>; | |
qcom,psci-mode-shift = <0x4>; | |
qcom,psci-mode-mask = <0xf>; | |
qcom,pm-cluster-level@0 { | |
reg = <0x0>; | |
label = "perf-l2-wfi"; | |
qcom,psci-mode = <0x1>; | |
qcom,latency-us = <0x33>; | |
qcom,ss-power = <0x200>; | |
qcom,energy-overhead = <0x18692>; | |
qcom,time-overhead = <0x63>; | |
}; | |
qcom,pm-cluster-level@1 { | |
reg = <0x1>; | |
label = "perf-l2-dynret"; | |
qcom,psci-mode = <0x2>; | |
qcom,latency-us = <0x211>; | |
qcom,ss-power = <0x1d4>; | |
qcom,energy-overhead = <0x7948f>; | |
qcom,time-overhead = <0x367>; | |
qcom,min-child-idx = <0x1>; | |
}; | |
qcom,pm-cluster-level@2 { | |
reg = <0x2>; | |
label = "perf-l2-ret"; | |
qcom,psci-mode = <0x3>; | |
qcom,latency-us = <0x25d>; | |
qcom,ss-power = <0x1c8>; | |
qcom,energy-overhead = <0x91c86>; | |
qcom,time-overhead = <0x401>; | |
qcom,min-child-idx = <0x2>; | |
}; | |
qcom,pm-cluster-level@3 { | |
reg = <0x3>; | |
label = "perf-l2-pc"; | |
qcom,psci-mode = <0x4>; | |
qcom,latency-us = <0x7eb>; | |
qcom,ss-power = <0x1a4>; | |
qcom,energy-overhead = <0x18c898>; | |
qcom,time-overhead = <0xabf>; | |
qcom,min-child-idx = <0x2>; | |
qcom,is-reset; | |
}; | |
qcom,pm-cpu { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
qcom,psci-mode-shift = <0x0>; | |
qcom,psci-mode-mask = <0xf>; | |
qcom,pm-cpu-level@0 { | |
reg = <0x0>; | |
qcom,spm-cpu-mode = "wfi"; | |
qcom,psci-cpu-mode = <0x1>; | |
qcom,latency-us = <0x2b>; | |
qcom,ss-power = <0x203>; | |
qcom,energy-overhead = <0xbd76>; | |
qcom,time-overhead = <0x56>; | |
}; | |
qcom,pm-cpu-level@1 { | |
reg = <0x1>; | |
qcom,psci-cpu-mode = <0x2>; | |
qcom,spm-cpu-mode = "ret"; | |
qcom,latency-us = <0x52>; | |
qcom,ss-power = <0x1f9>; | |
qcom,energy-overhead = <0x180e2>; | |
qcom,time-overhead = <0xa1>; | |
}; | |
qcom,pm-cpu-level@2 { | |
reg = <0x2>; | |
qcom,spm-cpu-mode = "pc"; | |
qcom,psci-cpu-mode = <0x3>; | |
qcom,latency-us = <0x20d>; | |
qcom,ss-power = <0x1dc>; | |
qcom,energy-overhead = <0x766ad>; | |
qcom,time-overhead = <0x35d>; | |
qcom,is-reset; | |
}; | |
}; | |
}; | |
}; | |
}; | |
qcom,rpm-stats@200000 { | |
compatible = "qcom,rpm-stats"; | |
reg = <0x200000 0x1000 0x290014 0x4 0x29001c 0x4>; | |
reg-names = "phys_addr_base", "offset_addr", "heap_phys_addrbase"; | |
qcom,sleep-stats-version = <0x2>; | |
}; | |
qcom,rpm-rail-stats@200000 { | |
compatible = "qcom,rpm-rail-stats"; | |
reg = <0x200000 0x100 0x29000c 0x4>; | |
reg-names = "phys_addr_base", "offset_addr"; | |
}; | |
qcom,rpm-log@200000 { | |
compatible = "qcom,rpm-log"; | |
reg = <0x200000 0x4000 0x290018 0x4>; | |
qcom,rpm-addr-phys = <0x200000>; | |
qcom,offset-version = <0x4>; | |
qcom,offset-page-buffer-addr = <0x24>; | |
qcom,offset-log-len = <0x28>; | |
qcom,offset-log-len-mask = <0x2c>; | |
qcom,offset-page-indices = <0x38>; | |
}; | |
qcom,rpm-master-stats@778150 { | |
compatible = "qcom,rpm-master-stats"; | |
reg = <0x778150 0x5000>; | |
qcom,masters = "APSS", "MPSS", "ADSP", "SLPI", "TZ", "SPSS"; | |
qcom,master-stats-version = <0x2>; | |
qcom,master-offset = <0x1000>; | |
}; | |
memory@0x200000 { | |
compatible = "qcom,rpm-msg-ram"; | |
reg = <0x200000 0x1000 0x290000 0x1000>; | |
linux,phandle = <0xd0>; | |
phandle = <0xd0>; | |
}; | |
rpm-memory@0x778000 { | |
compatible = "qcom,rpm-code-ram"; | |
reg = <0x778000 0x5000>; | |
linux,phandle = <0xd1>; | |
phandle = <0xd1>; | |
}; | |
qcom,system-stats { | |
compatible = "qcom,system-stats"; | |
qcom,rpm-msg-ram = <0xd0>; | |
qcom,rpm-code-ram = <0xd1>; | |
qcom,masters = "APSS", "MPSS", "ADSP", "SLPI", "TZ", "SPSS"; | |
}; | |
qcom,mpm@7781b8 { | |
compatible = "qcom,mpm-v2"; | |
reg = <0x7781b8 0x1000 0x17911008 0x4>; | |
reg-names = "vmpm", "ipc"; | |
interrupts = <0x0 0xab 0x1>; | |
clocks = <0x38 0x94adbf3d>; | |
clock-names = "xo"; | |
qcom,num-mpm-irqs = <0x60>; | |
qcom,ipc-bit-offset = <0x1>; | |
qcom,gic-parent = <0x1>; | |
qcom,gic-map = <0x1f 0xd4 0x2 0xd8 0x34 0x113 0x57 0x166 0x4f 0x17b 0x51 0x17b 0x50 0x180 0xff 0x10 0xff 0x11 0xff 0x12 0xff 0x13 0xff 0x14 0xff 0x15 0xff 0x16 0xff 0x17 0xff 0x18 0xff 0x1c 0xff 0x1d 0xff 0x1e 0xff 0x20 0xff 0x21 0xff 0x22 0xff 0x23 0xff 0x24 0xff 0x27 0xff 0x28 0xff 0x29 0xff 0x2a 0xff 0x2b 0xff 0x2c 0xff 0x2d 0xff 0x2e 0xff 0x2f 0xff 0x30 0xff 0x34 0xff 0x36 0xff 0x37 0xff 0x38 0xff 0x39 0xff 0x3a 0xff 0x3b 0xff 0x3c 0xff 0x3d 0xff 0x3e 0xff 0x3f 0xff 0x40 0xff 0x41 0xff 0x42 0xff 0x43 0xff 0x44 0xff 0x45 0xff 0x46 0xff 0x49 0xff 0x4a 0xff 0x4b 0xff 0x4c 0xff 0x4d 0xff 0x4e 0xff 0x4f 0xff 0x50 0xff 0x51 0xff 0x52 0xff 0x53 0xff 0x54 0xff 0x60 0xff 0x61 0xff 0x62 0xff 0x64 0xff 0x65 0xff 0x66 0xff 0x6a 0xff 0x6b 0xff 0x6d 0xff 0x6e 0xff 0x6f 0xff 0x70 0xff 0x73 0xff 0x74 0xff 0x75 0xff 0x77 0xff 0x7a 0xff 0x7b 0xff 0x7c 0xff 0x7d 0xff 0x7e 0xff 0x7f 0xff 0x80 0xff 0x81 0xff 0x82 0xff 0x83 0xff 0x84 0xff 0x85 0xff 0x86 0xff 0x87 0xff 0x88 0xff 0x89 0xff 0x8a 0xff 0x8b 0xff 0x8c 0xff 0x8d 0xff 0x91 0xff 0x92 0xff 0x93 0xff 0x94 0xff 0x95 0xff 0x97 0xff 0x98 0xff 0x99 0xff 0x9a 0xff 0x9b 0xff 0x9c 0xff 0x9d 0xff 0x9e 0xff 0x9f 0xff 0xa0 0xff 0xa1 0xff 0xa2 0xff 0xa3 0xff 0xa4 0xff 0xa5 0xff 0xa6 0xff 0xa7 0xff 0xa8 0xff 0xa9 0xff 0xaa 0xff 0xab 0xff 0xac 0xff 0xad 0xff 0xb8 0xff 0xb9 0xff 0xba 0xff 0xbc 0xff 0xbd 0xff 0xbe 0xff 0xbf 0xff 0xc0 0xff 0xc2 0xff 0xc3 0xff 0xc4 0xff 0xc5 0xff 0xc7 0xff 0xc8 0xff 0xc9 0xff 0xca 0xff 0xcb 0xff 0xcc 0xff 0xcd 0xff 0xce 0xff 0xcf 0xff 0xd0 0xff 0xd1 0xff 0xd2 0xff 0xd3 0xff 0xd5 0xff 0xd6 0xff 0xd7 0xff 0xd9 0xff 0xda 0xff 0xdb 0xff 0xdc 0xff 0xdd 0xff 0xde 0xff 0xdf 0xff 0xe0 0xff 0xe1 0xff 0xe2 0xff 0xe3 0xff 0xe4 0xff 0xe5 0xff 0xe6 0xff 0xe7 0xff 0xe8 0xff 0xe9 0xff 0xea 0xff 0xeb 0xff 0xec 0xff 0xed 0xff 0xee 0xff 0xef 0xff 0xf0 0xff 0xf1 0xff 0xf2 0xff 0xf3 0xff 0xf4 0xff 0xf5 0xff 0xf6 0xff 0xf7 0xff 0xf8 0xff 0xf9 0xff 0xfa 0xff 0xfb 0xff 0xfc 0xff 0xfd 0xff 0xfe 0xff 0xff 0xff 0x100 0xff 0x101 0xff 0x102 0xff 0x103 0xff 0x104 0xff 0x105 0xff 0x106 0xff 0x107 0xff 0x108 0xff 0x109 0xff 0x10a 0xff 0x10b 0xff 0x10c 0xff 0x10d 0xff 0x10e 0xff 0x10f 0xff 0x110 0xff 0x111 0xff 0x112 0xff 0x114 0xff 0x115 0xff 0x116 0xff 0x117 0xff 0x118 0xff 0x119 0xff 0x11a 0xff 0x11b 0xff 0x11c 0xff 0x11d 0xff 0x11e 0xff 0x11f 0xff 0x120 0xff 0x121 0xff 0x122 0xff 0x123 0xff 0x124 0xff 0x125 0xff 0x126 0xff 0x127 0xff 0x128 0xff 0x129 0xff 0x12a 0xff 0x12b 0xff 0x12c 0xff 0x12d 0xff 0x12e 0xff 0x12f 0xff 0x130 0xff 0x131 0xff 0x132 0xff 0x133 0xff 0x134 0xff 0x136 0xff 0x137 0xff 0x13c 0xff 0x13d 0xff 0x13e 0xff 0x13f 0xff 0x143 0xff 0x144 0xff 0x145 0xff 0x146 0xff 0x147 0xff 0x148 0xff 0x149 0xff 0x14a 0xff 0x14b 0xff 0x14c 0xff 0x14d 0xff 0x14e 0xff 0x14f 0xff 0x150 0xff 0x151 0xff 0x152 0xff 0x153 0xff 0x154 0xff 0x155 0xff 0x156 0xff 0x157 0xff 0x158 0xff 0x159 0xff 0x15a 0xff 0x15b 0xff 0x15c 0xff 0x15e 0xff 0x15f 0xff 0x164 0xff 0x165 0xff 0x167 0xff 0x168 0xff 0x169 0xff 0x16a 0xff 0x16b 0xff 0x16c 0xff 0x16d 0xff 0x16e 0xff 0x17c 0xff 0x17d 0xff 0x17e 0xff 0x17f 0xff 0x181 0xff 0x182 0xff 0x183 0xff 0x184 0xff 0x185 0xff 0x186 0xff 0x187 0xff 0x188 0xff 0x189 0xff 0x18b 0xff 0x18c 0xff 0x18d 0xff 0x18e 0xff 0x18f 0xff 0x190 0xff 0x191 0xff 0x192 0xff 0x193 0xff 0x194 0xff 0x195 0xff 0x196 0xff 0x197 0xff 0x198 0xff 0x199 0xff 0x19a 0xff 0x19b 0xff 0x19c 0xff 0x19d 0xff 0x19e 0xff 0x19f 0xff 0x1a0 0xff 0x1a1 0xff 0x1a2 0xff 0x1a3 0xff 0x1a4 0xff 0x1a5 0xff 0x1a6 0xff 0x1a7 0xff 0x1a8 0xff 0x1a9 0xff 0x1aa 0xff 0x1ab 0xff 0x1ac 0xff 0x1ad 0xff 0x1ae 0xff 0x1af 0xff 0x1b0 0xff 0x1b1 0xff 0x1b2 0xff 0x1b3 0xff 0x1b4 0xff 0x1b5 0xff 0x1b6 0xff 0x1b7 0xff 0x1b8 0xff 0x1b9 0xff 0x1ba 0xff 0x1bb 0xff 0x1bc 0xff 0x1bd 0xff 0x1be 0xff 0x1bf 0xff 0x1c0 0xff 0x1c1 0xff 0x1c2 0xff 0x1c4 0xff 0x1c5 0xff 0x1c6 0xff 0x1c7 0xff 0x1c8 0xff 0x1c9 0xff 0x1ca 0xff 0x1cd 0xff 0x1ce 0xff 0x1cf 0xff 0x1d0 0xff 0x1d1 0xff 0x1d2 0xff 0x1d4 0xff 0x1d5 0xff 0x1d7 0xff 0x1d8 0xff 0x1d9 0xff 0x1dd 0xff 0x1de 0xff 0x1e0 0xff 0x1e1 0xff 0x1e2 0xff 0x1e3 0xff 0x1e4 0xff 0x1e5 0xff 0x1e6 0xff 0x1e7 0xff 0x1e8 0xff 0x1e9 0xff 0x1ea 0xff 0x1ee 0xff 0x1ef 0xff 0x1f0 0xff 0x1f1 0xff 0x1f2 0xff 0x1f3 0xff 0x1f7>; | |
qcom,gpio-parent = <0x7c>; | |
qcom,gpio-map = <0x3 0x1 0x4 0x5 0x5 0x9 0x6 0xb 0x7 0x42 0x8 0x16 0x9 0x18 0xa 0x1a 0xb 0x22 0xc 0x24 0xd 0x25 0xe 0x26 0xf 0x28 0x10 0x2a 0x11 0x2e 0x12 0x32 0xff 0x34 0x13 0x35 0x14 0x36 0x15 0x38 0x16 0x39 0x17 0x3a 0x18 0x3b 0x19 0x3c 0x1a 0x3d 0x1b 0x3e 0x1c 0x3f 0x1d 0x40 0x1e 0x47 0x1f 0x49 0x20 0x4d 0x21 0x4e 0x22 0x4f 0x23 0x50 0x24 0x52 0x25 0x56 0x26 0x5b 0x27 0x5c 0x28 0x5f 0x29 0x61 0x2a 0x65 0x2b 0x68 0x2c 0x6a 0x2d 0x6c 0x2e 0x70 0x2f 0x71 0x30 0x6e 0x32 0x7f 0x33 0x73 0x36 0x74 0x37 0x75 0x38 0x76 0x39 0x77 0x3a 0x78 0x3b 0x79 0x3c 0x7a 0x3d 0x7b 0x3e 0x7c 0x3f 0x7d 0x40 0x7e 0x41 0x81 0x42 0x83 0x43 0x84 0x44 0x85 0x45 0x91>; | |
}; | |
arm,smmu-anoc1@1680000 { | |
status = "ok"; | |
compatible = "qcom,smmu-v2"; | |
reg = <0x1680000 0x10000>; | |
#iommu-cells = <0x0>; | |
qcom,register-save; | |
qcom,skip-init; | |
#global-interrupts = <0x0>; | |
interrupts = <0x0 0x16c 0x1 0x0 0x16d 0x1 0x0 0x16e 0x1 0x0 0x16f 0x1 0x0 0x170 0x1 0x0 0x171 0x1>; | |
qcom,msm-bus,name = "smmu-bus-client-anoc1"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,active-only; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x54 0x274e 0x0 0x0 0x54 0x274e 0x0 0x3e8>; | |
attach-impl-defs = <0x6000 0x3270 0x6060 0x1055 0x6070 0x19 0x6074 0x39 0x6078 0x41 0x607c 0x59 0x6080 0x95 0x6084 0x98 0x6088 0xc0 0x608c 0xc0 0x60f0 0x0 0x60f4 0x2 0x60f8 0x5 0x60fc 0x8 0x6100 0x16 0x6104 0x17 0x6108 0x19 0x610c 0x19 0x6170 0x0 0x6174 0x0 0x6178 0x0 0x617c 0x0 0x6180 0x0 0x6184 0x0 0x6188 0x0 0x618c 0x0 0x6270 0x0 0x6274 0xd 0x6278 0xe 0x627c 0x12 0x6280 0x16 0x6284 0x16 0x6288 0x18 0x628c 0x18 0x62f0 0x18 0x62f4 0x1b 0x62f8 0x1c 0x62fc 0x24 0x6300 0x28 0x6304 0x2b 0x6308 0x31 0x630c 0x31 0x6370 0x31 0x6374 0x34 0x6378 0x35 0x637c 0x47 0x6380 0x4f 0x6384 0x54 0x6388 0x60 0x638c 0x60 0x67a0 0x0 0x67a4 0xa7 0x67a8 0xc0 0x67b0 0x0 0x67b4 0x18 0x67b8 0x7c 0x67d0 0x0 0x67dc 0x4 0x67e0 0x8 0x6800 0x6 0x6900 0x3ff 0x6b64 0x121151 0x6b68 0xbb804080 0x6c00 0x0 0x6c04 0x0 0x6c08 0x0 0x6c0c 0x0 0x6c10 0x0 0x6c14 0x0 0x6c18 0x0 0x6c1c 0x0 0x6c20 0x0 0x6c24 0x0 0x6c28 0x0 0x6c2c 0x0 0x6c30 0x0 0x6c34 0x0 0x6c38 0x0 0x6c3c 0x0 0x6c40 0x0 0x6c44 0x0 0x6c48 0x0 0x6c4c 0x0 0x6c50 0x0 0x6c54 0x0 0x6c58 0x0 0x6c5c 0x0 0x6c60 0x0 0x6c64 0x0 0x6c68 0x0 0x6c6c 0x0 0x6c70 0x0 0x6c74 0x0 0x6c78 0x0 0x6c7c 0x0 0x6c80 0x0 0x6c84 0x1 0x6c88 0x0 0x6c8c 0x0 0x6c90 0x4 0x6c94 0x3 0x6c98 0x2 0x6c9c 0x0 0x6ca0 0x5 0x6ca4 0x5 0x6ca8 0x0 0x6cac 0x0 0x6cb0 0x0 0x6cb4 0x0 0x6cb8 0x0 0x6cbc 0x0 0x6cc0 0x0 0x6cc4 0x0 0x6cc8 0x0 0x6ccc 0x0 0x6cd0 0x0 0x6cd4 0x0 0x6cd8 0x0 0x6cdc 0x0 0x6ce0 0x0 0x6ce4 0x0 0x6ce8 0x0 0x6cec 0x0 0x6cf0 0x0 0x6cf4 0x0 0x6cf8 0x0 0x6cfc 0x0 0x6d00 0x0 0x6d04 0x0 0x6d08 0x0 0x6d0c 0x0 0x6d10 0x0 0x6d14 0x0 0x6d18 0x0 0x6d1c 0x0 0x6d20 0x0 0x6d24 0x0 0x6d28 0x0 0x6d2c 0x0 0x6d30 0x0 0x6d34 0x0 0x6d38 0x0 0x6d3c 0x0 0x6d40 0x0 0x6d44 0x0 0x6d48 0x0 0x6d4c 0x0 0x6d50 0x0 0x6d54 0x0 0x6d58 0x0 0x6d5c 0x0 0x6d60 0x0 0x6d64 0x0 0x6d68 0x0 0x6d6c 0x0 0x6d70 0x0 0x6d74 0x0 0x6d78 0x0 0x6d7c 0x0 0x6d80 0x0 0x6d84 0x0 0x6d88 0x0 0x6d8c 0x0 0x6d90 0x0 0x6d94 0x0 0x6d98 0x0 0x6d9c 0x0 0x6da0 0x0 0x6da4 0x0 0x6da8 0x0 0x6dac 0x0 0x6db0 0x0 0x6db4 0x0 0x6db8 0x0 0x6dbc 0x0 0x6dc0 0x0 0x6dc4 0x0 0x6dc8 0x0 0x6dcc 0x0 0x6dd0 0x0 0x6dd4 0x0 0x6dd8 0x0 0x6ddc 0x0 0x6de0 0x0 0x6de4 0x0 0x6de8 0x0 0x6dec 0x0 0x6df0 0x0 0x6df4 0x0 0x6df8 0x0 0x6dfc 0x0>; | |
linux,phandle = <0x9f>; | |
phandle = <0x9f>; | |
}; | |
arm,smmu-anoc2@16c0000 { | |
status = "ok"; | |
compatible = "qcom,smmu-v2"; | |
reg = <0x16c0000 0x40000>; | |
#iommu-cells = <0x1>; | |
qcom,register-save; | |
qcom,skip-init; | |
#global-interrupts = <0x0>; | |
interrupts = <0x0 0x175 0x1 0x0 0x176 0x1 0x0 0x177 0x1 0x0 0x178 0x1 0x0 0x179 0x1 0x0 0x17a 0x1 0x0 0x1ce 0x1 0x0 0x1cf 0x1 0x0 0x1d0 0x1 0x0 0x1d1 0x1>; | |
qcom,msm-bus,name = "smmu-bus-client-anoc2"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,active-only; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x75 0x2751 0x0 0x0 0x75 0x2751 0x0 0x3e8>; | |
attach-impl-defs = <0x6000 0x3270 0x6060 0x1055 0x6070 0x12 0x6074 0x26 0x6078 0x3a 0x607c 0x3c 0x6080 0x3f 0x6084 0x67 0x6088 0x6c 0x608c 0x74 0x6090 0x7c 0x6094 0x80 0x6098 0xa0 0x609c 0xa0 0x60a0 0xa0 0x60a4 0xa0 0x60a8 0xa0 0x60ac 0xa0 0x60f0 0x0 0x60f4 0x1 0x60f8 0x3 0x60fc 0x4 0x6100 0x5 0x6104 0x7 0x6108 0x8 0x610c 0x10 0x6110 0x10 0x6114 0x10 0x6118 0x12 0x611c 0x12 0x6120 0x12 0x6124 0x12 0x6128 0x12 0x612c 0x12 0x6170 0x0 0x6174 0x0 0x6178 0x0 0x617c 0x0 0x6180 0x0 0x6184 0x0 0x6188 0x0 0x618c 0x0 0x6190 0x0 0x6194 0x0 0x6198 0x0 0x619c 0x0 0x61a0 0x0 0x61a4 0x0 0x61a8 0x0 0x61ac 0x0 0x6270 0x0 0x6274 0x1 0x6278 0x2 0x627c 0x4 0x6280 0x4 0x6284 0x6 0x6288 0x6 0x628c 0x18 0x6290 0x1a 0x6294 0x1a 0x6298 0x1e 0x629c 0x1e 0x62a0 0x1e 0x62a4 0x1e 0x62a8 0x1e 0x62ac 0x1e 0x62f0 0x1e 0x62f4 0x24 0x62f8 0x2a 0x62fc 0x2c 0x6300 0x2d 0x6304 0x33 0x6308 0x34 0x630c 0x3a 0x6310 0x3c 0x6314 0x44 0x6318 0x48 0x631c 0x48 0x6320 0x48 0x6324 0x48 0x6328 0x48 0x632c 0x48 0x6370 0x48 0x6374 0x4d 0x6378 0x52 0x637c 0x56 0x6380 0x59 0x6384 0x63 0x6388 0x68 0x638c 0x70 0x6390 0x78 0x6394 0x88 0x6398 0x90 0x639c 0x90 0x63a0 0x90 0x63a4 0x90 0x63a8 0x90 0x63ac 0x90 0x67a0 0x0 0x67a4 0x8e 0x67a8 0xa0 0x67b0 0x0 0x67b4 0x1e 0x67b8 0xc6 0x67d0 0x0 0x67dc 0x4 0x67e0 0x8 0x6800 0x6 0x6900 0x3ff 0x6b48 0x330331 0x6b4c 0x81 0x6b50 0x1313 0x6b64 0x121155 0x6b68 0xea880920 0x6b70 0x10100101 0x6b74 0xc0c0000 0x6b78 0xc0c0000 0x6b80 0x20012001 0x6b84 0x20012001 0x6c00 0x5 0x6c04 0x0 0x6c08 0x5 0x6c0c 0x0 0x6c10 0x5 0x6c14 0x0 0x6c18 0x5 0x6c1c 0x0 0x6c20 0x5 0x6c24 0x0 0x6c28 0x0 0x6c2c 0x0 0x6c30 0x0 0x6c34 0x0 0x6c38 0x0 0x6c3c 0x0 0x6c40 0x0 0x6c44 0x0 0x6c48 0x0 0x6c4c 0x0 0x6c50 0x0 0x6c54 0x0 0x6c58 0x0 0x6c5c 0x0 0x6c60 0x0 0x6c64 0x0 0x6c68 0x0 0x6c6c 0x0 0x6c70 0x0 0x6c74 0x0 0x6c78 0x0 0x6c7c 0x0 0x6c80 0x0 0x6c84 0x0 0x6c88 0x0 0x6c8c 0x0 0x6c90 0x0 0x6c94 0x0 0x6c98 0x0 0x6c9c 0x0 0x6ca0 0x0 0x6ca4 0x0 0x6ca8 0x0 0x6cac 0x0 0x6cb0 0x0 0x6cb4 0x0 0x6cb8 0x0 0x6cbc 0x0 0x6cc0 0x0 0x6cc4 0x0 0x6cc8 0x0 0x6ccc 0x0 0x6cd0 0x0 0x6cd4 0x0 0x6cd8 0x0 0x6cdc 0x0 0x6ce0 0x0 0x6ce4 0x0 0x6ce8 0x0 0x6cec 0x0 0x6cf0 0x0 0x6cf4 0x0 0x6cf8 0x0 0x6cfc 0x0 0x6d00 0x8 0x6d04 0x0 0x6d08 0x8 0x6d0c 0x0 0x6d10 0x7 0x6d14 0x0 0x6d18 0x3 0x6d1c 0x2 0x6d20 0x4 0x6d24 0x0 0x6d28 0x4 0x6d2c 0x0 0x6d30 0x6 0x6d34 0x0 0x6d38 0x9 0x6d3c 0x0 0x6d40 0x0 0x6d44 0x1 0x6d48 0x4 0x6d4c 0x0 0x6d50 0x4 0x6d54 0x0 0x6d58 0x0 0x6d5c 0x0 0x6d60 0x0 0x6d64 0x0 0x6d68 0x0 0x6d6c 0x0 0x6d70 0x0 0x6d74 0x0 0x6d78 0x0 0x6d7c 0x0 0x6d80 0x0 0x6d84 0x0 0x6d88 0x0 0x6d8c 0x0 0x6d90 0x0 0x6d94 0x0 0x6d98 0x0 0x6d9c 0x0 0x6da0 0x0 0x6da4 0x0 0x6da8 0x0 0x6dac 0x0 0x6db0 0x0 0x6db4 0x0 0x6db8 0x0 0x6dbc 0x0 0x6dc0 0x0 0x6dc4 0x0 0x6dc8 0x0 0x6dcc 0x0 0x6dd0 0x0 0x6dd4 0x0 0x6dd8 0x0 0x6ddc 0x0 0x6de0 0x0 0x6de4 0x0 0x6de8 0x0 0x6dec 0x0 0x6df0 0x0 0x6df4 0x0 0x6df8 0x0 0x6dfc 0x0>; | |
linux,phandle = <0x63>; | |
phandle = <0x63>; | |
}; | |
arm,smmu-lpass_q6@5100000 { | |
status = "ok"; | |
compatible = "qcom,smmu-v2"; | |
reg = <0x5100000 0x40000>; | |
#iommu-cells = <0x1>; | |
qcom,tz-device-id = "LPASS"; | |
qcom,register-save; | |
qcom,skip-init; | |
#global-interrupts = <0x0>; | |
interrupts = <0x0 0xe2 0x4 0x0 0x189 0x4 0x0 0x18a 0x4 0x0 0x18b 0x4 0x0 0x18c 0x4 0x0 0x18d 0x4 0x0 0x18e 0x4 0x0 0x18f 0x4 0x0 0x190 0x4 0x0 0x191 0x4 0x0 0x192 0x4 0x0 0x193 0x4 0x0 0x89 0x4>; | |
vdd-supply = <0xd2>; | |
clocks = <0x38 0xc76f702f>; | |
clock-names = "lpass_q6_smmu_clk"; | |
#clock-cells = <0x1>; | |
attach-impl-defs = <0x6000 0x3270 0x6060 0x1055 0x6070 0xe0 0x6074 0xe0 0x6078 0xe0 0x607c 0xe0 0x60f0 0xc0 0x60f4 0xc8 0x60f8 0xd0 0x60fc 0xd8 0x6170 0x0 0x6174 0x30 0x6178 0x60 0x617c 0x90 0x6270 0x0 0x6274 0x2 0x6278 0x4 0x627c 0x6 0x62f0 0x8 0x62f4 0xe 0x62f8 0x14 0x62fc 0x1a 0x6370 0x20 0x6374 0x40 0x6378 0x60 0x637c 0x80 0x67a0 0x0 0x67a4 0x0 0x67a8 0x20 0x67b0 0x0 0x67b4 0x8 0x67b8 0xc8 0x67d0 0x4 0x67dc 0x8 0x67e0 0x8 0x6800 0x6 0x6900 0x3ff 0x6924 0x202 0x6928 0x10a00 0x6930 0x500 0x6b64 0x121151 0x6b68 0x8a840080 0x6c00 0x0 0x6c04 0x0 0x6c08 0x0 0x6c0c 0x0 0x6c10 0x1 0x6c14 0x1 0x6c18 0x1 0x6c1c 0x1 0x6c20 0x2 0x6c24 0x2 0x6c28 0x2 0x6c2c 0x2 0x6c30 0x3 0x6c34 0x3 0x6c38 0x3 0x6c3c 0x3>; | |
linux,phandle = <0x65>; | |
phandle = <0x65>; | |
}; | |
arm,smmu-mmss@cd00000 { | |
status = "ok"; | |
compatible = "qcom,smmu-v2"; | |
reg = <0xcd00000 0x40000>; | |
#iommu-cells = <0x1>; | |
qcom,register-save; | |
qcom,no-smr-check; | |
qcom,skip-init; | |
#global-interrupts = <0x0>; | |
interrupts = <0x0 0x107 0x4 0x0 0x10a 0x4 0x0 0x10b 0x4 0x0 0x10c 0x4 0x0 0xf4 0x4 0x0 0xf5 0x4 0x0 0xf7 0x4 0x0 0xf8 0x4 0x0 0xf9 0x4 0x0 0xfa 0x4 0x0 0xfb 0x4 0x0 0xfc 0x4 0x0 0xfd 0x4 0x0 0xfe 0x4 0x0 0xff 0x4 0x0 0x100 0x4 0x0 0x104 0x4 0x0 0x105 0x4 0x0 0x106 0x4 0x0 0x110 0x4>; | |
vdd-supply = <0x28>; | |
clocks = <0x27 0x49a394f4 0x27 0x4825baf4 0x27 0xc365ac39>; | |
clock-names = "mmss_mnoc_ahb_clk", "mmss_bimc_smmu_ahb_clk", "mmss_bimc_smmu_axi_clk"; | |
#clock-cells = <0x1>; | |
qcom,msm-bus,name = "smmu-bus-client-mmss"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,active-only; | |
qcom,msm-bus,num-paths = <0x2>; | |
qcom,msm-bus,vectors-KBps = <0x66 0x2d2 0x0 0x0 0x1d 0x200 0x0 0x0 0x66 0x2d2 0x0 0x3e8 0x1d 0x200 0x0 0x3e8>; | |
attach-impl-defs = <0x6000 0x3270 0x6060 0x1055 0x6800 0x6 0x6900 0x3ff 0x6924 0x204 0x6928 0x11002 0x6930 0x800 0x6960 0xffffffff 0x6964 0xffffffff 0x6968 0xffffffff 0x696c 0xffffffff 0x6b48 0x330330 0x6b4c 0x81 0x6b50 0x3333 0x6b54 0x3333 0x6b64 0x1a5555 0x6b68 0x9aaa892a 0x6b70 0x10100002 0x6b74 0x10100002 0x6b78 0x10100002 0x6b80 0x20042004 0x6b84 0x20042004>; | |
linux,phandle = <0xd4>; | |
phandle = <0xd4>; | |
}; | |
arm,smmu-kgsl@5040000 { | |
status = "ok"; | |
compatible = "qcom,smmu-v2"; | |
reg = <0x5040000 0x10000>; | |
#iommu-cells = <0x1>; | |
qcom-tz-device-id = "GPU"; | |
qcom,dynamic; | |
qcom,register-save; | |
qcom,skip-init; | |
#global-interrupts = <0x0>; | |
interrupts = <0x0 0x149 0x4 0x0 0x14a 0x4 0x0 0x14b 0x1>; | |
qcom,deferred-regulator-disable-delay = <0x50>; | |
vdd-supply = <0xd3>; | |
clocks = <0x38 0x72f20a57 0x38 0x3edd69ad 0x38 0x3909459b>; | |
clock-names = "gcc_gpu_cfg_ahb_clk", "gcc_bimc_gfx_clk", "gcc_gpu_bimc_gfx_clk"; | |
#clock-cells = <0x1>; | |
attach-impl-defs = <0x6000 0x2378 0x6060 0x1055 0x6470 0x110011 0x6478 0x0 0x647c 0x1000100 0x6480 0x81108110 0x6484 0x81108110 0x6488 0x3e003e0 0x648c 0x3e003e0 0x6490 0x80008010 0x6494 0x8020 0x649c 0x6 0x6800 0x6 0x6900 0x3ff 0x6924 0x604 0x6928 0x11000 0x6930 0x800 0x6960 0x3 0x6b64 0x1a5551 0x6b68 0x2aaa2f82>; | |
linux,phandle = <0x1a9>; | |
phandle = <0x1a9>; | |
}; | |
iommu_test_device { | |
compatible = "iommu-debug-test"; | |
iommus = <0xd4 0x2a>; | |
}; | |
iommu_coherent_test_device { | |
compatible = "iommu-debug-test"; | |
iommus = <0xd4 0x2b>; | |
dma-coherent; | |
}; | |
qcom,ion { | |
compatible = "qcom,msm-ion"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
qcom,ion-heap@25 { | |
reg = <0x19>; | |
qcom,ion-heap-type = "SYSTEM"; | |
}; | |
qcom,ion-heap@22 { | |
reg = <0x16>; | |
memory-region = <0x64>; | |
qcom,ion-heap-type = "DMA"; | |
}; | |
qcom,ion-heap@27 { | |
reg = <0x1b>; | |
memory-region = <0xd5>; | |
qcom,ion-heap-type = "DMA"; | |
}; | |
qcom,ion-heap@13 { | |
reg = <0xd>; | |
memory-region = <0xd6>; | |
qcom,ion-heap-type = "DMA"; | |
}; | |
qcom,ion-heap@10 { | |
reg = <0xa>; | |
memory-region = <0xd7>; | |
qcom,ion-heap-type = "HYP_CMA"; | |
}; | |
qcom,ion-heap@9 { | |
reg = <0x9>; | |
qcom,ion-heap-type = "SYSTEM_SECURE"; | |
}; | |
}; | |
qcom,msm-cam@8c0000 { | |
compatible = "qcom,msm-cam"; | |
reg = <0x8c0000 0x40000>; | |
reg-names = "msm-cam"; | |
status = "ok"; | |
bus-vectors = "suspend", "svs", "nominal", "turbo"; | |
qcom,bus-votes = <0x0 0x11e1a300 0x2625a000 0x2625a000>; | |
}; | |
qcom,csiphy@ca34000 { | |
cell-index = <0x0>; | |
compatible = "qcom,csiphy-v5.01", "qcom,csiphy"; | |
reg = <0xca34000 0x1000>; | |
reg-names = "csiphy"; | |
interrupts = <0x0 0x4e 0x0>; | |
interrupt-names = "csiphy"; | |
gdscr-supply = <0x29>; | |
bimc_smmu-supply = <0x28>; | |
qcom,cam-vreg-name = "gdscr", "bimc_smmu"; | |
clocks = <0x38 0xdb4b31e6 0x27 0x49a394f4 0x27 0x4825baf4 0x27 0xc365ac39 0x27 0xa51f2c1d 0x27 0x120618d6 0x27 0x227e65bc 0x27 0xccfe39ef 0x27 0x56114361 0x27 0xc8a309be 0x27 0x7a78864e 0x27 0xbda4f0e3 0x27 0x8cceb70a 0x27 0x96c81af8>; | |
clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "csi_src_clk", "csi_clk", "cphy_csid_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; | |
qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x10595550 0x0 0x0 0xbebc200 0x0 0x0 0x10595550 0x0>; | |
status = "ok"; | |
}; | |
qcom,csiphy@ca35000 { | |
cell-index = <0x1>; | |
compatible = "qcom,csiphy-v5.01", "qcom,csiphy"; | |
reg = <0xca35000 0x1000>; | |
reg-names = "csiphy"; | |
interrupts = <0x0 0x4f 0x0>; | |
interrupt-names = "csiphy"; | |
gdscr-supply = <0x29>; | |
bimc_smmu-supply = <0x28>; | |
qcom,cam-vreg-name = "gdscr", "bimc_smmu"; | |
clocks = <0x38 0xdb4b31e6 0x27 0x49a394f4 0x27 0x4825baf4 0x27 0xc365ac39 0x27 0xa51f2c1d 0x27 0x120618d6 0x27 0x6a2a6c36 0x27 0x3eeeaac0 0x27 0x79fbcd8a 0x27 0x7c0fe23a 0x27 0x6e6c1de5 0x27 0xbda4f0e3 0x27 0x8cceb70a 0x27 0xee9ac2bb>; | |
clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "csi_src_clk", "csi_clk", "cphy_csid_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; | |
qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x10595550 0x0 0x0 0xbebc200 0x0 0x0 0x10595550 0x0>; | |
status = "ok"; | |
}; | |
qcom,csiphy@ca36000 { | |
cell-index = <0x2>; | |
compatible = "qcom,csiphy-v5.01", "qcom,csiphy"; | |
reg = <0xca36000 0x1000>; | |
reg-names = "csiphy"; | |
interrupts = <0x0 0x50 0x0>; | |
interrupt-names = "csiphy"; | |
gdscr-supply = <0x29>; | |
bimc_smmu-supply = <0x28>; | |
qcom,cam-vreg-name = "gdscr", "bimc_smmu"; | |
clocks = <0x38 0xdb4b31e6 0x27 0x49a394f4 0x27 0x4825baf4 0x27 0xc365ac39 0x27 0xa51f2c1d 0x27 0x120618d6 0x27 0x4113589f 0x27 0x94524569 0x27 0xf295e3ef 0x27 0x62ffea9c 0x27 0x235e2de 0x27 0xbda4f0e3 0x27 0x8cceb70a 0x27 0x3365e70e>; | |
clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "csi_src_clk", "csi_clk", "cphy_csid_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; | |
qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x10595550 0x0 0x0 0xbebc200 0x0 0x0 0x10595550 0x0>; | |
status = "ok"; | |
}; | |
qcom,csid@ca30000 { | |
cell-index = <0x0>; | |
compatible = "qcom,csid-v5.0", "qcom,csid"; | |
reg = <0xca30000 0x400>; | |
reg-names = "csid"; | |
interrupts = <0x0 0x128 0x0>; | |
interrupt-names = "csid"; | |
qcom,csi-vdd-voltage = <0x124f80>; | |
qcom,mipi-csi-vdd-supply = <0x67>; | |
gdscr-supply = <0x29>; | |
vdd_sec-supply = <0x66>; | |
bimc_smmu-supply = <0x28>; | |
qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; | |
clocks = <0x38 0xdb4b31e6 0x27 0x49a394f4 0x27 0x4825baf4 0x27 0xc365ac39 0x27 0xa51f2c1d 0x27 0x120618d6 0x27 0xbda4f0e3 0x27 0x227e65bc 0x27 0x8cceb70a 0x27 0xccfe39ef 0x27 0x2b58d241 0x27 0x1d5bf83 0x27 0x9e26509d 0x27 0x56114361>; | |
clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", "csi_clk", "csi_ahb_clk", "csi_rdi_clk", "csi_pix_clk", "cphy_csid_clk"; | |
qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x10595550 0x10595550 0x0 0x0 0x0 0x0 0x0>; | |
status = "ok"; | |
}; | |
qcom,csid@ca30400 { | |
cell-index = <0x1>; | |
compatible = "qcom,csid-v5.0", "qcom,csid"; | |
reg = <0xca30400 0x400>; | |
reg-names = "csid"; | |
interrupts = <0x0 0x129 0x0>; | |
interrupt-names = "csid"; | |
qcom,csi-vdd-voltage = <0x124f80>; | |
qcom,mipi-csi-vdd-supply = <0x67>; | |
gdscr-supply = <0x29>; | |
vdd_sec-supply = <0x66>; | |
bimc_smmu-supply = <0x28>; | |
qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; | |
clocks = <0x38 0xdb4b31e6 0x27 0x49a394f4 0x27 0x4825baf4 0x27 0xc365ac39 0x27 0xa51f2c1d 0x27 0x120618d6 0x27 0xbda4f0e3 0x27 0x6a2a6c36 0x27 0x8cceb70a 0x27 0x3eeeaac0 0x27 0x7073244b 0x27 0x43185024 0x27 0xf1375139 0x27 0x79fbcd8a>; | |
clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", "csi_clk", "csi_ahb_clk", "csi_rdi_clk", "csi_pix_clk", "cphy_csid_clk"; | |
qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x10595550 0x10595550 0x0 0x0 0x0 0x0 0x0>; | |
status = "ok"; | |
}; | |
qcom,csid@ca30800 { | |
cell-index = <0x2>; | |
compatible = "qcom,csid-v5.0", "qcom,csid"; | |
reg = <0xca30800 0x400>; | |
reg-names = "csid"; | |
interrupts = <0x0 0x12a 0x0>; | |
interrupt-names = "csid"; | |
qcom,csi-vdd-voltage = <0x124f80>; | |
qcom,mipi-csi-vdd-supply = <0x67>; | |
gdscr-supply = <0x29>; | |
vdd_sec-supply = <0x66>; | |
bimc_smmu-supply = <0x28>; | |
qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; | |
clocks = <0x38 0xdb4b31e6 0x27 0x49a394f4 0x27 0x4825baf4 0x27 0xc365ac39 0x27 0xa51f2c1d 0x27 0x120618d6 0x27 0xbda4f0e3 0x27 0x4113589f 0x27 0x8cceb70a 0x27 0x94524569 0x27 0x681c1479 0x27 0x4bf01dc5 0x27 0xf4de617d 0x27 0xf295e3ef>; | |
clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", "csi_clk", "csi_ahb_clk", "csi_rdi_clk", "csi_pix_clk", "cphy_csid_clk"; | |
qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x10595550 0x10595550 0x0 0x0 0x0 0x0 0x0>; | |
status = "ok"; | |
}; | |
qcom,csid@ca30c00 { | |
cell-index = <0x3>; | |
compatible = "qcom,csid-v5.0", "qcom,csid"; | |
reg = <0xca30c00 0x400>; | |
reg-names = "csid"; | |
interrupts = <0x0 0x12b 0x0>; | |
interrupt-names = "csid"; | |
qcom,csi-vdd-voltage = <0x124f80>; | |
qcom,mipi-csi-vdd-supply = <0x67>; | |
gdscr-supply = <0x29>; | |
vdd_sec-supply = <0x66>; | |
bimc_smmu-supply = <0x28>; | |
qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; | |
clocks = <0x38 0xdb4b31e6 0x27 0x49a394f4 0x27 0x4825baf4 0x27 0xc365ac39 0x27 0xa51f2c1d 0x27 0x120618d6 0x27 0xbda4f0e3 0x27 0xfd934012 0x27 0x8cceb70a 0x27 0x55e4bbae 0x27 0xfae7c29b 0x27 0x6983a4cd 0x27 0xc166a015 0x27 0x100188e9>; | |
clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", "csi_clk", "csi_ahb_clk", "csi_rdi_clk", "csi_pix_clk", "cphy_csid_clk"; | |
qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x10595550 0x10595550 0x0 0x0 0x0 0x0 0x0>; | |
status = "ok"; | |
}; | |
qcom,cam_smmu { | |
compatible = "qcom,msm-cam-smmu"; | |
status = "ok"; | |
msm_cam_smmu_cb1 { | |
compatible = "qcom,msm-cam-smmu-cb"; | |
iommus = <0xd4 0xc00 0xd4 0xc01 0xd4 0xc02 0xd4 0xc03>; | |
label = "vfe"; | |
qcom,scratch-buf-support; | |
}; | |
msm_cam_smmu_cb2 { | |
compatible = "qcom,msm-cam-smmu-cb"; | |
iommus = <0xd4 0xa00>; | |
label = "cpp"; | |
}; | |
msm_cam_smmu_cb3 { | |
compatible = "qcom,msm-cam-smmu-cb"; | |
iommus = <0xd4 0xa01>; | |
label = "camera_fd"; | |
}; | |
msm_cam_smmu_cb4 { | |
compatible = "qcom,msm-cam-smmu-cb"; | |
iommus = <0xd4 0x800>; | |
label = "jpeg_enc0"; | |
}; | |
msm_cam_smmu_cb5 { | |
compatible = "qcom,msm-cam-smmu-cb"; | |
iommus = <0xd4 0x801>; | |
label = "jpeg_dma"; | |
}; | |
}; | |
qcom,fd@caa4000 { | |
cell-index = <0x0>; | |
compatible = "qcom,face-detection"; | |
reg = <0xcaa4000 0x800 0xcaa5000 0x400 0xca80000 0x3000>; | |
reg-names = "fd_core", "fd_misc", "fd_vbif"; | |
interrupts = <0x0 0x125 0x0>; | |
interrupt-names = "fd"; | |
smmu-vdd-supply = <0x28>; | |
camss-vdd-supply = <0x29>; | |
vdd-supply = <0xd8>; | |
qcom,vdd-names = "smmu-vdd", "camss-vdd", "vdd"; | |
clocks = <0x38 0xdb4b31e6 0x27 0x49a394f4 0x27 0x4825baf4 0x27 0xc365ac39 0x27 0xa51f2c1d 0x27 0x120618d6 0x27 0x749e7eb0 0x27 0x8ea480c5 0x27 0x4ff1da4d 0x27 0xd84e390b 0x27 0x1b33a88e>; | |
clock-names = "mmssnoc_axi", "mmss_mnoc_ahb_clk", "mmss_bimc_smmu_ahb_clk", "mmss_bimc_smmu_axi_clk", "mmss_camss_ahb_clk", "mmss_camss_top_ahb_clk", "mmss_fd_core_clk", "mmss_fd_core_uar_clk", "mmss_fd_ahb_clk", "mmss_camss_cpp_axi_clk", "mmss_camss_cpp_vbif_ahb_clk"; | |
qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x18148d00 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x5f5e100 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x18148d00 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x18148d00 0x0 0x0 0x0 0x0>; | |
qcom,msm-bus,name = "msm_camera_fd"; | |
qcom,msm-bus,num-cases = <0x4>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x6a 0x200 0x0 0x0 0x6a 0x200 0x659 0x0 0x6a 0x200 0xbb3 0x0 0x6a 0x200 0x1c20 0x0>; | |
qcom,fd-vbif-reg-settings = <0x20 0x10000000 0x30000000 0x24 0x10000000 0x30000000 0x28 0x10000000 0x30000000 0x2c 0x10000000 0x30000000>; | |
qcom,fd-misc-reg-settings = <0x20 0x2 0x3 0x24 0x2 0x3>; | |
status = "ok"; | |
}; | |
qcom,cpp@ca04000 { | |
cell-index = <0x0>; | |
compatible = "qcom,cpp"; | |
reg = <0xca04000 0x100 0xca80000 0x3000 0xca18000 0x3000 0xc8c36d4 0x4>; | |
reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp"; | |
interrupts = <0x0 0x126 0x0>; | |
interrupt-names = "cpp"; | |
smmu-vdd-supply = <0x28>; | |
camss-vdd-supply = <0x29>; | |
vdd-supply = <0xd8>; | |
qcom,vdd-names = "smmu-vdd", "camss-vdd", "vdd"; | |
clocks = <0x38 0xdb4b31e6 0x27 0x49a394f4 0x27 0xa51f2c1d 0x27 0x120618d6 0x27 0x8382f56d 0x27 0x8e99ef57 0x27 0xd5554f15 0x27 0xd84e390b 0x27 0x6c6fd3c7 0x27 0xc365ac39 0x27 0x1b33a88e>; | |
clock-names = "mmssnoc_axi_clk", "mnoc_ahb_clk", "camss_ahb_clk", "camss_top_ahb_clk", "cpp_src_clk", "cpp_core_clk", "camss_cpp_ahb_clk", "camss_cpp_axi_clk", "micro_iface_clk", "mmss_smmu_axi_clk", "cpp_vbif_ahb_clk"; | |
qcom,clock-rates = <0x0 0x0 0x0 0x0 0xbebc200 0xbebc200 0x0 0x0 0x0 0x0 0x0>; | |
qcom,min-clock-rate = <0xbebc200>; | |
qcom,bus-master = <0x1>; | |
qcom,vbif-qos-setting = <0x20 0x10000000 0x24 0x10000000 0x28 0x10000000 0x2c 0x10000000>; | |
status = "ok"; | |
qcom,msm-bus,name = "msm_camera_cpp"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x6a 0x200 0x0 0x0 0x6a 0x200 0x0 0x0>; | |
qcom,msm-bus-vector-dyn-vote; | |
resets = <0x27 0x0>; | |
reset-names = "micro_iface_reset"; | |
qcom,src-clock-rates = <0x5f5e100 0xbebc200 0x16e36000 0x18148d00 0x1c9c3800 0x22551000 0x23c34600>; | |
qcom,micro-reset; | |
qcom,cpp-fw-payload-info { | |
qcom,stripe-base = <0x316>; | |
qcom,plane-base = <0x2cb>; | |
qcom,stripe-size = <0x3f>; | |
qcom,plane-size = <0x19>; | |
qcom,fe-ptr-off = <0xb>; | |
qcom,we-ptr-off = <0x17>; | |
qcom,ref-fe-ptr-off = <0x11>; | |
qcom,ref-we-ptr-off = <0x24>; | |
qcom,we-meta-ptr-off = <0x2a>; | |
qcom,fe-mmu-pf-ptr-off = <0x7>; | |
qcom,ref-fe-mmu-pf-ptr-off = <0xa>; | |
qcom,we-mmu-pf-ptr-off = <0xd>; | |
qcom,dup-we-mmu-pf-ptr-off = <0x12>; | |
qcom,ref-we-mmu-pf-ptr-off = <0x17>; | |
qcom,set-group-buffer-len = <0x87>; | |
qcom,dup-frame-indicator-off = <0x46>; | |
}; | |
}; | |
qcom,ispif@ca31000 { | |
cell-index = <0x0>; | |
compatible = "qcom,ispif-v3.0", "qcom,ispif"; | |
reg = <0xca31000 0xc00 0xca00020 0x4>; | |
reg-names = "ispif", "csi_clk_mux"; | |
interrupts = <0x0 0x135 0x0>; | |
interrupt-names = "ispif"; | |
qcom,num-isps = <0x2>; | |
camss-vdd-supply = <0x29>; | |
vfe0-vdd-supply = <0xd9>; | |
vfe1-vdd-supply = <0xda>; | |
qcom,vdd-names = "camss-vdd", "vfe0-vdd", "vfe1-vdd"; | |
qcom,clock-cntl-support; | |
clocks = <0x38 0xdb4b31e6 0x27 0x49a394f4 0x27 0xa51f2c1d 0x27 0x120618d6 0x27 0xbda4f0e3 0x27 0x227e65bc 0x27 0x6a2a6c36 0x27 0x4113589f 0x27 0xfd934012 0x27 0x1d5bf83 0x27 0x43185024 0x27 0x4bf01dc5 0x27 0x6983a4cd 0x27 0x9e26509d 0x27 0xf1375139 0x27 0xf4de617d 0x27 0xc166a015 0x27 0xccfe39ef 0x27 0x3eeeaac0 0x27 0x94524569 0x27 0x55e4bbae 0x27 0xa0c2bd8f 0x27 0xead28288 0x27 0x3b30b798 0x27 0x4e357366 0x27 0xc216b14d 0x27 0xfe729af7>; | |
clock-names = "mmssnoc_axi", "mnoc_ahb_clk", "camss_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csi0_src_clk", "csi1_src_clk", "csi2_src_clk", "csi3_src_clk", "csi0_rdi_clk", "csi1_rdi_clk", "csi2_rdi_clk", "csi3_rdi_clk", "csi0_pix_clk", "csi1_pix_clk", "csi2_pix_clk", "csi3_pix_clk", "camss_csi0_clk", "camss_csi1_clk", "camss_csi2_clk", "camss_csi3_clk", "vfe0_clk_src", "camss_vfe_vfe0_clk", "camss_csi_vfe0_clk", "vfe1_clk_src", "camss_vfe_vfe1_clk", "camss_csi_vfe1_clk"; | |
qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; | |
qcom,clock-control = "INIT_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "INIT_RATE", "INIT_RATE", "INIT_RATE", "INIT_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "INIT_RATE", "INIT_RATE", "NO_SET_RATE", "INIT_RATE", "INIT_RATE", "NO_SET_RATE"; | |
status = "ok"; | |
}; | |
qcom,vfe0@ca10000 { | |
cell-index = <0x0>; | |
compatible = "qcom,vfe48"; | |
reg = <0xca10000 0x4000 0xca40000 0x3000>; | |
reg-names = "vfe", "vfe_vbif"; | |
interrupts = <0x0 0x13a 0x0>; | |
interrupt-names = "vfe"; | |
vdd-supply = <0xd9>; | |
camss-vdd-supply = <0x29>; | |
smmu-vdd-supply = <0x28>; | |
qcom,vdd-names = "vdd", "camss-vdd", "smmu-vdd"; | |
clocks = <0x38 0xdb4b31e6 0x27 0x49a394f4 0x27 0x4825baf4 0x27 0xc365ac39 0x27 0xa51f2c1d 0x27 0x120618d6 0x27 0xa0c2bd8f 0x27 0xead28288 0x27 0xa0428287 0x27 0x137bd0bd 0x27 0x109a9c6 0x27 0xe626d8a1 0x27 0x3b30b798>; | |
clock-names = "mmssnoc_axi", "mnoc_ahb_clk", "bimc_smmu_ahb_clk", "bimc_smmu_axi_clk", "camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src", "camss_vfe_clk", "camss_vfe_stream_clk", "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", "camss_vfe_vbif_axi_clk", "camss_csi_vfe_clk"; | |
qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x1c9c3800 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x22551000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x23c34600 0x0 0x0 0x0 0x0 0x0 0x0>; | |
status = "ok"; | |
qos-entries = <0x8>; | |
qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 0x41c 0x420>; | |
qos-settings = <0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9>; | |
vbif-entries = <0x1>; | |
vbif-regs = <0x124>; | |
vbif-settings = <0x3>; | |
ds-entries = <0x11>; | |
ds-regs = <0x424 0x428 0x42c 0x430 0x434 0x438 0x43c 0x440 0x444 0x448 0x44c 0x450 0x454 0x458 0x45c 0x460 0x464>; | |
ds-settings = <0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0x40000103>; | |
qcom,msm-bus,name = "msm_camera_vfe"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x1d 0x200 0x0 0x0 0x1d 0x200 0x5f5e100 0x5f5e100>; | |
qcom,msm-bus-vector-dyn-vote; | |
}; | |
qcom,vfe1@ca14000 { | |
cell-index = <0x1>; | |
compatible = "qcom,vfe48"; | |
reg = <0xca14000 0x4000 0xca40000 0x3000>; | |
reg-names = "vfe", "vfe_vbif"; | |
interrupts = <0x0 0x13b 0x0>; | |
interrupt-names = "vfe"; | |
vdd-supply = <0xda>; | |
camss-vdd-supply = <0x29>; | |
smmu-vdd-supply = <0x28>; | |
qcom,vdd-names = "vdd", "camss-vdd", "smmu-vdd"; | |
clocks = <0x38 0xdb4b31e6 0x27 0x49a394f4 0x27 0x4825baf4 0x27 0xc365ac39 0x27 0xa51f2c1d 0x27 0x120618d6 0x27 0x4e357366 0x27 0xc216b14d 0x27 0x745af3b6 0x27 0xac0154c0 0x27 0x109a9c6 0x27 0xe626d8a1 0x27 0xfe729af7>; | |
clock-names = "mmssnoc_axi", "mnoc_ahb_clk", "bimc_smmu_ahb_clk", "bimc_smmu_axi_clk", "camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src", "camss_vfe_clk", "camss_vfe_stream_clk", "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", "camss_vfe_vbif_axi_clk", "camss_csi_vfe_clk"; | |
qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x1c9c3800 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x22551000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x23c34600 0x0 0x0 0x0 0x0 0x0 0x0>; | |
status = "ok"; | |
qos-entries = <0x8>; | |
qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 0x41c 0x420>; | |
qos-settings = <0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9>; | |
vbif-entries = <0x1>; | |
vbif-regs = <0x124>; | |
vbif-settings = <0x3>; | |
ds-entries = <0x11>; | |
ds-regs = <0x424 0x428 0x42c 0x430 0x434 0x438 0x43c 0x440 0x444 0x448 0x44c 0x450 0x454 0x458 0x45c 0x460 0x464>; | |
ds-settings = <0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0x40000103>; | |
qcom,msm-bus,name = "msm_camera_vfe"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x1d 0x200 0x0 0x0 0x1d 0x200 0x5f5e100 0x5f5e100>; | |
qcom,msm-bus-vector-dyn-vote; | |
}; | |
qcom,vfe { | |
compatible = "qcom,vfe"; | |
num_child = <0x2>; | |
}; | |
qcom,cci@ca0c000 { | |
cell-index = <0x0>; | |
compatible = "qcom,cci"; | |
reg = <0xca0c000 0x4000>; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "cci"; | |
interrupts = <0x0 0x127 0x0>; | |
interrupt-names = "cci"; | |
status = "ok"; | |
mmagic-supply = <0x28>; | |
gdscr-supply = <0x29>; | |
qcom,cam-vreg-name = "mmagic", "gdscr"; | |
clocks = <0x38 0xdb4b31e6 0x27 0x49a394f4 0x27 0x4825baf4 0x27 0xc365ac39 0x27 0xa51f2c1d 0x27 0x120618d6 0x27 0x822f3d97 0x27 0xfda8bb6a 0x27 0x71bb5c97>; | |
clock-names = "mmssnoc_axi", "mnoc_ahb", "smmu_ahb", "smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "cci_src_clk", "cci_ahb_clk", "camss_cci_clk"; | |
qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x124f800 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x23c3460 0x0 0x0>; | |
pinctrl-names = "cci_default", "cci_suspend"; | |
pinctrl-0 = <0xdb 0xdc>; | |
pinctrl-1 = <0xdd 0xde>; | |
gpios = <0x7c 0x11 0x0 0x7c 0x12 0x0 0x7c 0x13 0x0 0x7c 0x14 0x0>; | |
qcom,gpio-tbl-num = <0x0 0x1 0x2 0x3>; | |
qcom,gpio-tbl-flags = <0x1 0x1 0x1 0x1>; | |
qcom,gpio-tbl-label = "CCI_I2C_DATA0", "CCI_I2C_CLK0", "CCI_I2C_DATA1", "CCI_I2C_CLK1"; | |
qcom,i2c_standard_mode { | |
status = "ok"; | |
qcom,hw-thigh = <0xc9>; | |
qcom,hw-tlow = <0xae>; | |
qcom,hw-tsu-sto = <0xcc>; | |
qcom,hw-tsu-sta = <0xe7>; | |
qcom,hw-thd-dat = <0x16>; | |
qcom,hw-thd-sta = <0xa2>; | |
qcom,hw-tbuf = <0xe3>; | |
qcom,hw-scl-stretch-en = <0x1>; | |
qcom,hw-trdhld = <0x6>; | |
qcom,hw-tsp = <0x3>; | |
qcom,cci-clk-src = <0x23c3460>; | |
}; | |
qcom,i2c_fast_mode { | |
status = "ok"; | |
qcom,hw-thigh = <0x26>; | |
qcom,hw-tlow = <0x38>; | |
qcom,hw-tsu-sto = <0x28>; | |
qcom,hw-tsu-sta = <0x28>; | |
qcom,hw-thd-dat = <0x16>; | |
qcom,hw-thd-sta = <0x23>; | |
qcom,hw-tbuf = <0x3e>; | |
qcom,hw-scl-stretch-en = <0x1>; | |
qcom,hw-trdhld = <0x6>; | |
qcom,hw-tsp = <0x3>; | |
qcom,cci-clk-src = <0x23c3460>; | |
}; | |
qcom,i2c_custom_mode { | |
status = "ok"; | |
qcom,hw-thigh = <0x26>; | |
qcom,hw-tlow = <0x38>; | |
qcom,hw-tsu-sto = <0x28>; | |
qcom,hw-tsu-sta = <0x28>; | |
qcom,hw-thd-dat = <0x16>; | |
qcom,hw-thd-sta = <0x23>; | |
qcom,hw-tbuf = <0x3e>; | |
qcom,hw-scl-stretch-en = <0x1>; | |
qcom,hw-trdhld = <0x6>; | |
qcom,hw-tsp = <0x3>; | |
qcom,cci-clk-src = <0x23c3460>; | |
}; | |
qcom,i2c_fast_plus_mode { | |
status = "ok"; | |
qcom,hw-thigh = <0x10>; | |
qcom,hw-tlow = <0x16>; | |
qcom,hw-tsu-sto = <0x11>; | |
qcom,hw-tsu-sta = <0x12>; | |
qcom,hw-thd-dat = <0x10>; | |
qcom,hw-thd-sta = <0xf>; | |
qcom,hw-tbuf = <0x18>; | |
qcom,hw-scl-stretch-en = <0x0>; | |
qcom,hw-trdhld = <0x3>; | |
qcom,hw-tsp = <0x3>; | |
qcom,cci-clk-src = <0x23c3460>; | |
}; | |
qcom,actuator@0 { | |
cell-index = <0x0>; | |
reg = <0x0>; | |
compatible = "qcom,actuator"; | |
qcom,cci-master = <0x0>; | |
cam_vio-supply = <0xdf>; | |
cam_vaf-supply = <0xe0>; | |
qcom,cam-vreg-name = "cam_vio", "cam_vaf"; | |
qcom,cam-vreg-min-voltage = <0x0 0x2ab980>; | |
qcom,cam-vreg-max-voltage = <0x0 0x2ab980>; | |
qcom,cam-vreg-op-mode = <0x0 0x186a0>; | |
linux,phandle = <0xed>; | |
phandle = <0xed>; | |
}; | |
qcom,actuator@1 { | |
cell-index = <0x1>; | |
reg = <0x1>; | |
compatible = "qcom,actuator"; | |
qcom,cci-master = <0x1>; | |
cam_vio-supply = <0xdf>; | |
cam_vaf-supply = <0xe0>; | |
qcom,cam-vreg-name = "cam_vio", "cam_vaf"; | |
qcom,cam-vreg-min-voltage = <0x0 0x2ab980>; | |
qcom,cam-vreg-max-voltage = <0x0 0x2ab980>; | |
qcom,cam-vreg-op-mode = <0x0 0x186a0>; | |
linux,phandle = <0xf0>; | |
phandle = <0xf0>; | |
}; | |
qcom,ois@0 { | |
cell-index = <0x0>; | |
reg = <0x0>; | |
compatible = "qcom,ois"; | |
qcom,cci-master = <0x0>; | |
cam_vaf-supply = <0xe0>; | |
qcom,cam-vreg-name = "cam_vaf"; | |
qcom,cam-vreg-min-voltage = <0x2ab980>; | |
qcom,cam-vreg-max-voltage = <0x2ab980>; | |
qcom,cam-vreg-op-mode = <0x186a0>; | |
linux,phandle = <0xef>; | |
phandle = <0xef>; | |
}; | |
qcom,eeprom@0 { | |
cell-index = <0x0>; | |
reg = <0x0>; | |
qcom,eeprom-name = "sagit_imx386_semco"; | |
compatible = "qcom,eeprom"; | |
qcom,slave-addr = <0xa0>; | |
qcom,i2c-freq-mode = <0x1>; | |
qcom,num-blocks = <0x1>; | |
qcom,page0 = <0x0 0x0 0x0 0x0 0x0 0x0>; | |
qcom,poll0 = <0x0 0x0 0x0 0x0 0x0 0x0>; | |
qcom,mem0 = <0x1b7f 0x0 0x2 0x0 0x1 0x0>; | |
cam_vio-supply = <0xdf>; | |
cam_vdig-supply = <0xe1>; | |
cam_vana-supply = <0xe2>; | |
qcom,cam-vreg-name = "cam_vio", "cam_vdig", "cam_vana"; | |
qcom,cam-vreg-min-voltage = <0x0 0xf4240 0x27ac40>; | |
qcom,cam-vreg-max-voltage = <0x0 0x124f80 0x2c4020>; | |
qcom,cam-vreg-op-mode = <0x0 0x10c8e0 0x2ab980>; | |
qcom,cam-power-seq-type = "sensor_vreg"; | |
qcom,cam-power-seq-val = "cam_vio"; | |
qcom,cam-power-seq-cfg-val = <0x1>; | |
qcom,cam-power-seq-delay = <0x1>; | |
qcom,gpio-no-mux = <0x0>; | |
pinctrl-names = "cam_default", "cam_suspend"; | |
pinctrl-0 = <0xe3 0xe4>; | |
pinctrl-1 = <0xe5 0xe6>; | |
gpios = <0x7c 0xd 0x0 0x7c 0x1e 0x0>; | |
qcom,gpio-reset = <0x1>; | |
qcom,gpio-req-tbl-num = <0x0 0x1>; | |
qcom,gpio-req-tbl-flags = <0x1 0x0>; | |
qcom,gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; | |
qcom,sensor-position = <0x0>; | |
qcom,sensor-mode = <0x0>; | |
qcom,cci-master = <0x0>; | |
status = "ok"; | |
clocks = <0x27 0x266b3853 0x27 0x56293a7>; | |
clock-names = "cam_src_clk", "cam_clk"; | |
qcom,clock-rates = <0x16e3600 0x0>; | |
linux,phandle = <0xee>; | |
phandle = <0xee>; | |
}; | |
qcom,eeprom@1 { | |
cell-index = <0x1>; | |
reg = <0x1>; | |
qcom,eeprom-name = "sagit_s5k3m3_semco"; | |
compatible = "qcom,eeprom"; | |
qcom,slave-addr = <0xa0>; | |
qcom,i2c-freq-mode = <0x1>; | |
qcom,num-blocks = <0x1>; | |
qcom,page0 = <0x0 0x0 0x0 0x0 0x0 0x0>; | |
qcom,poll0 = <0x0 0x0 0x0 0x0 0x0 0x0>; | |
qcom,mem0 = <0x1330 0x0 0x2 0x0 0x1 0x0>; | |
cam_vio-supply = <0xdf>; | |
cam_vdig-supply = <0xe1>; | |
cam_vana-supply = <0xe2>; | |
qcom,cam-vreg-name = "cam_vio", "cam_vdig", "cam_vana"; | |
qcom,cam-vreg-min-voltage = <0x0 0xf4240 0x2ab980>; | |
qcom,cam-vreg-max-voltage = <0x0 0x10c8e0 0x2ab980>; | |
qcom,cam-vreg-op-mode = <0x0 0x10c8e0 0x2ab980>; | |
qcom,cam-power-seq-type = "sensor_vreg"; | |
qcom,cam-power-seq-val = "cam_vio"; | |
qcom,cam-power-seq-cfg-val = <0x1>; | |
qcom,cam-power-seq-delay = <0x1>; | |
qcom,gpio-no-mux = <0x0>; | |
pinctrl-names = "cam_default", "cam_suspend"; | |
pinctrl-0 = <0xe3 0xe4>; | |
pinctrl-1 = <0xe5 0xe6>; | |
gpios = <0x7c 0xd 0x0 0x7c 0x1e 0x0>; | |
qcom,gpio-reset = <0x1>; | |
qcom,gpio-req-tbl-num = <0x0 0x1>; | |
qcom,gpio-req-tbl-flags = <0x1 0x0>; | |
qcom,gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; | |
qcom,sensor-position = <0x0>; | |
qcom,sensor-mode = <0x0>; | |
qcom,cci-master = <0x0>; | |
status = "ok"; | |
clocks = <0x27 0x266b3853 0x27 0x56293a7>; | |
clock-names = "cam_src_clk", "cam_clk"; | |
qcom,clock-rates = <0x16e3600 0x0>; | |
linux,phandle = <0xf1>; | |
phandle = <0xf1>; | |
}; | |
qcom,eeprom@2 { | |
cell-index = <0x2>; | |
reg = <0x2>; | |
qcom,eeprom-name = "sagit_imx268_primax"; | |
compatible = "qcom,eeprom"; | |
qcom,slave-addr = <0x34>; | |
qcom,i2c-freq-mode = <0x1>; | |
qcom,num-blocks = <0x4>; | |
qcom,saddr0 = <0x34>; | |
qcom,page0 = <0x1 0xa02 0x2 0x0 0x1 0x0>; | |
qcom,pageen0 = <0x1 0xa00 0x2 0x1 0x1 0x0>; | |
qcom,poll0 = <0x0 0x0 0x0 0x0 0x0 0x0>; | |
qcom,mem0 = <0x40 0xa04 0x2 0x0 0x1 0x0>; | |
qcom,saddr1 = <0x34>; | |
qcom,page1 = <0x1 0xa02 0x2 0x1 0x1 0x0>; | |
qcom,pageen1 = <0x1 0xa00 0x2 0x1 0x1 0x0>; | |
qcom,poll1 = <0x0 0x0 0x0 0x0 0x0 0x0>; | |
qcom,mem1 = <0x40 0xa04 0x2 0x0 0x1 0x0>; | |
qcom,saddr2 = <0x34>; | |
qcom,page2 = <0x1 0xa02 0x2 0x2 0x1 0x0>; | |
qcom,pageen2 = <0x1 0xa00 0x2 0x1 0x1 0x0>; | |
qcom,poll2 = <0x0 0x0 0x0 0x0 0x0 0x0>; | |
qcom,mem2 = <0x40 0xa04 0x2 0x0 0x1 0x0>; | |
qcom,saddr3 = <0x34>; | |
qcom,page3 = <0x1 0xa02 0x2 0x3 0x1 0x0>; | |
qcom,pageen3 = <0x1 0xa00 0x2 0x1 0x1 0x0>; | |
qcom,poll3 = <0x0 0x0 0x0 0x0 0x0 0x0>; | |
qcom,mem3 = <0x40 0xa04 0x2 0x0 0x1 0x0>; | |
cam_vio-supply = <0xdf>; | |
cam_vana-supply = <0xe7>; | |
qcom,cam-vreg-name = "cam_vio", "cam_vana"; | |
qcom,cam-vreg-min-voltage = <0x0 0x2bb380>; | |
qcom,cam-vreg-max-voltage = <0x0 0x2bb380>; | |
qcom,cam-vreg-op-mode = <0x0 0x13880>; | |
qcom,cam-power-seq-type = "sensor_gpio", "sensor_gpio", "sensor_gpio", "sensor_vreg", "sensor_vreg", "sensor_clk", "sensor_gpio", "sensor_gpio"; | |
qcom,cam-power-seq-val = "sensor_gpio_reset", "sensor_gpio_standby", "sensor_gpio_vdig", "cam_vio", "cam_vana", "sensor_cam_mclk", "sensor_gpio_reset", "sensor_gpio_standby"; | |
qcom,cam-power-seq-cfg-val = <0x0 0x0 0x1 0x1 0x2bb380 0x16e3600 0x1 0x1>; | |
qcom,cam-power-seq-delay = <0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1>; | |
qcom,gpio-no-mux = <0x0>; | |
pinctrl-names = "cam_default", "cam_suspend"; | |
pinctrl-0 = <0xe8 0xe9>; | |
pinctrl-1 = <0xea 0xeb>; | |
gpios = <0x7c 0xe 0x0 0x7c 0x1b 0x0 0x7c 0x1c 0x0 0x8f 0x9 0x0>; | |
qcom,gpio-standby = <0x1>; | |
qcom,gpio-reset = <0x2>; | |
qcom,gpio-vdig = <0x3>; | |
qcom,gpio-req-tbl-num = <0x0 0x1 0x2 0x3>; | |
qcom,gpio-req-tbl-flags = <0x1 0x0 0x0 0x0>; | |
qcom,gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_STANDBY1", "CAM_RESET1", "CAM_VDIG"; | |
qcom,cci-master = <0x1>; | |
status = "ok"; | |
clocks = <0x27 0xa73cad0c 0x27 0x96c7b69b>; | |
clock-names = "cam_src_clk", "cam_clk"; | |
qcom,clock-rates = <0x16e3600 0x0>; | |
linux,phandle = <0xf6>; | |
phandle = <0xf6>; | |
}; | |
qcom,eeprom@3 { | |
cell-index = <0x3>; | |
reg = <0x3>; | |
qcom,eeprom-name = "sagit_imx268_liteon"; | |
compatible = "qcom,eeprom"; | |
qcom,slave-addr = <0x34>; | |
qcom,i2c-freq-mode = <0x1>; | |
qcom,num-blocks = <0x4>; | |
qcom,saddr0 = <0x34>; | |
qcom,page0 = <0x1 0xa02 0x2 0x0 0x1 0x0>; | |
qcom,pageen0 = <0x1 0xa00 0x2 0x1 0x1 0x0>; | |
qcom,poll0 = <0x0 0x0 0x0 0x0 0x0 0x0>; | |
qcom,mem0 = <0x40 0xa04 0x2 0x0 0x1 0x0>; | |
qcom,saddr1 = <0x34>; | |
qcom,page1 = <0x1 0xa02 0x2 0x1 0x1 0x0>; | |
qcom,pageen1 = <0x1 0xa00 0x2 0x1 0x1 0x0>; | |
qcom,poll1 = <0x0 0x0 0x0 0x0 0x0 0x0>; | |
qcom,mem1 = <0x40 0xa04 0x2 0x0 0x1 0x0>; | |
qcom,saddr2 = <0x34>; | |
qcom,page2 = <0x1 0xa02 0x2 0x2 0x1 0x0>; | |
qcom,pageen2 = <0x1 0xa00 0x2 0x1 0x1 0x0>; | |
qcom,poll2 = <0x0 0x0 0x0 0x0 0x0 0x0>; | |
qcom,mem2 = <0x40 0xa04 0x2 0x0 0x1 0x0>; | |
qcom,saddr3 = <0x34>; | |
qcom,page3 = <0x1 0xa02 0x2 0x3 0x1 0x0>; | |
qcom,pageen3 = <0x1 0xa00 0x2 0x1 0x1 0x0>; | |
qcom,poll3 = <0x0 0x0 0x0 0x0 0x0 0x0>; | |
qcom,mem3 = <0x40 0xa04 0x2 0x0 0x1 0x0>; | |
cam_vio-supply = <0xdf>; | |
cam_vana-supply = <0xe7>; | |
qcom,cam-vreg-name = "cam_vio", "cam_vana"; | |
qcom,cam-vreg-min-voltage = <0x0 0x2bb380>; | |
qcom,cam-vreg-max-voltage = <0x0 0x2bb380>; | |
qcom,cam-vreg-op-mode = <0x0 0x13880>; | |
qcom,cam-power-seq-type = "sensor_gpio", "sensor_gpio", "sensor_gpio", "sensor_vreg", "sensor_vreg", "sensor_clk", "sensor_gpio", "sensor_gpio"; | |
qcom,cam-power-seq-val = "sensor_gpio_reset", "sensor_gpio_standby", "sensor_gpio_vdig", "cam_vio", "cam_vana", "sensor_cam_mclk", "sensor_gpio_reset", "sensor_gpio_standby"; | |
qcom,cam-power-seq-cfg-val = <0x0 0x0 0x1 0x1 0x2bb380 0x16e3600 0x1 0x1>; | |
qcom,cam-power-seq-delay = <0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1>; | |
qcom,gpio-no-mux = <0x0>; | |
pinctrl-names = "cam_default", "cam_suspend"; | |
pinctrl-0 = <0xe8 0xe9>; | |
pinctrl-1 = <0xea 0xeb>; | |
gpios = <0x7c 0xe 0x0 0x7c 0x1b 0x0 0x7c 0x1c 0x0 0x8f 0x9 0x0>; | |
qcom,gpio-standby = <0x1>; | |
qcom,gpio-reset = <0x2>; | |
qcom,gpio-vdig = <0x3>; | |
qcom,gpio-req-tbl-num = <0x0 0x1 0x2 0x3>; | |
qcom,gpio-req-tbl-flags = <0x1 0x0 0x0 0x0>; | |
qcom,gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_STANDBY1", "CAM_RESET1", "CAM_VDIG"; | |
qcom,cci-master = <0x1>; | |
status = "ok"; | |
clocks = <0x27 0xa73cad0c 0x27 0x96c7b69b>; | |
clock-names = "cam_src_clk", "cam_clk"; | |
qcom,clock-rates = <0x16e3600 0x0>; | |
linux,phandle = <0xf7>; | |
phandle = <0xf7>; | |
}; | |
qcom,camera@0 { | |
cell-index = <0x0>; | |
compatible = "qcom,camera"; | |
reg = <0x0>; | |
qcom,csiphy-sd-index = <0x0>; | |
qcom,csid-sd-index = <0x0>; | |
qcom,mount-angle = <0x5a>; | |
qcom,led-flash-src = <0xec>; | |
qcom,actuator-src = <0xed>; | |
qcom,eeprom-src = <0xee>; | |
qcom,ois-src = <0xef>; | |
cam_vio-supply = <0xdf>; | |
cam_vdig-supply = <0xe1>; | |
cam_vana-supply = <0xe2>; | |
qcom,cam-vreg-name = "cam_vio", "cam_vdig", "cam_vana"; | |
qcom,cam-vreg-min-voltage = <0x0 0xf4240 0x27ac40>; | |
qcom,cam-vreg-max-voltage = <0x0 0x124f80 0x2c4020>; | |
qcom,cam-vreg-op-mode = <0x0 0x10c8e0 0x2ab980>; | |
qcom,gpio-no-mux = <0x0>; | |
pinctrl-names = "cam_default", "cam_suspend"; | |
pinctrl-0 = <0xe3 0xe4>; | |
pinctrl-1 = <0xe5 0xe6>; | |
gpios = <0x7c 0xd 0x0 0x7c 0x1e 0x0>; | |
qcom,gpio-reset = <0x1>; | |
qcom,gpio-req-tbl-num = <0x0 0x1>; | |
qcom,gpio-req-tbl-flags = <0x1 0x0>; | |
qcom,gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; | |
qcom,sensor-position = <0x0>; | |
qcom,sensor-mode = <0x0>; | |
qcom,cci-master = <0x0>; | |
status = "ok"; | |
clocks = <0x27 0x266b3853 0x27 0x56293a7>; | |
clock-names = "cam_src_clk", "cam_clk"; | |
qcom,clock-rates = <0x16e3600 0x0>; | |
}; | |
qcom,camera@1 { | |
cell-index = <0x1>; | |
compatible = "qcom,camera"; | |
reg = <0x1>; | |
qcom,csiphy-sd-index = <0x2>; | |
qcom,csid-sd-index = <0x2>; | |
qcom,mount-angle = <0x5a>; | |
qcom,led-flash-src = <0xec>; | |
qcom,actuator-src = <0xf0>; | |
qcom,eeprom-src = <0xf1>; | |
cam_vio-supply = <0xdf>; | |
cam_vdig-supply = <0xe1>; | |
cam_vana-supply = <0xe2>; | |
qcom,cam-vreg-name = "cam_vio", "cam_vdig", "cam_vana"; | |
qcom,cam-vreg-min-voltage = <0x0 0xf4240 0x2ab980>; | |
qcom,cam-vreg-max-voltage = <0x0 0x10c8e0 0x2ab980>; | |
qcom,cam-vreg-op-mode = <0x0 0x10c8e0 0x2ab980>; | |
qcom,gpio-no-mux = <0x0>; | |
pinctrl-names = "cam_default", "cam_suspend"; | |
pinctrl-0 = <0xf2 0xf3>; | |
pinctrl-1 = <0xf4 0xf5>; | |
gpios = <0x7c 0xf 0x0 0x7c 0x9 0x0>; | |
qcom,gpio-reset = <0x1>; | |
qcom,gpio-req-tbl-num = <0x0 0x1>; | |
qcom,gpio-req-tbl-flags = <0x1 0x0>; | |
qcom,gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2"; | |
qcom,sensor-position = <0x0>; | |
qcom,sensor-mode = <0x0>; | |
qcom,cci-master = <0x1>; | |
status = "ok"; | |
clocks = <0x27 0x42545468 0x27 0x8820556e>; | |
clock-names = "cam_src_clk", "cam_clk"; | |
qcom,clock-rates = <0x16e3600 0x0>; | |
}; | |
qcom,camera@2 { | |
cell-index = <0x2>; | |
compatible = "qcom,camera"; | |
reg = <0x2>; | |
qcom,csiphy-sd-index = <0x1>; | |
qcom,csid-sd-index = <0x1>; | |
qcom,mount-angle = <0x10e>; | |
qcom,eeprom-src = <0xf6 0xf7>; | |
cam_vio-supply = <0xdf>; | |
cam_vana-supply = <0xe7>; | |
qcom,cam-vreg-name = "cam_vio", "cam_vana"; | |
qcom,cam-vreg-min-voltage = <0x0 0x2bb380>; | |
qcom,cam-vreg-max-voltage = <0x0 0x2bb380>; | |
qcom,cam-vreg-op-mode = <0x0 0x13880>; | |
qcom,gpio-no-mux = <0x0>; | |
pinctrl-names = "cam_default", "cam_suspend"; | |
pinctrl-0 = <0xe8 0xe9>; | |
pinctrl-1 = <0xea 0xeb>; | |
gpios = <0x7c 0xe 0x0 0x7c 0x1b 0x0 0x7c 0x1c 0x0 0x8f 0x9 0x0>; | |
qcom,gpio-standby = <0x1>; | |
qcom,gpio-reset = <0x2>; | |
qcom,gpio-vdig = <0x3>; | |
qcom,gpio-req-tbl-num = <0x0 0x1 0x2 0x3>; | |
qcom,gpio-req-tbl-flags = <0x1 0x0 0x0 0x0>; | |
qcom,gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_STANDBY1", "CAM_RESET1", "CAM_VDIG"; | |
qcom,sensor-position = <0x1>; | |
qcom,sensor-mode = <0x0>; | |
qcom,cci-master = <0x1>; | |
status = "ok"; | |
clocks = <0x27 0xa73cad0c 0x27 0x96c7b69b>; | |
clock-names = "cam_src_clk", "cam_clk"; | |
qcom,clock-rates = <0x16e3600 0x0>; | |
}; | |
}; | |
qcom,jpeg@ca1c000 { | |
cell-index = <0x0>; | |
compatible = "qcom,jpeg"; | |
reg = <0xca1c000 0x4000 0xca60000 0x3000>; | |
reg-names = "jpeg_hw", "jpeg_vbif"; | |
interrupts = <0x0 0x13c 0x0>; | |
interrupt-names = "jpeg"; | |
smmu-vdd-supply = <0x28>; | |
camss-vdd-supply = <0x29>; | |
qcom,vdd-names = "smmu-vdd", "camss-vdd"; | |
clock-names = "mmssnoc_axi", "mmss_mnoc_ahb_clk", "mmss_bimc_smmu_ahb_clk", "mmss_bimc_smmu_axi_clk", "mmss_camss_ahb_clk", "mmss_camss_top_ahb_clk", "core_clk", "mmss_camss_jpeg_ahb_clk", "mmss_camss_jpeg_axi_clk"; | |
clocks = <0x38 0xdb4b31e6 0x27 0x49a394f4 0x27 0x4825baf4 0x27 0xc365ac39 0x27 0xa51f2c1d 0x27 0x120618d6 0x27 0xc9efa6ac 0x27 0xde1fece3 0x27 0x7534616b>; | |
qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x1c9c3800 0x0 0x0>; | |
qcom,vbif-reg-settings = <0x4 0x1>; | |
qcom,prefetch-reg-settings = <0x30c 0x1111 0x318 0x31 0x324 0x31 0x330 0x31 0x33c 0x0>; | |
qcom,msm-bus,name = "msm_camera_jpeg0"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x3e 0x200 0x0 0x0 0x3e 0x200 0x1d4c00 0x2bf200>; | |
status = "ok"; | |
}; | |
qcom,jpeg@caa0000 { | |
cell-index = <0x3>; | |
compatible = "qcom,jpegdma"; | |
reg = <0xcaa0000 0x4000 0xca60000 0x3000>; | |
reg-names = "jpeg_hw", "jpeg_vbif"; | |
interrupts = <0x0 0x130 0x0>; | |
interrupt-names = "jpeg"; | |
smmu-vdd-supply = <0x28>; | |
camss-vdd-supply = <0x29>; | |
qcom,vdd-names = "smmu-vdd", "camss-vdd"; | |
clock-names = "mmssnoc_axi", "mmss_mnoc_ahb_clk", "mmss_bimc_smmu_ahb_clk", "mmss_bimc_smmu_axi_clk", "mmss_camss_ahb_clk", "mmss_camss_top_ahb_clk", "core_clk", "mmss_camss_jpeg_ahb_clk", "mmss_camss_jpeg_axi_clk"; | |
clocks = <0x38 0xdb4b31e6 0x27 0x49a394f4 0x27 0x4825baf4 0x27 0xc365ac39 0x27 0xa51f2c1d 0x27 0x120618d6 0x27 0x371ec109 0x27 0xde1fece3 0x27 0x7534616b>; | |
qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x1c9c3800 0x0 0x0>; | |
qcom,vbif-reg-settings = <0x4 0x1>; | |
qcom,prefetch-reg-settings = <0x18c 0x11 0x1a0 0x31 0x1b0 0x31>; | |
qcom,msm-bus,name = "msm_camera_jpeg_dma"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x3e 0x200 0x0 0x0 0x3e 0x200 0x1d4c00 0x2bf200>; | |
qcom,max-ds-factor = <0x80>; | |
status = "ok"; | |
}; | |
qcom,vidc@cc00000 { | |
compatible = "qcom,msm-vidc"; | |
status = "ok"; | |
reg = <0xcc00000 0x100000>; | |
interrupts = <0x0 0x11f 0x4>; | |
qcom,hfi = "venus"; | |
qcom,hfi-version = "3xx"; | |
qcom,firmware-name = "venus"; | |
qcom,never-unload-fw; | |
qcom,sw-power-collapse; | |
qcom,max-secure-instances = <0x5>; | |
qcom,reg-presets = <0x80124 0x3 0x80550 0x1111111 0x80560 0x1111111 0x80568 0x1111111 0x80570 0x1111111 0x80580 0x1111111 0x80588 0x1111111 0xe2010 0x0>; | |
qcom,imem-size = <0x80000>; | |
qcom,max-hw-load = <0x271c80>; | |
qcom,power-conf = <0x7e9000>; | |
qcom,load-freq-tbl = <0x10e000 0x1fc4ef40 0x55555555 0xfd200 0x1a76e700 0x55555555 0xca800 0x152bec00 0x55555555 0x77880 0x100da650 0x55555555 0x54600 0xbebc200 0x55555555 0x21c000 0x1fc4ef40 0xffffffff 0x1a5e00 0x1a76e700 0xffffffff 0x1990d0 0x152bec00 0xffffffff 0x10e000 0x100da650 0xffffffff 0xca800 0xbebc200 0xffffffff>; | |
qcom,dcvs-tbl = <0x1a5e00 0x1a5e00 0x21c000 0x3f00000c 0xfd200 0xfd200 0x10e000 0x4000004 0xca800 0xca800 0xfd200 0x4000004 0x77880 0x77880 0xca800 0x4000004>; | |
qcom,dcvs-limit = <0x7e90 0x1e 0x7e90 0x3c>; | |
qcom,imem-ab-tbl = <0xbebc200 0x17cdc0 0x100da650 0x367950 0x152bec00 0x367950 0x1a76e700 0x66ff30 0x1fc4ef40 0x818c10>; | |
smmu-vdd-supply = <0x28>; | |
venus-supply = <0xa6>; | |
venus-core0-supply = <0xf8>; | |
venus-core1-supply = <0xf9>; | |
clock-names = "sys_noc_axi_clk", "noc_axi_clk", "mnoc_ahb_clk", "smmu_ahb_clk", "smmu_axi_clk", "mnoc_maxi_clk", "core_clk", "iface_clk", "bus_clk", "maxi_clk", "core0_clk", "core1_clk"; | |
clocks = <0x38 0x4467b15b 0x38 0xdb4b31e6 0x27 0x49a394f4 0x27 0x4825baf4 0x27 0xc365ac39 0x27 0xd8b7278f 0x27 0x78f14c85 0x27 0x94334ae9 0x27 0xf3178ba5 0x27 0x1785ef88 0x27 0x23fae359 0x27 0x5213a0c7>; | |
qcom,clock-configs = <0x0 0x0 0x0 0x0 0x0 0x0 0x3 0x0 0x2 0x2 0x3 0x3>; | |
bus_cnoc { | |
compatible = "qcom,msm-vidc,bus"; | |
label = "cnoc"; | |
qcom,bus-master = <0x1>; | |
qcom,bus-slave = <0x254>; | |
qcom,bus-governor = "performance"; | |
qcom,bus-range-kbps = <0x1 0x1>; | |
}; | |
venus_bus_ddr { | |
compatible = "qcom,msm-vidc,bus"; | |
label = "venus-ddr"; | |
qcom,bus-master = <0x3f>; | |
qcom,bus-slave = <0x200>; | |
qcom,bus-governor = "msm-vidc-ddr"; | |
qcom,bus-range-kbps = <0x3e8 0x4b7850>; | |
}; | |
venus_bus_vmem { | |
compatible = "qcom,msm-vidc,bus"; | |
label = "venus-vmem"; | |
qcom,bus-master = <0x44>; | |
qcom,bus-slave = <0x2c6>; | |
qcom,bus-governor = "msm-vidc-vmem+"; | |
qcom,bus-range-kbps = <0x3e8 0x818c10>; | |
}; | |
arm9_bus_ddr { | |
compatible = "qcom,msm-vidc,bus"; | |
label = "venus-arm9-ddr"; | |
qcom,bus-master = <0x3f>; | |
qcom,bus-slave = <0x200>; | |
qcom,bus-governor = "performance"; | |
qcom,bus-range-kbps = <0x1 0x1>; | |
}; | |
non_secure_cb { | |
compatible = "qcom,msm-vidc,context-bank"; | |
label = "venus_ns"; | |
iommus = <0xd4 0x400 0xd4 0x401 0xd4 0x40a 0xd4 0x407 0xd4 0x40e 0xd4 0x40f 0xd4 0x408 0xd4 0x409 0xd4 0x40b 0xd4 0x40c 0xd4 0x40d 0xd4 0x410 0xd4 0x421 0xd4 0x428 0xd4 0x429 0xd4 0x42b 0xd4 0x42c 0xd4 0x42d 0xd4 0x411 0xd4 0x431>; | |
buffer-types = <0xfff>; | |
virtual-addr-pool = <0x70800000 0x6f800000>; | |
}; | |
firmware_cb { | |
compatible = "qcom,msm-vidc,context-bank"; | |
qcom,fw-context-bank; | |
iommus = <0xd4 0x580 0xd4 0x586>; | |
}; | |
secure_bitstream_cb { | |
compatible = "qcom,msm-vidc,context-bank"; | |
label = "venus_sec_bitstream"; | |
iommus = <0xd4 0x500 0xd4 0x502 0xd4 0x509 0xd4 0x50a 0xd4 0x50b 0xd4 0x50e 0xd4 0x526 0xd4 0x529 0xd4 0x52b>; | |
buffer-types = <0x241>; | |
virtual-addr-pool = <0x4b000000 0x25800000>; | |
qcom,secure-context-bank; | |
}; | |
secure_pixel_cb { | |
compatible = "qcom,msm-vidc,context-bank"; | |
label = "venus_sec_pixel"; | |
iommus = <0xd4 0x504 0xd4 0x50c 0xd4 0x510 0xd4 0x52c>; | |
buffer-types = <0x106>; | |
virtual-addr-pool = <0x25800000 0x25800000>; | |
qcom,secure-context-bank; | |
}; | |
secure_non_pixel_cb { | |
compatible = "qcom,msm-vidc,context-bank"; | |
label = "venus_sec_non_pixel"; | |
iommus = <0xd4 0x505 0xd4 0x507 0xd4 0x508 0xd4 0x50d 0xd4 0x50f 0xd4 0x525 0xd4 0x528 0xd4 0x52d 0xd4 0x540>; | |
buffer-types = <0x480>; | |
virtual-addr-pool = <0x1000000 0x24800000>; | |
qcom,secure-context-bank; | |
}; | |
}; | |
qcom,vmem@c880000 { | |
compatible = "qcom,msm-vmem"; | |
status = "ok"; | |
interrupts = <0x0 0x1ad 0x4>; | |
reg = <0xc880000 0x6b 0x14800000 0x80000>; | |
reg-names = "reg-base", "mem-base"; | |
clocks = <0x27 0x49a394f4 0x27 0xd8b7278f 0x27 0x4b18955b 0x27 0xb6067889>; | |
clock-names = "mnoc_ahb", "mnoc_maxi", "ahb", "maxi"; | |
clock-config = <0x0 0x0 0x0 0x1>; | |
qcom,msm-bus,name = "vmem"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x2>; | |
qcom,msm-bus,vectors-KBps = <0x44 0x2c6 0x0 0x0 0x1 0x2c4 0x0 0x0 0x44 0x2c6 0x3e8 0x3e8 0x1 0x2c4 0x1f4 0x320>; | |
qcom,bank-size = <0x20000>; | |
}; | |
tmc@6048000 { | |
compatible = "arm,primecell"; | |
arm,primecell-periphid = <0x3b961>; | |
reg = <0x6048000 0x1000 0x6064000 0x15000>; | |
reg-names = "tmc-base", "bam-base"; | |
arm,buffer-size = <0x400000>; | |
arm,sg-enable; | |
coresight-ctis = <0xfa 0xfb>; | |
coresight-name = "coresight-tmc-etr"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "apb_pclk", "core_a_clk"; | |
port { | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0xfc>; | |
linux,phandle = <0xfd>; | |
phandle = <0xfd>; | |
}; | |
}; | |
}; | |
replicator@6046000 { | |
compatible = "arm,primecell"; | |
arm,primecell-periphid = <0x3b909>; | |
reg = <0x6046000 0x1000>; | |
reg-names = "replicator-base"; | |
coresight-name = "coresight-replicator"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "apb_pclk", "core_a_clk"; | |
ports { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
port@0 { | |
reg = <0x0>; | |
endpoint { | |
remote-endpoint = <0xfd>; | |
linux,phandle = <0xfc>; | |
phandle = <0xfc>; | |
}; | |
}; | |
port@1 { | |
reg = <0x0>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0xfe>; | |
linux,phandle = <0xff>; | |
phandle = <0xff>; | |
}; | |
}; | |
}; | |
}; | |
tmc@6047000 { | |
compatible = "arm,primecell"; | |
arm,primecell-periphid = <0x3b961>; | |
reg = <0x6047000 0x1000>; | |
reg-names = "tmc-base"; | |
coresight-ctis = <0xfa 0xfb>; | |
coresight-name = "coresight-tmc-etf"; | |
arm,default-sink; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "apb_pclk", "core_a_clk"; | |
ports { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
port@0 { | |
reg = <0x0>; | |
endpoint { | |
remote-endpoint = <0xff>; | |
linux,phandle = <0xfe>; | |
phandle = <0xfe>; | |
}; | |
}; | |
port@1 { | |
reg = <0x0>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x100>; | |
linux,phandle = <0x101>; | |
phandle = <0x101>; | |
}; | |
}; | |
}; | |
}; | |
funnel@6045000 { | |
compatible = "arm,primecell"; | |
arm,primecell-periphid = <0x3b908>; | |
reg = <0x6045000 0x1000>; | |
reg-names = "funnel-base"; | |
coresight-name = "coresight-funnel-merg"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "apb_pclk", "core_a_clk"; | |
ports { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
port@0 { | |
reg = <0x0>; | |
endpoint { | |
remote-endpoint = <0x101>; | |
linux,phandle = <0x100>; | |
phandle = <0x100>; | |
}; | |
}; | |
port@1 { | |
reg = <0x0>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x102>; | |
linux,phandle = <0x104>; | |
phandle = <0x104>; | |
}; | |
}; | |
port@2 { | |
reg = <0x1>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x103>; | |
linux,phandle = <0x109>; | |
phandle = <0x109>; | |
}; | |
}; | |
}; | |
}; | |
funnel@6041000 { | |
compatible = "arm,primecell"; | |
arm,primecell-periphid = <0x3b908>; | |
reg = <0x6041000 0x1000>; | |
reg-names = "funnel-base"; | |
coresight-name = "coresight-funnel-in0"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "apb_pclk", "core_a_clk"; | |
ports { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
port@0 { | |
reg = <0x0>; | |
endpoint { | |
remote-endpoint = <0x104>; | |
linux,phandle = <0x102>; | |
phandle = <0x102>; | |
}; | |
}; | |
port@1 { | |
reg = <0x0>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x105>; | |
linux,phandle = <0x148>; | |
phandle = <0x148>; | |
}; | |
}; | |
port@2 { | |
reg = <0x3>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x106>; | |
linux,phandle = <0x141>; | |
phandle = <0x141>; | |
}; | |
}; | |
port@3 { | |
reg = <0x6>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x107>; | |
linux,phandle = <0x127>; | |
phandle = <0x127>; | |
}; | |
}; | |
port@4 { | |
reg = <0x7>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x108>; | |
linux,phandle = <0x11d>; | |
phandle = <0x11d>; | |
}; | |
}; | |
}; | |
}; | |
funnel@6042000 { | |
compatible = "arm,primecell"; | |
arm,primecell-periphid = <0x3b908>; | |
reg = <0x6042000 0x1000>; | |
reg-names = "funnel-base"; | |
coresight-name = "coresight-funnel-in1"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "apb_pclk", "core_a_clk"; | |
ports { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
port@0 { | |
reg = <0x0>; | |
endpoint { | |
remote-endpoint = <0x109>; | |
linux,phandle = <0x103>; | |
phandle = <0x103>; | |
}; | |
}; | |
port@1 { | |
reg = <0x2>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x10a>; | |
linux,phandle = <0x13b>; | |
phandle = <0x13b>; | |
}; | |
}; | |
port@2 { | |
reg = <0x3>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x10b>; | |
linux,phandle = <0x138>; | |
phandle = <0x138>; | |
}; | |
}; | |
port@3 { | |
reg = <0x4>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x10c>; | |
linux,phandle = <0x147>; | |
phandle = <0x147>; | |
}; | |
}; | |
port@4 { | |
reg = <0x5>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x10d>; | |
linux,phandle = <0x146>; | |
phandle = <0x146>; | |
}; | |
}; | |
port@5 { | |
reg = <0x6>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x10e>; | |
linux,phandle = <0x110>; | |
phandle = <0x110>; | |
}; | |
}; | |
port@6 { | |
reg = <0x7>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x10f>; | |
linux,phandle = <0x1a8>; | |
phandle = <0x1a8>; | |
}; | |
}; | |
}; | |
}; | |
funnel@7b70000 { | |
compatible = "arm,primecell"; | |
arm,primecell-periphid = <0x3b908>; | |
reg = <0x7b70000 0x1000>; | |
reg-names = "funnel-base"; | |
coresight-name = "coresight-funnel-apss-merg"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "apb_pclk", "core_a_clk"; | |
ports { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
port@0 { | |
reg = <0x0>; | |
endpoint { | |
remote-endpoint = <0x110>; | |
linux,phandle = <0x10e>; | |
phandle = <0x10e>; | |
}; | |
}; | |
port@1 { | |
reg = <0x0>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x111>; | |
linux,phandle = <0x114>; | |
phandle = <0x114>; | |
}; | |
}; | |
port@2 { | |
reg = <0x1>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x112>; | |
linux,phandle = <0x13e>; | |
phandle = <0x13e>; | |
}; | |
}; | |
port@3 { | |
reg = <0x3>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x113>; | |
linux,phandle = <0x135>; | |
phandle = <0x135>; | |
}; | |
}; | |
}; | |
}; | |
funnel@7b60000 { | |
compatible = "arm,primecell"; | |
arm,primecell-periphid = <0x3b908>; | |
reg = <0x7b60000 0x1000>; | |
reg-names = "funnel-base"; | |
coresight-name = "coresight-funnel-apss"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "apb_pclk", "core_a_clk"; | |
ports { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
port@0 { | |
reg = <0x0>; | |
endpoint { | |
remote-endpoint = <0x114>; | |
linux,phandle = <0x111>; | |
phandle = <0x111>; | |
}; | |
}; | |
port@1 { | |
reg = <0x0>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x115>; | |
linux,phandle = <0x11e>; | |
phandle = <0x11e>; | |
}; | |
}; | |
port@2 { | |
reg = <0x1>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x116>; | |
linux,phandle = <0x11f>; | |
phandle = <0x11f>; | |
}; | |
}; | |
port@3 { | |
reg = <0x2>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x117>; | |
linux,phandle = <0x120>; | |
phandle = <0x120>; | |
}; | |
}; | |
port@4 { | |
reg = <0x3>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x118>; | |
linux,phandle = <0x121>; | |
phandle = <0x121>; | |
}; | |
}; | |
port@5 { | |
reg = <0x4>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x119>; | |
linux,phandle = <0x122>; | |
phandle = <0x122>; | |
}; | |
}; | |
port@6 { | |
reg = <0x5>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x11a>; | |
linux,phandle = <0x123>; | |
phandle = <0x123>; | |
}; | |
}; | |
port@7 { | |
reg = <0x6>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x11b>; | |
linux,phandle = <0x124>; | |
phandle = <0x124>; | |
}; | |
}; | |
port@8 { | |
reg = <0x7>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x11c>; | |
linux,phandle = <0x125>; | |
phandle = <0x125>; | |
}; | |
}; | |
}; | |
}; | |
stm@6002000 { | |
compatible = "arm,primecell"; | |
arm,primecell-periphid = <0x3b962>; | |
reg = <0x6002000 0x1000 0x16280000 0x180000>; | |
reg-names = "stm-base", "stm-data-base"; | |
coresight-name = "coresight-stm"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "apb_pclk", "core_a_clk"; | |
port { | |
endpoint { | |
remote-endpoint = <0x11d>; | |
linux,phandle = <0x108>; | |
phandle = <0x108>; | |
}; | |
}; | |
}; | |
etm@7840000 { | |
compatible = "arm,primecell"; | |
arm,primecell-periphid = <0x3b95d>; | |
reg = <0x7840000 0x1000>; | |
cpu = <0x16>; | |
coresight-name = "coresight-etm0"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "apb_pclk", "core_a_clk"; | |
port { | |
endpoint { | |
remote-endpoint = <0x11e>; | |
linux,phandle = <0x115>; | |
phandle = <0x115>; | |
}; | |
}; | |
}; | |
etm@7940000 { | |
compatible = "arm,primecell"; | |
arm,primecell-periphid = <0x3b95d>; | |
reg = <0x7940000 0x1000>; | |
cpu = <0x17>; | |
coresight-name = "coresight-etm1"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "apb_pclk", "core_a_clk"; | |
port { | |
endpoint { | |
remote-endpoint = <0x11f>; | |
linux,phandle = <0x116>; | |
phandle = <0x116>; | |
}; | |
}; | |
}; | |
etm@7A40000 { | |
compatible = "arm,primecell"; | |
arm,primecell-periphid = <0x3b95d>; | |
reg = <0x7a40000 0x1000>; | |
cpu = <0x18>; | |
coresight-name = "coresight-etm2"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "apb_pclk", "core_a_clk"; | |
port { | |
endpoint { | |
remote-endpoint = <0x120>; | |
linux,phandle = <0x117>; | |
phandle = <0x117>; | |
}; | |
}; | |
}; | |
etm@7B40000 { | |
compatible = "arm,primecell"; | |
arm,primecell-periphid = <0x3b95d>; | |
reg = <0x7b40000 0x1000>; | |
cpu = <0x19>; | |
coresight-name = "coresight-etm3"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "apb_pclk", "core_a_clk"; | |
port { | |
endpoint { | |
remote-endpoint = <0x121>; | |
linux,phandle = <0x118>; | |
phandle = <0x118>; | |
}; | |
}; | |
}; | |
etm@7C40000 { | |
compatible = "arm,primecell"; | |
arm,primecell-periphid = <0x3b95d>; | |
reg = <0x7c40000 0x1000>; | |
cpu = <0x1a>; | |
coresight-name = "coresight-etm4"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "apb_pclk", "core_a_clk"; | |
port { | |
endpoint { | |
remote-endpoint = <0x122>; | |
linux,phandle = <0x119>; | |
phandle = <0x119>; | |
}; | |
}; | |
}; | |
etm@7D40000 { | |
compatible = "arm,primecell"; | |
arm,primecell-periphid = <0x3b95d>; | |
reg = <0x7d40000 0x1000>; | |
cpu = <0x1b>; | |
coresight-name = "coresight-etm5"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "apb_pclk", "core_a_clk"; | |
port { | |
endpoint { | |
remote-endpoint = <0x123>; | |
linux,phandle = <0x11a>; | |
phandle = <0x11a>; | |
}; | |
}; | |
}; | |
etm@7E40000 { | |
compatible = "arm,primecell"; | |
arm,primecell-periphid = <0x3b95d>; | |
reg = <0x7e40000 0x1000>; | |
cpu = <0x1c>; | |
coresight-name = "coresight-etm6"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "apb_pclk", "core_a_clk"; | |
port { | |
endpoint { | |
remote-endpoint = <0x124>; | |
linux,phandle = <0x11b>; | |
phandle = <0x11b>; | |
}; | |
}; | |
}; | |
etm@7F40000 { | |
compatible = "arm,primecell"; | |
arm,primecell-periphid = <0x3b95d>; | |
reg = <0x7f40000 0x1000>; | |
cpu = <0x1d>; | |
coresight-name = "coresight-etm7"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "apb_pclk", "core_a_clk"; | |
port { | |
endpoint { | |
remote-endpoint = <0x125>; | |
linux,phandle = <0x11c>; | |
phandle = <0x11c>; | |
}; | |
}; | |
}; | |
cti@6010000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x6010000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti0"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
linux,phandle = <0xfa>; | |
phandle = <0xfa>; | |
}; | |
cti@6011000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x6011000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti1"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@6012000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x6012000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti2"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
qcom,cti-gpio-trigout = <0x4>; | |
pinctrl-names = "cti-trigout-pctrl"; | |
pinctrl-0 = <0x126>; | |
}; | |
cti@6013000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x6013000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti3"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@6014000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x6014000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti4"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@6015000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x6015000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti5"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@6016000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x6016000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti6"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@6017000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x6017000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti7"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@6018000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x6018000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti8"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
linux,phandle = <0xfb>; | |
phandle = <0xfb>; | |
}; | |
cti@6019000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x6019000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti9"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@601a000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x601a000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti10"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@601b000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x601b000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti11"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@601c000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x601c000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti12"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@601d000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x601d000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti13"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@601e000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x601e000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti14"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@601f000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x601f000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti15"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@7820000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x7820000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti-cpu0"; | |
cpu = <0x16>; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@7920000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x7920000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti-cpu1"; | |
cpu = <0x17>; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@7a20000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x7a20000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti-cpu2"; | |
cpu = <0x18>; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@7b20000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x7b20000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti-cpu3"; | |
cpu = <0x19>; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@7c20000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x7c20000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti-cpu4"; | |
cpu = <0x1a>; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@7d20000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x7d20000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti-cpu5"; | |
cpu = <0x1b>; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@7e20000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x7e20000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti-cpu6"; | |
cpu = <0x1c>; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@7f20000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x7f20000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti-cpu7"; | |
cpu = <0x1d>; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@7b80000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x7b80000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti-apss"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@7bc1000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x7bc1000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti-apss-dl"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
cti@7b91000 { | |
compatible = "arm,coresight-cti"; | |
reg = <0x7b91000 0x1000>; | |
reg-names = "cti-base"; | |
coresight-name = "coresight-cti-olc"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
}; | |
funnel@6005000 { | |
compatible = "arm,primecell"; | |
arm,primecell-periphid = <0x3b908>; | |
reg = <0x6005000 0x1000>; | |
reg-names = "funnel-base"; | |
coresight-name = "coresight-funnel-qatb"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "apb_pclk", "core_a_clk"; | |
ports { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
port@0 { | |
reg = <0x0>; | |
endpoint { | |
remote-endpoint = <0x127>; | |
linux,phandle = <0x107>; | |
phandle = <0x107>; | |
}; | |
}; | |
port@1 { | |
reg = <0x0>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x128>; | |
linux,phandle = <0x12a>; | |
phandle = <0x12a>; | |
}; | |
}; | |
port@2 { | |
reg = <0x3>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x129>; | |
linux,phandle = <0x149>; | |
phandle = <0x149>; | |
}; | |
}; | |
}; | |
}; | |
tpda@6004000 { | |
compatible = "qcom,coresight-tpda"; | |
reg = <0x6004000 0x1000>; | |
reg-names = "tpda-base"; | |
coresight-name = "coresight-tpda"; | |
qcom,tpda-atid = <0x41>; | |
qcom,bc-elem-size = <0x7 0x20 0x9 0x20>; | |
qcom,tc-elem-size = <0x3 0x20 0x6 0x20 0x9 0x20>; | |
qcom,dsb-elem-size = <0x7 0x20 0x9 0x20>; | |
qcom,cmb-elem-size = <0x3 0x20 0x4 0x20 0x5 0x20 0x9 0x40>; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
ports { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
port@0 { | |
reg = <0x0>; | |
endpoint { | |
remote-endpoint = <0x12a>; | |
linux,phandle = <0x128>; | |
phandle = <0x128>; | |
}; | |
}; | |
port@1 { | |
reg = <0x3>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x12b>; | |
linux,phandle = <0x130>; | |
phandle = <0x130>; | |
}; | |
}; | |
port@2 { | |
reg = <0x4>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x12c>; | |
linux,phandle = <0x131>; | |
phandle = <0x131>; | |
}; | |
}; | |
port@3 { | |
reg = <0x5>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x12d>; | |
linux,phandle = <0x132>; | |
phandle = <0x132>; | |
}; | |
}; | |
port@4 { | |
reg = <0x7>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x12e>; | |
linux,phandle = <0x133>; | |
phandle = <0x133>; | |
}; | |
}; | |
port@5 { | |
reg = <0x9>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x12f>; | |
linux,phandle = <0x134>; | |
phandle = <0x134>; | |
}; | |
}; | |
}; | |
}; | |
tpdm@7038000 { | |
compatible = "qcom,coresight-tpdm"; | |
reg = <0x7038000 0x1000>; | |
reg-names = "tpdm-base"; | |
coresight-name = "coresight-tpdm-vsense"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
port { | |
endpoint { | |
remote-endpoint = <0x130>; | |
linux,phandle = <0x12b>; | |
phandle = <0x12b>; | |
}; | |
}; | |
}; | |
tpdm@7054000 { | |
compatible = "qcom,coresight-tpdm"; | |
reg = <0x7054000 0x1000>; | |
reg-names = "tpdm-base"; | |
coresight-name = "coresight-tpdm-dcc"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
port { | |
endpoint { | |
remote-endpoint = <0x131>; | |
linux,phandle = <0x12c>; | |
phandle = <0x12c>; | |
}; | |
}; | |
}; | |
tpdm@704c000 { | |
compatible = "qcom,coresight-tpdm"; | |
reg = <0x704c000 0x1000>; | |
reg-names = "tpdm-base"; | |
coresight-name = "coresight-tpdm-prng"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
port { | |
endpoint { | |
remote-endpoint = <0x132>; | |
linux,phandle = <0x12d>; | |
phandle = <0x12d>; | |
}; | |
}; | |
}; | |
tpdm@71d0000 { | |
compatible = "qcom,coresight-tpdm"; | |
reg = <0x71d0000 0x1000>; | |
reg-names = "tpdm-base"; | |
coresight-name = "coresight-tpdm-qm"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
qcom,msr-fix-req; | |
port { | |
endpoint { | |
remote-endpoint = <0x133>; | |
linux,phandle = <0x12e>; | |
phandle = <0x12e>; | |
}; | |
}; | |
}; | |
tpdm@7050000 { | |
compatible = "qcom,coresight-tpdm"; | |
reg = <0x7050000 0x1000>; | |
reg-names = "tpdm-base"; | |
coresight-name = "coresight-tpdm-pimem"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
qcom,msr-fix-req; | |
port { | |
endpoint { | |
remote-endpoint = <0x134>; | |
linux,phandle = <0x12f>; | |
phandle = <0x12f>; | |
}; | |
}; | |
}; | |
tpda@7bc2000 { | |
compatible = "qcom,coresight-tpda"; | |
reg = <0x7bc2000 0x1000>; | |
reg-names = "tpda-base"; | |
coresight-name = "coresight-tpda-apss"; | |
qcom,tpda-atid = <0x42>; | |
qcom,dsb-elem-size = <0x0 0x20>; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
ports { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
port@0 { | |
reg = <0x0>; | |
endpoint { | |
remote-endpoint = <0x135>; | |
linux,phandle = <0x113>; | |
phandle = <0x113>; | |
}; | |
}; | |
port@1 { | |
reg = <0x0>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x136>; | |
linux,phandle = <0x137>; | |
phandle = <0x137>; | |
}; | |
}; | |
}; | |
}; | |
tpdm@7bc0000 { | |
compatible = "qcom,coresight-tpdm"; | |
reg = <0x7bc0000 0x1000>; | |
reg-names = "tpdm-base"; | |
coresight-name = "coresight-tpdm-apss"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
qcom,msr-fix-req; | |
port { | |
endpoint { | |
remote-endpoint = <0x137>; | |
linux,phandle = <0x136>; | |
phandle = <0x136>; | |
}; | |
}; | |
}; | |
tpda@7043000 { | |
compatible = "qcom,coresight-tpda"; | |
reg = <0x7043000 0x1000>; | |
reg-names = "tpda-base"; | |
coresight-name = "coresight-tpda-mss"; | |
qcom,tpda-atid = <0x43>; | |
qcom,dsb-elem-size = <0x0 0x20>; | |
qcom,cmb-elem-size = <0x0 0x20>; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
ports { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
port@0 { | |
reg = <0x0>; | |
endpoint { | |
remote-endpoint = <0x138>; | |
linux,phandle = <0x10b>; | |
phandle = <0x10b>; | |
}; | |
}; | |
port@1 { | |
reg = <0x0>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x139>; | |
linux,phandle = <0x13a>; | |
phandle = <0x13a>; | |
}; | |
}; | |
}; | |
}; | |
tpdm@7042000 { | |
compatible = "qcom,coresight-tpdm"; | |
reg = <0x7042000 0x1000>; | |
reg-names = "tpdm-base"; | |
coresight-name = "coresight-tpdm-mss"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
qcom,msr-fix-req; | |
port { | |
endpoint { | |
remote-endpoint = <0x13a>; | |
linux,phandle = <0x139>; | |
phandle = <0x139>; | |
}; | |
}; | |
}; | |
tpda@7191000 { | |
compatible = "qcom,coresight-tpda"; | |
reg = <0x7191000 0x1000>; | |
reg-names = "tpda-base"; | |
coresight-name = "coresight-tpda-nav"; | |
qcom,tpda-atid = <0x44>; | |
qcom,cmb-elem-size = <0x0 0x20>; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
ports { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
port@0 { | |
reg = <0x0>; | |
endpoint { | |
remote-endpoint = <0x13b>; | |
linux,phandle = <0x10a>; | |
phandle = <0x10a>; | |
}; | |
}; | |
port@1 { | |
reg = <0x0>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x13c>; | |
linux,phandle = <0x13d>; | |
phandle = <0x13d>; | |
}; | |
}; | |
}; | |
}; | |
tpdm@7190000 { | |
compatible = "qcom,coresight-tpdm"; | |
reg = <0x7190000 0x1000>; | |
reg-names = "tpdm-base"; | |
coresight-name = "coresight-tpdm-nav"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
port { | |
endpoint { | |
remote-endpoint = <0x13d>; | |
linux,phandle = <0x13c>; | |
phandle = <0x13c>; | |
}; | |
}; | |
}; | |
tpda@7b92000 { | |
compatible = "qcom,coresight-tpda"; | |
reg = <0x7b92000 0x1000>; | |
reg-names = "tpda-base"; | |
coresight-name = "coresight-tpda-olc"; | |
qcom,tpda-atid = <0x45>; | |
qcom,cmb-elem-size = <0x0 0x40>; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
ports { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
port@0 { | |
reg = <0x0>; | |
endpoint { | |
remote-endpoint = <0x13e>; | |
linux,phandle = <0x112>; | |
phandle = <0x112>; | |
}; | |
}; | |
port@1 { | |
reg = <0x0>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x13f>; | |
linux,phandle = <0x140>; | |
phandle = <0x140>; | |
}; | |
}; | |
}; | |
}; | |
tpdm@7b90000 { | |
compatible = "qcom,coresight-tpdm"; | |
reg = <0x7b90000 0x1000>; | |
reg-names = "tpdm-base"; | |
coresight-name = "coresight-tpdm-olc"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
port { | |
endpoint { | |
remote-endpoint = <0x140>; | |
linux,phandle = <0x13f>; | |
phandle = <0x13f>; | |
}; | |
}; | |
}; | |
funnel@7083000 { | |
compatible = "arm,primecell"; | |
arm,primecell-periphid = <0x3b908>; | |
reg = <0x7083000 0x1000>; | |
reg-names = "funnel-base"; | |
coresight-name = "coresight-funnel-spss"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "apb_pclk", "core_a_clk"; | |
ports { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
port@0 { | |
reg = <0x0>; | |
endpoint { | |
remote-endpoint = <0x141>; | |
linux,phandle = <0x106>; | |
phandle = <0x106>; | |
}; | |
}; | |
port@1 { | |
reg = <0x0>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x142>; | |
linux,phandle = <0x143>; | |
phandle = <0x143>; | |
}; | |
}; | |
}; | |
}; | |
tpda@7082000 { | |
compatible = "qcom,coresight-tpda"; | |
reg = <0x7082000 0x1000>; | |
reg-names = "tpda-base"; | |
coresight-name = "coresight-tpda-spss"; | |
qcom,tpda-atid = <0x46>; | |
qcom,dsb-elem-size = <0x0 0x20>; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
ports { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
port@0 { | |
reg = <0x0>; | |
endpoint { | |
remote-endpoint = <0x143>; | |
linux,phandle = <0x142>; | |
phandle = <0x142>; | |
}; | |
}; | |
port@1 { | |
reg = <0x0>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x144>; | |
linux,phandle = <0x145>; | |
phandle = <0x145>; | |
}; | |
}; | |
}; | |
}; | |
tpdm@7080000 { | |
compatible = "qcom,coresight-tpdm"; | |
reg = <0x7080000 0x1000>; | |
reg-names = "tpdm-base"; | |
coresight-name = "coresight-tpdm-spss"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "core_clk", "core_a_clk"; | |
qcom,msr-fix-req; | |
port { | |
endpoint { | |
remote-endpoint = <0x145>; | |
linux,phandle = <0x144>; | |
phandle = <0x144>; | |
}; | |
}; | |
}; | |
hwevent@158000 { | |
compatible = "qcom,coresight-hwevent"; | |
reg = <0x158000 0x80 0x17091000 0x80 0x1730200c 0x4 0xc90137c 0x4 0xc828018 0x80 0x1c00058 0x80 0x5e02038 0x4 0x5e02028 0x10 0x1fcb360 0x80 0x1fcb760 0x80 0x1fcbf60 0x80 0xa8f8860 0x4 0x500c260 0x4 0x500d040 0x4 0x1da6400 0x80>; | |
reg-names = "gcc-ctrl", "lpass-stm", "lpass-qdsp", "mdss-mdp", "mdss-misc", "pcie0-hwev", "ssc-en", "ssc-hwev", "tcsr-qdss", "tcsr-mss0", "tcsr-mss1", "usb-ctrl", "vbif-stm", "vbif-stm-en", "ufs-mux"; | |
coresight-name = "coresight-hwevent"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669 0x27 0xea30b0e7>; | |
clock-names = "core_clk", "core_a_clk", "core_mmss_clk"; | |
qcom,hwevent-clks = "core_mmss_clk"; | |
}; | |
csr@6001000 { | |
compatible = "qcom,coresight-csr"; | |
reg = <0x6001000 0x1000>; | |
reg-names = "csr-base"; | |
coresight-name = "coresight-csr"; | |
qcom,blk-size = <0x1>; | |
}; | |
modem_etm0 { | |
compatible = "qcom,coresight-remote-etm"; | |
coresight-name = "coresight-modem-etm0"; | |
qcom,inst-id = <0x2>; | |
port { | |
endpoint { | |
remote-endpoint = <0x146>; | |
linux,phandle = <0x10d>; | |
phandle = <0x10d>; | |
}; | |
}; | |
}; | |
audio_etm0 { | |
compatible = "qcom,coresight-remote-etm"; | |
coresight-name = "coresight-audio-etm0"; | |
qcom,inst-id = <0x5>; | |
port { | |
endpoint { | |
remote-endpoint = <0x147>; | |
linux,phandle = <0x10c>; | |
phandle = <0x10c>; | |
}; | |
}; | |
}; | |
rpm_etm0 { | |
compatible = "qcom,coresight-remote-etm"; | |
coresight-name = "coresight-rpm-etm0"; | |
qcom,inst-id = <0x4>; | |
port { | |
endpoint { | |
remote-endpoint = <0x148>; | |
linux,phandle = <0x105>; | |
phandle = <0x105>; | |
}; | |
}; | |
}; | |
funnel@7225000 { | |
compatible = "arm,primecell"; | |
arm,primecell-periphid = <0x3b908>; | |
reg = <0x7225000 0x1000>; | |
reg-names = "funnel-base"; | |
coresight-name = "coresight-funnel-dlet-qatb"; | |
clocks = <0x38 0x1492202a 0x38 0xdd121669>; | |
clock-names = "apb_pclk", "core_a_clk"; | |
ports { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
port@0 { | |
reg = <0x0>; | |
endpoint { | |
remote-endpoint = <0x149>; | |
linux,phandle = <0x129>; | |
phandle = <0x129>; | |
}; | |
}; | |
port@1 { | |
reg = <0x1>; | |
endpoint { | |
slave-mode; | |
remote-endpoint = <0x14a>; | |
linux,phandle = <0x14b>; | |
phandle = <0x14b>; | |
}; | |
}; | |
}; | |
}; | |
dummy-tpdm-wcss { | |
compatible = "qcom,coresight-dummy"; | |
coresight-name = "coresight-tpdm-wcss"; | |
port { | |
endpoint { | |
remote-endpoint = <0x14b>; | |
linux,phandle = <0x14a>; | |
phandle = <0x14a>; | |
}; | |
}; | |
}; | |
ad-hoc-bus { | |
compatible = "qcom,msm-bus-device"; | |
reg = <0x1620000 0x40000 0x1000000 0x80000 0x1500000 0x10000 0x1660000 0x60000 0x1700000 0x60000 0x17900000 0x10000 0x1740000 0x10000 0x1740000 0x10000>; | |
reg-names = "snoc-base", "bimc-base", "cnoc-base", "a1noc-base", "a2noc-base", "gnoc-base", "mmnoc-ahb-base", "mnoc-base"; | |
fab-a1noc { | |
cell-id = <0x1802>; | |
label = "fab-a1noc"; | |
qcom,fab-dev; | |
qcom,base-name = "a1noc-base"; | |
qcom,bus-type = <0x1>; | |
qcom,qos-off = <0x1000>; | |
qcom,base-offset = <0x9000>; | |
clock-names = "bus_clk", "bus_a_clk"; | |
clocks = <0x38 0x49abba8 0x38 0xc12e4220>; | |
linux,phandle = <0x14d>; | |
phandle = <0x14d>; | |
qcom,node-qos-clks { | |
clock-names = "clk-ufs-axi-clk", "clk-aggre1-ufs-axi-no-rate", "clk-aggre1-usb3-axi-cfg-no-rate", "clk-blsp2-ahb-no-rate"; | |
clocks = <0x38 0x47c743a7 0x38 0x873459d8 0x38 0xc5c3fbe8 0x38 0x8f283c1d>; | |
}; | |
}; | |
fab-a2noc { | |
cell-id = <0x1803>; | |
label = "fab-a2noc"; | |
qcom,fab-dev; | |
qcom,base-name = "a2noc-base"; | |
qcom,bus-type = <0x1>; | |
qcom,qos-off = <0x1000>; | |
qcom,base-offset = <0x5000>; | |
clock-names = "bus_clk", "bus_a_clk"; | |
clocks = <0x38 0xaa681404 0x38 0xcab67089>; | |
linux,phandle = <0x14f>; | |
phandle = <0x14f>; | |
qcom,node-qos-clks { | |
clock-names = "clk-ipa-clk", "clk-sdcc2-ahb-no-rate", "clk-sdcc4-ahb-no-rate", "clk-blsp1-ahb-no-rate"; | |
clocks = <0x38 0xfa685cda 0x38 0x23d5727f 0x38 0x64f3e6a8 0x38 0x8caa5b4f>; | |
}; | |
}; | |
fab-bimc { | |
cell-id = <0x0>; | |
label = "fab-bimc"; | |
qcom,fab-dev; | |
qcom,base-name = "bimc-base"; | |
qcom,bus-type = <0x2>; | |
qcom,util-fact = <0x99>; | |
clock-names = "bus_clk", "bus_a_clk"; | |
clocks = <0x38 0xd212feea 0x38 0x71d1a499>; | |
linux,phandle = <0x152>; | |
phandle = <0x152>; | |
}; | |
fab-cnoc { | |
cell-id = <0x1400>; | |
label = "fab-cnoc"; | |
qcom,fab-dev; | |
qcom,base-name = "cnoc-base"; | |
qcom,bus-type = <0x1>; | |
clock-names = "bus_clk", "bus_a_clk"; | |
clocks = <0x38 0xd5ccb7f4 0x38 0xd8fe2ccc>; | |
linux,phandle = <0x17a>; | |
phandle = <0x17a>; | |
}; | |
fab-cr_virt { | |
cell-id = <0x1805>; | |
label = "fab-cr_virt"; | |
qcom,virt-dev; | |
qcom,base-name = "cr_virt-base"; | |
qcom,bypass-qos-prg; | |
}; | |
fab-gnoc { | |
cell-id = <0x1804>; | |
label = "fab-gnoc"; | |
qcom,virt-dev; | |
qcom,base-name = "gnoc-base"; | |
qcom,bypass-qos-prg; | |
linux,phandle = <0x17e>; | |
phandle = <0x17e>; | |
}; | |
fab-mnoc { | |
cell-id = <0x800>; | |
label = "fab-mnoc"; | |
qcom,fab-dev; | |
qcom,base-name = "mnoc-base"; | |
qcom,bus-type = <0x1>; | |
qcom,qos-off = <0x1000>; | |
qcom,base-offset = <0x4000>; | |
qcom,util-fact = <0x99>; | |
clock-names = "bus_clk", "bus_a_clk"; | |
clocks = <0x38 0xdb4b31e6 0x38 0xd4970614>; | |
clk-camss-ahb-no-rate-supply = <0x29>; | |
clk-video-ahb-no-rate-supply = <0xa6>; | |
clk-video-axi-no-rate-supply = <0xa6>; | |
linux,phandle = <0x18c>; | |
phandle = <0x18c>; | |
qcom,node-qos-clks { | |
clock-names = "clk-noc-cfg-ahb-no-rate", "clk-mnoc-ahb-no-rate", "clk-camss-ahb-no-rate", "clk-video-ahb-no-rate", "clk-video-axi-no-rate"; | |
clocks = <0x38 0xdb4b31e6 0x38 0xb41a9d99 0x27 0x49a394f4 0x27 0xa51f2c1d 0x27 0x94334ae9 0x27 0xf3178ba5>; | |
}; | |
}; | |
fab-snoc { | |
cell-id = <0x400>; | |
label = "fab-snoc"; | |
qcom,fab-dev; | |
qcom,base-name = "snoc-base"; | |
qcom,bus-type = <0x1>; | |
qcom,qos-off = <0x1000>; | |
qcom,base-offset = <0x5000>; | |
clock-names = "bus_clk", "bus_a_clk"; | |
clocks = <0x38 0x2c341aa0 0x38 0x8fcef2af>; | |
linux,phandle = <0x192>; | |
phandle = <0x192>; | |
}; | |
fab-mnoc-ahb { | |
cell-id = <0x801>; | |
label = "fab-mnoc-ahb"; | |
qcom,fab-dev; | |
qcom,base-name = "mmnoc-ahb-base"; | |
qcom,bypass-qos-prg; | |
qcom,setrate-only-clk; | |
qcom,bus-type = <0x1>; | |
clock-names = "bus_clk", "bus_a_clk"; | |
clocks = <0x27 0x86f49203 0x27 0x86f49203>; | |
linux,phandle = <0x18a>; | |
phandle = <0x18a>; | |
}; | |
mas-pcie-0 { | |
cell-id = <0x2d>; | |
label = "mas-pcie-0"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,qport = <0x1>; | |
qcom,qos-mode = "fixed"; | |
qcom,connections = <0x14c>; | |
qcom,prio1 = <0x1>; | |
qcom,prio0 = <0x1>; | |
qcom,bus-dev = <0x14d>; | |
qcom,mas-rpm-id = <0x41>; | |
}; | |
mas-usb3 { | |
cell-id = <0x3d>; | |
label = "mas-usb3"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,qport = <0x2>; | |
qcom,qos-mode = "fixed"; | |
qcom,connections = <0x14c>; | |
qcom,prio1 = <0x1>; | |
qcom,prio0 = <0x1>; | |
qcom,bus-dev = <0x14d>; | |
qcom,mas-rpm-id = <0x20>; | |
}; | |
mas-ufs { | |
cell-id = <0x5f>; | |
label = "mas-ufs"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,qport = <0x0>; | |
qcom,qos-mode = "fixed"; | |
qcom,connections = <0x14c>; | |
qcom,prio1 = <0x1>; | |
qcom,prio0 = <0x1>; | |
qcom,bus-dev = <0x14d>; | |
qcom,mas-rpm-id = <0x44>; | |
}; | |
mas-blsp-2 { | |
cell-id = <0x54>; | |
label = "mas-blsp-2"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,qport = <0x4>; | |
qcom,qos-mode = "fixed"; | |
qcom,connections = <0x14c>; | |
qcom,bus-dev = <0x14d>; | |
qcom,mas-rpm-id = <0x27>; | |
}; | |
mas-cnoc-a2noc { | |
cell-id = <0x0>; | |
label = "mas-cnoc-a2noc"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,connections = <0x14e>; | |
qcom,bus-dev = <0x14f>; | |
qcom,mas-rpm-id = <0x92>; | |
linux,phandle = <0x19e>; | |
phandle = <0x19e>; | |
}; | |
mas-ipa { | |
cell-id = <0x5a>; | |
label = "mas-ipa"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,qport = <0x1>; | |
qcom,qos-mode = "fixed"; | |
qcom,connections = <0x14e>; | |
qcom,prio1 = <0x1>; | |
qcom,prio0 = <0x1>; | |
qcom,bus-dev = <0x14f>; | |
qcom,mas-rpm-id = <0x3b>; | |
}; | |
mas-sdcc-2 { | |
cell-id = <0x51>; | |
label = "mas-sdcc-2"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,qport = <0x6>; | |
qcom,qos-mode = "fixed"; | |
qcom,connections = <0x14e>; | |
qcom,bus-dev = <0x14f>; | |
qcom,mas-rpm-id = <0x23>; | |
}; | |
mas-sdcc-4 { | |
cell-id = <0x50>; | |
label = "mas-sdcc-4"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,qport = <0x7>; | |
qcom,qos-mode = "fixed"; | |
qcom,connections = <0x14e>; | |
qcom,bus-dev = <0x14f>; | |
qcom,mas-rpm-id = <0x24>; | |
}; | |
mas-tsif { | |
cell-id = <0x52>; | |
label = "mas-tsif"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,connections = <0x14e>; | |
qcom,bus-dev = <0x14f>; | |
qcom,mas-rpm-id = <0x25>; | |
}; | |
mas-blsp-1 { | |
cell-id = <0x56>; | |
label = "mas-blsp-1"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,qport = <0x8>; | |
qcom,qos-mode = "fixed"; | |
qcom,connections = <0x14e>; | |
qcom,bus-dev = <0x14f>; | |
qcom,mas-rpm-id = <0x29>; | |
}; | |
mas-cr-virt-a2noc { | |
cell-id = <0x75>; | |
label = "mas-cr-virt-a2noc"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,qport = <0x9>; | |
qcom,qos-mode = "fixed"; | |
qcom,connections = <0x14e>; | |
qcom,bus-dev = <0x14f>; | |
qcom,mas-rpm-id = <0x91>; | |
linux,phandle = <0x1a1>; | |
phandle = <0x1a1>; | |
}; | |
mas-gnoc-bimc { | |
cell-id = <0x74>; | |
label = "mas-gnoc-bimc"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x2>; | |
qcom,ap-owned; | |
qcom,qport = <0x0>; | |
qcom,qos-mode = "fixed"; | |
qcom,connections = <0x150 0x151>; | |
qcom,prio-lvl = <0x0>; | |
qcom,prio-rd = <0x0>; | |
qcom,prio-wr = <0x0>; | |
qcom,bus-dev = <0x152>; | |
qcom,mas-rpm-id = <0x90>; | |
linux,phandle = <0x1a2>; | |
phandle = <0x1a2>; | |
}; | |
mas-oxili { | |
cell-id = <0x1a>; | |
label = "mas-oxili"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x2>; | |
qcom,ap-owned; | |
qcom,qport = <0x1>; | |
qcom,qos-mode = "bypass"; | |
qcom,connections = <0x153 0x154 0x150 0x151>; | |
qcom,bus-dev = <0x152>; | |
qcom,mas-rpm-id = <0x6>; | |
}; | |
mas-mnoc-bimc { | |
cell-id = <0x272b>; | |
label = "mas-mnoc-bimc"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x2>; | |
qcom,ap-owned; | |
qcom,qport = <0x2>; | |
qcom,qos-mode = "bypass"; | |
qcom,connections = <0x153 0x154 0x150 0x151>; | |
qcom,bus-dev = <0x152>; | |
qcom,mas-rpm-id = <0x2>; | |
linux,phandle = <0x1a3>; | |
phandle = <0x1a3>; | |
}; | |
mas-snoc-bimc { | |
cell-id = <0x272f>; | |
label = "mas-snoc-bimc"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x2>; | |
qcom,qport = <0x3>; | |
qcom,qos-mode = "bypass"; | |
qcom,connections = <0x154 0x150>; | |
qcom,bus-dev = <0x152>; | |
qcom,mas-rpm-id = <0x3>; | |
linux,phandle = <0x1a4>; | |
phandle = <0x1a4>; | |
}; | |
mas-snoc-cnoc { | |
cell-id = <0x2733>; | |
label = "mas-snoc-cnoc"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,connections = <0x155 0x156 0x157 0x158 0x159 0x15a 0x15b 0x15c 0x15d 0x15e 0x15f 0x160 0x161 0x162 0x163 0x164 0x165 0x166 0x167 0x168 0x169 0x16a 0x16b 0x16c 0x16d 0x16e 0x16f 0x170 0x171 0x172 0x173 0x174 0x175 0x176 0x177 0x178 0x179>; | |
qcom,bus-dev = <0x17a>; | |
qcom,mas-rpm-id = <0x34>; | |
linux,phandle = <0x1a5>; | |
phandle = <0x1a5>; | |
}; | |
mas-qdss-dap { | |
cell-id = <0x4c>; | |
label = "mas-qdss-dap"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,connections = <0x155 0x156 0x157 0x158 0x159 0x15a 0x15b 0x15c 0x15d 0x15e 0x15f 0x160 0x161 0x162 0x163 0x164 0x165 0x166 0x167 0x168 0x169 0x16a 0x16b 0x16c 0x16d 0x16f 0x170 0x171 0x172 0x173 0x174 0x175 0x176 0x177 0x16e 0x178 0x179 0x17b>; | |
qcom,bus-dev = <0x17a>; | |
qcom,mas-rpm-id = <0x31>; | |
}; | |
mas-crypto-c0 { | |
cell-id = <0x37>; | |
label = "mas-crypto-c0"; | |
qcom,buswidth = <0x28a>; | |
qcom,agg-ports = <0x1>; | |
qcom,connections = <0x17c>; | |
qcom,bus-dev = <0x14f>; | |
qcom,mas-rpm-id = <0x17>; | |
}; | |
mas-apps-proc { | |
cell-id = <0x1>; | |
label = "mas-apps-proc"; | |
qcom,buswidth = <0x20>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,connections = <0x17d>; | |
qcom,bus-dev = <0x17e>; | |
qcom,mas-rpm-id = <0x0>; | |
}; | |
mas-cnoc-mnoc-mmss-cfg { | |
cell-id = <0x66>; | |
label = "mas-cnoc-mnoc-mmss-cfg"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,connections = <0x17f 0x180 0x181 0x182 0x183 0x184 0x185 0x186 0x187 0x188 0x189>; | |
qcom,bus-dev = <0x18a>; | |
qcom,mas-rpm-id = <0x4>; | |
linux,phandle = <0x1a0>; | |
phandle = <0x1a0>; | |
}; | |
mas-cnoc-mnoc-cfg { | |
cell-id = <0x67>; | |
label = "mas-cnoc-mnoc-cfg"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,connections = <0x18b>; | |
qcom,bus-dev = <0x18c>; | |
qcom,mas-rpm-id = <0x5>; | |
linux,phandle = <0x19f>; | |
phandle = <0x19f>; | |
}; | |
mas-cpp { | |
cell-id = <0x6a>; | |
label = "mas-cpp"; | |
qcom,buswidth = <0x20>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,qport = <0x5>; | |
qcom,qos-mode = "bypass"; | |
qcom,connections = <0x18d>; | |
qcom,bus-dev = <0x18c>; | |
qcom,mas-rpm-id = <0x73>; | |
}; | |
mas-jpeg { | |
cell-id = <0x3e>; | |
label = "mas-jpeg"; | |
qcom,buswidth = <0x20>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,qport = <0x7>; | |
qcom,qos-mode = "bypass"; | |
qcom,connections = <0x18d>; | |
qcom,bus-dev = <0x18c>; | |
qcom,mas-rpm-id = <0x7>; | |
}; | |
mas-mdp-p0 { | |
cell-id = <0x16>; | |
label = "mas-mdp-p0"; | |
qcom,buswidth = <0x20>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,qport = <0x1>; | |
qcom,qos-mode = "bypass"; | |
qcom,connections = <0x18d>; | |
qcom,bus-dev = <0x18c>; | |
qcom,vrail-comp = <0x19>; | |
qcom,mas-rpm-id = <0x8>; | |
clk-mdss-axi-no-rate-supply = <0x2a>; | |
clk-mdss-ahb-no-rate-supply = <0x2a>; | |
qcom,node-qos-clks { | |
clock-names = "clk-mdss-ahb-no-rate", "clk-mdss-axi-no-rate"; | |
clocks = <0x27 0x85d37ab5 0x27 0xdf04fc1d>; | |
}; | |
}; | |
mas-mdp-p1 { | |
cell-id = <0x17>; | |
label = "mas-mdp-p1"; | |
qcom,buswidth = <0x20>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,qport = <0x2>; | |
qcom,qos-mode = "bypass"; | |
qcom,connections = <0x18d>; | |
qcom,bus-dev = <0x18c>; | |
qcom,vrail-comp = <0x19>; | |
qcom,mas-rpm-id = <0x3d>; | |
}; | |
mas-rotator { | |
cell-id = <0x19>; | |
label = "mas-rotator"; | |
qcom,buswidth = <0x20>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,qport = <0x0>; | |
qcom,qos-mode = "bypass"; | |
qcom,connections = <0x18d>; | |
qcom,bus-dev = <0x18c>; | |
qcom,mas-rpm-id = <0x78>; | |
}; | |
mas-venus { | |
cell-id = <0x3f>; | |
label = "mas-venus"; | |
qcom,buswidth = <0x20>; | |
qcom,agg-ports = <0x2>; | |
qcom,ap-owned; | |
qcom,qport = <0x3 0x4>; | |
qcom,qos-mode = "bypass"; | |
qcom,connections = <0x18d>; | |
qcom,bus-dev = <0x18c>; | |
qcom,mas-rpm-id = <0x9>; | |
}; | |
mas-vfe { | |
cell-id = <0x1d>; | |
label = "mas-vfe"; | |
qcom,buswidth = <0x20>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,qport = <0x6>; | |
qcom,qos-mode = "bypass"; | |
qcom,connections = <0x18d>; | |
qcom,bus-dev = <0x18c>; | |
qcom,mas-rpm-id = <0xb>; | |
}; | |
mas-venus-vmem { | |
cell-id = <0x44>; | |
label = "mas-venus-vmem"; | |
qcom,buswidth = <0x20>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,connections = <0x18e>; | |
qcom,bus-dev = <0x18c>; | |
qcom,mas-rpm-id = <0x79>; | |
}; | |
mas-hmss { | |
cell-id = <0x2b>; | |
label = "mas-hmss"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,qport = <0x3>; | |
qcom,qos-mode = "fixed"; | |
qcom,connections = <0x18f 0x190 0x191>; | |
qcom,prio1 = <0x1>; | |
qcom,prio0 = <0x1>; | |
qcom,bus-dev = <0x192>; | |
qcom,mas-rpm-id = <0x76>; | |
}; | |
mas-qdss-bam { | |
cell-id = <0x35>; | |
label = "mas-qdss-bam"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,qport = <0x1>; | |
qcom,qos-mode = "fixed"; | |
qcom,connections = <0x190 0x18f 0x193 0x191>; | |
qcom,prio1 = <0x1>; | |
qcom,prio0 = <0x1>; | |
qcom,bus-dev = <0x192>; | |
qcom,mas-rpm-id = <0x13>; | |
}; | |
mas-snoc-cfg { | |
cell-id = <0x36>; | |
label = "mas-snoc-cfg"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,connections = <0x194>; | |
qcom,bus-dev = <0x192>; | |
qcom,mas-rpm-id = <0x14>; | |
}; | |
mas-bimc-snoc-0 { | |
cell-id = <0x2720>; | |
label = "mas-bimc-snoc-0"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,connections = <0x18f 0x195 0x196 0x197 0x193 0x190 0x198>; | |
qcom,bus-dev = <0x192>; | |
qcom,mas-rpm-id = <0x15>; | |
linux,phandle = <0x19c>; | |
phandle = <0x19c>; | |
}; | |
mas-bimc-snoc-1 { | |
cell-id = <0x2747>; | |
label = "mas-bimc-snoc-1"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,connections = <0x199>; | |
qcom,bus-dev = <0x192>; | |
qcom,mas-rpm-id = <0x6d>; | |
linux,phandle = <0x19d>; | |
phandle = <0x19d>; | |
}; | |
mas-a1noc-snoc { | |
cell-id = <0x274f>; | |
label = "mas-a1noc-snoc"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,connections = <0x18f 0x199 0x195 0x196 0x191 0x193 0x190 0x198>; | |
qcom,bus-dev = <0x192>; | |
qcom,mas-rpm-id = <0x6f>; | |
linux,phandle = <0x19a>; | |
phandle = <0x19a>; | |
}; | |
mas-a2noc-snoc { | |
cell-id = <0x2750>; | |
label = "mas-a2noc-snoc"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,connections = <0x18f 0x199 0x195 0x196 0x191 0x197 0x193 0x190 0x198>; | |
qcom,bus-dev = <0x192>; | |
qcom,mas-rpm-id = <0x70>; | |
linux,phandle = <0x19b>; | |
phandle = <0x19b>; | |
}; | |
mas-qdss-etr { | |
cell-id = <0x3c>; | |
label = "mas-qdss-etr"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,qport = <0x2>; | |
qcom,qos-mode = "fixed"; | |
qcom,connections = <0x190 0x18f 0x193 0x191>; | |
qcom,prio1 = <0x1>; | |
qcom,prio0 = <0x1>; | |
qcom,bus-dev = <0x192>; | |
qcom,mas-rpm-id = <0x1f>; | |
}; | |
slv-a1noc-snoc { | |
cell-id = <0x274e>; | |
label = "slv-a1noc-snoc"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,bus-dev = <0x14d>; | |
qcom,connections = <0x19a>; | |
qcom,slv-rpm-id = <0x8e>; | |
linux,phandle = <0x14c>; | |
phandle = <0x14c>; | |
}; | |
slv-a2noc-snoc { | |
cell-id = <0x2751>; | |
label = "slv-a2noc-snoc"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,bus-dev = <0x14f>; | |
qcom,connections = <0x19b>; | |
qcom,slv-rpm-id = <0x8f>; | |
linux,phandle = <0x14e>; | |
phandle = <0x14e>; | |
}; | |
slv-ebi { | |
cell-id = <0x200>; | |
label = "slv-ebi"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x2>; | |
qcom,bus-dev = <0x152>; | |
qcom,slv-rpm-id = <0x0>; | |
linux,phandle = <0x150>; | |
phandle = <0x150>; | |
}; | |
slv-hmss-l3 { | |
cell-id = <0x2a8>; | |
label = "slv-hmss-l3"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,bus-dev = <0x152>; | |
qcom,slv-rpm-id = <0xa0>; | |
linux,phandle = <0x154>; | |
phandle = <0x154>; | |
}; | |
slv-bimc-snoc-0 { | |
cell-id = <0x2721>; | |
label = "slv-bimc-snoc-0"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,bus-dev = <0x152>; | |
qcom,connections = <0x19c>; | |
qcom,slv-rpm-id = <0x2>; | |
linux,phandle = <0x151>; | |
phandle = <0x151>; | |
}; | |
slv-bimc-snoc-1 { | |
cell-id = <0x2748>; | |
label = "slv-bimc-snoc-1"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x152>; | |
qcom,connections = <0x19d>; | |
qcom,slv-rpm-id = <0x8a>; | |
linux,phandle = <0x153>; | |
phandle = <0x153>; | |
}; | |
slv-cnoc-a2noc { | |
cell-id = <0x2732>; | |
label = "slv-cnoc-a2noc"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,connections = <0x19e>; | |
qcom,slv-rpm-id = <0xd0>; | |
linux,phandle = <0x17b>; | |
phandle = <0x17b>; | |
}; | |
slv-ssc-cfg { | |
cell-id = <0x2b9>; | |
label = "slv-ssc-cfg"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0xb1>; | |
linux,phandle = <0x16e>; | |
phandle = <0x16e>; | |
}; | |
slv-mpm { | |
cell-id = <0x218>; | |
label = "slv-mpm"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x3e>; | |
linux,phandle = <0x15a>; | |
phandle = <0x15a>; | |
}; | |
slv-pmic-arb { | |
cell-id = <0x278>; | |
label = "slv-pmic-arb"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x3b>; | |
linux,phandle = <0x167>; | |
phandle = <0x167>; | |
}; | |
slv-tlmm-north { | |
cell-id = <0x2db>; | |
label = "slv-tlmm-north"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0xd6>; | |
linux,phandle = <0x179>; | |
phandle = <0x179>; | |
}; | |
slv-pimem-cfg { | |
cell-id = <0x2a9>; | |
label = "slv-pimem-cfg"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0xa7>; | |
linux,phandle = <0x15e>; | |
phandle = <0x15e>; | |
}; | |
slv-imem-cfg { | |
cell-id = <0x273>; | |
label = "slv-imem-cfg"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x36>; | |
linux,phandle = <0x175>; | |
phandle = <0x175>; | |
}; | |
slv-message-ram { | |
cell-id = <0x274>; | |
label = "slv-message-ram"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x37>; | |
linux,phandle = <0x157>; | |
phandle = <0x157>; | |
}; | |
slv-skl { | |
cell-id = <0x2dd>; | |
label = "slv-skl"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0xc4>; | |
linux,phandle = <0x155>; | |
phandle = <0x155>; | |
}; | |
slv-bimc-cfg { | |
cell-id = <0x275>; | |
label = "slv-bimc-cfg"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x38>; | |
linux,phandle = <0x15b>; | |
phandle = <0x15b>; | |
}; | |
slv-prng { | |
cell-id = <0x26a>; | |
label = "slv-prng"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x2c>; | |
linux,phandle = <0x162>; | |
phandle = <0x162>; | |
}; | |
slv-a2noc-cfg { | |
cell-id = <0x2b0>; | |
label = "slv-a2noc-cfg"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x96>; | |
linux,phandle = <0x166>; | |
phandle = <0x166>; | |
}; | |
slv-ipa { | |
cell-id = <0x2a4>; | |
label = "slv-ipa"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0xb7>; | |
linux,phandle = <0x16b>; | |
phandle = <0x16b>; | |
}; | |
slv-tcsr { | |
cell-id = <0x26f>; | |
label = "slv-tcsr"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x32>; | |
linux,phandle = <0x178>; | |
phandle = <0x178>; | |
}; | |
slv-snoc-cfg { | |
cell-id = <0x282>; | |
label = "slv-snoc-cfg"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x46>; | |
linux,phandle = <0x16d>; | |
phandle = <0x16d>; | |
}; | |
slv-clk-ctl { | |
cell-id = <0x26c>; | |
label = "slv-clk-ctl"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x2f>; | |
linux,phandle = <0x161>; | |
phandle = <0x161>; | |
}; | |
slv-glm { | |
cell-id = <0x2d6>; | |
label = "slv-glm"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0xd1>; | |
linux,phandle = <0x16c>; | |
phandle = <0x16c>; | |
}; | |
slv-spdm { | |
cell-id = <0x279>; | |
label = "slv-spdm"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x3c>; | |
linux,phandle = <0x15d>; | |
phandle = <0x15d>; | |
}; | |
slv-gpuss-cfg { | |
cell-id = <0x256>; | |
label = "slv-gpuss-cfg"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0xb>; | |
linux,phandle = <0x177>; | |
phandle = <0x177>; | |
}; | |
slv-cnoc-mnoc-cfg { | |
cell-id = <0x280>; | |
label = "slv-cnoc-mnoc-cfg"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,connections = <0x19f>; | |
qcom,slv-rpm-id = <0x42>; | |
linux,phandle = <0x173>; | |
phandle = <0x173>; | |
}; | |
slv-qm-cfg { | |
cell-id = <0x2d9>; | |
label = "slv-qm-cfg"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0xd4>; | |
linux,phandle = <0x165>; | |
phandle = <0x165>; | |
}; | |
slv-mss-cfg { | |
cell-id = <0x26d>; | |
label = "slv-mss-cfg"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x30>; | |
linux,phandle = <0x174>; | |
phandle = <0x174>; | |
}; | |
slv-ufs-cfg { | |
cell-id = <0x28a>; | |
label = "slv-ufs-cfg"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x5c>; | |
linux,phandle = <0x168>; | |
phandle = <0x168>; | |
}; | |
slv-tlmm-west { | |
cell-id = <0x2dc>; | |
label = "slv-tlmm-west"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0xd7>; | |
linux,phandle = <0x158>; | |
phandle = <0x158>; | |
}; | |
slv-a1noc-cfg { | |
cell-id = <0x2af>; | |
label = "slv-a1noc-cfg"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x93>; | |
linux,phandle = <0x176>; | |
phandle = <0x176>; | |
}; | |
slv-ahb2phy { | |
cell-id = <0x2ad>; | |
label = "slv-ahb2phy"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0xa3>; | |
linux,phandle = <0x16a>; | |
phandle = <0x16a>; | |
}; | |
slv-blsp-2 { | |
cell-id = <0x263>; | |
label = "slv-blsp-2"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x25>; | |
linux,phandle = <0x156>; | |
phandle = <0x156>; | |
}; | |
slv-pdm { | |
cell-id = <0x267>; | |
label = "slv-pdm"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x29>; | |
linux,phandle = <0x171>; | |
phandle = <0x171>; | |
}; | |
slv-usb3-0 { | |
cell-id = <0x247>; | |
label = "slv-usb3-0"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x16>; | |
linux,phandle = <0x163>; | |
phandle = <0x163>; | |
}; | |
slv-a1noc-smmu-cfg { | |
cell-id = <0x2b4>; | |
label = "slv-a1noc-smmu-cfg"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x95>; | |
linux,phandle = <0x15f>; | |
phandle = <0x15f>; | |
}; | |
slv-blsp-1 { | |
cell-id = <0x265>; | |
label = "slv-blsp-1"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x27>; | |
linux,phandle = <0x160>; | |
phandle = <0x160>; | |
}; | |
slv-sdcc-2 { | |
cell-id = <0x260>; | |
label = "slv-sdcc-2"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x21>; | |
linux,phandle = <0x16f>; | |
phandle = <0x16f>; | |
}; | |
slv-sdcc-4 { | |
cell-id = <0x261>; | |
label = "slv-sdcc-4"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x22>; | |
linux,phandle = <0x170>; | |
phandle = <0x170>; | |
}; | |
slv-tsif { | |
cell-id = <0x23f>; | |
label = "slv-tsif"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x23>; | |
linux,phandle = <0x159>; | |
phandle = <0x159>; | |
}; | |
slv-qdss-cfg { | |
cell-id = <0x27b>; | |
label = "slv-qdss-cfg"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x3f>; | |
linux,phandle = <0x164>; | |
phandle = <0x164>; | |
}; | |
slv-tlmm-east { | |
cell-id = <0x2da>; | |
label = "slv-tlmm-east"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0xd5>; | |
linux,phandle = <0x15c>; | |
phandle = <0x15c>; | |
}; | |
slv-cnoc-mnoc-mmss-cfg { | |
cell-id = <0x277>; | |
label = "slv-cnoc-mnoc-mmss-cfg"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,connections = <0x1a0>; | |
qcom,slv-rpm-id = <0x3a>; | |
linux,phandle = <0x172>; | |
phandle = <0x172>; | |
}; | |
slv-srvc-cnoc { | |
cell-id = <0x286>; | |
label = "slv-srvc-cnoc"; | |
qcom,buswidth = <0x4>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17a>; | |
qcom,slv-rpm-id = <0x4c>; | |
linux,phandle = <0x169>; | |
phandle = <0x169>; | |
}; | |
slv-cr-virt-a2noc { | |
cell-id = <0x2d4>; | |
label = "slv-cr-virt-a2noc"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x14f>; | |
qcom,connections = <0x1a1>; | |
qcom,slv-rpm-id = <0xcf>; | |
linux,phandle = <0x17c>; | |
phandle = <0x17c>; | |
}; | |
slv-gnoc-bimc { | |
cell-id = <0x2d7>; | |
label = "slv-gnoc-bimc"; | |
qcom,buswidth = <0x20>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x17e>; | |
qcom,connections = <0x1a2>; | |
qcom,slv-rpm-id = <0xd2>; | |
linux,phandle = <0x17d>; | |
phandle = <0x17d>; | |
}; | |
slv-camera-cfg { | |
cell-id = <0x24d>; | |
label = "slv-camera-cfg"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x18a>; | |
qcom,slv-rpm-id = <0x3>; | |
linux,phandle = <0x182>; | |
phandle = <0x182>; | |
}; | |
slv-camera-throttle-cfg { | |
cell-id = <0x2c5>; | |
label = "slv-camera-throttle-cfg"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x18a>; | |
qcom,slv-rpm-id = <0x9a>; | |
linux,phandle = <0x17f>; | |
phandle = <0x17f>; | |
}; | |
slv-misc-cfg { | |
cell-id = <0x252>; | |
label = "slv-misc-cfg"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x18a>; | |
qcom,slv-rpm-id = <0x8>; | |
linux,phandle = <0x181>; | |
phandle = <0x181>; | |
}; | |
slv-venus-throttle-cfg { | |
cell-id = <0x2b8>; | |
label = "slv-venus-throttle-cfg"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x18a>; | |
qcom,slv-rpm-id = <0xb2>; | |
linux,phandle = <0x184>; | |
phandle = <0x184>; | |
}; | |
slv-venus-cfg { | |
cell-id = <0x254>; | |
label = "slv-venus-cfg"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x18a>; | |
qcom,slv-rpm-id = <0xa>; | |
linux,phandle = <0x180>; | |
phandle = <0x180>; | |
}; | |
slv-vmem-cfg { | |
cell-id = <0x2c4>; | |
label = "slv-vmem-cfg"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x18a>; | |
qcom,slv-rpm-id = <0xb4>; | |
qcom,enable-only-clk; | |
clock-names = "node_clk"; | |
clocks = <0x27 0xd8b7278f>; | |
linux,phandle = <0x187>; | |
phandle = <0x187>; | |
}; | |
slv-mmss-clk-xpu-cfg { | |
cell-id = <0x258>; | |
label = "slv-mmss-clk-xpu-cfg"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x18a>; | |
qcom,slv-rpm-id = <0xd>; | |
linux,phandle = <0x188>; | |
phandle = <0x188>; | |
}; | |
slv-mmss-clk-cfg { | |
cell-id = <0x257>; | |
label = "slv-mmss-clk-cfg"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x18a>; | |
qcom,slv-rpm-id = <0xc>; | |
linux,phandle = <0x186>; | |
phandle = <0x186>; | |
}; | |
slv-display-cfg { | |
cell-id = <0x24e>; | |
label = "slv-display-cfg"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x18a>; | |
qcom,slv-rpm-id = <0x4>; | |
linux,phandle = <0x185>; | |
phandle = <0x185>; | |
}; | |
slv-display-throttle-cfg { | |
cell-id = <0x2bc>; | |
label = "slv-display-throttle-cfg"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x18a>; | |
qcom,slv-rpm-id = <0x9c>; | |
linux,phandle = <0x183>; | |
phandle = <0x183>; | |
}; | |
slv-smmu-cfg { | |
cell-id = <0x2d2>; | |
label = "slv-smmu-cfg"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x18a>; | |
qcom,slv-rpm-id = <0xcd>; | |
linux,phandle = <0x189>; | |
phandle = <0x189>; | |
}; | |
slv-mnoc-bimc { | |
cell-id = <0x272c>; | |
label = "slv-mnoc-bimc"; | |
qcom,buswidth = <0x20>; | |
qcom,agg-ports = <0x2>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x18c>; | |
qcom,connections = <0x1a3>; | |
qcom,slv-rpm-id = <0x10>; | |
qcom,enable-only-clk; | |
clock-names = "node_clk"; | |
clocks = <0x38 0xdb4b31e6>; | |
linux,phandle = <0x18d>; | |
phandle = <0x18d>; | |
}; | |
slv-vmem { | |
cell-id = <0x2c6>; | |
label = "slv-vmem"; | |
qcom,buswidth = <0x20>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x18c>; | |
qcom,slv-rpm-id = <0xb3>; | |
clock-names = "node_clk"; | |
clocks = <0x27 0xd8b7278f>; | |
linux,phandle = <0x18e>; | |
phandle = <0x18e>; | |
}; | |
slv-srvc-mnoc { | |
cell-id = <0x25b>; | |
label = "slv-srvc-mnoc"; | |
qcom,buswidth = <0x8>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x18c>; | |
qcom,slv-rpm-id = <0x11>; | |
linux,phandle = <0x18b>; | |
phandle = <0x18b>; | |
}; | |
slv-hmss { | |
cell-id = <0x2a1>; | |
label = "slv-hmss"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x192>; | |
qcom,slv-rpm-id = <0x14>; | |
linux,phandle = <0x196>; | |
phandle = <0x196>; | |
}; | |
slv-lpass { | |
cell-id = <0x20a>; | |
label = "slv-lpass"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x192>; | |
qcom,slv-rpm-id = <0x15>; | |
linux,phandle = <0x195>; | |
phandle = <0x195>; | |
}; | |
slv-wlan { | |
cell-id = <0x2d3>; | |
label = "slv-wlan"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,bus-dev = <0x192>; | |
qcom,slv-rpm-id = <0xce>; | |
linux,phandle = <0x197>; | |
phandle = <0x197>; | |
}; | |
slv-snoc-bimc { | |
cell-id = <0x2730>; | |
label = "slv-snoc-bimc"; | |
qcom,buswidth = <0x20>; | |
qcom,agg-ports = <0x2>; | |
qcom,bus-dev = <0x192>; | |
qcom,connections = <0x1a4>; | |
qcom,slv-rpm-id = <0x18>; | |
linux,phandle = <0x191>; | |
phandle = <0x191>; | |
}; | |
slv-snoc-cnoc { | |
cell-id = <0x2734>; | |
label = "slv-snoc-cnoc"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,bus-dev = <0x192>; | |
qcom,connections = <0x1a5>; | |
qcom,slv-rpm-id = <0x19>; | |
linux,phandle = <0x193>; | |
phandle = <0x193>; | |
}; | |
slv-imem { | |
cell-id = <0x249>; | |
label = "slv-imem"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,bus-dev = <0x192>; | |
qcom,slv-rpm-id = <0x1a>; | |
linux,phandle = <0x190>; | |
phandle = <0x190>; | |
}; | |
slv-pimem { | |
cell-id = <0x2c8>; | |
label = "slv-pimem"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,bus-dev = <0x192>; | |
qcom,slv-rpm-id = <0xa6>; | |
linux,phandle = <0x18f>; | |
phandle = <0x18f>; | |
}; | |
slv-qdss-stm { | |
cell-id = <0x24c>; | |
label = "slv-qdss-stm"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,bus-dev = <0x192>; | |
qcom,slv-rpm-id = <0x1e>; | |
linux,phandle = <0x198>; | |
phandle = <0x198>; | |
}; | |
slv-pcie-0 { | |
cell-id = <0x299>; | |
label = "slv-pcie-0"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,ap-owned; | |
qcom,bus-dev = <0x192>; | |
qcom,slv-rpm-id = <0x54>; | |
linux,phandle = <0x199>; | |
phandle = <0x199>; | |
}; | |
slv-srvc-snoc { | |
cell-id = <0x24b>; | |
label = "slv-srvc-snoc"; | |
qcom,buswidth = <0x10>; | |
qcom,agg-ports = <0x1>; | |
qcom,bus-dev = <0x192>; | |
qcom,slv-rpm-id = <0x1d>; | |
linux,phandle = <0x194>; | |
phandle = <0x194>; | |
}; | |
}; | |
devfreq_spdm_cpu { | |
compatible = "qcom,devfreq_spdm"; | |
qcom,msm-bus,name = "devfreq_spdm"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x1 0x200 0x0 0x0 0x1 0x200 0x0 0x0>; | |
qcom,msm-bus,active-only; | |
qcom,spdm-client = <0x0>; | |
qcom,bw-upstep = <0x3e8>; | |
qcom,bw-dwnstep = <0x3e8>; | |
qcom,max-vote = <0x2710>; | |
qcom,up-step-multp = <0x2>; | |
qcom,spdm-interval = <0x64>; | |
qcom,ports = <0x18>; | |
qcom,alpha-up = <0xc>; | |
qcom,alpha-down = <0xf>; | |
qcom,bucket-size = <0x8>; | |
qcom,pl-freqs = <0x3f7a0 0xbbfd0>; | |
qcom,reject-rate = <0x1388 0x1388 0x1388 0x1388 0x1388 0x1388>; | |
qcom,response-time-us = <0x2710 0x2710 0x2710 0x2710 0x2710 0x2710>; | |
qcom,cci-response-time-us = <0x2710 0x2710 0x2710 0x2710 0x2710 0x2710>; | |
qcom,max-cci-freq = <0xfd200>; | |
}; | |
devfreq_spdm_gov { | |
compatible = "qcom,gov_spdm_hyp"; | |
interrupt-names = "spdm-irq"; | |
interrupts = <0x0 0xc0 0x1>; | |
}; | |
qcom,kgsl-hyp { | |
compatible = "qcom,pil-tz-generic"; | |
qcom,pas-id = <0xd>; | |
qcom,firmware-name = "a540_zap"; | |
}; | |
qcom,kgsl-busmon { | |
label = "kgsl-busmon"; | |
compatible = "qcom,kgsl-busmon"; | |
}; | |
qcom,gpubw { | |
compatible = "qcom,devbw"; | |
governor = "bw_vbif"; | |
qcom,src-dst-ports = <0x1a 0x200>; | |
qcom,active-only; | |
qcom,bw-tbl = <0x0 0x2fa 0x478 0x5f5 0x8f0 0xc47 0x104d 0x144b 0x16e3 0x1e4f 0x269f 0x2e57 0x35c3>; | |
linux,phandle = <0x1a6>; | |
phandle = <0x1a6>; | |
}; | |
qcom,kgsl-3d0@5000000 { | |
label = "kgsl-3d0"; | |
compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; | |
status = "ok"; | |
reg = <0x5000000 0x40000>; | |
reg-names = "kgsl_3d0_reg_memory"; | |
interrupts = <0x0 0x12c 0x0>; | |
interrupt-names = "kgsl_3d0_irq"; | |
qcom,id = <0x0>; | |
qcom,chipid = <0x5040001>; | |
qcom,gpu-efuse-leakage = <0x70130 0x18>; | |
qcom,base-leakage-coefficient = <0x22>; | |
qcom,lm-limit = <0x1770>; | |
qcom,initial-pwrlevel = <0x6>; | |
qcom,idle-timeout = <0x50>; | |
qcom,no-nap; | |
qcom,highest-bank-bit = <0xf>; | |
qcom,snapshot-size = <0x100000>; | |
qcom,gpu-qdss-stm = <0x161c0000 0x40000>; | |
qcom,gpu-qtimer = <0x17921000 0x1000>; | |
qcom,tsens-name = "tsens_tz_sensor12"; | |
qcom,l2pc-cpu-mask = <0xf0>; | |
qcom,gpu-quirk-lmloadkill-disable; | |
qcom,gpmu-tsens = <0xc000d>; | |
qcom,max-power = <0x1548>; | |
qcom,gpmu-firmware = "a540_gpmu.fw2"; | |
qcom,gpmu-version = <0x3 0x0>; | |
qcom,zap-shader = "a540_zap"; | |
clocks = <0x2b 0x95f01bd5 0x38 0x72f20a57 0x60 0x58a0a7ca 0x38 0x3edd69ad 0x38 0x3909459b 0x60 0xb2678e80 0x60 0x7bd750e8 0x38 0xfd82abad>; | |
clock-names = "core_clk", "iface_clk", "rbbmtimer_clk", "mem_clk", "mem_iface_clk", "isense_clk", "rbcpr_clk", "iref_clk"; | |
qcom,isense-clk-on-level = <0x1>; | |
qcom,gpubw-dev = <0x1a6>; | |
qcom,bus-control; | |
qcom,msm-bus,name = "grp3d"; | |
qcom,bus-width = <0x20>; | |
qcom,msm-bus,num-cases = <0xd>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x1a 0x200 0x0 0x0 0x1a 0x200 0x0 0xc3500 0x1a 0x200 0x0 0x124f80 0x1a 0x200 0x0 0x186a00 0x1a 0x200 0x0 0x249f00 0x1a 0x200 0x0 0x324b00 0x1a 0x200 0x0 0x42c5c0 0x1a 0x200 0x0 0x532140 0x1a 0x200 0x0 0x5dc000 0x1a 0x200 0x0 0x7c2540 0x1a 0x200 0x0 0x9e3400 0x1a 0x200 0x0 0xbdd1c0 0x1a 0x200 0x0 0xdc3700>; | |
regulator-names = "vddcx", "vdd"; | |
vddcx-supply = <0xd3>; | |
vdd-supply = <0x1a7>; | |
coresight-name = "coresight-gfx"; | |
coresight-atid = <0x3>; | |
linux,phandle = <0x5d>; | |
phandle = <0x5d>; | |
port { | |
endpoint { | |
remote-endpoint = <0x1a8>; | |
linux,phandle = <0x10f>; | |
phandle = <0x10f>; | |
}; | |
}; | |
qcom,gpu-mempools { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
compatible = "qcom,gpu-mempools"; | |
qcom,gpu-mempool@0 { | |
reg = <0x0>; | |
qcom,mempool-page-size = <0x1000>; | |
qcom,mempool-reserved = <0x800>; | |
qcom,mempool-allocate; | |
}; | |
qcom,gpu-mempool@1 { | |
reg = <0x1>; | |
qcom,mempool-page-size = <0x2000>; | |
qcom,mempool-reserved = <0x400>; | |
qcom,mempool-allocate; | |
}; | |
qcom,gpu-mempool@2 { | |
reg = <0x2>; | |
qcom,mempool-page-size = <0x10000>; | |
qcom,mempool-reserved = <0x100>; | |
}; | |
qcom,gpu-mempool@3 { | |
reg = <0x3>; | |
qcom,mempool-page-size = <0x100000>; | |
qcom,mempool-reserved = <0x20>; | |
}; | |
}; | |
qcom,gpu-pwrlevels { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
compatible = "qcom,gpu-pwrlevels"; | |
qcom,gpu-pwrlevel@0 { | |
reg = <0x0>; | |
qcom,gpu-freq = <0x2a51bd80>; | |
qcom,bus-freq = <0xc>; | |
qcom,bus-min = <0xc>; | |
qcom,bus-max = <0xc>; | |
}; | |
qcom,gpu-pwrlevel@1 { | |
reg = <0x1>; | |
qcom,gpu-freq = <0x27ef6380>; | |
qcom,bus-freq = <0xc>; | |
qcom,bus-min = <0xb>; | |
qcom,bus-max = <0xc>; | |
}; | |
qcom,gpu-pwrlevel@2 { | |
reg = <0x2>; | |
qcom,gpu-freq = <0x23863d00>; | |
qcom,bus-freq = <0xb>; | |
qcom,bus-min = <0x9>; | |
qcom,bus-max = <0xc>; | |
}; | |
qcom,gpu-pwrlevel@3 { | |
reg = <0x3>; | |
qcom,gpu-freq = <0x1eb246c0>; | |
qcom,bus-freq = <0xb>; | |
qcom,bus-min = <0x9>; | |
qcom,bus-max = <0xc>; | |
}; | |
qcom,gpu-pwrlevel@4 { | |
reg = <0x4>; | |
qcom,gpu-freq = <0x18ad2380>; | |
qcom,bus-freq = <0x9>; | |
qcom,bus-min = <0x8>; | |
qcom,bus-max = <0xb>; | |
}; | |
qcom,gpu-pwrlevel@5 { | |
reg = <0x5>; | |
qcom,gpu-freq = <0x14628180>; | |
qcom,bus-freq = <0x8>; | |
qcom,bus-min = <0x5>; | |
qcom,bus-max = <0x9>; | |
}; | |
qcom,gpu-pwrlevel@6 { | |
reg = <0x6>; | |
qcom,gpu-freq = <0xf518240>; | |
qcom,bus-freq = <0x5>; | |
qcom,bus-min = <0x3>; | |
qcom,bus-max = <0x8>; | |
}; | |
qcom,gpu-pwrlevel@7 { | |
reg = <0x7>; | |
qcom,gpu-freq = <0x19bfcc0>; | |
qcom,bus-freq = <0x0>; | |
qcom,bus-min = <0x0>; | |
qcom,bus-max = <0x0>; | |
}; | |
}; | |
}; | |
qcom,kgsl-iommu { | |
compatible = "qcom,kgsl-smmu-v2"; | |
reg = <0x5040000 0x10000>; | |
qcom,protect = <0x40000 0x10000>; | |
qcom,micro-mmu-control = <0x6000>; | |
clocks = <0x38 0x72f20a57 0x38 0x3edd69ad 0x38 0x3909459b>; | |
clock-names = "iface_clk", "mem_clk", "mem_iface_clk"; | |
qcom,secure_align_mask = <0xfff>; | |
qcom,retention; | |
qcom,hyp_secure_alloc; | |
gfx3d_user { | |
compatible = "qcom,smmu-kgsl-cb"; | |
label = "gfx3d_user"; | |
iommus = <0x1a9 0x0>; | |
qcom,gpu-offset = <0x48000>; | |
}; | |
gfx3d_secure { | |
compatible = "qcom,smmu-kgsl-cb"; | |
iommus = <0x1a9 0x2>; | |
}; | |
}; | |
pinctrl@03400000 { | |
compatible = "qcom,msm8998-pinctrl"; | |
reg = <0x3400000 0xc00000>; | |
interrupts = <0x0 0xd0 0x0>; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0x7c>; | |
phandle = <0x7c>; | |
uart_console_active { | |
linux,phandle = <0x39>; | |
phandle = <0x39>; | |
mux { | |
pins = "gpio4", "gpio5"; | |
function = "blsp_uart8_a"; | |
}; | |
config { | |
pins = "gpio4", "gpio5"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
wcd9xxx_intr { | |
wcd_intr_default { | |
linux,phandle = <0x28c>; | |
phandle = <0x28c>; | |
mux { | |
pins = "gpio54"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio54"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
}; | |
i2c_1 { | |
i2c_1_active { | |
linux,phandle = <0x1e0>; | |
phandle = <0x1e0>; | |
mux { | |
pins = "gpio2", "gpio3"; | |
function = "blsp_i2c1"; | |
}; | |
config { | |
pins = "gpio2", "gpio3"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
i2c_1_sleep { | |
linux,phandle = <0x1e1>; | |
phandle = <0x1e1>; | |
mux { | |
pins = "gpio2", "gpio3"; | |
function = "blsp_i2c1"; | |
}; | |
config { | |
pins = "gpio2", "gpio3"; | |
drive-strength = <0x2>; | |
bias-pull-up; | |
}; | |
}; | |
}; | |
i2c_2 { | |
i2c_2_active { | |
linux,phandle = <0x1e2>; | |
phandle = <0x1e2>; | |
mux { | |
pins = "gpio32", "gpio33"; | |
function = "blsp_i2c2"; | |
}; | |
config { | |
pins = "gpio32", "gpio33"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
i2c_2_sleep { | |
linux,phandle = <0x1e3>; | |
phandle = <0x1e3>; | |
mux { | |
pins = "gpio32", "gpio33"; | |
function = "blsp_i2c2"; | |
}; | |
config { | |
pins = "gpio32", "gpio33"; | |
drive-strength = <0x2>; | |
bias-pull-up; | |
}; | |
}; | |
}; | |
i2c_3 { | |
i2c_3_active { | |
linux,phandle = <0x1e4>; | |
phandle = <0x1e4>; | |
mux { | |
pins = "gpio47", "gpio48"; | |
function = "blsp_i2c3"; | |
}; | |
config { | |
pins = "gpio47", "gpio48"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
i2c_3_sleep { | |
linux,phandle = <0x1e5>; | |
phandle = <0x1e5>; | |
mux { | |
pins = "gpio47", "gpio48"; | |
function = "blsp_i2c3"; | |
}; | |
config { | |
pins = "gpio47", "gpio48"; | |
drive-strength = <0x2>; | |
bias-pull-up; | |
}; | |
}; | |
}; | |
i2c_4 { | |
i2c_4_active { | |
linux,phandle = <0x1e6>; | |
phandle = <0x1e6>; | |
mux { | |
pins = "gpio10", "gpio11"; | |
function = "blsp_i2c4"; | |
}; | |
config { | |
pins = "gpio10", "gpio11"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
i2c_4_sleep { | |
linux,phandle = <0x1e7>; | |
phandle = <0x1e7>; | |
mux { | |
pins = "gpio10", "gpio11"; | |
function = "blsp_i2c4"; | |
}; | |
config { | |
pins = "gpio10", "gpio11"; | |
drive-strength = <0x2>; | |
bias-pull-up; | |
}; | |
}; | |
}; | |
i2c_5 { | |
i2c_5_active { | |
linux,phandle = <0x1e8>; | |
phandle = <0x1e8>; | |
mux { | |
pins = "gpio87", "gpio88"; | |
function = "blsp_i2c5"; | |
}; | |
config { | |
pins = "gpio87", "gpio88"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
i2c_5_sleep { | |
linux,phandle = <0x1e9>; | |
phandle = <0x1e9>; | |
mux { | |
pins = "gpio87", "gpio88"; | |
function = "blsp_i2c5"; | |
}; | |
config { | |
pins = "gpio87", "gpio88"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
}; | |
i2c_6 { | |
i2c_6_active { | |
linux,phandle = <0x1ef>; | |
phandle = <0x1ef>; | |
mux { | |
pins = "gpio43", "gpio44"; | |
function = "blsp_i2c6"; | |
}; | |
config { | |
pins = "gpio43", "gpio44"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
i2c_6_sleep { | |
linux,phandle = <0x1f0>; | |
phandle = <0x1f0>; | |
mux { | |
pins = "gpio43", "gpio44"; | |
function = "blsp_i2c6"; | |
}; | |
config { | |
pins = "gpio43", "gpio44"; | |
drive-strength = <0x2>; | |
bias-pull-up; | |
}; | |
}; | |
}; | |
nfc { | |
nfc_int_active { | |
linux,phandle = <0x1f1>; | |
phandle = <0x1f1>; | |
mux { | |
pins = "gpio92"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio92"; | |
drive-strength = <0x6>; | |
bias-pull-up; | |
}; | |
}; | |
nfc_int_suspend { | |
linux,phandle = <0x1f3>; | |
phandle = <0x1f3>; | |
mux { | |
pins = "gpio92"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio92"; | |
drive-strength = <0x6>; | |
bias-pull-up; | |
}; | |
}; | |
nfc_enable_active { | |
linux,phandle = <0x1f2>; | |
phandle = <0x1f2>; | |
mux { | |
pins = "gpio12", "gpio116"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio12", "gpio116"; | |
drive-strength = <0x6>; | |
bias-pull-up; | |
}; | |
}; | |
nfc_enable_suspend { | |
linux,phandle = <0x1f4>; | |
phandle = <0x1f4>; | |
mux { | |
pins = "gpio12", "gpio116"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio12", "gpio116"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
}; | |
i2c_7 { | |
i2c_7_active { | |
linux,phandle = <0x1f6>; | |
phandle = <0x1f6>; | |
mux { | |
pins = "gpio55", "gpio56"; | |
function = "blsp_i2c7"; | |
}; | |
config { | |
pins = "gpio55", "gpio56"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
i2c_7_sleep { | |
linux,phandle = <0x1f7>; | |
phandle = <0x1f7>; | |
mux { | |
pins = "gpio55", "gpio56"; | |
function = "blsp_i2c7"; | |
}; | |
config { | |
pins = "gpio55", "gpio56"; | |
drive-strength = <0x2>; | |
bias-pull-up; | |
}; | |
}; | |
}; | |
i2c_8 { | |
i2c_8_active { | |
linux,phandle = <0x1fc>; | |
phandle = <0x1fc>; | |
mux { | |
pins = "gpio6", "gpio7"; | |
function = "blsp_i2c8"; | |
}; | |
config { | |
pins = "gpio6", "gpio7"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
i2c_8_sleep { | |
linux,phandle = <0x1fd>; | |
phandle = <0x1fd>; | |
mux { | |
pins = "gpio6", "gpio7"; | |
function = "blsp_i2c8"; | |
}; | |
config { | |
pins = "gpio6", "gpio7"; | |
drive-strength = <0x2>; | |
bias-pull-up; | |
}; | |
}; | |
}; | |
i2c_9 { | |
i2c_9_active { | |
linux,phandle = <0x1fe>; | |
phandle = <0x1fe>; | |
mux { | |
pins = "gpio51", "gpio52"; | |
function = "blsp_i2c9"; | |
}; | |
config { | |
pins = "gpio51", "gpio52"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
i2c_9_sleep { | |
linux,phandle = <0x1ff>; | |
phandle = <0x1ff>; | |
mux { | |
pins = "gpio51", "gpio52"; | |
function = "blsp_i2c9"; | |
}; | |
config { | |
pins = "gpio51", "gpio52"; | |
drive-strength = <0x2>; | |
bias-pull-up; | |
}; | |
}; | |
}; | |
i2c_10 { | |
i2c_10_active { | |
linux,phandle = <0x200>; | |
phandle = <0x200>; | |
mux { | |
pins = "gpio67", "gpio68"; | |
function = "blsp_i2c10"; | |
}; | |
config { | |
pins = "gpio67", "gpio68"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
i2c_10_sleep { | |
linux,phandle = <0x201>; | |
phandle = <0x201>; | |
mux { | |
pins = "gpio67", "gpio68"; | |
function = "blsp_i2c10"; | |
}; | |
config { | |
pins = "gpio67", "gpio68"; | |
drive-strength = <0x2>; | |
bias-pull-up; | |
}; | |
}; | |
}; | |
i2c_11 { | |
i2c_11_active { | |
linux,phandle = <0x203>; | |
phandle = <0x203>; | |
mux { | |
pins = "gpio60", "gpio61"; | |
function = "blsp_i2c11"; | |
}; | |
config { | |
pins = "gpio60", "gpio61"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
i2c_11_sleep { | |
linux,phandle = <0x204>; | |
phandle = <0x204>; | |
mux { | |
pins = "gpio60", "gpio61"; | |
function = "blsp_i2c11"; | |
}; | |
config { | |
pins = "gpio60", "gpio61"; | |
drive-strength = <0x2>; | |
bias-pull-up; | |
}; | |
}; | |
}; | |
i2c_12 { | |
i2c_12_active { | |
linux,phandle = <0x205>; | |
phandle = <0x205>; | |
mux { | |
pins = "gpio83", "gpio84"; | |
function = "blsp_i2c12"; | |
}; | |
config { | |
pins = "gpio83", "gpio84"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
i2c_12_sleep { | |
linux,phandle = <0x206>; | |
phandle = <0x206>; | |
mux { | |
pins = "gpio83", "gpio84"; | |
function = "blsp_i2c12"; | |
}; | |
config { | |
pins = "gpio83", "gpio84"; | |
drive-strength = <0x2>; | |
bias-pull-up; | |
}; | |
}; | |
}; | |
spi_1 { | |
spi_1_active { | |
linux,phandle = <0x207>; | |
phandle = <0x207>; | |
mux { | |
pins = "gpio0", "gpio1", "gpio2", "gpio3"; | |
function = "blsp_spi1"; | |
}; | |
config { | |
pins = "gpio0", "gpio1", "gpio2", "gpio3"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
spi_1_sleep { | |
linux,phandle = <0x208>; | |
phandle = <0x208>; | |
mux { | |
pins = "gpio0", "gpio1", "gpio2", "gpio3"; | |
function = "blsp_spi1"; | |
}; | |
config { | |
pins = "gpio0", "gpio1", "gpio2", "gpio3"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
}; | |
spi_2 { | |
spi_2_active { | |
linux,phandle = <0x209>; | |
phandle = <0x209>; | |
mux { | |
pins = "gpio31", "gpio34", "gpio32", "gpio33"; | |
function = "blsp_spi2"; | |
}; | |
config { | |
pins = "gpio31", "gpio34", "gpio32", "gpio33"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
spi_2_sleep { | |
linux,phandle = <0x20a>; | |
phandle = <0x20a>; | |
mux { | |
pins = "gpio31", "gpio34", "gpio32", "gpio33"; | |
function = "blsp_spi2"; | |
}; | |
config { | |
pins = "gpio31", "gpio34", "gpio32", "gpio33"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
}; | |
spi_3 { | |
spi_3_active { | |
linux,phandle = <0x20b>; | |
phandle = <0x20b>; | |
mux { | |
pins = "gpio45", "gpio46", "gpio47", "gpio48"; | |
function = "blsp_spi3"; | |
}; | |
config { | |
pins = "gpio45", "gpio46", "gpio47", "gpio48"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
spi_3_sleep { | |
linux,phandle = <0x20c>; | |
phandle = <0x20c>; | |
mux { | |
pins = "gpio45", "gpio46", "gpio47", "gpio48"; | |
function = "blsp_spi3"; | |
}; | |
config { | |
pins = "gpio45", "gpio46", "gpio47", "gpio48"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
}; | |
pcie0 { | |
pcie0_clkreq_default { | |
linux,phandle = <0x9a>; | |
phandle = <0x9a>; | |
mux { | |
pins = "gpio36"; | |
function = "pci_e0"; | |
}; | |
config { | |
pins = "gpio36"; | |
drive-strength = <0x2>; | |
bias-pull-up; | |
}; | |
}; | |
pcie0_perst_default { | |
linux,phandle = <0x9b>; | |
phandle = <0x9b>; | |
mux { | |
pins = "gpio35"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio35"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
}; | |
}; | |
pcie0_wake_default { | |
linux,phandle = <0x9c>; | |
phandle = <0x9c>; | |
mux { | |
pins = "gpio37"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio37"; | |
drive-strength = <0x2>; | |
bias-pull-up; | |
}; | |
}; | |
pcie0_wake_sleep { | |
linux,phandle = <0x9d>; | |
phandle = <0x9d>; | |
mux { | |
pins = "gpio37"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio37"; | |
drive-strength = <0x2>; | |
bias-pull-up; | |
}; | |
}; | |
}; | |
hph_en0_ctrl { | |
hph_en0_idle { | |
linux,phandle = <0x27d>; | |
phandle = <0x27d>; | |
mux { | |
pins = "gpio67"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio67"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
output-low; | |
}; | |
}; | |
hph_en0_active { | |
linux,phandle = <0x27c>; | |
phandle = <0x27c>; | |
mux { | |
pins = "gpio67"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio67"; | |
drive-strength = <0x2>; | |
bias-disable; | |
output-high; | |
}; | |
}; | |
}; | |
hph_en1_ctrl { | |
hph_en1_idle { | |
linux,phandle = <0x27f>; | |
phandle = <0x27f>; | |
mux { | |
pins = "gpio68"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio68"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
output-low; | |
}; | |
}; | |
hph_en1_active { | |
linux,phandle = <0x27e>; | |
phandle = <0x27e>; | |
mux { | |
pins = "gpio68"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio68"; | |
drive-strength = <0x2>; | |
bias-disable; | |
output-high; | |
}; | |
}; | |
}; | |
wcd_gnd_mic_swap { | |
wcd_gnd_mic_swap_idle { | |
linux,phandle = <0x28b>; | |
phandle = <0x28b>; | |
mux { | |
pins = "gpio75"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio75"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
output-low; | |
}; | |
}; | |
wcd_gnd_mic_swap_active { | |
linux,phandle = <0x28a>; | |
phandle = <0x28a>; | |
mux { | |
pins = "gpio75"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio75"; | |
drive-strength = <0x2>; | |
bias-disable; | |
output-high; | |
}; | |
}; | |
}; | |
wcd_usbc_analog_en1 { | |
wcd_usbc_ana_en1_idle { | |
mux { | |
pins = "gpio59"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio59"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
output-low; | |
}; | |
}; | |
wcd_usbc_ana_en1_active { | |
mux { | |
pins = "gpio59"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio59"; | |
drive-strength = <0x2>; | |
bias-disable; | |
output-high; | |
}; | |
}; | |
}; | |
wcd_usbc_analog_en2n { | |
wcd_usbc_ana_en2n_idle { | |
mux { | |
pins = "gpio60"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio60"; | |
drive-strength = <0x2>; | |
bias-disable; | |
output-high; | |
}; | |
}; | |
wcd_usbc_ana_en2n_active { | |
mux { | |
pins = "gpio60"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio60"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
output-low; | |
}; | |
}; | |
}; | |
cdc_reset_ctrl { | |
cdc_reset_sleep { | |
linux,phandle = <0x290>; | |
phandle = <0x290>; | |
mux { | |
pins = "gpio64"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio64"; | |
drive-strength = <0x10>; | |
bias-disable; | |
output-low; | |
}; | |
}; | |
cdc_reset_active { | |
linux,phandle = <0x28f>; | |
phandle = <0x28f>; | |
mux { | |
pins = "gpio64"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio64"; | |
drive-strength = <0x10>; | |
bias-pull-down; | |
output-high; | |
}; | |
}; | |
}; | |
spi_4 { | |
spi_4_active { | |
linux,phandle = <0x20d>; | |
phandle = <0x20d>; | |
mux { | |
pins = "gpio8", "gpio9", "gpio10", "gpio11"; | |
function = "blsp_spi4"; | |
}; | |
config { | |
pins = "gpio8", "gpio9", "gpio10", "gpio11"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
spi_4_sleep { | |
linux,phandle = <0x20e>; | |
phandle = <0x20e>; | |
mux { | |
pins = "gpio8", "gpio9", "gpio10", "gpio11"; | |
function = "blsp_spi4"; | |
}; | |
config { | |
pins = "gpio8", "gpio9", "gpio10", "gpio11"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
}; | |
spkr_1_sd_n { | |
spkr_1_sd_n_sleep { | |
linux,phandle = <0x3f>; | |
phandle = <0x3f>; | |
mux { | |
pins = "gpio65"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio65"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
spkr_1_sd_n_active { | |
linux,phandle = <0x3e>; | |
phandle = <0x3e>; | |
mux { | |
pins = "gpio65"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio65"; | |
drive-strength = <0x10>; | |
bias-disable; | |
output-high; | |
}; | |
}; | |
}; | |
spi_5 { | |
spi_5_active { | |
linux,phandle = <0x20f>; | |
phandle = <0x20f>; | |
mux { | |
pins = "gpio85", "gpio86", "gpio87", "gpio88"; | |
function = "blsp_spi5"; | |
}; | |
config { | |
pins = "gpio85", "gpio86", "gpio87", "gpio88"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
spi_5_sleep { | |
linux,phandle = <0x210>; | |
phandle = <0x210>; | |
mux { | |
pins = "gpio85", "gpio86", "gpio87", "gpio88"; | |
function = "blsp_spi5"; | |
}; | |
config { | |
pins = "gpio85", "gpio86", "gpio87", "gpio88"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
}; | |
spkr_2_sd_n { | |
spkr_2_sd_n_sleep { | |
linux,phandle = <0x41>; | |
phandle = <0x41>; | |
mux { | |
pins = "gpio66"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio66"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
spkr_2_sd_n_active { | |
linux,phandle = <0x40>; | |
phandle = <0x40>; | |
mux { | |
pins = "gpio66"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio66"; | |
drive-strength = <0x10>; | |
bias-disable; | |
output-high; | |
}; | |
}; | |
}; | |
cci0_active { | |
linux,phandle = <0xdb>; | |
phandle = <0xdb>; | |
mux { | |
pins = "gpio17", "gpio18"; | |
function = "cci_i2c"; | |
}; | |
config { | |
pins = "gpio17", "gpio18"; | |
bias-pull-up; | |
drive-strength = <0x2>; | |
}; | |
}; | |
cci0_suspend { | |
linux,phandle = <0xdd>; | |
phandle = <0xdd>; | |
mux { | |
pins = "gpio17", "gpio18"; | |
function = "cci_i2c"; | |
}; | |
config { | |
pins = "gpio17", "gpio18"; | |
bias-pull-down; | |
drive-strength = <0x2>; | |
}; | |
}; | |
cci1_active { | |
linux,phandle = <0xdc>; | |
phandle = <0xdc>; | |
mux { | |
pins = "gpio19", "gpio20"; | |
function = "cci_i2c"; | |
}; | |
config { | |
pins = "gpio19", "gpio20"; | |
bias-pull-up; | |
drive-strength = <0x2>; | |
}; | |
}; | |
cci1_suspend { | |
linux,phandle = <0xde>; | |
phandle = <0xde>; | |
mux { | |
pins = "gpio19", "gpio20"; | |
function = "cci_i2c"; | |
}; | |
config { | |
pins = "gpio19", "gpio20"; | |
bias-pull-down; | |
drive-strength = <0x2>; | |
}; | |
}; | |
cam_actuator_vaf_active { | |
mux { | |
pins = "gpio29"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio29"; | |
bias-disable; | |
drive-strength = <0x2>; | |
}; | |
}; | |
cam_actuator_vaf_suspend { | |
mux { | |
pins = "gpio29"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio29"; | |
bias-pull-down; | |
drive-strength = <0x2>; | |
}; | |
}; | |
cam_tof_active { | |
mux { | |
pins = "gpio26", "gpio126"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio26", "gpio126"; | |
bias-pull-up; | |
drive-strength = <0x2>; | |
}; | |
}; | |
cam_tof_suspend { | |
mux { | |
pins = "gpio26", "gpio126"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio26", "gpio126"; | |
bias-pull-down; | |
drive-strength = <0x2>; | |
}; | |
}; | |
cam_sensor_depth_default { | |
mux { | |
pins = "gpio28", "gpio23", "gpio7"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio28", "gpio23", "gpio7"; | |
bias-disable; | |
drive-strength = <0x2>; | |
}; | |
}; | |
cam_sensor_depth_sleep { | |
mux { | |
pins = "gpio28", "gpio23", "gpio7"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio28", "gpio23", "gpio7"; | |
bias-disable; | |
drive-strength = <0x2>; | |
}; | |
}; | |
cam_sensor_depth_v1_active { | |
mux { | |
pins = "gpio24"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio24"; | |
bias-disable; | |
drive-strength = <0x2>; | |
}; | |
}; | |
cam_sensor_depth_v1_sleep { | |
mux { | |
pins = "gpio24"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio24"; | |
bias-disable; | |
drive-strength = <0x2>; | |
}; | |
}; | |
cam_sensor_depth_v2_active { | |
mux { | |
pins = "gpio21"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio21"; | |
bias-disable; | |
drive-strength = <0x2>; | |
}; | |
}; | |
cam_sensor_depth_v2_sleep { | |
mux { | |
pins = "gpio21"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio21"; | |
bias-disable; | |
drive-strength = <0x2>; | |
}; | |
}; | |
cam_sensor_mclk0_active { | |
linux,phandle = <0xe3>; | |
phandle = <0xe3>; | |
mux { | |
pins = "gpio13"; | |
function = "cam_mclk"; | |
}; | |
config { | |
pins = "gpio13"; | |
bias-disable; | |
drive-strength = <0x4>; | |
}; | |
}; | |
cam_sensor_mclk0_suspend { | |
linux,phandle = <0xe5>; | |
phandle = <0xe5>; | |
mux { | |
pins = "gpio13"; | |
function = "cam_mclk"; | |
}; | |
config { | |
pins = "gpio13"; | |
bias-pull-down; | |
drive-strength = <0x4>; | |
}; | |
}; | |
cam_sensor_mclk0_active_chiron { | |
mux { | |
pins = "gpio13"; | |
function = "cam_mclk"; | |
}; | |
config { | |
pins = "gpio13"; | |
bias-disable; | |
drive-strength = <0x6>; | |
}; | |
}; | |
cam_sensor_mclk0_suspend_chiron { | |
mux { | |
pins = "gpio13"; | |
function = "cam_mclk"; | |
}; | |
config { | |
pins = "gpio13"; | |
bias-pull-down; | |
drive-strength = <0x6>; | |
}; | |
}; | |
cam_sensor_rear_active { | |
linux,phandle = <0xe4>; | |
phandle = <0xe4>; | |
mux { | |
pins = "gpio30", "gpio80"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio30", "gpio80"; | |
bias-disable; | |
drive-strength = <0x2>; | |
}; | |
}; | |
spi_6 { | |
spi_6_active { | |
linux,phandle = <0x211>; | |
phandle = <0x211>; | |
mux { | |
pins = "gpio41", "gpio42", "gpio43", "gpio44"; | |
function = "blsp_spi6"; | |
}; | |
config { | |
pins = "gpio41", "gpio42", "gpio43", "gpio44"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
spi_6_sleep { | |
linux,phandle = <0x212>; | |
phandle = <0x212>; | |
mux { | |
pins = "gpio41", "gpio42", "gpio43", "gpio44"; | |
function = "blsp_spi6"; | |
}; | |
config { | |
pins = "gpio41", "gpio42", "gpio43", "gpio44"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
}; | |
spi_7 { | |
spi_7_active { | |
linux,phandle = <0x213>; | |
phandle = <0x213>; | |
mux { | |
pins = "gpio53", "gpio54", "gpio55", "gpio56"; | |
function = "blsp_spi7"; | |
}; | |
config { | |
pins = "gpio53", "gpio54", "gpio55", "gpio56"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
spi_7_sleep { | |
linux,phandle = <0x214>; | |
phandle = <0x214>; | |
mux { | |
pins = "gpio53", "gpio54", "gpio55", "gpio56"; | |
function = "blsp_spi7"; | |
}; | |
config { | |
pins = "gpio53", "gpio54", "gpio55", "gpio56"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
}; | |
spi_8 { | |
spi_8_active { | |
linux,phandle = <0x215>; | |
phandle = <0x215>; | |
mux { | |
pins = "gpio4", "gpio5", "gpio6", "gpio7"; | |
function = "blsp_spi8"; | |
}; | |
config { | |
pins = "gpio4", "gpio5", "gpio6", "gpio7"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
spi_8_sleep { | |
linux,phandle = <0x216>; | |
phandle = <0x216>; | |
mux { | |
pins = "gpio4", "gpio5", "gpio6", "gpio7"; | |
function = "blsp_spi8"; | |
}; | |
config { | |
pins = "gpio4", "gpio5", "gpio6", "gpio7"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
}; | |
spi_9 { | |
spi_9_active { | |
linux,phandle = <0x217>; | |
phandle = <0x217>; | |
mux { | |
pins = "gpio49", "gpio50", "gpio51", "gpio52"; | |
function = "blsp_spi9"; | |
}; | |
config { | |
pins = "gpio49", "gpio50", "gpio51", "gpio52"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
spi_9_sleep { | |
linux,phandle = <0x218>; | |
phandle = <0x218>; | |
mux { | |
pins = "gpio49", "gpio50", "gpio51", "gpio52"; | |
function = "blsp_spi9"; | |
}; | |
config { | |
pins = "gpio49", "gpio50", "gpio51", "gpio52"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
}; | |
spi_10 { | |
spi_10_active { | |
linux,phandle = <0x219>; | |
phandle = <0x219>; | |
mux { | |
pins = "gpio65", "gpio66", "gpio67", "gpio68"; | |
function = "blsp_spi10"; | |
}; | |
config { | |
pins = "gpio65", "gpio66", "gpio67", "gpio68"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
spi_10_sleep { | |
linux,phandle = <0x21a>; | |
phandle = <0x21a>; | |
mux { | |
pins = "gpio65", "gpio66", "gpio67", "gpio68"; | |
function = "blsp_spi10"; | |
}; | |
config { | |
pins = "gpio65", "gpio66", "gpio67", "gpio68"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
}; | |
spi_11 { | |
spi_11_active { | |
linux,phandle = <0x21b>; | |
phandle = <0x21b>; | |
mux { | |
pins = "gpio58", "gpio59", "gpio60", "gpio61"; | |
function = "blsp_spi11"; | |
}; | |
config { | |
pins = "gpio58", "gpio59", "gpio60", "gpio61"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
spi_11_sleep { | |
linux,phandle = <0x21c>; | |
phandle = <0x21c>; | |
mux { | |
pins = "gpio58", "gpio59", "gpio60", "gpio61"; | |
function = "blsp_spi11"; | |
}; | |
config { | |
pins = "gpio58", "gpio59", "gpio60", "gpio61"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
}; | |
spi_12 { | |
spi_12_active { | |
linux,phandle = <0x21d>; | |
phandle = <0x21d>; | |
mux { | |
pins = "gpio81", "gpio82", "gpio83", "gpio84"; | |
function = "blsp_spi12"; | |
}; | |
config { | |
pins = "gpio81", "gpio82", "gpio83", "gpio84"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
spi_12_sleep { | |
linux,phandle = <0x21e>; | |
phandle = <0x21e>; | |
mux { | |
pins = "gpio81", "gpio82", "gpio83", "gpio84"; | |
function = "blsp_spi12"; | |
}; | |
config { | |
pins = "gpio81", "gpio82", "gpio83", "gpio84"; | |
drive-strength = <0x6>; | |
bias-disable; | |
}; | |
}; | |
}; | |
blsp1_uart1_active { | |
linux,phandle = <0x221>; | |
phandle = <0x221>; | |
mux { | |
pins = "gpio0", "gpio1", "gpio2", "gpio3"; | |
function = "blsp_uart1_a"; | |
}; | |
config { | |
pins = "gpio0", "gpio1", "gpio2", "gpio3"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
blsp1_uart1_sleep { | |
linux,phandle = <0x220>; | |
phandle = <0x220>; | |
mux { | |
pins = "gpio0", "gpio1", "gpio2", "gpio3"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio0", "gpio1", "gpio2", "gpio3"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
cam_sensor_rear_suspend { | |
linux,phandle = <0xe6>; | |
phandle = <0xe6>; | |
mux { | |
pins = "gpio30", "gpio80"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio30", "gpio80"; | |
bias-disable; | |
drive-strength = <0x2>; | |
}; | |
}; | |
cam_sensor_mclk1_active { | |
linux,phandle = <0xe8>; | |
phandle = <0xe8>; | |
mux { | |
pins = "gpio14"; | |
function = "cam_mclk"; | |
}; | |
config { | |
pins = "gpio14"; | |
bias-disable; | |
drive-strength = <0x4>; | |
}; | |
}; | |
cam_sensor_mclk1_suspend { | |
linux,phandle = <0xea>; | |
phandle = <0xea>; | |
mux { | |
pins = "gpio14"; | |
function = "cam_mclk"; | |
}; | |
config { | |
pins = "gpio14"; | |
bias-pull-down; | |
drive-strength = <0x4>; | |
}; | |
}; | |
cam_sensor_mclk1_active_chiron { | |
mux { | |
pins = "gpio14"; | |
function = "cam_mclk"; | |
}; | |
config { | |
pins = "gpio14"; | |
bias-disable; | |
drive-strength = <0x6>; | |
}; | |
}; | |
cam_sensor_mclk1_suspend_chiron { | |
mux { | |
pins = "gpio14"; | |
function = "cam_mclk"; | |
}; | |
config { | |
pins = "gpio14"; | |
bias-pull-down; | |
drive-strength = <0x4>; | |
}; | |
}; | |
cam_sensor_mclk3_active { | |
mux { | |
pins = "gpio16"; | |
function = "cam_mclk"; | |
}; | |
config { | |
pins = "gpio16"; | |
bias-disable; | |
drive-strength = <0x2>; | |
}; | |
}; | |
cam_sensor_mclk3_suspend { | |
mux { | |
pins = "gpio16"; | |
function = "cam_mclk"; | |
}; | |
config { | |
pins = "gpio16"; | |
bias-pull-down; | |
drive-strength = <0x2>; | |
}; | |
}; | |
cam_sensor_rear2_active { | |
linux,phandle = <0xf3>; | |
phandle = <0xf3>; | |
mux { | |
pins = "gpio9"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio9"; | |
bias-disable; | |
drive-strength = <0x2>; | |
}; | |
}; | |
blsp1_uart2_active { | |
linux,phandle = <0x224>; | |
phandle = <0x224>; | |
mux { | |
pins = "gpio31", "gpio34", "gpio33", "gpio32"; | |
function = "blsp_uart2_a"; | |
}; | |
config { | |
pins = "gpio31", "gpio34", "gpio33", "gpio32"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
blsp1_uart2_sleep { | |
linux,phandle = <0x223>; | |
phandle = <0x223>; | |
mux { | |
pins = "gpio31", "gpio34", "gpio33", "gpio32"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio31", "gpio34", "gpio33", "gpio32"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
blsp1_uart3 { | |
blsp1_uart3_tx_active { | |
linux,phandle = <0x229>; | |
phandle = <0x229>; | |
mux { | |
pins = "gpio45"; | |
function = "blsp_uart3_a"; | |
}; | |
config { | |
pins = "gpio45"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
blsp1_uart3_tx_sleep { | |
linux,phandle = <0x226>; | |
phandle = <0x226>; | |
mux { | |
pins = "gpio45"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio45"; | |
drive-strength = <0x2>; | |
bias-pull-up; | |
}; | |
}; | |
blsp1_uart3_rxcts_active { | |
linux,phandle = <0x22a>; | |
phandle = <0x22a>; | |
mux { | |
pins = "gpio46", "gpio47"; | |
function = "blsp_uart3_a"; | |
}; | |
config { | |
pins = "gpio46", "gpio47"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
blsp1_uart3_rxcts_sleep { | |
linux,phandle = <0x227>; | |
phandle = <0x227>; | |
mux { | |
pins = "gpio46", "gpio47"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio46", "gpio47"; | |
drive-strength = <0x2>; | |
bias-no-pull; | |
}; | |
}; | |
blsp1_uart3_rfr_active { | |
linux,phandle = <0x22b>; | |
phandle = <0x22b>; | |
mux { | |
pins = "gpio48"; | |
function = "blsp_uart3_a"; | |
}; | |
config { | |
pins = "gpio48"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
blsp1_uart3_rfr_sleep { | |
linux,phandle = <0x228>; | |
phandle = <0x228>; | |
mux { | |
pins = "gpio48"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio48"; | |
drive-strength = <0x2>; | |
bias-no-pull; | |
}; | |
}; | |
}; | |
cam_sensor_rear2_suspend { | |
linux,phandle = <0xf5>; | |
phandle = <0xf5>; | |
mux { | |
pins = "gpio9"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio9"; | |
bias-disable; | |
drive-strength = <0x2>; | |
}; | |
}; | |
cam_sensor_mclk2_active { | |
linux,phandle = <0xf2>; | |
phandle = <0xf2>; | |
mux { | |
pins = "gpio15"; | |
function = "cam_mclk"; | |
}; | |
config { | |
pins = "gpio15"; | |
bias-disable; | |
drive-strength = <0x4>; | |
}; | |
}; | |
cam_sensor_mclk2_suspend { | |
linux,phandle = <0xf4>; | |
phandle = <0xf4>; | |
mux { | |
pins = "gpio15"; | |
function = "cam_mclk"; | |
}; | |
config { | |
pins = "gpio15"; | |
bias-pull-down; | |
drive-strength = <0x4>; | |
}; | |
}; | |
cam_sensor_front_active { | |
linux,phandle = <0xe9>; | |
phandle = <0xe9>; | |
mux { | |
pins = "gpio28", "gpio27", "gpio9"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio28", "gpio27", "gpio9"; | |
bias-disable; | |
drive-strength = <0x2>; | |
}; | |
}; | |
cam_sensor_front_iris_active { | |
mux { | |
pins = "gpio23"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio23"; | |
bias-disable; | |
drive-strength = <0x2>; | |
}; | |
}; | |
blsp2_uart1_active { | |
linux,phandle = <0x22e>; | |
phandle = <0x22e>; | |
mux { | |
pins = "gpio53", "gpio54", "gpio55", "gpio56"; | |
function = "blsp_uart7_a"; | |
}; | |
config { | |
pins = "gpio53", "gpio54", "gpio55", "gpio56"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
blsp2_uart1_sleep { | |
linux,phandle = <0x22d>; | |
phandle = <0x22d>; | |
mux { | |
pins = "gpio53", "gpio54", "gpio55", "gpio56"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio53", "gpio54", "gpio55", "gpio56"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
blsp2_uart2_active { | |
linux,phandle = <0x231>; | |
phandle = <0x231>; | |
mux { | |
pins = "gpio4", "gpio5", "gpio6", "gpio7"; | |
function = "blsp_uart8_a"; | |
}; | |
config { | |
pins = "gpio4", "gpio5", "gpio6", "gpio7"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
blsp2_uart2_sleep { | |
linux,phandle = <0x230>; | |
phandle = <0x230>; | |
mux { | |
pins = "gpio4", "gpio5", "gpio6", "gpio7"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio4", "gpio5", "gpio6", "gpio7"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
cam_sensor_front_suspend { | |
linux,phandle = <0xeb>; | |
phandle = <0xeb>; | |
mux { | |
pins = "gpio28", "gpio27", "gpio9"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio28", "gpio27", "gpio9"; | |
bias-disable; | |
drive-strength = <0x2>; | |
}; | |
}; | |
cam_sensor_front_iris_suspend { | |
mux { | |
pins = "gpio23"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio23"; | |
bias-disable; | |
drive-strength = <0x2>; | |
}; | |
}; | |
pmx_mdss { | |
mdss_dsi_active { | |
linux,phandle = <0x1c0>; | |
phandle = <0x1c0>; | |
mux { | |
pins = "gpio94"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio94"; | |
drive-strength = <0x8>; | |
bias-disable = <0x0>; | |
}; | |
}; | |
mdss_dsi_suspend { | |
linux,phandle = <0x1c2>; | |
phandle = <0x1c2>; | |
mux { | |
pins = "gpio94"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio94"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
}; | |
}; | |
}; | |
pmx_mdss_te { | |
mdss_te_active { | |
linux,phandle = <0x1c1>; | |
phandle = <0x1c1>; | |
mux { | |
pins = "gpio10"; | |
function = "mdp_vsync_a"; | |
}; | |
config { | |
pins = "gpio10"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
}; | |
}; | |
mdss_te_suspend { | |
linux,phandle = <0x1c3>; | |
phandle = <0x1c3>; | |
mux { | |
pins = "gpio10"; | |
function = "mdp_vsync_a"; | |
}; | |
config { | |
pins = "gpio10"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
}; | |
}; | |
}; | |
mdss_dp_aux_active { | |
mux { | |
pins = "gpio77", "gpio78"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio77", "gpio78"; | |
bias-disable = <0x0>; | |
drive-strength = <0x8>; | |
}; | |
}; | |
mdss_dp_aux_suspend { | |
mux { | |
pins = "gpio77", "gpio78"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio77", "gpio78"; | |
bias-pull-down; | |
drive-strength = <0x2>; | |
}; | |
}; | |
mdss_dp_usbplug_cc_active { | |
mux { | |
pins = "gpio38"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio38"; | |
bias-disable; | |
drive-strength = <0x10>; | |
}; | |
}; | |
mdss_dp_usbplug_cc_suspend { | |
mux { | |
pins = "gpio38"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio38"; | |
bias-pull-down; | |
drive-strength = <0x2>; | |
}; | |
}; | |
mdss_dp_hpd_active { | |
mux { | |
pins = "gpio34"; | |
function = "edp_hot"; | |
}; | |
config { | |
pins = "gpio34"; | |
bias-pull-down; | |
drive-strength = <0x10>; | |
}; | |
}; | |
mdss_dp_hpd_suspend { | |
mux { | |
pins = "gpio34"; | |
function = "edp_hot"; | |
}; | |
config { | |
pins = "gpio34"; | |
bias-pull-down; | |
drive-strength = <0x2>; | |
}; | |
}; | |
blsp2_uart3_active { | |
linux,phandle = <0x234>; | |
phandle = <0x234>; | |
mux { | |
pins = "gpio49", "gpio50", "gpio51", "gpio52"; | |
function = "blsp_uart9_a"; | |
}; | |
config { | |
pins = "gpio49", "gpio50", "gpio51", "gpio52"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
blsp2_uart3_sleep { | |
linux,phandle = <0x233>; | |
phandle = <0x233>; | |
mux { | |
pins = "gpio49", "gpio50", "gpio51", "gpio52"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio49", "gpio50", "gpio51", "gpio52"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
pmx_ts_int_active { | |
ts_int_active { | |
mux { | |
pins = "gpio125"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio125"; | |
drive-strength = <0x8>; | |
bias-pull-up; | |
}; | |
}; | |
}; | |
pmx_ts_int_suspend { | |
ts_int_suspend1 { | |
mux { | |
pins = "gpio125"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio125"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
}; | |
}; | |
}; | |
pmx_ts_reset_active { | |
ts_reset_active { | |
mux { | |
pins = "gpio89"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio89"; | |
drive-strength = <0x8>; | |
bias-pull-up; | |
}; | |
}; | |
}; | |
pmx_ts_reset_suspend { | |
ts_reset_suspend1 { | |
mux { | |
pins = "gpio89"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio89"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
}; | |
}; | |
}; | |
pmx_ts_release { | |
ts_release { | |
mux { | |
pins = "gpio125", "gpio89"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio125", "gpio89"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
}; | |
}; | |
}; | |
ts_mux { | |
ts_active { | |
linux,phandle = <0x1ec>; | |
phandle = <0x1ec>; | |
mux { | |
pins = "gpio89", "gpio125"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio89", "gpio125"; | |
drive-strength = <0x10>; | |
bias-pull-up; | |
}; | |
}; | |
ts_reset_suspend { | |
linux,phandle = <0x1ee>; | |
phandle = <0x1ee>; | |
mux { | |
pins = "gpio89"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio89"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
ts_int_suspend { | |
linux,phandle = <0x1ed>; | |
phandle = <0x1ed>; | |
mux { | |
pins = "gpio125"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio125"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
}; | |
ufs_dev_reset_assert { | |
linux,phandle = <0x81>; | |
phandle = <0x81>; | |
config { | |
pins = "ufs_reset"; | |
bias-pull-down; | |
drive-strength = <0x8>; | |
output-low; | |
}; | |
}; | |
ufs_dev_reset_deassert { | |
linux,phandle = <0x82>; | |
phandle = <0x82>; | |
config { | |
pins = "ufs_reset"; | |
bias-pull-down; | |
drive-strength = <0x8>; | |
output-high; | |
}; | |
}; | |
sdc2_clk_on { | |
linux,phandle = <0x74>; | |
phandle = <0x74>; | |
config { | |
pins = "sdc2_clk"; | |
bias-disable; | |
drive-strength = <0x10>; | |
}; | |
}; | |
sdc2_clk_off { | |
linux,phandle = <0x78>; | |
phandle = <0x78>; | |
config { | |
pins = "sdc2_clk"; | |
bias-disable; | |
drive-strength = <0x2>; | |
}; | |
}; | |
sdc2_cmd_on { | |
linux,phandle = <0x75>; | |
phandle = <0x75>; | |
config { | |
pins = "sdc2_cmd"; | |
bias-pull-up; | |
drive-strength = <0xa>; | |
}; | |
}; | |
sdc2_cmd_off { | |
linux,phandle = <0x79>; | |
phandle = <0x79>; | |
config { | |
pins = "sdc2_cmd"; | |
bias-pull-up; | |
drive-strength = <0x2>; | |
}; | |
}; | |
sdc2_data_on { | |
linux,phandle = <0x76>; | |
phandle = <0x76>; | |
config { | |
pins = "sdc2_data"; | |
bias-pull-up; | |
drive-strength = <0xa>; | |
}; | |
}; | |
sdc2_data_off { | |
linux,phandle = <0x7a>; | |
phandle = <0x7a>; | |
config { | |
pins = "sdc2_data"; | |
bias-pull-up; | |
drive-strength = <0x2>; | |
}; | |
}; | |
sdc2_cd_on { | |
linux,phandle = <0x77>; | |
phandle = <0x77>; | |
mux { | |
pins = "gpio95"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio95"; | |
bias-pull-up; | |
drive-strength = <0x2>; | |
}; | |
}; | |
sdc2_cd_off { | |
linux,phandle = <0x7b>; | |
phandle = <0x7b>; | |
mux { | |
pins = "gpio95"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio95"; | |
bias-pull-up; | |
drive-strength = <0x2>; | |
}; | |
}; | |
led_enable { | |
mux { | |
pins = "gpio21"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio21"; | |
drive_strength = <0x2>; | |
output-high; | |
bias-disable; | |
}; | |
}; | |
led_disable { | |
mux { | |
pins = "gpio21"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio21"; | |
drive_strength = <0x2>; | |
output-low; | |
bias-disable; | |
}; | |
}; | |
trigout_a { | |
linux,phandle = <0x126>; | |
phandle = <0x126>; | |
mux { | |
pins = "gpio58"; | |
function = "qdss_cti1_a"; | |
}; | |
config { | |
pins = "gpio58"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
mdss_hdmi_5v_active { | |
linux,phandle = <0x1cd>; | |
phandle = <0x1cd>; | |
mux { | |
pins = "gpio133"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio133"; | |
bias-pull-up; | |
drive-strength = <0x10>; | |
}; | |
}; | |
mdss_hdmi_5v_suspend { | |
linux,phandle = <0x1d3>; | |
phandle = <0x1d3>; | |
mux { | |
pins = "gpio133"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio133"; | |
bias-pull-down; | |
drive-strength = <0x2>; | |
}; | |
}; | |
mdss_hdmi_hpd_active { | |
linux,phandle = <0x1ce>; | |
phandle = <0x1ce>; | |
mux { | |
pins = "gpio34"; | |
function = "hdmi_hot"; | |
}; | |
config { | |
pins = "gpio34"; | |
bias-pull-down; | |
drive-strength = <0x10>; | |
}; | |
}; | |
mdss_hdmi_hpd_suspend { | |
linux,phandle = <0x1d4>; | |
phandle = <0x1d4>; | |
mux { | |
pins = "gpio34"; | |
function = "hdmi_hot"; | |
}; | |
config { | |
pins = "gpio34"; | |
bias-pull-down; | |
drive-strength = <0x2>; | |
}; | |
}; | |
mdss_hdmi_ddc_active { | |
linux,phandle = <0x1d1>; | |
phandle = <0x1d1>; | |
mux { | |
pins = "gpio32", "gpio33"; | |
function = "hdmi_ddc"; | |
}; | |
config { | |
pins = "gpio32", "gpio33"; | |
drive-strength = <0x2>; | |
bias-pull-up; | |
}; | |
}; | |
mdss_hdmi_ddc_suspend { | |
linux,phandle = <0x1cf>; | |
phandle = <0x1cf>; | |
mux { | |
pins = "gpio32", "gpio33"; | |
function = "hdmi_ddc"; | |
}; | |
config { | |
pins = "gpio32", "gpio33"; | |
drive-strength = <0x2>; | |
bias-pull-up; | |
}; | |
}; | |
mdss_hdmi_cec_active { | |
linux,phandle = <0x1d2>; | |
phandle = <0x1d2>; | |
mux { | |
pins = "gpio31"; | |
function = "hdmi_cec"; | |
}; | |
config { | |
pins = "gpio31"; | |
drive-strength = <0x2>; | |
bias-pull-up; | |
}; | |
}; | |
mdss_hdmi_cec_suspend { | |
linux,phandle = <0x1d0>; | |
phandle = <0x1d0>; | |
mux { | |
pins = "gpio31"; | |
function = "hdmi_cec"; | |
}; | |
config { | |
pins = "gpio31"; | |
drive-strength = <0x2>; | |
bias-pull-up; | |
}; | |
}; | |
tsif0_signals_active { | |
linux,phandle = <0xc6>; | |
phandle = <0xc6>; | |
tsif1_clk { | |
pins = "gpio89"; | |
function = "tsif1_clk"; | |
}; | |
tsif1_en { | |
pins = "gpio90"; | |
function = "tsif1_en"; | |
}; | |
tsif1_data { | |
pins = "gpio91"; | |
function = "tsif1_data"; | |
}; | |
signals_cfg { | |
pins = "gpio89", "gpio90", "gpio91"; | |
drive_strength = <0x2>; | |
bias-pull-down; | |
}; | |
}; | |
tsif0_sync_active { | |
linux,phandle = <0xc7>; | |
phandle = <0xc7>; | |
tsif1_sync { | |
pins = "gpio9"; | |
function = "tsif1_sync"; | |
drive_strength = <0x2>; | |
bias-pull-down; | |
}; | |
}; | |
tsif1_signals_active { | |
linux,phandle = <0xc8>; | |
phandle = <0xc8>; | |
tsif2_clk { | |
pins = "gpio93"; | |
function = "tsif2_clk"; | |
}; | |
tsif2_en { | |
pins = "gpio94"; | |
function = "tsif2_en"; | |
}; | |
tsif2_data { | |
pins = "gpio95"; | |
function = "tsif2_data"; | |
}; | |
signals_cfg { | |
pins = "gpio93", "gpio94", "gpio95"; | |
drive_strength = <0x2>; | |
bias-pull-down; | |
}; | |
}; | |
tsif1_sync_active { | |
linux,phandle = <0xc9>; | |
phandle = <0xc9>; | |
tsif2_sync { | |
pins = "gpio96"; | |
function = "tsif2_sync"; | |
drive_strength = <0x2>; | |
bias-pull-down; | |
}; | |
}; | |
pri_aux_pcm_clk { | |
pri_aux_pcm_clk_sleep { | |
mux { | |
pins = "gpio65"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio65"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
pri_aux_pcm_clk_active { | |
mux { | |
pins = "gpio65"; | |
function = "pri_mi2s"; | |
}; | |
config { | |
pins = "gpio65"; | |
drive-strength = <0x8>; | |
bias-disable; | |
output-high; | |
}; | |
}; | |
}; | |
pri_aux_pcm_sync { | |
pri_aux_pcm_sync_sleep { | |
mux { | |
pins = "gpio66"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio66"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
pri_aux_pcm_sync_active { | |
mux { | |
pins = "gpio66"; | |
function = "pri_mi2s_ws"; | |
}; | |
config { | |
pins = "gpio66"; | |
drive-strength = <0x8>; | |
bias-disable; | |
output-high; | |
}; | |
}; | |
}; | |
pri_aux_pcm_din { | |
pri_aux_pcm_din_sleep { | |
mux { | |
pins = "gpio67"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio67"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
pri_aux_pcm_din_active { | |
mux { | |
pins = "gpio67"; | |
function = "pri_mi2s"; | |
}; | |
config { | |
pins = "gpio67"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
pri_aux_pcm_dout { | |
pri_aux_pcm_dout_sleep { | |
mux { | |
pins = "gpio68"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio68"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
pri_aux_pcm_dout_active { | |
mux { | |
pins = "gpio68"; | |
function = "pri_mi2s"; | |
}; | |
config { | |
pins = "gpio68"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
sec_aux_pcm { | |
sec_aux_pcm_sleep { | |
mux { | |
pins = "gpio80", "gpio81"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio80", "gpio81"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
sec_aux_pcm_active { | |
mux { | |
pins = "gpio80", "gpio81"; | |
function = "sec_mi2s"; | |
}; | |
config { | |
pins = "gpio80", "gpio81"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
sec_aux_pcm_din { | |
sec_aux_pcm_din_sleep { | |
mux { | |
pins = "gpio82"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio82"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
sec_aux_pcm_din_active { | |
mux { | |
pins = "gpio82"; | |
function = "sec_mi2s"; | |
}; | |
config { | |
pins = "gpio82"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
sec_aux_pcm_dout { | |
sec_aux_pcm_dout_sleep { | |
mux { | |
pins = "gpio83"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio83"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
sec_aux_pcm_dout_active { | |
mux { | |
pins = "gpio83"; | |
function = "sec_mi2s"; | |
}; | |
config { | |
pins = "gpio83"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
tert_aux_pcm { | |
tert_aux_pcm_sleep { | |
mux { | |
pins = "gpio75", "gpio76"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio75", "gpio76"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
tert_aux_pcm_active { | |
mux { | |
pins = "gpio75", "gpio76"; | |
function = "ter_mi2s"; | |
}; | |
config { | |
pins = "gpio75", "gpio76"; | |
drive-strength = <0x8>; | |
bias-disable; | |
output-high; | |
}; | |
}; | |
}; | |
tert_aux_pcm_din { | |
tert_aux_pcm_din_sleep { | |
mux { | |
pins = "gpio77"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio77"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
tert_aux_pcm_din_active { | |
mux { | |
pins = "gpio77"; | |
function = "ter_mi2s"; | |
}; | |
config { | |
pins = "gpio77"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
tert_aux_pcm_dout { | |
tert_aux_pcm_dout_sleep { | |
mux { | |
pins = "gpio78"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio78"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
tert_aux_pcm_dout_active { | |
mux { | |
pins = "gpio78"; | |
function = "ter_mi2s"; | |
}; | |
config { | |
pins = "gpio78"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
quat_aux_pcm { | |
quat_aux_pcm_sleep { | |
mux { | |
pins = "gpio58", "gpio59"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio58", "gpio59"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
quat_aux_pcm_active { | |
mux { | |
pins = "gpio58", "gpio59"; | |
function = "qua_mi2s"; | |
}; | |
config { | |
pins = "gpio58", "gpio59"; | |
drive-strength = <0x8>; | |
bias-disable; | |
output-high; | |
}; | |
}; | |
}; | |
quat_aux_pcm_din { | |
quat_aux_pcm_din_sleep { | |
mux { | |
pins = "gpio60"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio60"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
quat_aux_pcm_din_active { | |
mux { | |
pins = "gpio60"; | |
function = "qua_mi2s"; | |
}; | |
config { | |
pins = "gpio60"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
quat_aux_pcm_dout { | |
quat_aux_pcm_dout_sleep { | |
mux { | |
pins = "gpio61"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio61"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
quat_aux_pcm_dout_active { | |
mux { | |
pins = "gpio61"; | |
function = "qua_mi2s"; | |
}; | |
config { | |
pins = "gpio61"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
pri_mi2s_mclk { | |
pri_mi2s_mclk_sleep { | |
mux { | |
pins = "gpio64"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio64"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
pri_mi2s_mclk_active { | |
mux { | |
pins = "gpio64"; | |
function = "pri_mi2s"; | |
}; | |
config { | |
pins = "gpio64"; | |
drive-strength = <0x8>; | |
bias-disable; | |
output-high; | |
}; | |
}; | |
}; | |
pri_mi2s_sck { | |
pri_mi2s_sck_sleep { | |
mux { | |
pins = "gpio65"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio65"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
pri_mi2s_sck_active { | |
mux { | |
pins = "gpio65"; | |
function = "pri_mi2s"; | |
}; | |
config { | |
pins = "gpio65"; | |
drive-strength = <0x8>; | |
bias-disable; | |
output-high; | |
}; | |
}; | |
}; | |
pri_mi2s_ws { | |
pri_mi2s_ws_sleep { | |
mux { | |
pins = "gpio66"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio66"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
pri_mi2s_ws_active { | |
mux { | |
pins = "gpio66"; | |
function = "pri_mi2s_ws"; | |
}; | |
config { | |
pins = "gpio66"; | |
drive-strength = <0x8>; | |
bias-disable; | |
output-high; | |
}; | |
}; | |
}; | |
pri_mi2s_sd0 { | |
pri_mi2s_sd0_sleep { | |
mux { | |
pins = "gpio67"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio67"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
pri_mi2s_sd0_active { | |
mux { | |
pins = "gpio67"; | |
function = "pri_mi2s"; | |
}; | |
config { | |
pins = "gpio67"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
pri_mi2s_sd1 { | |
pri_mi2s_sd1_sleep { | |
mux { | |
pins = "gpio68"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio68"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
pri_mi2s_sd1_active { | |
mux { | |
pins = "gpio68"; | |
function = "pri_mi2s"; | |
}; | |
config { | |
pins = "gpio68"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
sec_mi2s_mclk { | |
sec_mi2s_mclk_sleep { | |
mux { | |
pins = "gpio79"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio79"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
sec_mi2s_mclk_active { | |
mux { | |
pins = "gpio79"; | |
function = "sec_mi2s"; | |
}; | |
config { | |
pins = "gpio79"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
sec_mi2s { | |
sec_mi2s_sleep { | |
mux { | |
pins = "gpio80", "gpio81"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio80", "gpio81"; | |
drive-strength = <0x2>; | |
bias-disable; | |
input-enable; | |
}; | |
}; | |
sec_mi2s_active { | |
mux { | |
pins = "gpio80", "gpio81"; | |
function = "sec_mi2s"; | |
}; | |
config { | |
pins = "gpio80", "gpio81"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
sec_mi2s_sd0 { | |
sec_mi2s_sd0_sleep { | |
mux { | |
pins = "gpio82"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio82"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
sec_mi2s_sd0_active { | |
mux { | |
pins = "gpio82"; | |
function = "sec_mi2s"; | |
}; | |
config { | |
pins = "gpio82"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
sec_mi2s_sd1 { | |
sec_mi2s_sd1_sleep { | |
mux { | |
pins = "gpio83"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio83"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
sec_mi2s_sd1_active { | |
mux { | |
pins = "gpio83"; | |
function = "sec_mi2s"; | |
}; | |
config { | |
pins = "gpio83"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
tert_mi2s_mclk { | |
tert_mi2s_mclk_sleep { | |
mux { | |
pins = "gpio74"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio74"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
tert_mi2s_mclk_active { | |
mux { | |
pins = "gpio74"; | |
function = "ter_mi2s"; | |
}; | |
config { | |
pins = "gpio74"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
tert_mi2s { | |
tert_mi2s_sleep { | |
mux { | |
pins = "gpio75", "gpio76"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio75", "gpio76"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
tert_mi2s_active { | |
mux { | |
pins = "gpio75", "gpio76"; | |
function = "ter_mi2s"; | |
}; | |
config { | |
pins = "gpio75", "gpio76"; | |
drive-strength = <0x8>; | |
bias-disable; | |
output-high; | |
}; | |
}; | |
}; | |
tert_mi2s_sd0 { | |
tert_mi2s_sd0_sleep { | |
mux { | |
pins = "gpio77"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio77"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
tert_mi2s_sd0_active { | |
mux { | |
pins = "gpio77"; | |
function = "ter_mi2s"; | |
}; | |
config { | |
pins = "gpio77"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
tert_mi2s_sd1 { | |
tert_mi2s_sd1_sleep { | |
mux { | |
pins = "gpio78"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio78"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
tert_mi2s_sd1_active { | |
mux { | |
pins = "gpio78"; | |
function = "ter_mi2s"; | |
}; | |
config { | |
pins = "gpio78"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
quat_mi2s_mclk { | |
quat_mi2s_mclk_sleep { | |
mux { | |
pins = "gpio57"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio57"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
quat_mi2s_mclk_active { | |
mux { | |
pins = "gpio57"; | |
function = "qua_mi2s"; | |
}; | |
config { | |
pins = "gpio57"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
quat_mi2s { | |
quat_mi2s_sleep { | |
linux,phandle = <0x1ad>; | |
phandle = <0x1ad>; | |
mux { | |
pins = "gpio58", "gpio59"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio58", "gpio59"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
quat_mi2s_active { | |
linux,phandle = <0x1aa>; | |
phandle = <0x1aa>; | |
mux { | |
pins = "gpio58", "gpio59"; | |
function = "qua_mi2s"; | |
}; | |
config { | |
pins = "gpio58", "gpio59"; | |
drive-strength = <0x8>; | |
bias-disable; | |
output-high; | |
}; | |
}; | |
}; | |
quat_mi2s_sd0 { | |
quat_mi2s_sd0_sleep { | |
linux,phandle = <0x1ae>; | |
phandle = <0x1ae>; | |
mux { | |
pins = "gpio60"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio60"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
quat_mi2s_sd0_active { | |
linux,phandle = <0x1ab>; | |
phandle = <0x1ab>; | |
mux { | |
pins = "gpio60"; | |
function = "qua_mi2s"; | |
}; | |
config { | |
pins = "gpio60"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
quat_mi2s_sd1 { | |
quat_mi2s_sd1_sleep { | |
linux,phandle = <0x1af>; | |
phandle = <0x1af>; | |
mux { | |
pins = "gpio61"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio61"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
quat_mi2s_sd1_active { | |
linux,phandle = <0x1ac>; | |
phandle = <0x1ac>; | |
mux { | |
pins = "gpio61"; | |
function = "qua_mi2s"; | |
}; | |
config { | |
pins = "gpio61"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
quat_mi2s_sd2 { | |
quat_mi2s_sd2_sleep { | |
mux { | |
pins = "gpio62"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio62"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
quat_mi2s_sd2_active { | |
mux { | |
pins = "gpio62"; | |
function = "qua_mi2s"; | |
}; | |
config { | |
pins = "gpio62"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
quat_mi2s_sd3 { | |
quat_mi2s_sd3_sleep { | |
mux { | |
pins = "gpio63"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio63"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
quat_mi2s_sd3_active { | |
mux { | |
pins = "gpio63"; | |
function = "qua_mi2s"; | |
}; | |
config { | |
pins = "gpio63"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
spkr_i2s_clk_pin { | |
spkr_i2s_clk_sleep { | |
linux,phandle = <0x28d>; | |
phandle = <0x28d>; | |
mux { | |
pins = "gpio69"; | |
function = "spkr_i2s"; | |
}; | |
config { | |
pins = "gpio69"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
}; | |
}; | |
spkr_i2s_clk_active { | |
linux,phandle = <0x28e>; | |
phandle = <0x28e>; | |
mux { | |
pins = "gpio69"; | |
function = "spkr_i2s"; | |
}; | |
config { | |
pins = "gpio69"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
}; | |
fp_mux { | |
fp_active { | |
linux,phandle = <0x2a9>; | |
phandle = <0x2a9>; | |
mux { | |
pins = "gpio121"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio121"; | |
drive-strength = <0x8>; | |
bias-disable; | |
}; | |
}; | |
fp_suspend { | |
linux,phandle = <0x2aa>; | |
phandle = <0x2aa>; | |
mux { | |
pins = "gpio121"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio121"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
}; | |
msm_gpio_37 { | |
linux,phandle = <0x2a6>; | |
phandle = <0x2a6>; | |
mux { | |
pins = "gpio37"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio37"; | |
drive-strength = <0x2>; | |
bias-disable; | |
output-low; | |
}; | |
}; | |
msm_gpio_37_output_high { | |
linux,phandle = <0x2a7>; | |
phandle = <0x2a7>; | |
mux { | |
pins = "gpio37"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio37"; | |
drive-strength = <0x2>; | |
bias-disable; | |
output-high; | |
}; | |
}; | |
msm_gpio_121 { | |
linux,phandle = <0x2a8>; | |
phandle = <0x2a8>; | |
mux { | |
pins = "gpio121"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio121"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
}; | |
}; | |
msm_gpio_78 { | |
mux { | |
pins = "gpio78"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio78"; | |
drive-strength = <0x2>; | |
bias-disable; | |
output-low; | |
}; | |
}; | |
msm_gpio_78_output_high { | |
mux { | |
pins = "gpio78"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio78"; | |
drive-strength = <0x2>; | |
bias-disable; | |
output-high; | |
}; | |
}; | |
spkr_1_sd_mediabox { | |
spkr_1_sd_sleep_mediabox { | |
mux { | |
pins = "gpio85"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio85"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
spkr_1_sd_active_mediabox { | |
mux { | |
pins = "gpio85"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio85"; | |
drive-strength = <0x8>; | |
bias-disable; | |
output-high; | |
}; | |
}; | |
}; | |
spkr_2_sd_mediabox_mediabox { | |
spkr_2_sd_sleep_mediabox { | |
mux { | |
pins = "gpio112"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio112"; | |
drive-strength = <0x2>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
spkr_2_sd_active_mediabox { | |
mux { | |
pins = "gpio112"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio112"; | |
drive-strength = <0x8>; | |
bias-disable; | |
output-high; | |
}; | |
}; | |
}; | |
sdc2_cd_on_mediabox { | |
mux { | |
pins = "gpio86"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio86"; | |
bias-pull-up; | |
drive-strength = <0x2>; | |
}; | |
}; | |
sdc2_cd_off_mediabox { | |
mux { | |
pins = "gpio86"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio86"; | |
bias-pull-up; | |
drive-strength = <0x2>; | |
}; | |
}; | |
rcv_id { | |
rcv_id_no_pull { | |
linux,phandle = <0x2a2>; | |
phandle = <0x2a2>; | |
mux { | |
pins = "gpio11"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio11"; | |
drive-strength = <0x8>; | |
bias-disable; | |
input-enable; | |
}; | |
}; | |
rcv_id_pull_up { | |
linux,phandle = <0x2a1>; | |
phandle = <0x2a1>; | |
mux { | |
pins = "gpio11"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio11"; | |
drive-strength = <0x8>; | |
bias-pull-up; | |
input-enable; | |
}; | |
}; | |
rcv_id_pull_down { | |
linux,phandle = <0x2a0>; | |
phandle = <0x2a0>; | |
mux { | |
pins = "gpio11"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio11"; | |
drive-strength = <0x8>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
}; | |
spk_id { | |
spk_id_no_pull { | |
linux,phandle = <0x29f>; | |
phandle = <0x29f>; | |
mux { | |
pins = "gpio100"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio100"; | |
drive-strength = <0x8>; | |
bias-disable; | |
input-enable; | |
}; | |
}; | |
spk_id_pull_up { | |
linux,phandle = <0x29e>; | |
phandle = <0x29e>; | |
mux { | |
pins = "gpio100"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio100"; | |
drive-strength = <0x8>; | |
bias-pull-up; | |
input-enable; | |
}; | |
}; | |
spk_id_pull_down { | |
linux,phandle = <0x29d>; | |
phandle = <0x29d>; | |
mux { | |
pins = "gpio100"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio100"; | |
drive-strength = <0x8>; | |
bias-pull-down; | |
input-enable; | |
}; | |
}; | |
}; | |
gpio_rf { | |
gpio_rf_active { | |
linux,phandle = <0x2a3>; | |
phandle = <0x2a3>; | |
mux { | |
pins = "gpio119"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio119"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
gpio_rf_suspend { | |
linux,phandle = <0x2a4>; | |
phandle = <0x2a4>; | |
mux { | |
pins = "gpio119"; | |
function = "gpio"; | |
}; | |
config { | |
pins = "gpio119"; | |
drive-strength = <0x2>; | |
bias-disable; | |
}; | |
}; | |
}; | |
}; | |
qcom,msm-pcm { | |
compatible = "qcom,msm-pcm-dsp"; | |
qcom,msm-pcm-dsp-id = <0x0>; | |
linux,phandle = <0x237>; | |
phandle = <0x237>; | |
}; | |
qcom,msm-pcm-routing { | |
compatible = "qcom,msm-pcm-routing"; | |
linux,phandle = <0x241>; | |
phandle = <0x241>; | |
}; | |
qcom,msm-compr-dsp { | |
compatible = "qcom,msm-compr-dsp"; | |
linux,phandle = <0x243>; | |
phandle = <0x243>; | |
}; | |
qcom,msm-pcm-low-latency { | |
compatible = "qcom,msm-pcm-dsp"; | |
qcom,msm-pcm-dsp-id = <0x1>; | |
qcom,msm-pcm-low-latency; | |
qcom,latency-level = "regular"; | |
linux,phandle = <0x238>; | |
phandle = <0x238>; | |
}; | |
qcom,msm-ultra-low-latency { | |
compatible = "qcom,msm-pcm-dsp"; | |
qcom,msm-pcm-dsp-id = <0x2>; | |
qcom,msm-pcm-low-latency; | |
qcom,latency-level = "ultra"; | |
linux,phandle = <0x239>; | |
phandle = <0x239>; | |
}; | |
qcom,msm-pcm-dsp-noirq { | |
compatible = "qcom,msm-pcm-dsp-noirq"; | |
qcom,msm-pcm-low-latency; | |
qcom,latency-level = "ultra"; | |
linux,phandle = <0x244>; | |
phandle = <0x244>; | |
}; | |
qcom,msm-compress-dsp { | |
compatible = "qcom,msm-compress-dsp"; | |
linux,phandle = <0x23d>; | |
phandle = <0x23d>; | |
}; | |
qcom,msm-voip-dsp { | |
compatible = "qcom,msm-voip-dsp"; | |
linux,phandle = <0x23a>; | |
phandle = <0x23a>; | |
}; | |
qcom,msm-pcm-voice { | |
compatible = "qcom,msm-pcm-voice"; | |
qcom,destroy-cvd; | |
linux,phandle = <0x23b>; | |
phandle = <0x23b>; | |
}; | |
qcom,msm-stub-codec { | |
compatible = "qcom,msm-stub-codec"; | |
linux,phandle = <0x273>; | |
phandle = <0x273>; | |
}; | |
qcom,msm-dai-fe { | |
compatible = "qcom,msm-dai-fe"; | |
}; | |
qcom,msm-pcm-afe { | |
compatible = "qcom,msm-pcm-afe"; | |
linux,phandle = <0x23f>; | |
phandle = <0x23f>; | |
}; | |
qcom,msm-dai-q6-hdmi { | |
compatible = "qcom,msm-dai-q6-hdmi"; | |
qcom,msm-dai-q6-dev-id = <0x8>; | |
linux,phandle = <0x247>; | |
phandle = <0x247>; | |
}; | |
qcom,msm-dai-q6-dp { | |
compatible = "qcom,msm-dai-q6-hdmi"; | |
qcom,msm-dai-q6-dev-id = <0x6020>; | |
linux,phandle = <0x248>; | |
phandle = <0x248>; | |
}; | |
qcom,msm-pcm-loopback { | |
compatible = "qcom,msm-pcm-loopback"; | |
linux,phandle = <0x23c>; | |
phandle = <0x23c>; | |
}; | |
qcom,msm-transcode-loopback { | |
compatible = "qcom,msm-transcode-loopback"; | |
linux,phandle = <0x246>; | |
phandle = <0x246>; | |
}; | |
qcom,msm-dai-mi2s { | |
compatible = "qcom,msm-dai-mi2s"; | |
qcom,msm-dai-q6-mi2s-prim { | |
compatible = "qcom,msm-dai-q6-mi2s"; | |
qcom,msm-dai-q6-mi2s-dev-id = <0x0>; | |
qcom,msm-mi2s-rx-lines = <0x3>; | |
qcom,msm-mi2s-tx-lines = <0x0>; | |
linux,phandle = <0x249>; | |
phandle = <0x249>; | |
}; | |
qcom,msm-dai-q6-mi2s-sec { | |
compatible = "qcom,msm-dai-q6-mi2s"; | |
qcom,msm-dai-q6-mi2s-dev-id = <0x1>; | |
qcom,msm-mi2s-rx-lines = <0x1>; | |
qcom,msm-mi2s-tx-lines = <0x0>; | |
linux,phandle = <0x24a>; | |
phandle = <0x24a>; | |
}; | |
qcom,msm-dai-q6-mi2s-tert { | |
compatible = "qcom,msm-dai-q6-mi2s"; | |
qcom,msm-dai-q6-mi2s-dev-id = <0x2>; | |
qcom,msm-mi2s-rx-lines = <0x0>; | |
qcom,msm-mi2s-tx-lines = <0x3>; | |
linux,phandle = <0x24b>; | |
phandle = <0x24b>; | |
}; | |
qcom,msm-dai-q6-mi2s-quat { | |
compatible = "qcom,msm-dai-q6-mi2s"; | |
qcom,msm-dai-q6-mi2s-dev-id = <0x3>; | |
qcom,msm-mi2s-rx-lines = <0x1>; | |
qcom,msm-mi2s-tx-lines = <0x2>; | |
pinctrl-names = "default", "sleep"; | |
pinctrl-0 = <0x1aa 0x1ab 0x1ac>; | |
pinctrl-1 = <0x1ad 0x1ae 0x1af>; | |
linux,phandle = <0x24c>; | |
phandle = <0x24c>; | |
}; | |
qcom,msm-dai-q6-mi2s-quin { | |
compatible = "qcom,msm-dai-q6-mi2s"; | |
qcom,msm-dai-q6-mi2s-dev-id = <0x5>; | |
qcom,msm-mi2s-rx-lines = <0x1>; | |
qcom,msm-mi2s-tx-lines = <0x2>; | |
}; | |
qcom,msm-dai-q6-mi2s-senary { | |
compatible = "qcom,msm-dai-q6-mi2s"; | |
qcom,msm-dai-q6-mi2s-dev-id = <0x6>; | |
qcom,msm-mi2s-rx-lines = <0x0>; | |
qcom,msm-mi2s-tx-lines = <0x3>; | |
}; | |
}; | |
qcom,msm-lsm-client { | |
compatible = "qcom,msm-lsm-client"; | |
linux,phandle = <0x240>; | |
phandle = <0x240>; | |
}; | |
qcom,msm-dai-q6 { | |
compatible = "qcom,msm-dai-q6"; | |
qcom,msm-dai-q6-sb-0-rx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x4000>; | |
linux,phandle = <0x251>; | |
phandle = <0x251>; | |
}; | |
qcom,msm-dai-q6-sb-0-tx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x4001>; | |
linux,phandle = <0x252>; | |
phandle = <0x252>; | |
}; | |
qcom,msm-dai-q6-sb-1-rx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x4002>; | |
linux,phandle = <0x253>; | |
phandle = <0x253>; | |
}; | |
qcom,msm-dai-q6-sb-1-tx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x4003>; | |
linux,phandle = <0x254>; | |
phandle = <0x254>; | |
}; | |
qcom,msm-dai-q6-sb-2-rx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x4004>; | |
linux,phandle = <0x255>; | |
phandle = <0x255>; | |
}; | |
qcom,msm-dai-q6-sb-2-tx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x4005>; | |
linux,phandle = <0x256>; | |
phandle = <0x256>; | |
}; | |
qcom,msm-dai-q6-sb-3-rx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x4006>; | |
linux,phandle = <0x257>; | |
phandle = <0x257>; | |
}; | |
qcom,msm-dai-q6-sb-3-tx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x4007>; | |
linux,phandle = <0x258>; | |
phandle = <0x258>; | |
}; | |
qcom,msm-dai-q6-sb-4-rx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x4008>; | |
linux,phandle = <0x259>; | |
phandle = <0x259>; | |
}; | |
qcom,msm-dai-q6-sb-4-tx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x4009>; | |
linux,phandle = <0x25a>; | |
phandle = <0x25a>; | |
}; | |
qcom,msm-dai-q6-sb-5-tx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x400b>; | |
linux,phandle = <0x25b>; | |
phandle = <0x25b>; | |
}; | |
qcom,msm-dai-q6-sb-5-rx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x400a>; | |
linux,phandle = <0x264>; | |
phandle = <0x264>; | |
}; | |
qcom,msm-dai-q6-sb-6-rx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x400c>; | |
linux,phandle = <0x265>; | |
phandle = <0x265>; | |
}; | |
qcom,msm-dai-q6-sb-7-rx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x400e>; | |
linux,phandle = <0x266>; | |
phandle = <0x266>; | |
}; | |
qcom,msm-dai-q6-sb-7-tx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x400f>; | |
linux,phandle = <0x267>; | |
phandle = <0x267>; | |
}; | |
qcom,msm-dai-q6-sb-8-rx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x4010>; | |
}; | |
qcom,msm-dai-q6-sb-8-tx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x4011>; | |
linux,phandle = <0x268>; | |
phandle = <0x268>; | |
}; | |
qcom,msm-dai-q6-bt-sco-rx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x3000>; | |
}; | |
qcom,msm-dai-q6-bt-sco-tx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x3001>; | |
}; | |
qcom,msm-dai-q6-int-fm-rx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x3004>; | |
}; | |
qcom,msm-dai-q6-int-fm-tx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x3005>; | |
}; | |
qcom,msm-dai-q6-be-afe-pcm-rx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0xe0>; | |
linux,phandle = <0x25c>; | |
phandle = <0x25c>; | |
}; | |
qcom,msm-dai-q6-be-afe-pcm-tx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0xe1>; | |
linux,phandle = <0x25d>; | |
phandle = <0x25d>; | |
}; | |
qcom,msm-dai-q6-afe-proxy-rx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0xf1>; | |
linux,phandle = <0x25e>; | |
phandle = <0x25e>; | |
}; | |
qcom,msm-dai-q6-afe-proxy-tx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0xf0>; | |
linux,phandle = <0x25f>; | |
phandle = <0x25f>; | |
}; | |
qcom,msm-dai-q6-incall-record-rx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x8003>; | |
linux,phandle = <0x260>; | |
phandle = <0x260>; | |
}; | |
qcom,msm-dai-q6-incall-record-tx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x8004>; | |
linux,phandle = <0x261>; | |
phandle = <0x261>; | |
}; | |
qcom,msm-dai-q6-incall-music-rx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x8005>; | |
linux,phandle = <0x262>; | |
phandle = <0x262>; | |
}; | |
qcom,msm-dai-q6-incall-music-2-rx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x8002>; | |
linux,phandle = <0x263>; | |
phandle = <0x263>; | |
}; | |
qcom,msm-dai-q6-usb-audio-rx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x7000>; | |
linux,phandle = <0x269>; | |
phandle = <0x269>; | |
}; | |
qcom,msm-dai-q6-usb-audio-tx { | |
compatible = "qcom,msm-dai-q6-dev"; | |
qcom,msm-dai-q6-dev-id = <0x7001>; | |
linux,phandle = <0x26a>; | |
phandle = <0x26a>; | |
}; | |
}; | |
qcom,msm-pcm-hostless { | |
compatible = "qcom,msm-pcm-hostless"; | |
linux,phandle = <0x23e>; | |
phandle = <0x23e>; | |
}; | |
qcom,msm-pri-auxpcm { | |
compatible = "qcom,msm-auxpcm-dev"; | |
qcom,msm-cpudai-auxpcm-mode = <0x0 0x0>; | |
qcom,msm-cpudai-auxpcm-sync = <0x1 0x1>; | |
qcom,msm-cpudai-auxpcm-frame = <0x5 0x4>; | |
qcom,msm-cpudai-auxpcm-quant = <0x2 0x2>; | |
qcom,msm-cpudai-auxpcm-num-slots = <0x1 0x1>; | |
qcom,msm-cpudai-auxpcm-slot-mapping = <0x1 0x1>; | |
qcom,msm-cpudai-auxpcm-data = <0x0 0x0>; | |
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
qcom,msm-auxpcm-interface = "primary"; | |
qcom,msm-cpudai-afe-clk-ver = <0x2>; | |
linux,phandle = <0x24d>; | |
phandle = <0x24d>; | |
}; | |
qcom,msm-sec-auxpcm { | |
compatible = "qcom,msm-auxpcm-dev"; | |
qcom,msm-cpudai-auxpcm-mode = <0x0 0x0>; | |
qcom,msm-cpudai-auxpcm-sync = <0x1 0x1>; | |
qcom,msm-cpudai-auxpcm-frame = <0x5 0x4>; | |
qcom,msm-cpudai-auxpcm-quant = <0x2 0x2>; | |
qcom,msm-cpudai-auxpcm-num-slots = <0x1 0x1>; | |
qcom,msm-cpudai-auxpcm-slot-mapping = <0x1 0x1>; | |
qcom,msm-cpudai-auxpcm-data = <0x0 0x0>; | |
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
qcom,msm-auxpcm-interface = "secondary"; | |
qcom,msm-cpudai-afe-clk-ver = <0x2>; | |
linux,phandle = <0x24e>; | |
phandle = <0x24e>; | |
}; | |
qcom,msm-tert-auxpcm { | |
compatible = "qcom,msm-auxpcm-dev"; | |
qcom,msm-cpudai-auxpcm-mode = <0x0 0x0>; | |
qcom,msm-cpudai-auxpcm-sync = <0x1 0x1>; | |
qcom,msm-cpudai-auxpcm-frame = <0x5 0x4>; | |
qcom,msm-cpudai-auxpcm-quant = <0x2 0x2>; | |
qcom,msm-cpudai-auxpcm-num-slots = <0x1 0x1>; | |
qcom,msm-cpudai-auxpcm-slot-mapping = <0x1 0x1>; | |
qcom,msm-cpudai-auxpcm-data = <0x0 0x0>; | |
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
qcom,msm-auxpcm-interface = "tertiary"; | |
qcom,msm-cpudai-afe-clk-ver = <0x2>; | |
linux,phandle = <0x24f>; | |
phandle = <0x24f>; | |
}; | |
qcom,msm-quat-auxpcm { | |
compatible = "qcom,msm-auxpcm-dev"; | |
qcom,msm-cpudai-auxpcm-mode = <0x0 0x0>; | |
qcom,msm-cpudai-auxpcm-sync = <0x1 0x1>; | |
qcom,msm-cpudai-auxpcm-frame = <0x5 0x4>; | |
qcom,msm-cpudai-auxpcm-quant = <0x2 0x2>; | |
qcom,msm-cpudai-auxpcm-num-slots = <0x1 0x1>; | |
qcom,msm-cpudai-auxpcm-slot-mapping = <0x1 0x1>; | |
qcom,msm-cpudai-auxpcm-data = <0x0 0x0>; | |
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
qcom,msm-auxpcm-interface = "quaternary"; | |
qcom,msm-cpudai-afe-clk-ver = <0x2>; | |
linux,phandle = <0x250>; | |
phandle = <0x250>; | |
}; | |
qcom,msm-hdmi-dba-codec-rx { | |
compatible = "qcom,msm-hdmi-dba-codec-rx"; | |
qcom,dba-bridge-chip = "adv7533"; | |
}; | |
qcom,msm-audio-ion { | |
compatible = "qcom,msm-audio-ion"; | |
qcom,smmu-version = <0x2>; | |
qcom,smmu-enabled; | |
iommus = <0x65 0x1>; | |
}; | |
qcom,msm-adsp-loader { | |
status = "ok"; | |
compatible = "qcom,adsp-loader"; | |
qcom,adsp-state = <0x0>; | |
}; | |
qcom,msm-dai-tdm-pri-rx { | |
compatible = "qcom,msm-dai-tdm"; | |
qcom,msm-cpudai-tdm-group-id = <0x9100>; | |
qcom,msm-cpudai-tdm-group-num-ports = <0x1>; | |
qcom,msm-cpudai-tdm-group-port-id = <0x9000>; | |
qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
qcom,msm-cpudai-tdm-clk-internal = <0x1>; | |
qcom,msm-cpudai-tdm-sync-mode = <0x1>; | |
qcom,msm-cpudai-tdm-sync-src = <0x1>; | |
qcom,msm-cpudai-tdm-data-out = <0x0>; | |
qcom,msm-cpudai-tdm-invert-sync = <0x1>; | |
qcom,msm-cpudai-tdm-data-delay = <0x1>; | |
qcom,msm-dai-q6-tdm-pri-rx-0 { | |
compatible = "qcom,msm-dai-q6-tdm"; | |
qcom,msm-cpudai-tdm-dev-id = <0x9000>; | |
qcom,msm-cpudai-tdm-data-align = <0x0>; | |
linux,phandle = <0x26b>; | |
phandle = <0x26b>; | |
}; | |
}; | |
qcom,msm-dai-tdm-pri-tx { | |
compatible = "qcom,msm-dai-tdm"; | |
qcom,msm-cpudai-tdm-group-id = <0x9101>; | |
qcom,msm-cpudai-tdm-group-num-ports = <0x1>; | |
qcom,msm-cpudai-tdm-group-port-id = <0x9001>; | |
qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
qcom,msm-cpudai-tdm-clk-internal = <0x1>; | |
qcom,msm-cpudai-tdm-sync-mode = <0x1>; | |
qcom,msm-cpudai-tdm-sync-src = <0x1>; | |
qcom,msm-cpudai-tdm-data-out = <0x0>; | |
qcom,msm-cpudai-tdm-invert-sync = <0x1>; | |
qcom,msm-cpudai-tdm-data-delay = <0x1>; | |
qcom,msm-dai-q6-tdm-pri-tx-0 { | |
compatible = "qcom,msm-dai-q6-tdm"; | |
qcom,msm-cpudai-tdm-dev-id = <0x9001>; | |
qcom,msm-cpudai-tdm-data-align = <0x0>; | |
linux,phandle = <0x26c>; | |
phandle = <0x26c>; | |
}; | |
}; | |
qcom,msm-dai-tdm-sec-rx { | |
compatible = "qcom,msm-dai-tdm"; | |
qcom,msm-cpudai-tdm-group-id = <0x9110>; | |
qcom,msm-cpudai-tdm-group-num-ports = <0x1>; | |
qcom,msm-cpudai-tdm-group-port-id = <0x9010>; | |
qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
qcom,msm-cpudai-tdm-clk-internal = <0x1>; | |
qcom,msm-cpudai-tdm-sync-mode = <0x1>; | |
qcom,msm-cpudai-tdm-sync-src = <0x1>; | |
qcom,msm-cpudai-tdm-data-out = <0x0>; | |
qcom,msm-cpudai-tdm-invert-sync = <0x1>; | |
qcom,msm-cpudai-tdm-data-delay = <0x1>; | |
qcom,msm-dai-q6-tdm-sec-rx-0 { | |
compatible = "qcom,msm-dai-q6-tdm"; | |
qcom,msm-cpudai-tdm-dev-id = <0x9010>; | |
qcom,msm-cpudai-tdm-data-align = <0x0>; | |
linux,phandle = <0x26d>; | |
phandle = <0x26d>; | |
}; | |
}; | |
qcom,msm-dai-tdm-sec-tx { | |
compatible = "qcom,msm-dai-tdm"; | |
qcom,msm-cpudai-tdm-group-id = <0x9111>; | |
qcom,msm-cpudai-tdm-group-num-ports = <0x1>; | |
qcom,msm-cpudai-tdm-group-port-id = <0x9011>; | |
qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
qcom,msm-cpudai-tdm-clk-internal = <0x1>; | |
qcom,msm-cpudai-tdm-sync-mode = <0x1>; | |
qcom,msm-cpudai-tdm-sync-src = <0x1>; | |
qcom,msm-cpudai-tdm-data-out = <0x0>; | |
qcom,msm-cpudai-tdm-invert-sync = <0x1>; | |
qcom,msm-cpudai-tdm-data-delay = <0x1>; | |
qcom,msm-dai-q6-tdm-sec-tx-0 { | |
compatible = "qcom,msm-dai-q6-tdm"; | |
qcom,msm-cpudai-tdm-dev-id = <0x9011>; | |
qcom,msm-cpudai-tdm-data-align = <0x0>; | |
linux,phandle = <0x26e>; | |
phandle = <0x26e>; | |
}; | |
}; | |
qcom,msm-dai-tdm-tert-rx { | |
compatible = "qcom,msm-dai-tdm"; | |
qcom,msm-cpudai-tdm-group-id = <0x9120>; | |
qcom,msm-cpudai-tdm-group-num-ports = <0x1>; | |
qcom,msm-cpudai-tdm-group-port-id = <0x9020>; | |
qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
qcom,msm-cpudai-tdm-clk-internal = <0x1>; | |
qcom,msm-cpudai-tdm-sync-mode = <0x1>; | |
qcom,msm-cpudai-tdm-sync-src = <0x1>; | |
qcom,msm-cpudai-tdm-data-out = <0x0>; | |
qcom,msm-cpudai-tdm-invert-sync = <0x1>; | |
qcom,msm-cpudai-tdm-data-delay = <0x1>; | |
qcom,msm-dai-q6-tdm-tert-rx-0 { | |
compatible = "qcom,msm-dai-q6-tdm"; | |
qcom,msm-cpudai-tdm-dev-id = <0x9020>; | |
qcom,msm-cpudai-tdm-data-align = <0x0>; | |
linux,phandle = <0x26f>; | |
phandle = <0x26f>; | |
}; | |
}; | |
qcom,msm-dai-tdm-tert-tx { | |
compatible = "qcom,msm-dai-tdm"; | |
qcom,msm-cpudai-tdm-group-id = <0x9121>; | |
qcom,msm-cpudai-tdm-group-num-ports = <0x1>; | |
qcom,msm-cpudai-tdm-group-port-id = <0x9021>; | |
qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
qcom,msm-cpudai-tdm-clk-internal = <0x1>; | |
qcom,msm-cpudai-tdm-sync-mode = <0x1>; | |
qcom,msm-cpudai-tdm-sync-src = <0x1>; | |
qcom,msm-cpudai-tdm-data-out = <0x0>; | |
qcom,msm-cpudai-tdm-invert-sync = <0x1>; | |
qcom,msm-cpudai-tdm-data-delay = <0x1>; | |
qcom,msm-dai-q6-tdm-tert-tx-0 { | |
compatible = "qcom,msm-dai-q6-tdm"; | |
qcom,msm-cpudai-tdm-dev-id = <0x9021>; | |
qcom,msm-cpudai-tdm-data-align = <0x0>; | |
linux,phandle = <0x270>; | |
phandle = <0x270>; | |
}; | |
}; | |
qcom,msm-dai-tdm-quat-rx { | |
compatible = "qcom,msm-dai-tdm"; | |
qcom,msm-cpudai-tdm-group-id = <0x9130>; | |
qcom,msm-cpudai-tdm-group-num-ports = <0x1>; | |
qcom,msm-cpudai-tdm-group-port-id = <0x9030>; | |
qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
qcom,msm-cpudai-tdm-clk-internal = <0x1>; | |
qcom,msm-cpudai-tdm-sync-mode = <0x1>; | |
qcom,msm-cpudai-tdm-sync-src = <0x1>; | |
qcom,msm-cpudai-tdm-data-out = <0x0>; | |
qcom,msm-cpudai-tdm-invert-sync = <0x1>; | |
qcom,msm-cpudai-tdm-data-delay = <0x1>; | |
qcom,msm-dai-q6-tdm-quat-rx-0 { | |
compatible = "qcom,msm-dai-q6-tdm"; | |
qcom,msm-cpudai-tdm-dev-id = <0x9030>; | |
qcom,msm-cpudai-tdm-data-align = <0x0>; | |
linux,phandle = <0x271>; | |
phandle = <0x271>; | |
}; | |
}; | |
qcom,msm-dai-tdm-quat-tx { | |
compatible = "qcom,msm-dai-tdm"; | |
qcom,msm-cpudai-tdm-group-id = <0x9131>; | |
qcom,msm-cpudai-tdm-group-num-ports = <0x1>; | |
qcom,msm-cpudai-tdm-group-port-id = <0x9031>; | |
qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
qcom,msm-cpudai-tdm-clk-internal = <0x1>; | |
qcom,msm-cpudai-tdm-sync-mode = <0x1>; | |
qcom,msm-cpudai-tdm-sync-src = <0x1>; | |
qcom,msm-cpudai-tdm-data-out = <0x0>; | |
qcom,msm-cpudai-tdm-invert-sync = <0x1>; | |
qcom,msm-cpudai-tdm-data-delay = <0x1>; | |
qcom,msm-dai-q6-tdm-quat-tx-0 { | |
compatible = "qcom,msm-dai-q6-tdm"; | |
qcom,msm-cpudai-tdm-dev-id = <0x9031>; | |
qcom,msm-cpudai-tdm-data-align = <0x0>; | |
linux,phandle = <0x272>; | |
phandle = <0x272>; | |
}; | |
}; | |
qcom,mdss_mdp@c900000 { | |
compatible = "qcom,mdss_mdp"; | |
status = "ok"; | |
reg = <0xc900000 0x90000 0xc9b0000 0x1040>; | |
reg-names = "mdp_phys", "vbif_phys"; | |
interrupts = <0x0 0x53 0x0>; | |
interrupt-controller; | |
#interrupt-cells = <0x1>; | |
vdd-supply = <0x2a>; | |
gdsc-core-supply = <0x28>; | |
qcom,msm-bus,name = "mdss_mdp"; | |
qcom,msm-bus,num-cases = <0x3>; | |
qcom,msm-bus,num-paths = <0x2>; | |
qcom,msm-bus,vectors-KBps = <0x16 0x200 0x0 0x0 0x17 0x200 0x0 0x0 0x16 0x200 0x0 0x61a800 0x17 0x200 0x0 0x61a800 0x16 0x200 0x0 0x61a800 0x17 0x200 0x0 0x61a800>; | |
qcom,mdss-ab-factor = <0x1 0x1>; | |
qcom,mdss-ib-factor = <0x1 0x1>; | |
qcom,mdss-clk-factor = <0x69 0x64>; | |
qcom,max-mixer-width = <0xa00>; | |
qcom,max-pipe-width = <0xa00>; | |
qcom,max-dest-scaler-input-width = <0x800>; | |
qcom,max-dest-scaler-output-width = <0xa00>; | |
qcom,mdss-vbif-qos-rt-setting = <0x1 0x2 0x2 0x2>; | |
qcom,mdss-vbif-qos-nrt-setting = <0x1 0x1 0x1 0x1>; | |
qcom,vbif-settings = <0xd0 0x2020>; | |
qcom,mdss-has-panic-ctrl; | |
qcom,mdss-per-pipe-panic-luts = <0xf 0xffff 0xfffc 0xff00>; | |
qcom,mdss-mdp-reg-offset = <0x1000>; | |
qcom,max-bandwidth-low-kbps = <0x8f6ec0>; | |
qcom,max-bandwidth-high-kbps = <0x8f6ec0>; | |
qcom,max-bandwidth-per-pipe-kbps = <0x47b760>; | |
qcom,max-clk-rate = <0x18964020>; | |
qcom,mdss-default-ot-rd-limit = <0x20>; | |
qcom,mdss-default-ot-wr-limit = <0x20>; | |
qcom,mdss-dram-channels = <0x2>; | |
qcom,mdss-pipe-vig-off = <0x5000 0x7000 0x9000 0xb000>; | |
qcom,mdss-pipe-dma-off = <0x25000 0x27000 0x29000 0x2b000>; | |
qcom,mdss-pipe-cursor-off = <0x35000 0x37000>; | |
qcom,mdss-pipe-vig-xin-id = <0x0 0x4 0x8 0xc>; | |
qcom,mdss-pipe-dma-xin-id = <0x1 0x5 0x9 0xd>; | |
qcom,mdss-pipe-cursor-xin-id = <0x2 0xa>; | |
qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x2ac 0x0 0x0 0x2b4 0x0 0x0 0x2bc 0x0 0x0 0x2c4 0x0 0x0>; | |
qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2ac 0x8 0xc 0x2b4 0x8 0xc 0x2c4 0x8 0xc 0x2c4 0xc 0xe>; | |
qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3a8 0x10 0xf 0x3b0 0x10 0xf>; | |
qcom,mdss-ctl-off = <0x2000 0x2200 0x2400 0x2600 0x2800>; | |
qcom,mdss-mixer-intf-off = <0x45000 0x46000 0x47000 0x4a000>; | |
qcom,mdss-dspp-off = <0x55000 0x57000>; | |
qcom,mdss-wb-off = <0x66000>; | |
qcom,mdss-intf-off = <0x6b000 0x6b800 0x6c000 0x6c800>; | |
qcom,mdss-pingpong-off = <0x71000 0x71800 0x72000 0x72800>; | |
qcom,mdss-slave-pingpong-off = <0x73000>; | |
qcom,mdss-ppb-ctl-off = <0x330 0x338 0x370 0x374>; | |
qcom,mdss-ppb-cfg-off = <0x334 0x33c>; | |
qcom,mdss-has-pingpong-split; | |
qcom,mdss-has-separate-rotator; | |
qcom,mdss-ad-off = <0x79000 0x79800>; | |
qcom,mdss-cdm-off = <0x7a200>; | |
qcom,mdss-dsc-off = <0x81000 0x81400>; | |
qcom,mdss-wfd-mode = "intf"; | |
qcom,mdss-has-source-split; | |
qcom,mdss-highest-bank-bit = <0x2>; | |
qcom,mdss-has-decimation; | |
qcom,mdss-idle-power-collapse-enabled; | |
clocks = <0x27 0x49a394f4 0x27 0x85d37ab5 0x27 0xdf04fc1d 0x27 0x6dc1f8f1 0x27 0x43539b0e 0x27 0x629b36dc 0x27 0x627b2b>; | |
clock-names = "mnoc_clk", "iface_clk", "bus_clk", "core_clk_src", "core_clk", "vsync_clk", "lut_clk"; | |
qcom,mdp-settings = <0x1190 0x0 0x12ac 0xc0000ccc 0x12b4 0xc0000ccc 0x12bc 0xcccccc 0x12c4 0xcccc 0x13a8 0xcccc0c0 0x13b0 0xccccc0c0 0x13b8 0xcccc0000 0x13d0 0xcc0000 0x506c 0x0 0x706c 0x0 0x906c 0x0 0xb06c 0x0 0x1506c 0x0 0x1706c 0x0 0x1906c 0x0 0x1b06c 0x0 0x2506c 0x0 0x2706c 0x0>; | |
qcom,regs-dump-mdp = <0x1000 0x1458 0x2000 0x2094 0x2200 0x2294 0x2400 0x2494 0x2600 0x2694 0x2800 0x2894 0x5000 0x5154 0x5a00 0x5b00 0x7000 0x7154 0x7a00 0x7b00 0x9000 0x9154 0x9a00 0x9b00 0xb000 0xb154 0xba00 0xbb00 0x25000 0x25184 0x27000 0x27184 0x29000 0x29184 0x2b000 0x2b184 0x35000 0x35150 0x37000 0x37150 0x45000 0x452bc 0x46000 0x462bc 0x47000 0x472bc 0x48000 0x482bc 0x49000 0x492bc 0x4a000 0x4a2bc 0x55000 0x5522c 0x57000 0x5722c 0x61000 0x61014 0x61800 0x61888 0x62000 0x62088 0x66000 0x662c0 0x6b000 0x6b268 0x6b800 0x6ba68 0x6c000 0x6c268 0x6c800 0x6ca68 0x71000 0x710d4 0x71800 0x718d4 0x73000 0x730d4 0x81000 0x81140 0x81400 0x81540>; | |
qcom,regs-dump-names-mdp = "MDP", "CTL_0", "CTL_1", "CTL_2", "CTL_3", "CTL_4", "VIG0_SSPP", "VIG0", "VIG1_SSPP", "VIG1", "VIG2_SSPP", "VIG2", "VIG3_SSPP", "VIG3", "DMA0_SSPP", "DMA1_SSPP", "DMA2_SSPP", "DMA3_SSPP", "CURSOR0_SSPP", "CURSOR1_SSPP", "LAYER_0", "LAYER_1", "LAYER_2", "LAYER_3", "LAYER_4", "LAYER_5", "DSPP_0", "DSPP_1", "DEST_SCALER_OP", "DEST_SCALER_0", "DEST_SCALER_1", "WB_2", "INTF_0", "INTF_1", "INTF_2", "INTF_3", "PP_0", "PP_1", "PP_4", "DSC_0", "DSC_1"; | |
qcom,mdss-prefill-outstanding-buffer-bytes = <0x0>; | |
qcom,mdss-prefill-y-buffer-bytes = <0x0>; | |
qcom,mdss-prefill-scaler-buffer-lines-bilinear = <0x2>; | |
qcom,mdss-prefill-scaler-buffer-lines-caf = <0x4>; | |
qcom,mdss-prefill-post-scaler-buffer-pixels = <0xa00>; | |
qcom,mdss-prefill-pingpong-buffer-pixels = <0x1400>; | |
qcom,mdss-pref-prim-intf = "dsi"; | |
linux,phandle = <0x1c6>; | |
phandle = <0x1c6>; | |
qcom,mdss-pp-offsets { | |
qcom,mdss-sspp-mdss-igc-lut-off = <0x2000>; | |
qcom,mdss-sspp-vig-pcc-off = <0x1780>; | |
qcom,mdss-sspp-rgb-pcc-off = <0x380>; | |
qcom,mdss-sspp-dma-pcc-off = <0x380>; | |
qcom,mdss-lm-pgc-off = <0x3c0>; | |
qcom,mdss-dspp-gamut-off = <0x1600>; | |
qcom,mdss-dspp-pcc-off = <0x1700>; | |
qcom,mdss-dspp-pgc-off = <0x17c0>; | |
}; | |
qcom,mdss-scaler-offsets { | |
qcom,mdss-vig-scaler-off = <0xa00>; | |
qcom,mdss-vig-scaler-lut-off = <0xb00>; | |
qcom,mdss-has-dest-scaler; | |
qcom,mdss-dest-block-off = <0x61000>; | |
qcom,mdss-dest-scaler-off = <0x800 0x1000>; | |
qcom,mdss-dest-scaler-lut-off = <0x900 0x1100>; | |
}; | |
qcom,smmu_mdp_unsec_cb { | |
compatible = "qcom,smmu_mdp_unsec"; | |
iommus = <0xd4 0x0>; | |
gdsc-mmagic-mdss-supply = <0x28>; | |
clocks = <0x38 0xdb4b31e6 0x27 0x49a394f4 0x27 0x4825baf4 0x27 0xc365ac39>; | |
clock-names = "mmss_noc_axi_clk", "mmss_noc_ahb_clk", "mmss_smmu_ahb_clk", "mmss_smmu_axi_clk"; | |
}; | |
qcom,smmu_mdp_sec_cb { | |
compatible = "qcom,smmu_mdp_sec"; | |
iommus = <0xd4 0x1>; | |
gdsc-mmagic-mdss-supply = <0x28>; | |
clocks = <0x38 0xdb4b31e6 0x27 0x49a394f4 0x27 0x4825baf4 0x27 0xc365ac39>; | |
clock-names = "mmss_noc_axi_clk", "mmss_noc_ahb_clk", "mmss_smmu_ahb_clk", "mmss_smmu_axi_clk"; | |
}; | |
qcom,mdss_fb_primary { | |
cell-index = <0x0>; | |
compatible = "qcom,mdss-fb"; | |
linux,phandle = <0x1c7>; | |
phandle = <0x1c7>; | |
qcom,cont-splash-memory { | |
linux,contiguous-region = <0x1b0>; | |
}; | |
}; | |
qcom,mdss_fb_wfd { | |
cell-index = <0x1>; | |
compatible = "qcom,mdss-fb"; | |
linux,phandle = <0x1c9>; | |
phandle = <0x1c9>; | |
}; | |
qcom,mdss_fb_hdmi { | |
cell-index = <0x2>; | |
compatible = "qcom,mdss-fb"; | |
qcom,mdss-intf = <0x1b1>; | |
linux,phandle = <0x1cc>; | |
phandle = <0x1cc>; | |
}; | |
qcom,mdss_fb_dp { | |
cell-index = <0x3>; | |
compatible = "qcom,mdss-fb"; | |
qcom,mdss-intf = <0x1b2>; | |
linux,phandle = <0x1cb>; | |
phandle = <0x1cb>; | |
}; | |
qcom,mdss_dsi_sim_video { | |
qcom,mdss-dsi-panel-name = "Simulator video mode dsi panel"; | |
qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x280>; | |
qcom,mdss-dsi-panel-height = <0x1e0>; | |
qcom,mdss-dsi-h-front-porch = <0x8>; | |
qcom,mdss-dsi-h-back-porch = <0x8>; | |
qcom,mdss-dsi-h-pulse-width = <0x8>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x6>; | |
qcom,mdss-dsi-v-front-porch = <0x6>; | |
qcom,mdss-dsi-v-pulse-width = <0x2>; | |
qcom,mdss-dsi-h-left-border = <0x0>; | |
qcom,mdss-dsi-h-right-border = <0x0>; | |
qcom,mdss-dsi-v-top-border = <0x0>; | |
qcom,mdss-dsi-v-bottom-border = <0x0>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-underflow-color = <0xff>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00]; | |
qcom,mdss-dsi-off-command = [22 01 00 00 00 00 02 00 00]; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-panel-timings = <0x0 0x0 0x0>; | |
qcom,mdss-dsi-t-clk-post = <0x4>; | |
qcom,mdss-dsi-t-clk-pre = <0x1b>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-reset-sequence = <0x1 0x0 0x0 0x0 0x1 0x0>; | |
qcom,panel-ack-disabled; | |
}; | |
qcom,mdss_dsi_dual_sim_video { | |
qcom,mdss-dsi-panel-name = "Sim dual video mode dsi panel"; | |
qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x500>; | |
qcom,mdss-dsi-panel-height = <0x5a0>; | |
qcom,mdss-dsi-h-front-porch = <0x78>; | |
qcom,mdss-dsi-h-back-porch = <0x2c>; | |
qcom,mdss-dsi-h-pulse-width = <0x10>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x4>; | |
qcom,mdss-dsi-v-front-porch = <0x8>; | |
qcom,mdss-dsi-v-pulse-width = <0x4>; | |
qcom,mdss-dsi-h-left-border = <0x0>; | |
qcom,mdss-dsi-h-right-border = <0x0>; | |
qcom,mdss-dsi-v-top-border = <0x0>; | |
qcom,mdss-dsi-v-bottom-border = <0x0>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-underflow-color = <0xff>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-panel-broadcast-mode; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-panel-timings = <0xcd322200 0x60642634 0x29030400>; | |
qcom,mdss-dsi-t-clk-post = <0x3>; | |
qcom,mdss-dsi-t-clk-pre = <0x27>; | |
qcom,mdss-dsi-bl-max-level = <0xfff>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-reset-sequence = <0x1 0x14 0x0 0xc8 0x1 0x14>; | |
qcom,panel-ack-disabled; | |
}; | |
qcom,mdss_dsi_nt35597_wqxga_video { | |
qcom,mdss-dsi-panel-name = "Dual nt35597 video mode dsi panel without DSC"; | |
qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x2d0>; | |
qcom,mdss-dsi-panel-height = <0xa00>; | |
qcom,mdss-dsi-h-front-porch = <0x64>; | |
qcom,mdss-dsi-h-back-porch = <0x20>; | |
qcom,mdss-dsi-h-pulse-width = <0x10>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x7>; | |
qcom,mdss-dsi-v-front-porch = <0x8>; | |
qcom,mdss-dsi-v-pulse-width = <0x1>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-underflow-color = <0x3ff>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-panel-hdr-enabled; | |
qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 ba 03 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 bb 03 15 01 00 00 00 00 02 b0 03 39 01 00 00 00 00 06 3b 03 08 08 64 9a 15 01 00 00 00 00 02 ff e0 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 6b 3d 15 01 00 00 00 00 02 6c 3d 15 01 00 00 00 00 02 6d 3d 15 01 00 00 00 00 02 6e 3d 15 01 00 00 00 00 02 6f 3d 15 01 00 00 00 00 02 35 02 15 01 00 00 00 00 02 36 72 15 01 00 00 00 00 02 37 10 15 01 00 00 00 00 02 08 c0 15 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 02 11 00 05 01 00 00 32 00 02 29 00]; | |
qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00 05 01 00 00 3c 00 02 10 00]; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,cmd-sync-wait-broadcast; | |
qcom,mdss-dsi-panel-timings = <0x1c0807 0x23220707 0x5030400>; | |
qcom,mdss-dsi-t-clk-post = <0xd>; | |
qcom,mdss-dsi-t-clk-pre = <0x2d>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
qcom,mdss-pan-physical-height-dimension = <0x83>; | |
qcom,mdss-dsi-min-refresh-rate = <0x37>; | |
qcom,mdss-dsi-max-refresh-rate = <0x3c>; | |
qcom,mdss-dsi-pan-enable-dynamic-fps; | |
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; | |
qcom,config-select = <0x1b3>; | |
qcom,esd-check-enabled; | |
qcom,mdss-dsi-panel-status-check-mode = "bta_check"; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
qcom,mdss-dsi-bl-min-level = <0x1>; | |
qcom,mdss-dsi-bl-max-level = <0xfff>; | |
qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; | |
qcom,panel-supply-entries = <0x1b4>; | |
config0 { | |
qcom,split-mode = "dualctl-split"; | |
linux,phandle = <0x1b3>; | |
phandle = <0x1b3>; | |
}; | |
config1 { | |
qcom,split-mode = "pingpong-split"; | |
}; | |
}; | |
qcom,mdss_dsi_nt35597_wqxga_cmd { | |
qcom,mdss-dsi-panel-name = "Dual nt35597 cmd mode dsi panel without DSC"; | |
qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x2d0>; | |
qcom,mdss-dsi-panel-height = <0xa00>; | |
qcom,mdss-dsi-h-front-porch = <0x64>; | |
qcom,mdss-dsi-h-back-porch = <0x20>; | |
qcom,mdss-dsi-h-pulse-width = <0x10>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x7>; | |
qcom,mdss-dsi-v-front-porch = <0x8>; | |
qcom,mdss-dsi-v-pulse-width = <0x1>; | |
qcom,mdss-dsi-h-left-border = <0x0>; | |
qcom,mdss-dsi-h-right-border = <0x0>; | |
qcom,mdss-dsi-v-top-border = <0x0>; | |
qcom,mdss-dsi-v-bottom-border = <0x0>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
qcom,mdss-dsi-underflow-color = <0xff>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-panel-timings = <0x1c0807 0x23220707 0x5030400>; | |
qcom,adjust-timer-wakeup-ms = <0x1>; | |
qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
qcom,mdss-pan-physical-height-dimension = <0x83>; | |
qcom,mdss-dsi-t-clk-post = <0xd>; | |
qcom,mdss-dsi-t-clk-pre = <0x2d>; | |
qcom,mdss-dsi-bl-max-level = <0xfff>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-te-pin-select = <0x1>; | |
qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
qcom,mdss-dsi-te-dcs-command = <0x1>; | |
qcom,mdss-dsi-te-check-enable; | |
qcom,mdss-dsi-te-using-te-pin; | |
qcom,ulps-enabled; | |
qcom,mdss-dsi-on-command = <0x15010000 0x100002ff 0x10150100 0x100002 0xfb011501 0x1000 0x2ba0315 0x1000010 0x2e501 0x15010000 0x10000235 0x150100 0x100002 0xbb101501 0x1000 0x2b00315 0x1000010 0x2ffe0 0x15010000 0x100002fb 0x1150100 0x100002 0x6b3d1501 0x1000 0x26c3d15 0x1000010 0x26d3d 0x15010000 0x1000026e 0x3d150100 0x100002 0x6f3d1501 0x1000 0x2350215 0x1000010 0x23672 0x15010000 0x10000237 0x10150100 0x100002 0x8c01501 0x1000 0x2ff2415 0x1000010 0x2fb01 0x15010000 0x100002c6 0x6150100 0x100002 0xff100501 0xa000 0x2110005 0x10000a0 0x22900>; | |
qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00 05 01 00 00 3c 00 02 10 00]; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,config-select = <0x1b5>; | |
qcom,cmd-sync-wait-broadcast; | |
qcom,esd-check-enabled; | |
qcom,mdss-dsi-panel-status-check-mode = "bta_check"; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
qcom,mdss-dsi-bl-min-level = <0x1>; | |
qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; | |
qcom,panel-supply-entries = <0x1b4>; | |
config0 { | |
qcom,split-mode = "dualctl-split"; | |
linux,phandle = <0x1b5>; | |
phandle = <0x1b5>; | |
}; | |
config1 { | |
qcom,split-mode = "pingpong-split"; | |
}; | |
}; | |
qcom,mdss_dsi_nt35597_wqxga_video_truly { | |
qcom,mdss-dsi-panel-name = "Dual nt35597 video mode dsi truly panel without DSC"; | |
qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x2d0>; | |
qcom,mdss-dsi-panel-height = <0xa00>; | |
qcom,mdss-dsi-h-front-porch = <0x64>; | |
qcom,mdss-dsi-h-back-porch = <0x20>; | |
qcom,mdss-dsi-h-pulse-width = <0x10>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x7>; | |
qcom,mdss-dsi-v-front-porch = <0x8>; | |
qcom,mdss-dsi-v-pulse-width = <0x1>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-underflow-color = <0x3ff>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 03 15 01 00 00 00 00 02 fb 01 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; | |
qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,cmd-sync-wait-broadcast; | |
qcom,mdss-dsi-panel-timings = <0x190506 0xa0f0506 0x5030400>; | |
qcom,mdss-dsi-t-clk-post = <0x7>; | |
qcom,mdss-dsi-t-clk-pre = <0x26>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-reset-sequence = <0x1 0x14 0x0 0x14 0x1 0x32>; | |
qcom,mdss-dsi-tx-eot-append; | |
qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
qcom,mdss-pan-physical-height-dimension = <0x83>; | |
qcom,config-select = <0x1b6>; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
qcom,mdss-dsi-bl-min-level = <0x1>; | |
qcom,mdss-dsi-bl-max-level = <0xfff>; | |
qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; | |
qcom,panel-supply-entries = <0x1b4>; | |
config0 { | |
qcom,split-mode = "dualctl-split"; | |
linux,phandle = <0x1b6>; | |
phandle = <0x1b6>; | |
}; | |
}; | |
qcom,mdss_dsi_nt35597_truly_wqxga_cmd { | |
qcom,mdss-dsi-panel-name = "Dual nt35597 cmd mode dsi truly panel without DSC"; | |
qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x2d0>; | |
qcom,mdss-dsi-panel-height = <0xa00>; | |
qcom,mdss-dsi-h-front-porch = <0x64>; | |
qcom,mdss-dsi-h-back-porch = <0x20>; | |
qcom,mdss-dsi-h-pulse-width = <0x10>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x7>; | |
qcom,mdss-dsi-v-front-porch = <0x8>; | |
qcom,mdss-dsi-v-pulse-width = <0x1>; | |
qcom,mdss-dsi-h-left-border = <0x0>; | |
qcom,mdss-dsi-h-right-border = <0x0>; | |
qcom,mdss-dsi-v-top-border = <0x0>; | |
qcom,mdss-dsi-v-bottom-border = <0x0>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
qcom,mdss-dsi-underflow-color = <0xff>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-panel-timings = <0x190506 0xa0f0506 0x5030400>; | |
qcom,adjust-timer-wakeup-ms = <0x1>; | |
qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
qcom,mdss-dsi-tx-eot-append; | |
qcom,mdss-dsi-t-clk-post = <0x7>; | |
qcom,mdss-dsi-t-clk-pre = <0x26>; | |
qcom,mdss-dsi-bl-max-level = <0xfff>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-te-pin-select = <0x1>; | |
qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
qcom,mdss-dsi-te-dcs-command = <0x1>; | |
qcom,mdss-dsi-te-check-enable; | |
qcom,mdss-dsi-te-using-te-pin; | |
qcom,ulps-enabled; | |
qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 fb 01 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; | |
qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
qcom,mdss-pan-physical-height-dimension = <0x83>; | |
qcom,config-select = <0x1b7>; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
qcom,mdss-dsi-bl-min-level = <0x1>; | |
qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; | |
qcom,panel-supply-entries = <0x1b4>; | |
config0 { | |
qcom,split-mode = "dualctl-split"; | |
linux,phandle = <0x1b7>; | |
phandle = <0x1b7>; | |
}; | |
}; | |
qcom,mdss_dsi_nt35597_dsc_wqxga_video { | |
qcom,mdss-dsi-panel-name = "NT35597 video mode dsc dsi panel"; | |
qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x5a0>; | |
qcom,mdss-dsi-panel-height = <0xa00>; | |
qcom,mdss-dsi-h-front-porch = <0x64>; | |
qcom,mdss-dsi-h-back-porch = <0x20>; | |
qcom,mdss-dsi-h-pulse-width = <0x10>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x7>; | |
qcom,mdss-dsi-v-front-porch = <0x8>; | |
qcom,mdss-dsi-v-pulse-width = <0x1>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-underflow-color = <0xff>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-panel-hdr-enabled; | |
qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 ba 03 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 b0 03 39 01 00 00 00 00 06 3b 03 08 08 2e 64 15 01 00 00 00 00 02 ff 28 15 01 00 00 00 00 02 7a 02 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 c0 03 15 01 00 00 00 00 02 bb 03 15 01 00 00 00 00 02 ff e0 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 6b 3d 15 01 00 00 00 00 02 6c 3d 15 01 00 00 00 00 02 6d 3d 15 01 00 00 00 00 02 6e 3d 15 01 00 00 00 00 02 6f 3d 15 01 00 00 00 00 02 35 02 15 01 00 00 00 00 02 36 72 15 01 00 00 00 00 02 37 10 15 01 00 00 00 00 02 08 c0 15 01 00 00 00 00 02 ff 10 05 01 00 00 a0 00 01 11 05 01 00 00 00 00 01 29 07 01 00 00 0a 00 01 01]; | |
qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00 05 01 00 00 0a 00 02 10 00]; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-panel-timings = <0x110404 0x70c0404 0x3030400>; | |
qcom,mdss-dsi-t-clk-post = <0x5>; | |
qcom,mdss-dsi-t-clk-pre = <0x1b>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
qcom,mdss-pan-physical-height-dimension = <0x83>; | |
qcom,compression-mode = "dsc"; | |
qcom,config-select = <0x1b8>; | |
qcom,esd-check-enabled; | |
qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-panel-status-value = <0x9c>; | |
qcom,mdss-dsi-panel-on-check-value = <0x9c>; | |
qcom,mdss-dsi-panel-status-read-length = <0x1>; | |
qcom,mdss-dsi-panel-max-error-count = <0x3>; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
qcom,mdss-dsi-bl-min-level = <0x1>; | |
qcom,mdss-dsi-bl-max-level = <0xfff>; | |
qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; | |
qcom,panel-supply-entries = <0x1b4>; | |
config0 { | |
qcom,mdss-dsc-encoders = <0x1>; | |
qcom,mdss-dsc-slice-height = <0x10>; | |
qcom,mdss-dsc-slice-width = <0x2d0>; | |
qcom,mdss-dsc-slice-per-pkt = <0x2>; | |
qcom,mdss-dsc-bit-per-component = <0x8>; | |
qcom,mdss-dsc-bit-per-pixel = <0x8>; | |
qcom,mdss-dsc-block-prediction-enable; | |
linux,phandle = <0x1b8>; | |
phandle = <0x1b8>; | |
}; | |
config1 { | |
qcom,lm-split = <0x2d0 0x2d0>; | |
qcom,mdss-dsc-encoders = <0x1>; | |
qcom,mdss-dsc-slice-height = <0x10>; | |
qcom,mdss-dsc-slice-width = <0x2d0>; | |
qcom,mdss-dsc-slice-per-pkt = <0x2>; | |
qcom,mdss-dsc-bit-per-component = <0x8>; | |
qcom,mdss-dsc-bit-per-pixel = <0x8>; | |
qcom,mdss-dsc-block-prediction-enable; | |
}; | |
config2 { | |
qcom,lm-split = <0x2d0 0x2d0>; | |
qcom,mdss-dsc-encoders = <0x2>; | |
qcom,mdss-dsc-slice-height = <0x10>; | |
qcom,mdss-dsc-slice-width = <0x2d0>; | |
qcom,mdss-dsc-slice-per-pkt = <0x2>; | |
qcom,mdss-dsc-bit-per-component = <0x8>; | |
qcom,mdss-dsc-bit-per-pixel = <0x8>; | |
qcom,mdss-dsc-block-prediction-enable; | |
}; | |
}; | |
qcom,mdss_dsi_nt35597_dsc_wqxga_cmd { | |
qcom,mdss-dsi-panel-name = "NT35597 cmd mode dsc dsi panel"; | |
qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x5a0>; | |
qcom,mdss-dsi-panel-height = <0xa00>; | |
qcom,mdss-dsi-h-front-porch = <0x64>; | |
qcom,mdss-dsi-h-back-porch = <0x20>; | |
qcom,mdss-dsi-h-pulse-width = <0x10>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x7>; | |
qcom,mdss-dsi-v-front-porch = <0x8>; | |
qcom,mdss-dsi-v-pulse-width = <0x1>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-panel-timings = <0x110404 0x70c0404 0x3030400>; | |
qcom,mdss-dsi-t-clk-post = <0x5>; | |
qcom,mdss-dsi-t-clk-pre = <0x1b>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
qcom,mdss-pan-physical-height-dimension = <0x83>; | |
qcom,mdss-dsi-te-pin-select = <0x1>; | |
qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
qcom,mdss-dsi-te-dcs-command = <0x1>; | |
qcom,mdss-dsi-te-check-enable; | |
qcom,mdss-dsi-te-using-te-pin; | |
qcom,ulps-enabled; | |
qcom,mdss-dsi-panel-hdr-enabled; | |
qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
qcom,adjust-timer-wakeup-ms = <0x1>; | |
qcom,mdss-dsi-on-command = <0x15010000 0x2ff 0x10150100 0x2 0xfb011501 0x0 0x2ba0315 0x1000000 0x2e501 0x15010000 0x2b0 0x3150100 0x2 0xff281501 0x0 0x27a0215 0x1000000 0x2fb01 0x15010000 0x2ff 0x10150100 0x2 0xfb011501 0x0 0x2c00315 0x1000000 0x2bb10 0x15010000 0x2ff 0xe0150100 0x2 0xfb011501 0x0 0x26b3d15 0x1000000 0x26c3d 0x15010000 0x26d 0x3d150100 0x2 0x6e3d1501 0x0 0x26f3d15 0x1000000 0x23502 0x15010000 0x236 0x72150100 0x2 0x37101501 0x0 0x208c015 0x1000000 0x2ff24 0x15010000 0x2fb 0x1150100 0x2 0xc6061501 0x0 0x2ff1005 0x10000a0 0x11105 0x1000000 0x12907 0x100000a 0x20100>; | |
qcom,mdss-dsi-post-panel-on-command = <0x5010000 0xa0000129>; | |
qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00 05 01 00 00 0a 00 02 10 00]; | |
qcom,compression-mode = "dsc"; | |
qcom,config-select = <0x1b9>; | |
qcom,esd-check-enabled; | |
qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-panel-status-value = <0x9c>; | |
qcom,mdss-dsi-panel-on-check-value = <0x9c>; | |
qcom,mdss-dsi-panel-status-read-length = <0x1>; | |
qcom,mdss-dsi-panel-max-error-count = <0x3>; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
qcom,mdss-dsi-bl-min-level = <0x1>; | |
qcom,mdss-dsi-bl-max-level = <0xfff>; | |
qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; | |
qcom,panel-supply-entries = <0x1b4>; | |
config0 { | |
qcom,mdss-dsc-encoders = <0x1>; | |
qcom,mdss-dsc-slice-height = <0x10>; | |
qcom,mdss-dsc-slice-width = <0x2d0>; | |
qcom,mdss-dsc-slice-per-pkt = <0x2>; | |
qcom,mdss-dsc-bit-per-component = <0x8>; | |
qcom,mdss-dsc-bit-per-pixel = <0x8>; | |
qcom,mdss-dsc-block-prediction-enable; | |
}; | |
config1 { | |
qcom,lm-split = <0x2d0 0x2d0>; | |
qcom,mdss-dsc-encoders = <0x1>; | |
qcom,mdss-dsc-slice-height = <0x10>; | |
qcom,mdss-dsc-slice-width = <0x2d0>; | |
qcom,mdss-dsc-slice-per-pkt = <0x2>; | |
qcom,mdss-dsc-bit-per-component = <0x8>; | |
qcom,mdss-dsc-bit-per-pixel = <0x8>; | |
qcom,mdss-dsc-block-prediction-enable; | |
}; | |
config2 { | |
qcom,lm-split = <0x2d0 0x2d0>; | |
qcom,mdss-dsc-encoders = <0x2>; | |
qcom,mdss-dsc-slice-height = <0x10>; | |
qcom,mdss-dsc-slice-width = <0x2d0>; | |
qcom,mdss-dsc-slice-per-pkt = <0x2>; | |
qcom,mdss-dsc-bit-per-component = <0x8>; | |
qcom,mdss-dsc-bit-per-pixel = <0x8>; | |
qcom,mdss-dsc-block-prediction-enable; | |
linux,phandle = <0x1b9>; | |
phandle = <0x1b9>; | |
}; | |
}; | |
qcom,mdss_dsi_sharp_4k_dsc_video { | |
qcom,mdss-dsi-panel-name = "Sharp 4k video mode dsc dsi panel"; | |
qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x438>; | |
qcom,mdss-dsi-panel-height = <0xf00>; | |
qcom,mdss-dsi-h-front-porch = <0x1e>; | |
qcom,mdss-dsi-h-back-porch = <0x64>; | |
qcom,mdss-dsi-h-pulse-width = <0x4>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x7>; | |
qcom,mdss-dsi-v-front-porch = <0x8>; | |
qcom,mdss-dsi-v-pulse-width = <0x1>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-panel-timings = <0x350a0c 0x151b090d 0xa030400>; | |
qcom,mdss-dsi-t-clk-post = <0xd>; | |
qcom,mdss-dsi-t-clk-pre = <0x26>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-reset-sequence = <0x1 0x14 0x0 0x14 0x1 0x14>; | |
qcom,mdss-dsi-tx-eot-append; | |
qcom,adjust-timer-wakeup-ms = <0x1>; | |
qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 10 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
qcom,compression-mode = "dsc"; | |
qcom,config-select = <0x1ba>; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
qcom,mdss-dsi-bl-min-level = <0x1>; | |
qcom,mdss-dsi-bl-max-level = <0xfff>; | |
qcom,panel-supply-entries = <0x1b4>; | |
config0 { | |
qcom,mdss-dsc-encoders = <0x1>; | |
qcom,mdss-dsc-slice-height = <0x20>; | |
qcom,mdss-dsc-slice-width = <0x438>; | |
qcom,mdss-dsc-slice-per-pkt = <0x1>; | |
qcom,mdss-dsc-bit-per-component = <0x8>; | |
qcom,mdss-dsc-bit-per-pixel = <0x8>; | |
qcom,mdss-dsc-block-prediction-enable; | |
linux,phandle = <0x1ba>; | |
phandle = <0x1ba>; | |
}; | |
}; | |
qcom,mdss_dsi_sharp_4k_dsc_cmd { | |
qcom,mdss-dsi-panel-name = "Sharp 4k cmd mode dsc dsi panel"; | |
qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x438>; | |
qcom,mdss-dsi-panel-height = <0xf00>; | |
qcom,mdss-dsi-h-front-porch = <0x1e>; | |
qcom,mdss-dsi-h-back-porch = <0x64>; | |
qcom,mdss-dsi-h-pulse-width = <0x4>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x7>; | |
qcom,mdss-dsi-v-front-porch = <0x8>; | |
qcom,mdss-dsi-v-pulse-width = <0x1>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-panel-timings = <0x350a0c 0x151b090d 0xa030400>; | |
qcom,mdss-dsi-t-clk-post = <0xd>; | |
qcom,mdss-dsi-t-clk-pre = <0x26>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-reset-sequence = <0x1 0x14 0x0 0x14 0x1 0x14>; | |
qcom,mdss-dsi-te-pin-select = <0x1>; | |
qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
qcom,mdss-dsi-te-dcs-command = <0x1>; | |
qcom,mdss-dsi-te-check-enable; | |
qcom,mdss-dsi-te-using-te-pin; | |
qcom,ulps-enabled; | |
qcom,dcs-cmd-by-left; | |
qcom,mdss-dsi-tx-eot-append; | |
qcom,adjust-timer-wakeup-ms = <0x1>; | |
qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
qcom,compression-mode = "dsc"; | |
qcom,config-select = <0x1bb>; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
qcom,mdss-dsi-bl-min-level = <0x1>; | |
qcom,mdss-dsi-bl-max-level = <0xfff>; | |
qcom,panel-supply-entries = <0x1b4>; | |
config0 { | |
qcom,mdss-dsc-encoders = <0x1>; | |
qcom,mdss-dsc-slice-height = <0x20>; | |
qcom,mdss-dsc-slice-width = <0x438>; | |
qcom,mdss-dsc-slice-per-pkt = <0x1>; | |
qcom,mdss-dsc-bit-per-component = <0x8>; | |
qcom,mdss-dsc-bit-per-pixel = <0x8>; | |
qcom,mdss-dsc-block-prediction-enable; | |
linux,phandle = <0x1bb>; | |
phandle = <0x1bb>; | |
}; | |
}; | |
qcom,dsi_jdi_qhd_video { | |
qcom,mdss-dsi-panel-name = "Dual JDI video mode dsi panel"; | |
qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x500>; | |
qcom,mdss-dsi-panel-height = <0x5a0>; | |
qcom,mdss-dsi-h-front-porch = <0x78>; | |
qcom,mdss-dsi-h-back-porch = <0x2c>; | |
qcom,mdss-dsi-h-pulse-width = <0x10>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x4>; | |
qcom,mdss-dsi-v-front-porch = <0x8>; | |
qcom,mdss-dsi-v-pulse-width = <0x4>; | |
qcom,mdss-dsi-h-left-border = <0x0>; | |
qcom,mdss-dsi-h-right-border = <0x0>; | |
qcom,mdss-dsi-v-top-border = <0x0>; | |
qcom,mdss-dsi-v-bottom-border = <0x0>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-underflow-color = <0xff>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,cmd-sync-wait-broadcast; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-panel-timings = <0x170505 0x90f0506 0x4030400>; | |
qcom,mdss-dsi-t-clk-post = <0x6>; | |
qcom,mdss-dsi-t-clk-pre = <0x23>; | |
qcom,mdss-dsi-bl-max-level = <0xfff>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
qcom,mdss-dsi-on-command = [05 01 00 00 0a 00 01 00 15 01 00 00 0a 00 02 3a 77 39 01 00 00 0a 00 05 2a 00 00 04 ff 39 01 00 00 0a 00 05 2b 00 00 05 9f 15 01 00 00 0a 00 02 35 00 39 01 00 00 0a 00 03 44 00 00 15 01 00 00 0a 00 02 51 ff 15 01 00 00 0a 00 02 53 24 15 01 00 00 0a 00 02 55 00 05 01 00 00 78 00 01 11 23 01 00 00 0a 00 02 b0 00 29 01 00 00 0a 00 02 b3 14 29 01 00 00 0a 00 14 ce 7d 40 48 56 67 78 88 98 a7 b5 c3 d1 de e9 f2 fa ff 04 00 23 01 00 00 0a 00 02 b0 03 05 01 00 00 10 00 01 29]; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-post-mode-switch-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
qcom,mdss-dsi-post-mode-switch-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
qcom,dynamic-mode-switch-enabled; | |
qcom,dynamic-mode-switch-type = "dynamic-switch-immediate"; | |
qcom,video-to-cmd-mode-switch-commands = [23 00 00 00 00 00 02 b0 00 29 00 00 00 00 00 02 b3 0c 23 01 00 00 00 00 02 b0 03]; | |
qcom,cmd-to-video-mode-switch-commands = [23 00 00 00 00 00 02 b0 00 29 00 00 00 00 00 02 b3 1c 23 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-bl-min-level = <0x1>; | |
qcom,5v-boost-gpio = <0x7c 0x33 0x0>; | |
qcom,panel-supply-entries = <0x1b4>; | |
}; | |
qcom,mdss_dsi_jdi_qhd_dualmipi_cmd { | |
qcom,mdss-dsi-panel-name = "Dual cmd mode dsi panel"; | |
qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x500>; | |
qcom,mdss-dsi-panel-height = <0x5a0>; | |
qcom,mdss-dsi-h-front-porch = <0x78>; | |
qcom,mdss-dsi-h-back-porch = <0x2c>; | |
qcom,mdss-dsi-h-pulse-width = <0x10>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x4>; | |
qcom,mdss-dsi-v-front-porch = <0x8>; | |
qcom,mdss-dsi-v-pulse-width = <0x4>; | |
qcom,mdss-dsi-h-left-border = <0x0>; | |
qcom,mdss-dsi-h-right-border = <0x0>; | |
qcom,mdss-dsi-v-top-border = <0x0>; | |
qcom,mdss-dsi-v-bottom-border = <0x0>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
qcom,mdss-dsi-underflow-color = <0xff>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,cmd-sync-wait-broadcast; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-hor-line-idle = <0x0 0x28 0x100 0x28 0x78 0x80 0x78 0xf0 0x40>; | |
qcom,mdss-dsi-panel-timings = <0x170505 0x90f0506 0x4030400>; | |
qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
qcom,mdss-dsi-t-clk-post = <0x6>; | |
qcom,mdss-dsi-t-clk-pre = <0x23>; | |
qcom,mdss-dsi-bl-max-level = <0xfff>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-te-pin-select = <0x1>; | |
qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
qcom,mdss-dsi-te-dcs-command = <0x1>; | |
qcom,mdss-dsi-te-check-enable; | |
qcom,mdss-dsi-te-using-te-pin; | |
qcom,ulps-enabled; | |
qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-post-mode-switch-on-command = [05 01 00 00 0a 00 01 00 15 01 00 00 0a 00 02 3a 77 39 01 00 00 0a 00 05 2a 00 00 04 ff 39 01 00 00 0a 00 05 2b 00 00 05 9f 15 01 00 00 0a 00 02 35 00 39 01 00 00 0a 00 03 44 00 00 15 01 00 00 0a 00 02 51 ff 15 01 00 00 0a 00 02 53 24 15 01 00 00 0a 00 02 55 00 05 01 00 00 78 00 01 11 23 01 00 00 0a 00 02 b0 00 29 01 00 00 0a 00 02 b3 14 29 01 00 00 0a 00 14 ce 7d 40 48 56 67 78 88 98 a7 b5 c3 d1 de e9 f2 fa ff 04 00 23 01 00 00 0a 00 02 b0 03 05 01 00 00 10 00 01 29]; | |
qcom,mdss-dsi-post-mode-switch-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,dynamic-mode-switch-enabled; | |
qcom,dynamic-mode-switch-type = "dynamic-switch-immediate"; | |
qcom,mode-switch-commands-state = "dsi_hs_mode"; | |
qcom,video-to-cmd-mode-switch-commands = [23 00 00 00 00 00 02 b0 00 29 00 00 00 00 00 02 b3 0c 23 01 00 00 00 00 02 b0 03]; | |
qcom,cmd-to-video-mode-switch-commands = [23 00 00 00 00 00 02 b0 00 29 00 00 00 00 00 02 b3 1c 23 01 00 00 00 00 02 b0 03]; | |
qcom,esd-check-enabled; | |
qcom,mdss-dsi-panel-status-check-mode = "te_signal_check"; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
qcom,mdss-dsi-bl-min-level = <0x1>; | |
qcom,5v-boost-gpio = <0x7c 0x33 0x0>; | |
qcom,panel-supply-entries = <0x1b4>; | |
}; | |
qcom,mdss_dsi_sharp_1080p_cmd { | |
qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel"; | |
qcom,mdss-dsi-panel-controller = <0x1bc>; | |
qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
qcom,mdss-dsi-panel-destination = "display_1"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-panel-clockrate = <0x32a9f880>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x438>; | |
qcom,mdss-dsi-panel-height = <0x780>; | |
qcom,mdss-dsi-h-front-porch = <0x0>; | |
qcom,mdss-dsi-h-back-porch = <0x0>; | |
qcom,mdss-dsi-h-pulse-width = <0x0>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x0>; | |
qcom,mdss-dsi-v-front-porch = <0x0>; | |
qcom,mdss-dsi-v-pulse-width = <0x0>; | |
qcom,mdss-dsi-h-left-border = <0x0>; | |
qcom,mdss-dsi-h-right-border = <0x0>; | |
qcom,mdss-dsi-v-top-border = <0x0>; | |
qcom,mdss-dsi-v-bottom-border = <0x0>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-underflow-color = <0xff>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 b0 03 05 01 00 00 78 00 01 11 15 01 00 00 00 00 02 51 ff 15 01 00 00 00 00 02 53 24 15 01 00 00 00 00 02 ff 23 15 01 00 00 00 00 02 08 05 15 01 00 00 00 00 02 46 90 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 ff f0 15 01 00 00 00 00 02 92 01 15 01 00 00 00 00 02 ff 10 05 01 00 00 28 00 01 29]; | |
qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-panel-timings = <0x160505 0x90e0506 0x4030400>; | |
qcom,mdss-dsi-t-clk-post = <0x6>; | |
qcom,mdss-dsi-t-clk-pre = <0x22>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; | |
qcom,mdss-dsi-te-pin-select = <0x1>; | |
qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
qcom,mdss-dsi-te-dcs-command = <0x1>; | |
qcom,mdss-dsi-te-check-enable; | |
qcom,mdss-dsi-te-using-te-pin; | |
}; | |
qcom,mdss_dsi_jdi_1080p_video { | |
qcom,mdss-dsi-panel-name = "jdi 1080p video mode dsi panel"; | |
qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x438>; | |
qcom,mdss-dsi-panel-height = <0x780>; | |
qcom,mdss-dsi-h-front-porch = <0x60>; | |
qcom,mdss-dsi-h-back-porch = <0x40>; | |
qcom,mdss-dsi-h-pulse-width = <0x10>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x10>; | |
qcom,mdss-dsi-v-front-porch = <0x4>; | |
qcom,mdss-dsi-v-pulse-width = <0x1>; | |
qcom,mdss-dsi-h-left-border = <0x0>; | |
qcom,mdss-dsi-h-right-border = <0x0>; | |
qcom,mdss-dsi-v-top-border = <0x0>; | |
qcom,mdss-dsi-v-bottom-border = <0x0>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
qcom,mdss-dsi-underflow-color = <0xff>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 55 00 15 01 00 00 00 00 02 53 2c 15 01 00 00 00 00 02 35 00 05 01 00 00 78 00 02 29 00 05 01 00 00 78 00 02 11 00]; | |
qcom,mdss-dsi-off-command = [05 01 00 00 02 00 02 28 00 05 01 00 00 79 00 02 10 00]; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-panel-timings = <0x1a0606 0xa110507 0x5030400>; | |
qcom,mdss-dsi-t-clk-post = <0x7>; | |
qcom,mdss-dsi-t-clk-pre = <0x28>; | |
qcom,mdss-dsi-bl-min-level = <0x1>; | |
qcom,mdss-dsi-bl-max-level = <0xfff>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
qcom,mdss-pan-physical-width-dimension = <0x3d>; | |
qcom,mdss-pan-physical-heigth-dimenstion = <0x6e>; | |
qcom,mdss-dsi-tx-eot-append; | |
qcom,ulps-enabled; | |
}; | |
qcom,mdss_dual_sharp_1080p_120hz_cmd { | |
qcom,mdss-dsi-panel-name = "sharp 1080p 120hz dual dsi cmd mode panel"; | |
qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x78>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x21c>; | |
qcom,mdss-dsi-panel-height = <0x780>; | |
qcom,mdss-dsi-h-front-porch = <0x1c>; | |
qcom,mdss-dsi-h-back-porch = <0x4>; | |
qcom,mdss-dsi-h-pulse-width = <0x4>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0xc>; | |
qcom,mdss-dsi-v-front-porch = <0xc>; | |
qcom,mdss-dsi-v-pulse-width = <0x2>; | |
qcom,mdss-dsi-h-left-border = <0x0>; | |
qcom,mdss-dsi-h-right-border = <0x0>; | |
qcom,mdss-dsi-v-top-border = <0x0>; | |
qcom,mdss-dsi-v-bottom-border = <0x0>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-underflow-color = <0xff>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-reset-sequence = <0x1 0x14 0x0 0x1 0x1 0xa>; | |
qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 ba 07 15 01 00 00 00 00 02 c0 00 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 d9 00 15 01 00 00 00 00 02 ef 70 15 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 06 3b 03 0e 0c 08 1c 15 01 00 00 00 00 02 e9 0e 15 01 00 00 00 00 02 ea 0c 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 c0 00 15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 59 6a 15 01 00 00 00 00 02 0b 1b 15 01 00 00 00 00 02 61 f7 15 01 00 00 00 00 02 62 6c 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 04 c8 15 01 00 00 00 00 02 05 1a 15 01 00 00 00 00 02 0d 93 15 01 00 00 00 00 02 0e 93 15 01 00 00 00 00 02 0f 7e 15 01 00 00 00 00 02 06 69 15 01 00 00 00 00 02 07 bc 15 01 00 00 00 00 02 10 03 15 01 00 00 00 00 02 11 64 15 01 00 00 00 00 02 12 5a 15 01 00 00 00 00 02 13 40 15 01 00 00 00 00 02 14 40 15 01 00 00 00 00 02 15 00 15 01 00 00 00 00 02 33 13 15 01 00 00 00 00 02 5a 40 15 01 00 00 00 00 02 5b 40 15 01 00 00 00 00 02 5e 80 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 80 15 01 00 00 00 00 02 14 80 15 01 00 00 00 00 02 01 80 15 01 00 00 00 00 02 15 80 15 01 00 00 00 00 02 02 80 15 01 00 00 00 00 02 16 80 15 01 00 00 00 00 02 03 0a 15 01 00 00 00 00 02 17 0c 15 01 00 00 00 00 02 04 06 15 01 00 00 00 00 02 18 08 15 01 00 00 00 00 02 05 80 15 01 00 00 00 00 02 19 80 15 01 00 00 00 00 02 06 80 15 01 00 00 00 00 02 1a 80 15 01 00 00 00 00 02 07 80 15 01 00 00 00 00 02 1b 80 15 01 00 00 00 00 02 08 80 15 01 00 00 00 00 02 1c 80 15 01 00 00 00 00 02 09 80 15 01 00 00 00 00 02 1d 80 15 01 00 00 00 00 02 0a 80 15 01 00 00 00 00 02 1e 80 15 01 00 00 00 00 02 0b 1a 15 01 00 00 00 00 02 1f 1b 15 01 00 00 00 00 02 0c 16 15 01 00 00 00 00 02 20 17 15 01 00 00 00 00 02 0d 1c 15 01 00 00 00 00 02 21 1d 15 01 00 00 00 00 02 0e 18 15 01 00 00 00 00 02 22 19 15 01 00 00 00 00 02 0f 0e 15 01 00 00 00 00 02 23 10 15 01 00 00 00 00 02 10 80 15 01 00 00 00 00 02 24 80 15 01 00 00 00 00 02 11 80 15 01 00 00 00 00 02 25 80 15 01 00 00 00 00 02 12 80 15 01 00 00 00 00 02 26 80 15 01 00 00 00 00 02 13 80 15 01 00 00 00 00 02 27 80 15 01 00 00 00 00 02 74 ff 15 01 00 00 00 00 02 75 ff 15 01 00 00 00 00 02 8d 00 15 01 00 00 00 00 02 8e 00 15 01 00 00 00 00 02 8f 9c 15 01 00 00 00 00 02 90 0c 15 01 00 00 00 00 02 91 0e 15 01 00 00 00 00 02 d6 00 15 01 00 00 00 00 02 d7 20 15 01 00 00 00 00 02 d8 00 15 01 00 00 00 00 02 d9 88 15 01 00 00 00 00 02 e5 05 15 01 00 00 00 00 02 e6 10 15 01 00 00 00 00 02 54 06 15 01 00 00 00 00 02 55 05 15 01 00 00 00 00 02 56 04 15 01 00 00 00 00 02 58 03 15 01 00 00 00 00 02 59 33 15 01 00 00 00 00 02 5a 33 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5d 01 15 01 00 00 00 00 02 5e 0a 15 01 00 00 00 00 02 5f 0a 15 01 00 00 00 00 02 60 0a 15 01 00 00 00 00 02 61 0a 15 01 00 00 00 00 02 62 10 15 01 00 00 00 00 02 63 01 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 65 00 15 01 00 00 00 00 02 ef 00 15 01 00 00 00 00 02 f0 00 15 01 00 00 00 00 02 6d 20 15 01 00 00 00 00 02 66 44 15 01 00 00 00 00 02 68 01 15 01 00 00 00 00 02 69 00 15 01 00 00 00 00 02 67 11 15 01 00 00 00 00 02 6a 06 15 01 00 00 00 00 02 6b 31 15 01 00 00 00 00 02 6c 90 15 01 00 00 00 00 02 ab c3 15 01 00 00 00 00 02 b1 49 15 01 00 00 00 00 02 aa 80 15 01 00 00 00 00 02 b0 90 15 01 00 00 00 00 02 b2 a4 15 01 00 00 00 00 02 b3 00 15 01 00 00 00 00 02 b4 23 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 00 15 01 00 00 00 00 02 b7 00 15 01 00 00 00 00 02 b8 00 15 01 00 00 00 00 02 b9 00 15 01 00 00 00 00 02 ba 00 15 01 00 00 00 00 02 bb 00 15 01 00 00 00 00 02 bc 00 15 01 00 00 00 00 02 bd 00 15 01 00 00 00 00 02 be 00 15 01 00 00 00 00 02 bf 00 15 01 00 00 00 00 02 c0 00 15 01 00 00 00 00 02 c7 40 15 01 00 00 00 00 02 c9 00 15 01 00 00 00 00 02 c1 2a 15 01 00 00 00 00 02 c2 2a 15 01 00 00 00 00 02 c3 00 15 01 00 00 00 00 02 c4 00 15 01 00 00 00 00 02 c5 00 15 01 00 00 00 00 02 c6 00 15 01 00 00 00 00 02 c8 ab 15 01 00 00 00 00 02 ca 00 15 01 00 00 00 00 02 cb 00 15 01 00 00 00 00 02 cc 20 15 01 00 00 00 00 02 cd 40 15 01 00 00 00 00 02 ce a8 15 01 00 00 00 00 02 cf a8 15 01 00 00 00 00 02 d0 00 15 01 00 00 00 00 02 d1 00 15 01 00 00 00 00 02 d2 00 15 01 00 00 00 00 02 d3 00 15 01 00 00 00 00 02 af 01 15 01 00 00 00 00 02 a4 1e 15 01 00 00 00 00 02 95 41 15 01 00 00 00 00 02 96 03 15 01 00 00 00 00 02 98 00 15 01 00 00 00 00 02 9a 9a 15 01 00 00 00 00 02 9b 03 15 01 00 00 00 00 02 9d 80 15 01 00 00 00 00 02 ff 26 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 fa d0 15 01 00 00 00 00 02 6b 80 15 01 00 00 00 00 02 6c 5c 15 01 00 00 00 00 02 6d 0c 15 01 00 00 00 00 02 6e 0e 15 01 00 00 00 00 02 58 01 15 01 00 00 00 00 02 59 15 15 01 00 00 00 00 02 5a 01 15 01 00 00 00 00 02 5b 00 15 01 00 00 00 00 02 5c 01 15 01 00 00 00 00 02 5d 2b 15 01 00 00 00 00 02 74 00 15 01 00 00 00 00 02 75 ba 15 01 00 00 00 00 02 81 0a 15 01 00 00 00 00 02 4e 81 15 01 00 00 00 00 02 4f 83 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 53 4d 15 01 00 00 00 00 02 54 03 15 01 00 00 00 00 02 ff e0 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 b2 81 15 01 00 00 00 00 02 62 28 15 01 00 00 00 00 02 a2 09 15 01 00 00 00 00 02 b3 01 15 01 00 00 00 00 02 ed 00 15 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 75 00 15 01 00 00 00 00 02 76 71 15 01 00 00 00 00 02 77 00 15 01 00 00 00 00 02 78 84 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 7a a5 15 01 00 00 00 00 02 7b 00 15 01 00 00 00 00 02 7c bb 15 01 00 00 00 00 02 7d 00 15 01 00 00 00 00 02 7e ce 15 01 00 00 00 00 02 7f 00 15 01 00 00 00 00 02 80 e0 15 01 00 00 00 00 02 81 00 15 01 00 00 00 00 02 82 ef 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 84 ff 15 01 00 00 00 00 02 85 01 15 01 00 00 00 00 02 86 0b 15 01 00 00 00 00 02 87 01 15 01 00 00 00 00 02 88 38 15 01 00 00 00 00 02 89 01 15 01 00 00 00 00 02 8a 5b 15 01 00 00 00 00 02 8b 01 15 01 00 00 00 00 02 8c 95 15 01 00 00 00 00 02 8d 01 15 01 00 00 00 00 02 8e c4 15 01 00 00 00 00 02 8f 02 15 01 00 00 00 00 02 90 0d 15 01 00 00 00 00 02 91 02 15 01 00 00 00 00 02 92 4a 15 01 00 00 00 00 02 93 02 15 01 00 00 00 00 02 94 4c 15 01 00 00 00 00 02 95 02 15 01 00 00 00 00 02 96 85 15 01 00 00 00 00 02 97 02 15 01 00 00 00 00 02 98 c3 15 01 00 00 00 00 02 99 02 15 01 00 00 00 00 02 9a e9 15 01 00 00 00 00 02 9b 03 15 01 00 00 00 00 02 9c 16 15 01 00 00 00 00 02 9d 03 15 01 00 00 00 00 02 9e 34 15 01 00 00 00 00 02 9f 03 15 01 00 00 00 00 02 a0 56 15 01 00 00 00 00 02 a2 03 15 01 00 00 00 00 02 a3 62 15 01 00 00 00 00 02 a4 03 15 01 00 00 00 00 02 a5 6c 15 01 00 00 00 00 02 a6 03 15 01 00 00 00 00 02 a7 74 15 01 00 00 00 00 02 a9 03 15 01 00 00 00 00 02 aa 80 15 01 00 00 00 00 02 ab 03 15 01 00 00 00 00 02 ac 89 15 01 00 00 00 00 02 ad 03 15 01 00 00 00 00 02 ae 8b 15 01 00 00 00 00 02 af 03 15 01 00 00 00 00 02 b0 8d 15 01 00 00 00 00 02 b1 03 15 01 00 00 00 00 02 b2 8e 15 01 00 00 00 00 02 b3 00 15 01 00 00 00 00 02 b4 71 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 84 15 01 00 00 00 00 02 b7 00 15 01 00 00 00 00 02 b8 a5 15 01 00 00 00 00 02 b9 00 15 01 00 00 00 00 02 ba bb 15 01 00 00 00 00 02 bb 00 15 01 00 00 00 00 02 bc ce 15 01 00 00 00 00 02 bd 00 15 01 00 00 00 00 02 be e0 15 01 00 00 00 00 02 bf 00 15 01 00 00 00 00 02 c0 ef 15 01 00 00 00 00 02 c1 00 15 01 00 00 00 00 02 c2 ff 15 01 00 00 00 00 02 c3 01 15 01 00 00 00 00 02 c4 0b 15 01 00 00 00 00 02 c5 01 15 01 00 00 00 00 02 c6 38 15 01 00 00 00 00 02 c7 01 15 01 00 00 00 00 02 c8 5b 15 01 00 00 00 00 02 c9 01 15 01 00 00 00 00 02 ca 95 15 01 00 00 00 00 02 cb 01 15 01 00 00 00 00 02 cc c4 15 01 00 00 00 00 02 cd 02 15 01 00 00 00 00 02 ce 0d 15 01 00 00 00 00 02 cf 02 15 01 00 00 00 00 02 d0 4a 15 01 00 00 00 00 02 d1 02 15 01 00 00 00 00 02 d2 4c 15 01 00 00 00 00 02 d3 02 15 01 00 00 00 00 02 d4 85 15 01 00 00 00 00 02 d5 02 15 01 00 00 00 00 02 d6 c3 15 01 00 00 00 00 02 d7 02 15 01 00 00 00 00 02 d8 e9 15 01 00 00 00 00 02 d9 03 15 01 00 00 00 00 02 da 16 15 01 00 00 00 00 02 db 03 15 01 00 00 00 00 02 dc 34 15 01 00 00 00 00 02 dd 03 15 01 00 00 00 00 02 de 56 15 01 00 00 00 00 02 df 03 15 01 00 00 00 00 02 e0 62 15 01 00 00 00 00 02 e1 03 15 01 00 00 00 00 02 e2 6c 15 01 00 00 00 00 02 e3 03 15 01 00 00 00 00 02 e4 74 15 01 00 00 00 00 02 e5 03 15 01 00 00 00 00 02 e6 80 15 01 00 00 00 00 02 e7 03 15 01 00 00 00 00 02 e8 89 15 01 00 00 00 00 02 e9 03 15 01 00 00 00 00 02 ea 8b 15 01 00 00 00 00 02 eb 03 15 01 00 00 00 00 02 ec 8d 15 01 00 00 00 00 02 ed 03 15 01 00 00 00 00 02 ee 8e 15 01 00 00 00 00 02 ef 00 15 01 00 00 00 00 02 f0 71 15 01 00 00 00 00 02 f1 00 15 01 00 00 00 00 02 f2 84 15 01 00 00 00 00 02 f3 00 15 01 00 00 00 00 02 f4 a5 15 01 00 00 00 00 02 f5 00 15 01 00 00 00 00 02 f6 bb 15 01 00 00 00 00 02 f7 00 15 01 00 00 00 00 02 f8 ce 15 01 00 00 00 00 02 f9 00 15 01 00 00 00 00 02 fa e0 15 01 00 00 00 00 02 ff 21 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 00 15 01 00 00 00 00 02 01 ef 15 01 00 00 00 00 02 02 00 15 01 00 00 00 00 02 03 ff 15 01 00 00 00 00 02 04 01 15 01 00 00 00 00 02 05 0b 15 01 00 00 00 00 02 06 01 15 01 00 00 00 00 02 07 38 15 01 00 00 00 00 02 08 01 15 01 00 00 00 00 02 09 5b 15 01 00 00 00 00 02 0a 01 15 01 00 00 00 00 02 0b 95 15 01 00 00 00 00 02 0c 01 15 01 00 00 00 00 02 0d c4 15 01 00 00 00 00 02 0e 02 15 01 00 00 00 00 02 0f 0d 15 01 00 00 00 00 02 10 02 15 01 00 00 00 00 02 11 4a 15 01 00 00 00 00 02 12 02 15 01 00 00 00 00 02 13 4c 15 01 00 00 00 00 02 14 02 15 01 00 00 00 00 02 15 85 15 01 00 00 00 00 02 16 02 15 01 00 00 00 00 02 17 c3 15 01 00 00 00 00 02 18 02 15 01 00 00 00 00 02 19 e9 15 01 00 00 00 00 02 1a 03 15 01 00 00 00 00 02 1b 16 15 01 00 00 00 00 02 1c 03 15 01 00 00 00 00 02 1d 34 15 01 00 00 00 00 02 1e 03 15 01 00 00 00 00 02 1f 56 15 01 00 00 00 00 02 20 03 15 01 00 00 00 00 02 21 62 15 01 00 00 00 00 02 22 03 15 01 00 00 00 00 02 23 6c 15 01 00 00 00 00 02 24 03 15 01 00 00 00 00 02 25 74 15 01 00 00 00 00 02 26 03 15 01 00 00 00 00 02 27 80 15 01 00 00 00 00 02 28 03 15 01 00 00 00 00 02 29 89 15 01 00 00 00 00 02 2a 03 15 01 00 00 00 00 02 2b 8b 15 01 00 00 00 00 02 2d 03 15 01 00 00 00 00 02 2f 8d 15 01 00 00 00 00 02 30 03 15 01 00 00 00 00 02 31 8e 15 01 00 00 00 00 02 32 00 15 01 00 00 00 00 02 33 71 15 01 00 00 00 00 02 34 00 15 01 00 00 00 00 02 35 84 15 01 00 00 00 00 02 36 00 15 01 00 00 00 00 02 37 a5 15 01 00 00 00 00 02 38 00 15 01 00 00 00 00 02 39 bb 15 01 00 00 00 00 02 3a 00 15 01 00 00 00 00 02 3b ce 15 01 00 00 00 00 02 3d 00 15 01 00 00 00 00 02 3f e0 15 01 00 00 00 00 02 40 00 15 01 00 00 00 00 02 41 ef 15 01 00 00 00 00 02 42 00 15 01 00 00 00 00 02 43 ff 15 01 00 00 00 00 02 44 01 15 01 00 00 00 00 02 45 0b 15 01 00 00 00 00 02 46 01 15 01 00 00 00 00 02 47 38 15 01 00 00 00 00 02 48 01 15 01 00 00 00 00 02 49 5b 15 01 00 00 00 00 02 4a 01 15 01 00 00 00 00 02 4b 95 15 01 00 00 00 00 02 4c 01 15 01 00 00 00 00 02 4d c4 15 01 00 00 00 00 02 4e 02 15 01 00 00 00 00 02 4f 0d 15 01 00 00 00 00 02 50 02 15 01 00 00 00 00 02 51 4a 15 01 00 00 00 00 02 52 02 15 01 00 00 00 00 02 53 4c 15 01 00 00 00 00 02 54 02 15 01 00 00 00 00 02 55 85 15 01 00 00 00 00 02 56 02 15 01 00 00 00 00 02 58 c3 15 01 00 00 00 00 02 59 02 15 01 00 00 00 00 02 5a e9 15 01 00 00 00 00 02 5b 03 15 01 00 00 00 00 02 5c 16 15 01 00 00 00 00 02 5d 03 15 01 00 00 00 00 02 5e 34 15 01 00 00 00 00 02 5f 03 15 01 00 00 00 00 02 60 56 15 01 00 00 00 00 02 61 03 15 01 00 00 00 00 02 62 62 15 01 00 00 00 00 02 63 03 15 01 00 00 00 00 02 64 6c 15 01 00 00 00 00 02 65 03 15 01 00 00 00 00 02 66 74 15 01 00 00 00 00 02 67 03 15 01 00 00 00 00 02 68 80 15 01 00 00 00 00 02 69 03 15 01 00 00 00 00 02 6a 89 15 01 00 00 00 00 02 6b 03 15 01 00 00 00 00 02 6c 8b 15 01 00 00 00 00 02 6d 03 15 01 00 00 00 00 02 6e 8d 15 01 00 00 00 00 02 6f 03 15 01 00 00 00 00 02 70 8e 15 01 00 00 00 00 02 71 00 15 01 00 00 00 00 02 72 71 15 01 00 00 00 00 02 73 00 15 01 00 00 00 00 02 74 84 15 01 00 00 00 00 02 75 00 15 01 00 00 00 00 02 76 a5 15 01 00 00 00 00 02 77 00 15 01 00 00 00 00 02 78 bb 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 7a ce 15 01 00 00 00 00 02 7b 00 15 01 00 00 00 00 02 7c e0 15 01 00 00 00 00 02 7d 00 15 01 00 00 00 00 02 7e ef 15 01 00 00 00 00 02 7f 00 15 01 00 00 00 00 02 80 ff 15 01 00 00 00 00 02 81 01 15 01 00 00 00 00 02 82 0b 15 01 00 00 00 00 02 83 01 15 01 00 00 00 00 02 84 38 15 01 00 00 00 00 02 85 01 15 01 00 00 00 00 02 86 5b 15 01 00 00 00 00 02 87 01 15 01 00 00 00 00 02 88 95 15 01 00 00 00 00 02 89 01 15 01 00 00 00 00 02 8a c4 15 01 00 00 00 00 02 8b 02 15 01 00 00 00 00 02 8c 0d 15 01 00 00 00 00 02 8d 02 15 01 00 00 00 00 02 8e 4a 15 01 00 00 00 00 02 8f 02 15 01 00 00 00 00 02 90 4c 15 01 00 00 00 00 02 91 02 15 01 00 00 00 00 02 92 85 15 01 00 00 00 00 02 93 02 15 01 00 00 00 00 02 94 c3 15 01 00 00 00 00 02 95 02 15 01 00 00 00 00 02 96 e9 15 01 00 00 00 00 02 97 03 15 01 00 00 00 00 02 98 16 15 01 00 00 00 00 02 99 03 15 01 00 00 00 00 02 9a 34 15 01 00 00 00 00 02 9b 03 15 01 00 00 00 00 02 9c 56 15 01 00 00 00 00 02 9d 03 15 01 00 00 00 00 02 9e 62 15 01 00 00 00 00 02 9f 03 15 01 00 00 00 00 02 a0 6c 15 01 00 00 00 00 02 a2 03 15 01 00 00 00 00 02 a3 74 15 01 00 00 00 00 02 a4 03 15 01 00 00 00 00 02 a5 80 15 01 00 00 00 00 02 a6 03 15 01 00 00 00 00 02 a7 89 15 01 00 00 00 00 02 a9 03 15 01 00 00 00 00 02 aa 8b 15 01 00 00 00 00 02 ab 03 15 01 00 00 00 00 02 ac 8d 15 01 00 00 00 00 02 ad 03 15 01 00 00 00 00 02 ae 8e 15 01 00 00 00 00 02 af 00 15 01 00 00 00 00 02 b0 71 15 01 00 00 00 00 02 b1 00 15 01 00 00 00 00 02 b2 84 15 01 00 00 00 00 02 b3 00 15 01 00 00 00 00 02 b4 a5 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 bb 15 01 00 00 00 00 02 b7 00 15 01 00 00 00 00 02 b8 ce 15 01 00 00 00 00 02 b9 00 15 01 00 00 00 00 02 ba e0 15 01 00 00 00 00 02 bb 00 15 01 00 00 00 00 02 bc ef 15 01 00 00 00 00 02 bd 00 15 01 00 00 00 00 02 be ff 15 01 00 00 00 00 02 bf 01 15 01 00 00 00 00 02 c0 0b 15 01 00 00 00 00 02 c1 01 15 01 00 00 00 00 02 c2 38 15 01 00 00 00 00 02 c3 01 15 01 00 00 00 00 02 c4 5b 15 01 00 00 00 00 02 c5 01 15 01 00 00 00 00 02 c6 95 15 01 00 00 00 00 02 c7 01 15 01 00 00 00 00 02 c8 c4 15 01 00 00 00 00 02 c9 02 15 01 00 00 00 00 02 ca 0d 15 01 00 00 00 00 02 cb 02 15 01 00 00 00 00 02 cc 4a 15 01 00 00 00 00 02 cd 02 15 01 00 00 00 00 02 ce 4c 15 01 00 00 00 00 02 cf 02 15 01 00 00 00 00 02 d0 85 15 01 00 00 00 00 02 d1 02 15 01 00 00 00 00 02 d2 c3 15 01 00 00 00 00 02 d3 02 15 01 00 00 00 00 02 d4 e9 15 01 00 00 00 00 02 d5 03 15 01 00 00 00 00 02 d6 16 15 01 00 00 00 00 02 d7 03 15 01 00 00 00 00 02 d8 34 15 01 00 00 00 00 02 d9 03 15 01 00 00 00 00 02 da 56 15 01 00 00 00 00 02 db 03 15 01 00 00 00 00 02 dc 62 15 01 00 00 00 00 02 dd 03 15 01 00 00 00 00 02 de 6c 15 01 00 00 00 00 02 df 03 15 01 00 00 00 00 02 e0 74 15 01 00 00 00 00 02 e1 03 15 01 00 00 00 00 02 e2 80 15 01 00 00 00 00 02 e3 03 15 01 00 00 00 00 02 e4 89 15 01 00 00 00 00 02 e5 03 15 01 00 00 00 00 02 e6 8b 15 01 00 00 00 00 02 e7 03 15 01 00 00 00 00 02 e8 8d 15 01 00 00 00 00 02 e9 03 15 01 00 00 00 00 02 ea 8e 15 01 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 29]; | |
qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 05 01 00 00 10 00 01 28 15 01 00 00 00 00 02 b0 00 05 01 00 00 40 00 01 10 15 01 00 00 00 00 02 4f 01]; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,cmd-sync-wait-broadcast; | |
qcom,cmd-sync-wait-trigger; | |
qcom,mdss-tear-check-frame-rate = <0x2ee0>; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-panel-timings = <0x190506 0xa0f0506 0x5030400>; | |
qcom,mdss-dsi-t-clk-post = <0x7>; | |
qcom,mdss-dsi-t-clk-pre = <0x26>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-te-pin-select = <0x1>; | |
qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
qcom,mdss-dsi-te-dcs-command = <0x1>; | |
qcom,mdss-dsi-te-check-enable; | |
qcom,mdss-dsi-te-using-te-pin; | |
qcom,config-select = <0x1bd>; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
qcom,mdss-dsi-bl-min-level = <0x1>; | |
qcom,mdss-dsi-bl-max-level = <0xfff>; | |
qcom,panel-supply-entries = <0x1b4>; | |
config0 { | |
qcom,split-mode = "dualctl-split"; | |
linux,phandle = <0x1bd>; | |
phandle = <0x1bd>; | |
}; | |
}; | |
qcom,mdss_dsi_jdi_a407_wqhd_cmd { | |
qcom,mdss-dsi-panel-name = "JDI a407 wqhd cmd mode dsi panel"; | |
qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-panel-clockrate = <0x31fc0540>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x2d0>; | |
qcom,mdss-dsi-panel-height = <0xa00>; | |
qcom,mdss-dsi-h-front-porch = <0x10>; | |
qcom,mdss-dsi-h-back-porch = <0x28>; | |
qcom,mdss-dsi-h-pulse-width = <0x4>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x14>; | |
qcom,mdss-dsi-v-front-porch = <0x7>; | |
qcom,mdss-dsi-v-pulse-width = <0x1>; | |
qcom,mdss-dsi-h-left-border = <0x0>; | |
qcom,mdss-dsi-h-right-border = <0x0>; | |
qcom,mdss-dsi-v-top-border = <0x0>; | |
qcom,mdss-dsi-v-bottom-border = <0x0>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
qcom,mdss-dsi-underflow-color = <0xff>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 35 00 05 01 00 00 78 00 02 11 00 05 01 00 00 32 00 02 29 00]; | |
qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
qcom,mdss-dsi-bl-min-level = <0x1>; | |
qcom,mdss-dsi-bl-max-level = <0xfff>; | |
qcom,mdss-dsi-te-using-te-pin; | |
qcom,mdss-dsi-te-pin-select = <0x1>; | |
qcom,mdss-dsi-te-v-sync-rd-ptr-irq-line = <0x2c>; | |
qcom,mdss-dsi-te-dcs-command = <0x1>; | |
qcom,mdss-dsi-lp11-init; | |
qcom,adjust-timer-wakeup-ms = <0x1>; | |
qcom,mdss-dsi-reset-sequence = <0x1 0x14 0x0 0xa 0x1 0x14>; | |
qcom,dcs-cmd-by-left; | |
qcom,config-select = <0x1be>; | |
qcom,mdss-dsi-panel-timings = <0x160505 0x90e0505 0x4030400>; | |
qcom,mdss-dsi-t-clk-post = <0x6>; | |
qcom,mdss-dsi-t-clk-pre = <0x22>; | |
config0 { | |
qcom,split-mode = "dualctl-split"; | |
linux,phandle = <0x1be>; | |
phandle = <0x1be>; | |
}; | |
config1 { | |
qcom,split-mode = "pingpong-split"; | |
}; | |
}; | |
qcom,mdss_dsi_sim_cmd { | |
qcom,mdss-dsi-panel-name = "Simulator cmd mode dsi DSC panel"; | |
qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x5a0>; | |
qcom,mdss-dsi-panel-height = <0xa00>; | |
qcom,mdss-dsi-h-front-porch = <0x98>; | |
qcom,mdss-dsi-h-back-porch = <0x9c>; | |
qcom,mdss-dsi-h-pulse-width = <0x34>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0xa0>; | |
qcom,mdss-dsi-v-front-porch = <0x96>; | |
qcom,mdss-dsi-v-pulse-width = <0x64>; | |
qcom,mdss-dsi-h-left-border = <0x0>; | |
qcom,mdss-dsi-h-right-border = <0x0>; | |
qcom,mdss-dsi-v-top-border = <0x0>; | |
qcom,mdss-dsi-v-bottom-border = <0x0>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
qcom,mdss-dsi-underflow-color = <0xff>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-hor-line-idle = <0x0 0x28 0x100 0x28 0x78 0x80 0x78 0xf0 0x40>; | |
qcom,mdss-dsi-panel-timings = <0xcd322200 0x60642634 0x29030400>; | |
qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
qcom,mdss-dsi-t-clk-post = <0x3>; | |
qcom,mdss-dsi-t-clk-pre = <0x27>; | |
qcom,mdss-dsi-bl-max-level = <0xfff>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-te-pin-select = <0x1>; | |
qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
qcom,mdss-dsi-te-dcs-command = <0x1>; | |
qcom,mdss-dsi-te-check-enable; | |
qcom,mdss-dsi-te-using-te-pin; | |
qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,panel-ack-disabled; | |
qcom,ulps-enabled; | |
qcom,partial-update-enabled = "single_roi"; | |
qcom,panel-roi-alignment = <0x2d0 0x20 0x2d0 0x20 0x2d0 0x20>; | |
qcom,compression-mode = "dsc"; | |
qcom,config-select = <0x1bf>; | |
config0 { | |
qcom,lm-split = <0x2d0 0x2d0>; | |
qcom,mdss-dsc-encoders = <0x2>; | |
qcom,mdss-dsc-slice-height = <0x20>; | |
qcom,mdss-dsc-slice-width = <0x2d0>; | |
qcom,mdss-dsc-slice-per-pkt = <0x1>; | |
qcom,mdss-dsc-bit-per-component = <0x8>; | |
qcom,mdss-dsc-bit-per-pixel = <0x8>; | |
qcom,mdss-dsc-block-prediction-enable; | |
linux,phandle = <0x1bf>; | |
phandle = <0x1bf>; | |
}; | |
}; | |
qcom,mdss_dsi_dual_sim_cmd { | |
qcom,mdss-dsi-panel-name = "Sim dual cmd mode dsi panel"; | |
qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x500>; | |
qcom,mdss-dsi-panel-height = <0x5a0>; | |
qcom,mdss-dsi-h-front-porch = <0x78>; | |
qcom,mdss-dsi-h-back-porch = <0x2c>; | |
qcom,mdss-dsi-h-pulse-width = <0x10>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x4>; | |
qcom,mdss-dsi-v-front-porch = <0x8>; | |
qcom,mdss-dsi-v-pulse-width = <0x4>; | |
qcom,mdss-dsi-h-left-border = <0x0>; | |
qcom,mdss-dsi-h-right-border = <0x0>; | |
qcom,mdss-dsi-v-top-border = <0x0>; | |
qcom,mdss-dsi-v-bottom-border = <0x0>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
qcom,mdss-dsi-underflow-color = <0xff>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,cmd-sync-wait-broadcast; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-hor-line-idle = <0x0 0x28 0x100 0x28 0x78 0x80 0x78 0xf0 0x40>; | |
qcom,mdss-dsi-panel-timings = <0xcd322200 0x60642634 0x29030400>; | |
qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
qcom,mdss-dsi-t-clk-post = <0x3>; | |
qcom,mdss-dsi-t-clk-pre = <0x27>; | |
qcom,mdss-dsi-bl-max-level = <0xfff>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-te-pin-select = <0x1>; | |
qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
qcom,mdss-dsi-te-dcs-command = <0x1>; | |
qcom,mdss-dsi-te-check-enable; | |
qcom,mdss-dsi-te-using-te-pin; | |
qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,panel-ack-disabled; | |
}; | |
qcom,mdss_dsi_s6e3ha3_amoled_wqhd_cmd { | |
qcom,mdss-dsi-panel-name = "Dual s6e3ha3 amoled cmd mode dsi panel"; | |
qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x2d0>; | |
qcom,mdss-dsi-panel-height = <0xa00>; | |
qcom,mdss-dsi-h-front-porch = <0x64>; | |
qcom,mdss-dsi-h-back-porch = <0x64>; | |
qcom,mdss-dsi-h-pulse-width = <0x28>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x1f>; | |
qcom,mdss-dsi-v-front-porch = <0x1e>; | |
qcom,mdss-dsi-v-pulse-width = <0x8>; | |
qcom,mdss-dsi-h-left-border = <0x0>; | |
qcom,mdss-dsi-h-right-border = <0x0>; | |
qcom,mdss-dsi-v-top-border = <0x0>; | |
qcom,mdss-dsi-v-bottom-border = <0x0>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-underflow-color = <0xff>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
qcom,mdss-dsi-on-command = [05 01 00 00 05 00 02 11 00 39 01 00 00 00 00 05 2a 00 00 05 9f 39 01 00 00 00 00 05 2b 00 00 09 ff 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 02 b0 10 39 01 00 00 00 00 02 b5 a0 39 01 00 00 00 00 02 c4 03 39 01 00 00 00 00 0a f6 42 57 37 00 aa cc d0 00 00 39 01 00 00 00 00 02 f9 03 39 01 00 00 00 00 14 c2 00 00 d8 d8 00 80 2b 05 08 0e 07 0b 05 0d 0a 15 13 20 1e 39 01 00 00 78 00 03 f0 a5 a5 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 02 51 60 05 01 00 00 05 00 02 29 00]; | |
qcom,mdss-dsi-off-command = [05 01 00 00 3c 00 02 28 00 05 01 00 00 b4 00 02 10 00]; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-lp-mode-on = [39 00 00 00 05 00 03 f0 5a 5a 39 00 00 00 05 00 03 f1 5a 5a 39 00 00 00 05 00 03 fc 5a 5a 39 00 00 00 05 00 02 b0 17 39 00 00 00 05 00 02 cb 10 39 00 00 00 05 00 02 b0 2d 39 00 00 00 05 00 02 cb cd 39 00 00 00 05 00 02 b0 0e 39 00 00 00 05 00 02 cb 02 39 00 00 00 05 00 02 b0 0f 39 00 00 00 05 00 02 cb 09 39 00 00 00 05 00 02 b0 02 39 00 00 00 05 00 02 f2 c9 39 00 00 00 05 00 02 b0 03 39 00 00 00 05 00 02 f2 c0 39 00 00 00 05 00 02 b0 03 39 00 00 00 05 00 02 f4 aa 39 00 00 00 05 00 02 b0 08 39 00 00 00 05 00 02 b1 30 39 00 00 00 05 00 02 b0 09 39 00 00 00 05 00 02 b1 0a 39 00 00 00 05 00 02 b0 0d 39 00 00 00 05 00 02 b1 10 39 00 00 00 05 00 02 b0 00 39 00 00 00 05 00 02 f7 03 39 00 00 00 05 00 02 fe 30 39 01 00 00 05 00 02 fe b0]; | |
qcom,mdss-dsi-lp-mode-off = [39 00 00 00 05 00 03 f0 5a 5a 39 00 00 00 05 00 03 f1 5a 5a 39 00 00 00 05 00 03 fc 5a 5a 39 00 00 00 05 00 02 b0 2d 39 00 00 00 05 00 02 cb 4d 39 00 00 00 05 00 02 b0 17 39 00 00 00 05 00 02 cb 04 39 00 00 00 05 00 02 b0 0e 39 00 00 00 05 00 02 cb 06 39 00 00 00 05 00 02 b0 0f 39 00 00 00 05 00 02 cb 05 39 00 00 00 05 00 02 b0 02 39 00 00 00 05 00 02 f2 b8 39 00 00 00 05 00 02 b0 03 39 00 00 00 05 00 02 f2 80 39 00 00 00 05 00 02 b0 03 39 00 00 00 05 00 02 f4 8a 39 00 00 00 05 00 02 b0 08 39 00 00 00 05 00 02 b1 10 39 00 00 00 05 00 02 b0 09 39 00 00 00 05 00 02 b1 0a 39 00 00 00 05 00 02 b0 0d 39 00 00 00 05 00 02 b1 80 39 00 00 00 05 00 02 b0 00 39 00 00 00 05 00 02 f7 03 39 00 00 00 05 00 02 fe 30 39 01 00 00 05 00 02 fe b0]; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-tx-eot-append; | |
qcom,dcs-cmd-by-left; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
qcom,mdss-dsi-te-pin-select = <0x1>; | |
qcom,mdss-dsi-te-dcs-command = <0x1>; | |
qcom,mdss-dsi-te-check-enable; | |
qcom,mdss-dsi-te-using-te-pin; | |
qcom,mdss-dsi-panel-timings = <0x1c0606 0xb100607 0x5030400>; | |
qcom,mdss-dsi-t-clk-post = <0x7>; | |
qcom,mdss-dsi-t-clk-pre = <0x2a>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-lp11-init; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
qcom,mdss-dsi-bl-min-level = <0x1>; | |
qcom,mdss-dsi-bl-max-level = <0xff>; | |
qcom,mdss-pan-physical-width-dimension = <0x44>; | |
qcom,mdss-pan-physical-height-dimension = <0x7a>; | |
qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
}; | |
qcom,mdss_dsi_nt36850_truly_wqhd_cmd { | |
qcom,mdss-dsi-panel-name = "Dual nt36850 cmd mode dsi truly panel without DSC"; | |
qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x2d0>; | |
qcom,mdss-dsi-panel-height = <0xa00>; | |
qcom,mdss-dsi-h-front-porch = <0x78>; | |
qcom,mdss-dsi-h-back-porch = <0x8c>; | |
qcom,mdss-dsi-h-pulse-width = <0x14>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x14>; | |
qcom,mdss-dsi-v-front-porch = <0x8>; | |
qcom,mdss-dsi-v-pulse-width = <0x4>; | |
qcom,mdss-dsi-h-left-border = <0x0>; | |
qcom,mdss-dsi-h-right-border = <0x0>; | |
qcom,mdss-dsi-v-top-border = <0x0>; | |
qcom,mdss-dsi-v-bottom-border = <0x0>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
qcom,mdss-dsi-underflow-color = <0xff>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 19 15 01 00 00 00 00 02 01 03 15 01 00 00 00 00 02 02 04 15 01 00 00 00 00 02 03 1b 15 01 00 00 00 00 02 04 1d 15 01 00 00 00 00 02 05 01 15 01 00 00 00 00 02 06 0c 15 01 00 00 00 00 02 07 0f 15 01 00 00 00 00 02 08 1f 15 01 00 00 00 00 02 09 00 15 01 00 00 00 00 02 0a 00 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 16 15 01 00 00 00 00 02 0d 14 15 01 00 00 00 00 02 0e 15 15 01 00 00 00 00 02 0f 00 15 01 00 00 00 00 02 10 19 15 01 00 00 00 00 02 11 03 15 01 00 00 00 00 02 12 04 15 01 00 00 00 00 02 13 1b 15 01 00 00 00 00 02 14 1d 15 01 00 00 00 00 02 15 01 15 01 00 00 00 00 02 16 0c 15 01 00 00 00 00 02 17 0f 15 01 00 00 00 00 02 18 1f 15 01 00 00 00 00 02 19 00 15 01 00 00 00 00 02 1a 00 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 16 15 01 00 00 00 00 02 1d 14 15 01 00 00 00 00 02 1e 15 15 01 00 00 00 00 02 1f 00 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 10 15 01 00 00 00 00 02 23 28 15 01 00 00 00 00 02 24 28 15 01 00 00 00 00 02 25 5d 15 01 00 00 00 00 02 26 28 15 01 00 00 00 00 02 27 28 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 15 15 01 00 00 00 00 02 2b 00 15 01 00 00 00 00 02 2d 00 15 01 00 00 00 00 02 2f 02 15 01 00 00 00 00 02 30 02 15 01 00 00 00 00 02 31 00 15 01 00 00 00 00 02 32 23 15 01 00 00 00 00 02 33 01 15 01 00 00 00 00 02 34 03 15 01 00 00 00 00 02 35 49 15 01 00 00 00 00 02 36 00 15 01 00 00 00 00 02 37 1d 15 01 00 00 00 00 02 38 08 15 01 00 00 00 00 02 39 03 15 01 00 00 00 00 02 3a 49 15 01 00 00 00 00 02 42 01 15 01 00 00 00 00 02 43 8c 15 01 00 00 00 00 02 44 a3 15 01 00 00 00 00 02 48 8c 15 01 00 00 00 00 02 49 a3 15 01 00 00 00 00 02 5b 00 15 01 00 00 00 00 02 5f 4d 15 01 00 00 00 00 02 63 00 15 01 00 00 00 00 02 67 04 15 01 00 00 00 00 02 6e 10 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 73 00 15 01 00 00 00 00 02 74 04 15 01 00 00 00 00 02 75 1b 15 01 00 00 00 00 02 76 05 15 01 00 00 00 00 02 77 01 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 7a 00 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c da 15 01 00 00 00 00 02 7d 10 15 01 00 00 00 00 02 7e 04 15 01 00 00 00 00 02 7f 1b 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 81 05 15 01 00 00 00 00 02 82 01 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 84 05 15 01 00 00 00 00 02 85 05 15 01 00 00 00 00 02 86 1b 15 01 00 00 00 00 02 87 1b 15 01 00 00 00 00 02 88 1b 15 01 00 00 00 00 02 89 1b 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 8b f0 15 01 00 00 00 00 02 8c 00 15 01 00 00 00 00 02 8f 63 15 01 00 00 00 00 02 90 51 15 01 00 00 00 00 02 91 40 15 01 00 00 00 00 02 92 51 15 01 00 00 00 00 02 93 08 15 01 00 00 00 00 02 94 08 15 01 00 00 00 00 02 95 51 15 01 00 00 00 00 02 96 51 15 01 00 00 00 00 02 97 00 15 01 00 00 00 00 02 98 00 15 01 00 00 00 00 02 99 33 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9c 01 15 01 00 00 00 00 02 9d 30 15 01 00 00 00 00 02 a5 10 15 01 00 00 00 00 02 a6 01 15 01 00 00 00 00 02 a9 21 15 01 00 00 00 00 02 b3 2a 15 01 00 00 00 00 02 b4 da 15 01 00 00 00 00 02 ba 83 15 01 00 00 00 00 02 c4 24 15 01 00 00 00 00 02 c5 aa 15 01 00 00 00 00 02 c6 09 15 01 00 00 00 00 02 c7 00 15 01 00 00 00 00 02 c9 c0 15 01 00 00 00 00 02 ca 04 15 01 00 00 00 00 02 d5 3f 15 01 00 00 00 00 02 d6 10 15 01 00 00 00 00 02 d7 3f 15 01 00 00 00 00 02 d8 10 15 01 00 00 00 00 02 d9 ee 15 01 00 00 00 00 02 da 49 15 01 00 00 00 00 02 db 94 15 01 00 00 00 00 02 e9 33 15 01 00 00 00 00 02 eb 28 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ee 00 15 01 00 00 00 00 02 ef 06 15 01 00 00 00 00 02 f0 01 15 01 00 00 00 00 02 f1 01 15 01 00 00 00 00 02 f2 0d 15 01 00 00 00 00 02 f3 48 15 01 00 00 00 00 02 f6 00 15 01 00 00 00 00 02 f7 00 15 01 00 00 00 00 02 f8 00 15 01 00 00 00 00 02 f9 00 15 01 00 00 00 00 02 ff 26 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 ab 15 01 00 00 00 00 02 01 00 15 01 00 00 00 00 02 02 80 15 01 00 00 00 00 02 03 08 15 01 00 00 00 00 02 04 01 15 01 00 00 00 00 02 05 32 15 01 00 00 00 00 02 06 4c 15 01 00 00 00 00 02 07 26 15 01 00 00 00 00 02 08 09 15 01 00 00 00 00 02 09 02 15 01 00 00 00 00 02 0a 32 15 01 00 00 00 00 02 0b 55 15 01 00 00 00 00 02 0c 14 15 01 00 00 00 00 02 0d 28 15 01 00 00 00 00 02 0e 00 15 01 00 00 00 00 02 0f 00 15 01 00 00 00 00 02 10 00 15 01 00 00 00 00 02 11 22 15 01 00 00 00 00 02 12 0a 15 01 00 00 00 00 02 13 20 15 01 00 00 00 00 02 14 06 15 01 00 00 00 00 02 15 00 15 01 00 00 00 00 02 16 40 15 01 00 00 00 00 02 19 43 15 01 00 00 00 00 02 1a 03 15 01 00 00 00 00 02 1b 25 15 01 00 00 00 00 02 1c 11 15 01 00 00 00 00 02 1d 00 15 01 00 00 00 00 02 1e 80 15 01 00 00 00 00 02 1f 00 15 01 00 00 00 00 02 20 00 15 01 00 00 00 00 02 21 03 15 01 00 00 00 00 02 22 22 15 01 00 00 00 00 02 23 25 15 01 00 00 00 00 02 24 00 15 01 00 00 00 00 02 25 a7 15 01 00 00 00 00 02 26 00 15 01 00 00 00 00 02 27 a5 15 01 00 00 00 00 02 28 06 15 01 00 00 00 00 02 29 85 15 01 00 00 00 00 02 2a 3f 15 01 00 00 00 00 02 2b 97 15 01 00 00 00 00 02 2f 25 15 01 00 00 00 00 02 30 26 15 01 00 00 00 00 02 31 41 15 01 00 00 00 00 02 32 04 15 01 00 00 00 00 02 33 04 15 01 00 00 00 00 02 34 2b 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 36 00 15 01 00 00 00 00 02 37 c8 15 01 00 00 00 00 02 38 26 15 01 00 00 00 00 02 39 25 15 01 00 00 00 00 02 3a 26 15 01 00 00 00 00 02 3f eb 15 01 00 00 00 00 02 41 21 15 01 00 00 00 00 02 42 03 15 01 00 00 00 00 02 43 00 15 01 00 00 00 00 02 44 11 15 01 00 00 00 00 02 45 00 15 01 00 00 00 00 02 46 00 15 01 00 00 00 00 02 47 00 15 01 00 00 00 00 02 48 00 15 01 00 00 00 00 02 49 03 15 01 00 00 00 00 02 4a 00 15 01 00 00 00 00 02 4b 00 15 01 00 00 00 00 02 4c 01 15 01 00 00 00 00 02 4d 4e 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 4c 15 01 00 00 00 00 02 50 0d 15 01 00 00 00 00 02 51 0e 15 01 00 00 00 00 02 52 23 15 01 00 00 00 00 02 53 97 15 01 00 00 00 00 02 54 4b 15 01 00 00 00 00 02 55 4c 15 01 00 00 00 00 02 56 20 15 01 00 00 00 00 02 58 04 15 01 00 00 00 00 02 59 04 15 01 00 00 00 00 02 5a 09 15 01 00 00 00 00 02 5b 00 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5d c8 15 01 00 00 00 00 02 5e 4c 15 01 00 00 00 00 02 5f 4b 15 01 00 00 00 00 02 60 00 15 01 00 00 00 00 02 80 2b 15 01 00 00 00 00 02 81 43 15 01 00 00 00 00 02 82 03 15 01 00 00 00 00 02 83 25 15 01 00 00 00 00 02 84 11 15 01 00 00 00 00 02 85 00 15 01 00 00 00 00 02 86 80 15 01 00 00 00 00 02 87 00 15 01 00 00 00 00 02 88 00 15 01 00 00 00 00 02 89 03 15 01 00 00 00 00 02 8a 22 15 01 00 00 00 00 02 8b 25 15 01 00 00 00 00 02 8c 00 15 01 00 00 00 00 02 8d a4 15 01 00 00 00 00 02 8e 00 15 01 00 00 00 00 02 8f a2 15 01 00 00 00 00 02 90 06 15 01 00 00 00 00 02 91 63 15 01 00 00 00 00 02 92 30 15 01 00 00 00 00 02 93 97 15 01 00 00 00 00 02 94 25 15 01 00 00 00 00 02 95 26 15 01 00 00 00 00 02 96 41 15 01 00 00 00 00 02 97 04 15 01 00 00 00 00 02 98 04 15 01 00 00 00 00 02 99 f0 15 01 00 00 00 00 02 9a 00 15 01 00 00 00 00 02 9b 00 15 01 00 00 00 00 02 9c c8 15 01 00 00 00 00 02 9d 50 15 01 00 00 00 00 02 9e 26 15 01 00 00 00 00 02 9f 25 15 01 00 00 00 00 02 a0 26 15 01 00 00 00 00 02 a2 00 15 01 00 00 00 00 02 a3 33 15 01 00 00 00 00 02 a5 40 15 01 00 00 00 00 02 a6 40 15 01 00 00 00 00 02 ac 91 15 01 00 00 00 00 02 ad 66 15 01 00 00 00 00 02 ae 66 15 01 00 00 00 00 02 b1 40 15 01 00 00 00 00 02 b2 40 15 01 00 00 00 00 02 b4 40 15 01 00 00 00 00 02 b5 40 15 01 00 00 00 00 02 b7 40 15 01 00 00 00 00 02 b8 40 15 01 00 00 00 00 02 ba 22 15 01 00 00 00 00 02 bb 00 15 01 00 00 00 00 02 c2 01 15 01 00 00 00 00 02 c3 01 15 01 00 00 00 00 02 c4 01 15 01 00 00 00 00 02 c5 01 15 01 00 00 00 00 02 c6 01 15 01 00 00 00 00 02 c8 00 15 01 00 00 00 00 02 c9 00 15 01 00 00 00 00 02 ca 00 15 01 00 00 00 00 02 cd 00 15 01 00 00 00 00 02 ce 00 15 01 00 00 00 00 02 d6 04 15 01 00 00 00 00 02 d7 00 15 01 00 00 00 00 02 d8 0d 15 01 00 00 00 00 02 d9 00 15 01 00 00 00 00 02 da 00 15 01 00 00 00 00 02 db 00 15 01 00 00 00 00 02 dc 00 15 01 00 00 00 00 02 dd 00 15 01 00 00 00 00 02 de 00 15 01 00 00 00 00 02 df 01 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 e1 00 15 01 00 00 00 00 02 e2 19 15 01 00 00 00 00 02 e3 04 15 01 00 00 00 00 02 e4 00 15 01 00 00 00 00 02 e5 04 15 01 00 00 00 00 02 e6 00 15 01 00 00 00 00 02 e7 12 15 01 00 00 00 00 02 e8 00 15 01 00 00 00 00 02 e9 50 15 01 00 00 00 00 02 ea 10 15 01 00 00 00 00 02 eb 02 15 01 00 00 00 00 02 ff 27 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 ff 28 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 60 0a 15 01 00 00 00 00 02 63 32 15 01 00 00 00 00 02 64 01 15 01 00 00 00 00 02 68 da 15 01 00 00 00 00 02 69 00 15 01 00 00 00 00 02 ff 29 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 60 0a 15 01 00 00 00 00 02 63 32 15 01 00 00 00 00 02 64 01 15 01 00 00 00 00 02 68 da 15 01 00 00 00 00 02 69 00 15 01 00 00 00 00 02 ff e0 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 35 40 15 01 00 00 00 00 02 36 40 15 01 00 00 00 00 02 37 00 15 01 00 00 00 00 02 89 c6 15 01 00 00 00 00 02 ff f0 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 ea 40 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 36 00 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 03 44 03 e8 15 01 00 00 00 00 02 51 ff 15 01 00 00 00 00 02 53 2c 15 01 00 00 00 00 02 55 01 05 01 00 00 0a 00 02 20 00 15 01 00 00 00 00 02 bb 10 05 01 00 00 78 00 02 11 00 05 01 00 00 14 00 02 29 00]; | |
qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-tx-eot-append; | |
qcom,cmd-sync-wait-broadcast; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
qcom,mdss-dsi-te-pin-select = <0x1>; | |
qcom,mdss-dsi-te-dcs-command = <0x1>; | |
qcom,mdss-dsi-te-check-enable; | |
qcom,mdss-dsi-te-using-te-pin; | |
qcom,mdss-dsi-panel-timings = <0x1c0606 0xb110607 0x5030400>; | |
qcom,mdss-dsi-t-clk-pre = <0x2a>; | |
qcom,mdss-dsi-t-clk-post = <0x34>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-lp11-init; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
qcom,mdss-dsi-bl-min-level = <0x1>; | |
qcom,mdss-dsi-bl-max-level = <0xfff>; | |
qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
}; | |
}; | |
qcom,mdss_dsi@0 { | |
compatible = "qcom,mdss-dsi"; | |
#address-cells = <0x1>; | |
#size-cells = <0x1>; | |
gdsc-supply = <0x2a>; | |
vdda-1p2-supply = <0x67>; | |
vdda-0p9-supply = <0x66>; | |
ranges = <0xc994000 0xc994000 0x400 0xc994400 0xc994400 0x7c0 0xc828000 0xc828000 0xac 0xc996000 0xc996000 0x400 0xc996400 0xc996400 0x7c0 0xc828000 0xc828000 0xac>; | |
qcom,msm-bus,name = "mdss_dsi"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x16 0x200 0x0 0x0 0x16 0x200 0x0 0x3e8>; | |
qcom,mmss-ulp-clamp-ctrl-offset = <0x14>; | |
clocks = <0x27 0x43539b0e 0x27 0x49a394f4 0x27 0x85d37ab5 0x27 0xdf04fc1d 0x27 0xea30b0e7 0x27 0xfb32f31e 0x27 0x585ef6d4 0x27 0x87c1612 0x27 0x8067c5a3>; | |
clock-names = "mdp_core_clk", "mnoc_clk", "iface_clk", "bus_clk", "core_mmss_clk", "ext_byte0_clk", "ext_byte1_clk", "ext_pixel0_clk", "ext_pixel1_clk"; | |
hw-config = "single_dsi"; | |
qcom,core-supply-entries { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
qcom,core-supply-entry@0 { | |
reg = <0x0>; | |
qcom,supply-name = "gdsc"; | |
qcom,supply-min-voltage = <0x0>; | |
qcom,supply-max-voltage = <0x0>; | |
qcom,supply-enable-load = <0x0>; | |
qcom,supply-disable-load = <0x0>; | |
qcom,supply-lp-mode-disable-allowed; | |
}; | |
}; | |
qcom,ctrl-supply-entries { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
qcom,ctrl-supply-entry@0 { | |
reg = <0x0>; | |
qcom,supply-name = "vdda-1p2"; | |
qcom,supply-min-voltage = <0x124f80>; | |
qcom,supply-max-voltage = <0x124f80>; | |
qcom,supply-enable-load = <0x3110>; | |
qcom,supply-disable-load = <0x4>; | |
}; | |
}; | |
qcom,phy-supply-entries { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
qcom,phy-supply-entry@0 { | |
reg = <0x0>; | |
qcom,supply-name = "vdda-0p9"; | |
qcom,supply-min-voltage = <0xd6d80>; | |
qcom,supply-max-voltage = <0xd6d80>; | |
qcom,supply-enable-load = <0x11eb8>; | |
qcom,supply-disable-load = <0x20>; | |
qcom,supply-lp-mode-disable-allowed; | |
}; | |
}; | |
qcom,mdss_dsi_ctrl0@c994000 { | |
pinctrl-names = "mdss_default", "mdss_sleep"; | |
pinctrl-0 = <0x1c0 0x1c1>; | |
pinctrl-1 = <0x1c2 0x1c3>; | |
compatible = "qcom,mdss-dsi-ctrl"; | |
label = "MDSS DSI CTRL->0"; | |
cell-index = <0x0>; | |
reg = <0xc994000 0x400 0xc994400 0x7c0 0xc828000 0xac>; | |
reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys"; | |
qcom,timing-db-mode; | |
wqhd-vddio-supply = <0x68>; | |
lab-supply = <0x1c4>; | |
ibb-supply = <0x1c5>; | |
qcom,mdss-mdp = <0x1c6>; | |
qcom,mdss-fb-map = <0x1c7>; | |
qcom,null-insertion-enabled; | |
clocks = <0x27 0x38105d25 0x27 0xcc0e909d 0x27 0x5721ff83 0x27 0x75cc885b 0x27 0xccac1f35 0x27 0x38e5aa79>; | |
clock-names = "byte_clk", "pixel_clk", "core_clk", "byte_clk_rcg", "pixel_clk_rcg", "byte_intf_clk"; | |
qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; | |
qcom,platform-lane-config = <0x0 0x0 0x0 0x0 0x80>; | |
qcom,dsi-pref-prim-pan = <0x1c8>; | |
qcom,platform-reset-gpio = <0x7c 0x5e 0x0>; | |
qcom,platform-te-gpio = <0x7c 0xa 0x0>; | |
linux,phandle = <0x1bc>; | |
phandle = <0x1bc>; | |
}; | |
qcom,mdss_dsi_ctrl1@c996000 { | |
compatible = "qcom,mdss-dsi-ctrl"; | |
label = "MDSS DSI CTRL->1"; | |
cell-index = <0x1>; | |
reg = <0xc996000 0x400 0xc996400 0x7c0 0xc828000 0xac>; | |
reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys"; | |
qcom,timing-db-mode; | |
wqhd-vddio-supply = <0x68>; | |
lab-supply = <0x1c4>; | |
ibb-supply = <0x1c5>; | |
qcom,mdss-mdp = <0x1c6>; | |
qcom,mdss-fb-map = <0x1c7>; | |
qcom,null-insertion-enabled; | |
clocks = <0x27 0xe0c21354 0x27 0x850d9146 0x27 0xc3d0376b 0x27 0x63c2c955 0x27 0x90f68ac 0x27 0xcf654d8e>; | |
clock-names = "byte_clk", "pixel_clk", "core_clk", "byte_clk_rcg", "pixel_clk_rcg", "byte_intf_clk"; | |
qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; | |
qcom,platform-lane-config = <0x0 0x0 0x0 0x0 0x80>; | |
status = "disabled"; | |
}; | |
}; | |
qcom,mdss_wb_panel { | |
compatible = "qcom,mdss_wb"; | |
qcom,mdss_pan_res = <0x280 0x1e0>; | |
qcom,mdss_pan_bpp = <0x18>; | |
qcom,mdss-fb-map = <0x1c9>; | |
}; | |
qcom,msm_ext_disp { | |
compatible = "qcom,msm-ext-disp"; | |
linux,phandle = <0x1ca>; | |
phandle = <0x1ca>; | |
qcom,msm-ext-disp-audio-codec-rx { | |
compatible = "qcom,msm-ext-disp-audio-codec-rx"; | |
qcom,msm_ext_disp = <0x1ca>; | |
linux,phandle = <0x274>; | |
phandle = <0x274>; | |
}; | |
}; | |
qcom,dp_ctrl@c990000 { | |
cell-index = <0x0>; | |
compatible = "qcom,mdss-dp"; | |
qcom,mdss-fb-map = <0x1cb>; | |
gdsc-supply = <0x2a>; | |
vdda-1p2-supply = <0x67>; | |
vdda-0p9-supply = <0x66>; | |
reg = <0xc990000 0xa84 0xc011000 0x910 0x1fcb200 0x50 0xc8c2200 0x1a0 0x780000 0x621c 0xc9e1000 0x2c>; | |
reg-names = "dp_ctrl", "dp_phy", "tcsr_regs", "dp_mmss_cc", "qfprom_physical", "hdcp_physical"; | |
clocks = <0x27 0x49a394f4 0x27 0x85d37ab5 0x27 0xdf04fc1d 0x27 0x43539b0e 0x27 0x5448519f 0x27 0x23125eb6 0x38 0xb867b147 0x38 0xb6cc8f00 0x27 0x8dd302d1 0x27 0x70e386e6 0x27 0x9a072d4e 0x27 0xb707b765 0x5b 0x3f8197c2 0x5b 0xb5cfc6a8 0x5b 0xe0da19c0>; | |
clock-names = "core_mnoc_clk", "core_iface_clk", "core_bus_clk", "core_mdp_core_clk", "core_alt_iface_clk", "core_aux_clk", "core_ref_clk_src", "core_ref_clk", "ctrl_link_clk", "ctrl_link_iface_clk", "ctrl_crypto_clk", "ctrl_pixel_clk", "pixel_parent", "pixel_clk_two_div", "pixel_clk_four_div"; | |
qcom,dp-usbpd-detection = <0x86>; | |
qcom,msm_ext_disp = <0x1ca>; | |
qcom,aux-cfg0-settings = [1c 00]; | |
qcom,aux-cfg1-settings = <0x2013231d>; | |
qcom,aux-cfg2-settings = [24 00]; | |
qcom,aux-cfg3-settings = [28 00]; | |
qcom,aux-cfg4-settings = [2c 0a]; | |
qcom,aux-cfg5-settings = [30 26]; | |
qcom,aux-cfg6-settings = [34 0a]; | |
qcom,aux-cfg7-settings = [38 03]; | |
qcom,aux-cfg8-settings = [3c bb]; | |
qcom,aux-cfg9-settings = [40 03]; | |
qcom,logical2physical-lane-map = <0x2030100>; | |
linux,phandle = <0x1b2>; | |
phandle = <0x1b2>; | |
qcom,core-supply-entries { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
qcom,core-supply-entry@0 { | |
reg = <0x0>; | |
qcom,supply-name = "gdsc"; | |
qcom,supply-min-voltage = <0x0>; | |
qcom,supply-max-voltage = <0x0>; | |
qcom,supply-enable-load = <0x0>; | |
qcom,supply-disable-load = <0x0>; | |
}; | |
}; | |
qcom,ctrl-supply-entries { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
qcom,ctrl-supply-entry@0 { | |
reg = <0x0>; | |
qcom,supply-name = "vdda-1p2"; | |
qcom,supply-min-voltage = <0x124f80>; | |
qcom,supply-max-voltage = <0x124f80>; | |
qcom,supply-enable-load = <0x3110>; | |
qcom,supply-disable-load = <0x4>; | |
}; | |
}; | |
qcom,phy-supply-entries { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
qcom,phy-supply-entry@0 { | |
reg = <0x0>; | |
qcom,supply-name = "vdda-0p9"; | |
qcom,supply-min-voltage = <0xd6d80>; | |
qcom,supply-max-voltage = <0xd6d80>; | |
qcom,supply-enable-load = <0x11eb8>; | |
qcom,supply-disable-load = <0x20>; | |
}; | |
}; | |
}; | |
qcom,mdss_rotator { | |
compatible = "qcom,sde_rotator"; | |
reg = <0xc900000 0xab100 0xc9b8000 0x1040>; | |
reg-names = "mdp_phys", "rot_vbif_phys"; | |
qcom,mdss-rot-mode = <0x1>; | |
qcom,mdss-highest-bank-bit = <0x2>; | |
qcom,msm-bus,name = "mdss_rotator"; | |
qcom,msm-bus,num-cases = <0x3>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x19 0x200 0x0 0x0 0x19 0x200 0x0 0x61a800 0x19 0x200 0x0 0x61a800>; | |
rot-vdd-supply = <0x2a>; | |
qcom,supply-names = "rot-vdd"; | |
clocks = <0x27 0x49a394f4 0x27 0x85d37ab5 0x27 0xce49b56c 0x27 0xbb7e71c4 0x27 0xdf04fc1d>; | |
clock-names = "mnoc_clk", "iface_clk", "rot_core_clk", "rot_clk", "axi_clk"; | |
interrupt-parent = <0x1c6>; | |
interrupts = <0x2 0x0>; | |
qcom,mdss-rot-vbif-qos-setting = <0x1 0x1 0x1 0x1>; | |
qcom,mdss-default-ot-rd-limit = <0x20>; | |
qcom,mdss-default-ot-wr-limit = <0x20>; | |
qcom,smmu_rot_unsec_cb { | |
compatible = "qcom,smmu_sde_rot_unsec"; | |
iommus = <0xd4 0xe00>; | |
gdsc-mdss-supply = <0x28>; | |
clocks = <0x38 0xdb4b31e6 0x27 0x49a394f4 0x27 0x4825baf4 0x27 0xc365ac39>; | |
clock-names = "mmss_noc_axi_clk", "mmss_noc_ahb_clk", "mmss_smmu_ahb_clk", "mmss_smmu_axi_clk"; | |
}; | |
qcom,smmu_rot_sec_cb { | |
compatible = "qcom,smmu_sde_rot_sec"; | |
iommus = <0xd4 0xe01>; | |
gdsc-mdss-supply = <0x28>; | |
clocks = <0x38 0xdb4b31e6 0x27 0x49a394f4 0x27 0x4825baf4 0x27 0xc365ac39>; | |
clock-names = "mmss_noc_axi_clk", "mmss_noc_ahb_clk", "mmss_smmu_ahb_clk", "mmss_smmu_axi_clk"; | |
}; | |
}; | |
qcom,hdmi_tx@c9a0000 { | |
cell-index = <0x0>; | |
compatible = "qcom,hdmi-tx"; | |
reg = <0xc9a0000 0x50c 0x780000 0x621c 0xc9e0000 0x28>; | |
reg-names = "core_physical", "qfprom_physical", "hdcp_physical"; | |
hpd-gdsc-supply = <0x2a>; | |
qcom,supply-names = "hpd-gdsc"; | |
qcom,min-voltage-level = <0x0>; | |
qcom,max-voltage-level = <0x0>; | |
qcom,enable-load = <0x0>; | |
qcom,disable-load = <0x0>; | |
qcom,msm_ext_disp = <0x1ca>; | |
clocks = <0x27 0x49a394f4 0x27 0x85d37ab5 0x27 0x28460a6d 0x27 0x43539b0e 0x27 0x5448519f 0x27 0x74d5a954>; | |
clock-names = "hpd_mnoc_clk", "hpd_iface_clk", "hpd_core_clk", "hpd_mdp_core_clk", "hpd_alt_iface_clk", "core_extp_clk"; | |
qcom,mdss-fb-map = <0x1cc>; | |
qcom,pluggable; | |
status = "disabled"; | |
pinctrl-names = "hdmi_hpd_active", "hdmi_ddc_active", "hdmi_cec_active", "hdmi_active", "hdmi_sleep"; | |
pinctrl-0 = <0x1cd 0x1ce 0x1cf 0x1d0>; | |
pinctrl-1 = <0x1cd 0x1ce 0x1d1 0x1d0>; | |
pinctrl-2 = <0x1cd 0x1ce 0x1d2 0x1cf>; | |
pinctrl-3 = <0x1cd 0x1ce 0x1d1 0x1d2>; | |
pinctrl-4 = <0x1d3 0x1d4 0x1cf 0x1d0>; | |
linux,phandle = <0x1b1>; | |
phandle = <0x1b1>; | |
}; | |
qcom,mdss_dsi_jdi_fhd_r63452_cmd { | |
qcom,mdss-dsi-panel-name = "jdi fhd cmd incell dsi panel"; | |
qcom,mdss-dsi-panel-id = <0x0>; | |
qcom,mdss-dsi-panel-model = "JDI FHD R63452 CMD PANEL"; | |
qcom,mdss-dsi-panel-sleepwrmod = <0x0>; | |
qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x438>; | |
qcom,mdss-dsi-panel-height = <0x780>; | |
qcom,mdss-dsi-h-front-porch = <0x78>; | |
qcom,mdss-dsi-h-back-porch = <0x28>; | |
qcom,mdss-dsi-h-pulse-width = <0x10>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x4>; | |
qcom,mdss-dsi-v-front-porch = <0x4>; | |
qcom,mdss-dsi-v-pulse-width = <0x2>; | |
qcom,mdss-dsi-h-left-border = <0x0>; | |
qcom,mdss-dsi-h-right-border = <0x0>; | |
qcom,mdss-dsi-v-top-border = <0x0>; | |
qcom,mdss-dsi-v-bottom-border = <0x0>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-color-order = <0x0>; | |
qcom,mdss-dsi-underflow-color = <0xff>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-on-command = <0x29000000 0x2b0 0x290000 0x2 0xd6012900 0x0 0xeec64dc 0xec3b5200 0xb0b1315 0x680bb529 0x0 0x2b003 0x39000000 0x235 0x390000 0x2 0x36003900 0x0 0x23a7739 0x0 0x52a00 0x43739 0x0 0x52b00 0x77f39 0x0 0x34400 0x390000 0x2 0x51ff3900 0x0 0x2532439 0x0 0x25500 0x39000000 0x25e 0x390000 0x2 0x84000501 0x1400 0x2290005 0x1000050 0x21100 0x29000000 0x2b0 0x4390000 0x2 0x84002900 0x0 0x2c81129 0x1000000 0x2b003>; | |
qcom,mdss-dsi-off-command = [29 00 00 00 00 00 02 b0 00 29 00 00 00 00 00 02 d6 01 29 00 00 00 00 00 0e ec 64 dc ec 3b 52 00 0b 0b 13 15 68 0b 95 29 00 00 00 00 00 02 b0 03 05 01 00 00 02 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
qcom,mdss-dsi-displayoff-command = [05 01 00 00 20 00 02 28 00]; | |
qcom,mdss-dsi-displayon-command = [05 01 00 00 20 00 02 29 00]; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-displayoff-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-displayon-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-lp11-init; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-panel-timings = <0x1a0706 0xa110707 0x5030400>; | |
qcom,mdss-dsi-t-clk-post = <0x7>; | |
qcom,mdss-dsi-t-clk-pre = <0x28>; | |
qcom,mdss-dsi-bl-min-level = <0x1>; | |
qcom,mdss-dsi-bl-max-level = <0xfff>; | |
qcom,mdss-brightness-max-level = <0xfff>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0x1 0x1 0xa>; | |
qcom,mdss-pan-physical-width-dimension = <0x40>; | |
qcom,mdss-pan-physical-height-dimension = <0x72>; | |
qcom,mdss-dsi-te-pin-select = <0x1>; | |
qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
qcom,mdss-dsi-te-dcs-command = <0x1>; | |
qcom,mdss-dsi-te-check-enable; | |
qcom,mdss-dsi-te-using-te-pin; | |
qcom,mdss-dsi-tx-eot-append; | |
qcom,mdss-panel-on-dimming-delay = <0x78>; | |
qcom,dispblnotify-enabled; | |
qcom,dispccbb-enabled; | |
qcom,dispparam-enabled; | |
qcom,mdss-night-brightness = <0x7 0x19 0x2b 0x3d>; | |
qcom,mdss-dsi-dispparam-cabcon-command = <0x29010000 0x2b0 0x4150100 0x2 0x55812901 0x0 0x8b88951 0xd000200 0x290100 0x1a 0xce55404c 0x5a697784 0x93a2b1c1 0xd1e0f0f1 0xf2ff0400 0x4044200 0x695a2901 0x0 0xaf9663f 0xe0be008d 0xbf800029 0x1000000 0x2b003>; | |
qcom,mdss-dsi-dispparam-cabcguion-command = <0x29010000 0x2b0 0x4150100 0x2 0x55812901 0x0 0x8b88951 0xd000200 0x290100 0x1a 0xce55404c 0x5a697784 0x93a2b1c1 0xd1e0f0f1 0xf2ff0400 0x4044200 0x695a2901 0x0 0xaf9663f 0xe0be008d 0xbf800029 0x1000000 0x2b003>; | |
qcom,mdss-dsi-dispparam-cabcstillon-command = <0x29010000 0x2b0 0x4150100 0x2 0x55822901 0x0 0x8b9ff27 0x37000400 0x290100 0x1a 0xce55404c 0x5a697784 0x93a2b1c1 0xd1e0f0f1 0xf2ff0400 0x4044200 0x695a2901 0x0 0xaf9663f 0xe0be008d 0xbf800029 0x1000000 0x2b003>; | |
qcom,mdss-dsi-dispparam-cabcmovieon-command = <0x29010000 0x2b0 0x4150100 0x2 0x55832901 0x0 0x8babb3d 0x22000300 0x290100 0x1a 0xce55404c 0x5a697784 0x93a2b1c1 0xd1e0f0f1 0xf2ff0400 0x4044200 0x695a2901 0x0 0xaf9663f 0xe0be008d 0xbf800029 0x1000000 0x2b003>; | |
qcom,mdss-dsi-dispparam-cabcoff-command = [39 01 00 00 01 00 02 55 00]; | |
qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 2c]; | |
qcom,mdss-dsi-dispparam-idleon-command = [39 01 00 00 01 00 02 39 00]; | |
qcom,mdss-dsi-dispparam-idleoff-command = [39 01 00 00 01 00 02 38 00]; | |
qcom,mdss-dsi-dispparam-warm-command = [29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 80 29 01 00 00 00 00 32 c8 01 00 fb 05 fd fc e0 00 fa 02 f6 fc f0 00 f8 ff ed fc 01 00 fa 05 f9 bc 00 fa 02 f4 eb 00 fb fe ec fc 00 fa 05 fc fc 00 f9 03 f6 db 00 fa 00 f6 ab 29 01 00 00 00 00 02 ca 1c 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-warm-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-cold-command = [29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 7f 29 01 00 00 00 00 32 c8 01 00 fb 05 fd fc e0 00 fa 02 f6 fc f0 00 f8 ff ed fc 01 00 fa 05 f9 bc 00 fa 02 f4 eb 00 fb fe ec fc 00 fa 05 fc fc 00 f9 03 f6 db 00 fa 00 f6 ab 29 01 00 00 00 00 02 ca 1c 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-cold-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-default-command = [29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 00 29 01 00 00 00 00 02 c8 11 29 01 00 00 00 00 02 ca 1c 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-default-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-papermode-command = [29 01 00 00 00 00 02 55 80 29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 00 29 01 00 00 00 00 14 c8 01 00 f4 07 fc e3 f3 00 f6 04 f7 fc f2 00 fd ff 02 00 12 29 01 00 00 00 00 2c ca 1d fc fc 48 00 00 d3 00 00 d3 00 00 d3 00 00 d3 00 00 d3 00 00 d3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-papermode-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-papermode1-command = [29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 00 29 01 00 00 00 00 32 c8 01 00 f8 07 fb d7 f1 00 f8 01 f7 fc f1 00 f6 01 f2 c0 02 00 f9 05 01 59 00 f8 01 f9 b1 00 f7 fe ed fc 00 f9 06 fc ed 00 f8 01 f7 fc 00 f7 01 f6 82 29 01 00 00 00 00 02 ca 1c 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-papermode1-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-papermode2-command = [29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 00 29 01 00 00 00 00 32 c8 01 00 fc 03 f8 fc 00 00 fc ff f5 bb 00 00 02 ff f9 76 00 00 fc 03 f8 fc 00 fc ff f5 bb 00 02 ff f9 76 00 fc 03 f8 fc 00 fc ff f5 bb 00 02 ff f9 76 29 01 00 00 00 00 02 ca 1c 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-papermode2-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-papermode3-command = [29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 00 29 01 00 00 00 00 32 c8 01 00 fc 03 f8 fc 00 00 fb ff f6 aa 00 00 fe 01 fa 4b 00 00 fc 03 f8 fc 00 fb ff f6 aa 00 fe 01 fa 4b 00 fc 03 f8 fc 00 fb ff f6 aa 00 fe 01 fa 4b 29 01 00 00 00 00 02 ca 1c 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-papermode3-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-papermode4-command = [29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 00 29 01 00 00 00 00 32 c8 01 00 fc 03 f8 fc 00 00 fd ff f7 9a 00 00 03 01 fc 27 00 00 fc 03 f8 fc 00 fd ff f7 9a 00 03 01 fc 27 00 fc 03 f8 fc 00 fd ff f7 9a 00 03 01 fc 27 29 01 00 00 00 00 02 ca 1c 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-papermode4-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-papermode5-command = [29 01 00 00 00 00 02 55 80 29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 00 29 01 00 00 00 00 14 c8 01 00 f4 08 fb d5 f3 00 f5 04 f7 fc f1 00 fd ff 02 00 22 29 01 00 00 00 00 2c ca 1d fc fc e4 00 00 fa 00 00 fa 00 00 fa 00 00 fa 00 00 fa 00 00 fa 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-papermode5-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-papermode6-command = [29 01 00 00 00 00 02 55 80 29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 00 29 01 00 00 00 00 14 c8 01 00 f4 08 fb db f2 00 f6 04 f7 fc f3 00 fd ff 02 00 22 29 01 00 00 00 00 2c ca 1d fc fc b0 00 00 ed 00 00 ed 00 00 ed 00 00 ed 00 00 ed 00 00 ed 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-papermode6-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-papermode7-command = [29 01 00 00 00 00 02 55 80 29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 00 29 01 00 00 00 00 14 c8 01 00 f4 08 fc df f2 00 f6 04 f7 fc f1 00 fd ff 02 00 12 29 01 00 00 00 00 2c ca 1d fc fc 7c 00 00 e0 00 00 e0 00 00 e0 00 00 e0 00 00 e0 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-papermode7-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-normal1-command = [29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 00 29 01 00 00 00 00 32 c8 01 00 fd fe fc d8 00 00 fc fe fb dc 00 00 01 f3 f0 fc 00 00 fe fd f9 99 00 fe fc fb c8 00 ff f4 eb fc 00 fe fa fd fc 00 fe fb fa e5 00 ff f6 f2 d3 29 01 00 00 00 00 02 ca 1c 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-normal1-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-normal2-command = [29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 00 29 01 00 00 00 00 02 c8 11 29 01 00 00 00 00 02 ca 1c 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-normal2-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-srgb-command = <0x5010000 0x10000211 0x290100 0x2 0xb0002901 0x0 0x2d60129 0x1000000 0x13c801 0xfdfefc 0xfc0000fc 0xfefbfc00 0x1f3f0 0xfc290100 0x2 0xca1d2901 0x0 0x2840029 0x1000000 0x2b003>; | |
qcom,mdss-dsi-dispparam-srgb-command-state = "dsi_hs_mode"; | |
qcom,panel-supply-entries = <0x1b4>; | |
linux,phandle = <0x1c8>; | |
phandle = <0x1c8>; | |
}; | |
qcom,mdss_dsi_lgd_fhd_td4322_cmd { | |
qcom,mdss-dsi-panel-name = "lgd fhd cmd incell dsi panel"; | |
qcom,mdss-dsi-panel-id = <0x1>; | |
qcom,mdss-dsi-panel-model = "LGD FHD TD4322 CMD PANEL"; | |
qcom,mdss-dsi-panel-sleepwrmod = <0x0>; | |
qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x438>; | |
qcom,mdss-dsi-panel-height = <0x780>; | |
qcom,mdss-dsi-h-front-porch = <0x78>; | |
qcom,mdss-dsi-h-back-porch = <0x28>; | |
qcom,mdss-dsi-h-pulse-width = <0x10>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x4>; | |
qcom,mdss-dsi-v-front-porch = <0x4>; | |
qcom,mdss-dsi-v-pulse-width = <0x2>; | |
qcom,mdss-dsi-h-left-border = <0x0>; | |
qcom,mdss-dsi-h-right-border = <0x0>; | |
qcom,mdss-dsi-v-top-border = <0x0>; | |
qcom,mdss-dsi-v-bottom-border = <0x0>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-color-order = <0x0>; | |
qcom,mdss-dsi-underflow-color = <0xff>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-on-command = <0x15000000 0x251 0xff150000 0x2 0x53241500 0x0 0x2550015 0x0 0x23500 0x39010000 0x530 0x2a7 0x5010000 0x46000211 0x50100 0x140002 0x29002900 0x0 0x2b00439 0x0 0x28400 0x29000000 0x2c8 0x11290000 0x2 0xca1c2900 0x0 0x2ea0f29 0x1000000 0x2b003>; | |
qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
qcom,mdss-dsi-displayoff-command = [05 01 00 00 20 00 02 28 00]; | |
qcom,mdss-dsi-displayon-command = [05 01 00 00 20 00 02 29 00]; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-displayoff-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-displayon-command-state = "dsi_hs_mode"; | |
qcom,esd-check-enabled; | |
qcom,mdss-dsi-panel-status-check-mode = "reg_multi_read"; | |
qcom,mdss-dsi-panel-status-command = [06 01 00 00 00 00 02 0a 1c 06 01 00 00 00 00 02 eb 00]; | |
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-panel-mcap-off-cmds = [29 01 00 00 00 00 02 b0 00]; | |
qcom,mdss-dsi-panel-mcap-on-cmds = [29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-panel-mcap-off-cmds-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-panel-mcap-on-cmds-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-tx-eot-append; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-lp11-init; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-panel-timings = <0x1a0706 0xa110707 0x5030400>; | |
qcom,mdss-dsi-t-clk-post = <0x7>; | |
qcom,mdss-dsi-t-clk-pre = <0x28>; | |
qcom,mdss-dsi-bl-min-level = <0x1>; | |
qcom,mdss-dsi-bl-max-level = <0xfff>; | |
qcom,mdss-brightness-max-level = <0xfff>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
qcom,mdss-dsi-reset-sequence = <0x0 0x1 0x1 0x14>; | |
qcom,mdss-pan-physical-width-dimension = <0x40>; | |
qcom,mdss-pan-physical-height-dimension = <0x72>; | |
qcom,mdss-dsi-te-pin-select = <0x1>; | |
qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
qcom,mdss-dsi-te-dcs-command = <0x1>; | |
qcom,mdss-dsi-te-check-enable; | |
qcom,mdss-dsi-te-using-te-pin; | |
qcom,mdss-panel-on-dimming-delay = <0x78>; | |
qcom,dispblnotify-enabled; | |
qcom,dispccbb-enabled; | |
qcom,dispparam-enabled; | |
qcom,mdss-night-brightness = <0x7 0x19 0x2b 0x3d>; | |
qcom,mdss-dsi-dispparam-cabcon-command = <0x29010000 0x2b0 0x4150100 0x2 0x55812901 0x0 0x8b88951 0xd000200 0x290100 0x1a 0xce55404c 0x5a697784 0x93a2b1c1 0xd1e0f0f1 0xf2ff0400 0x4044200 0x695a2901 0x0 0xaf9663f 0xe0be008d 0xbf800029 0x1000000 0x2b003>; | |
qcom,mdss-dsi-dispparam-cabcguion-command = <0x29010000 0x2b0 0x4150100 0x2 0x55812901 0x0 0x8b88951 0xd000200 0x290100 0x1a 0xce55404c 0x5a697784 0x93a2b1c1 0xd1e0f0f1 0xf2ff0400 0x4044200 0x695a2901 0x0 0xaf9663f 0xe0be008d 0xbf800029 0x1000000 0x2b003>; | |
qcom,mdss-dsi-dispparam-cabcstillon-command = <0x29010000 0x2b0 0x4150100 0x2 0x55822901 0x0 0x8b9ff27 0x37000400 0x290100 0x1a 0xce55404c 0x5a697784 0x93a2b1c1 0xd1e0f0f1 0xf2ff0400 0x4044200 0x695a2901 0x0 0xaf9663f 0xe0be008d 0xbf800029 0x1000000 0x2b003>; | |
qcom,mdss-dsi-dispparam-cabcmovieon-command = <0x29010000 0x2b0 0x4150100 0x2 0x55832901 0x0 0x8babb3d 0x22000300 0x290100 0x1a 0xce55404c 0x5a697784 0x93a2b1c1 0xd1e0f0f1 0xf2ff0400 0x4044200 0x695a2901 0x0 0xaf9663f 0xe0be008d 0xbf800029 0x1000000 0x2b003>; | |
qcom,mdss-dsi-dispparam-cabcoff-command = [39 01 00 00 01 00 02 55 00]; | |
qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 2c]; | |
qcom,mdss-dsi-dispparam-idleon-command = [39 01 00 00 01 00 02 39 00]; | |
qcom,mdss-dsi-dispparam-idleoff-command = [39 01 00 00 01 00 02 38 00]; | |
qcom,mdss-dsi-dispparam-warm-command = [29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 80 29 01 00 00 00 00 38 c8 01 00 11 04 0a fc f0 00 0e 01 07 fc f0 00 10 01 01 fc 00 00 0e 04 02 be f0 00 0d 01 05 db f0 00 10 01 01 fc 00 00 11 04 0a fc f0 00 0e 00 06 e0 f0 00 10 01 01 b9 00 29 01 00 00 00 00 02 ca 1c 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-warm-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-cold-command = [29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 7f 29 01 00 00 00 00 38 c8 01 00 11 04 0a fc f0 00 0e 01 07 fc f0 00 10 01 01 fc 00 00 0e 04 02 be f0 00 0d 01 05 db f0 00 10 01 01 fc 00 00 11 04 0a fc f0 00 0e 00 06 e0 f0 00 10 01 01 b9 00 29 01 00 00 00 00 02 ca 1c 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-cold-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-default-command = [29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 00 29 01 00 00 00 00 02 c8 11 29 01 00 00 00 00 02 ca 1c 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-default-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-papermode-command = [29 01 00 00 00 00 02 55 80 29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 00 29 01 00 00 00 00 14 c8 01 00 ff 01 ff fc 00 00 fd ff ff f9 00 00 fe 01 fb 00 00 29 01 00 00 00 00 2c ca 1d fc fc 50 00 00 d5 00 00 d5 00 00 d5 00 00 d5 00 00 d5 00 00 d5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-papermode-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-papermode1-command = [29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 00 29 01 00 00 00 00 14 c8 01 00 ff 01 02 fc 00 00 fa 01 ff f7 00 00 fe 01 fa c2 00 29 01 00 00 00 00 02 ca 1c 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-papermode1-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-papermode2-command = [29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 00 29 01 00 00 00 00 32 c8 01 00 fc 03 f8 fc 00 00 fc ff f5 bb 00 00 02 ff f9 76 00 00 fc 03 f8 fc 00 fc ff f5 bb 00 02 ff f9 76 00 fc 03 f8 fc 00 fc ff f5 bb 00 02 ff f9 76 29 01 00 00 00 00 02 ca 1c 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-papermode2-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-papermode3-command = [29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 00 29 01 00 00 00 00 32 c8 01 00 fc 03 f8 fc 00 00 fb ff f6 aa 00 00 fe 01 fa 4b 00 00 fc 03 f8 fc 00 fb ff f6 aa 00 fe 01 fa 4b 00 fc 03 f8 fc 00 fb ff f6 aa 00 fe 01 fa 4b 29 01 00 00 00 00 02 ca 1c 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-papermode3-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-papermode4-command = [29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 00 29 01 00 00 00 00 32 c8 01 00 fc 03 f8 fc 00 00 fd ff f7 9a 00 00 03 01 fc 27 00 00 fc 03 f8 fc 00 fd ff f7 9a 00 03 01 fc 27 00 fc 03 f8 fc 00 fd ff f7 9a 00 03 01 fc 27 29 01 00 00 00 00 02 ca 1c 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-papermode4-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-papermode5-command = [29 01 00 00 00 00 02 55 80 29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 00 29 01 00 00 00 00 14 c8 01 00 ff 01 ff fc 00 00 f9 01 fe f8 00 00 fe 01 fc 00 00 29 01 00 00 00 00 2c ca 1d fc fc e4 00 00 fa 00 00 fa 00 00 fa 00 00 fa 00 00 fa 00 00 fa 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-papermode5-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-papermode6-command = [29 01 00 00 00 00 02 55 80 29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 00 29 01 00 00 00 00 14 c8 01 00 ff 01 ff fc 00 00 f9 01 fe f8 00 00 fe 01 fc 00 00 29 01 00 00 00 00 2c ca 1d fc fc c4 00 00 f2 00 00 f2 00 00 f2 00 00 f2 00 00 f2 00 00 f2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-papermode6-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-papermode7-command = [29 01 00 00 00 00 02 55 80 29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 00 29 01 00 00 00 00 14 c8 01 00 ff 01 ff fc 00 00 fd ff ff f9 00 00 fe 01 fb 00 00 29 01 00 00 00 00 2c ca 1d fc fc 84 00 00 e2 00 00 e2 00 00 e2 00 00 e2 00 00 e2 00 00 e2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-papermode7-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-normal1-command = [29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 00 29 01 00 00 00 00 38 c8 01 00 11 04 0a fc f0 00 0e 01 07 fc f0 00 10 01 01 fc 00 00 0e 04 02 be f0 00 0d 01 05 db f0 00 10 01 01 fc 00 00 11 04 0a fc f0 00 0e 00 06 e0 f0 00 10 01 01 b9 00 29 01 00 00 00 00 02 ca 1c 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-normal1-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-normal2-command = [29 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 02 84 00 29 01 00 00 00 00 02 c8 11 29 01 00 00 00 00 02 ca 1c 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-normal2-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-srgb-command = [05 01 00 00 10 00 02 11 00 29 01 00 00 00 00 02 b0 00 29 01 00 00 00 00 02 84 00 29 01 00 00 00 00 02 c8 00 29 01 00 00 00 00 02 ca 1d 29 01 00 00 00 00 02 b0 03]; | |
qcom,mdss-dsi-dispparam-srgb-command-state = "dsi_hs_mode"; | |
qcom,panel-supply-entries = <0x1d5>; | |
}; | |
qcom,mdss_dsi_lgd_sw43401_wqhd_cmd { | |
qcom,mdss-dsi-panel-name = "lgd sw43401 cmd wqhd oled panel"; | |
qcom,mdss-dsi-panel-sleepwrmod = <0x0>; | |
qcom,mdss-dsi-panel-id = <0x4>; | |
qcom,mdss-dsi-panel-model = "LGD SW43401 WQHD DSC CMD"; | |
qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x5a0>; | |
qcom,mdss-dsi-panel-height = <0xa00>; | |
qcom,mdss-dsi-h-front-porch = <0x90>; | |
qcom,mdss-dsi-h-back-porch = <0x90>; | |
qcom,mdss-dsi-h-pulse-width = <0x40>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x30>; | |
qcom,mdss-dsi-v-front-porch = <0x28>; | |
qcom,mdss-dsi-v-pulse-width = <0x8>; | |
qcom,mdss-dsi-h-left-border = <0x0>; | |
qcom,mdss-dsi-h-right-border = <0x0>; | |
qcom,mdss-dsi-v-top-border = <0x0>; | |
qcom,mdss-dsi-v-bottom-border = <0x0>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-color-order = <0x0>; | |
qcom,mdss-dsi-underflow-color = <0xff>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 b0 5a 39 01 00 00 00 00 06 f3 13 01 07 00 31 05 01 00 00 78 00 02 11 00 39 01 00 00 00 00 03 51 00 00 15 01 00 00 00 00 02 53 20 15 01 00 00 00 00 02 55 00 05 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 b0 5a 15 01 00 00 00 00 02 b2 5d 39 01 00 00 00 00 03 b3 00 00 05 01 00 00 05 00 02 29 00]; | |
qcom,mdss-dsi-off-command = [05 01 00 00 02 00 02 28 00 05 01 00 00 80 00 02 10 00]; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-lp11-init; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-panel-timings = <0x180505 0x90f0506 0x4030400>; | |
qcom,mdss-dsi-t-clk-post = <0x5>; | |
qcom,mdss-dsi-t-clk-pre = <0x1b>; | |
qcom,mdss-dsi-bl-min-level = <0x1>; | |
qcom,mdss-dsi-bl-max-level = <0xff>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0x1 0x1 0x19>; | |
qcom,mdss-pan-physical-width-dimension = <0x44>; | |
qcom,mdss-pan-physical-height-dimension = <0x79>; | |
qcom,mdss-dsi-hor-line-idle = <0x0 0x5a0 0x200>; | |
qcom,mdss-dsi-tx-eot-append; | |
qcom,esd-check-enabled; | |
qcom,mdss-dsi-panel-status-check-mode = "reg_multi_read"; | |
qcom,mdss-dsi-panel-status-command = [06 01 00 00 00 00 02 0a 9c]; | |
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-panel-orientation = "180"; | |
qcom,panel-supply-entries = <0x1d6>; | |
qcom,dispparam-enabled; | |
qcom,mdss-dsi-aod-mode; | |
qcom,mdss-dsi-aodon-command = [05 01 00 00 00 00 02 28 00 39 01 00 00 00 00 03 51 00 00 15 01 00 00 00 00 02 53 20 15 01 00 00 01 00 02 b0 5a 15 01 00 00 01 00 02 b1 8e 39 01 00 00 00 00 08 e1 00 63 03 83 0f 00 00 39 01 00 00 00 00 0a e2 06 d2 f4 80 80 80 5c 5c 5c 39 01 00 00 00 00 04 e5 91 e0 91 39 01 00 00 3c 00 08 e9 26 02 06 82 02 06 82 15 01 00 00 00 00 02 b8 26 05 01 00 00 05 00 02 29 00]; | |
qcom,mdss-dsi-aodon-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-aodoff-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 64 00 02 10 00 15 01 00 00 00 00 02 b0 5a 39 01 00 00 00 00 06 f3 13 01 07 00 31 05 01 00 00 78 00 02 11 00 39 01 00 00 00 00 03 51 00 00 15 01 00 00 00 00 02 53 20 15 01 00 00 00 00 02 55 0c 05 01 00 00 78 00 02 35 00 15 01 00 00 01 00 02 b0 5a 15 01 00 00 01 00 02 b2 5d 39 01 00 00 00 00 03 b3 00 00 05 01 00 00 05 00 02 29 00]; | |
qcom,mdss-dsi-aodoff-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-vr-on-command = [15 01 00 00 00 00 02 b0 5a 39 01 00 00 00 00 04 e8 0e 11 06 39 01 00 00 00 00 08 e9 26 27 f0 30 27 f0 30 39 01 00 00 00 00 03 51 ff c0]; | |
qcom,mdss-dsi-vr-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-vr-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 64 00 02 10 00 15 01 00 00 00 00 02 b0 5a 39 01 00 00 00 00 06 f3 13 01 07 00 31 05 01 00 00 78 00 02 11 00 39 01 00 00 00 00 03 51 64 00 15 01 00 00 00 00 02 53 20 15 01 00 00 00 00 02 55 0c 05 01 00 00 78 00 02 35 00 15 01 00 00 01 00 02 b0 5a 15 01 00 00 01 00 02 b2 5d 39 01 00 00 00 00 03 b3 00 00 05 01 00 00 05 00 02 29 00]; | |
qcom,mdss-dsi-vr-off-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-te-pin-select = <0x1>; | |
qcom,mdss-dsi-te-dcs-command = <0x1>; | |
qcom,mdss-dsi-te-check-enable; | |
qcom,mdss-dsi-te-using-te-pin; | |
qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
qcom,compression-mode = "dsc"; | |
qcom,config-select = <0x1d7>; | |
config0 { | |
qcom,lm-split = <0x2d0 0x2d0>; | |
qcom,mdss-dsc-encoders = <0x2>; | |
qcom,mdss-dsc-slice-height = <0x500>; | |
qcom,mdss-dsc-slice-width = <0x2d0>; | |
qcom,mdss-dsc-slice-per-pkt = <0x2>; | |
qcom,mdss-dsc-bit-per-component = <0x8>; | |
qcom,mdss-dsc-bit-per-pixel = <0x8>; | |
qcom,mdss-dsc-block-prediction-enable; | |
linux,phandle = <0x1d7>; | |
phandle = <0x1d7>; | |
}; | |
}; | |
qcom,mdss_dsi_lgd_ea8151a_wqhd_cmd { | |
qcom,mdss-dsi-panel-name = "lgd ea8151a cmd wqhd oled panel"; | |
qcom,mdss-dsi-panel-sleepwrmod = <0x0>; | |
qcom,mdss-dsi-panel-id = <0x4>; | |
qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x5a0>; | |
qcom,mdss-dsi-panel-height = <0xa00>; | |
qcom,mdss-dsi-h-front-porch = <0x64>; | |
qcom,mdss-dsi-h-back-porch = <0x44>; | |
qcom,mdss-dsi-h-pulse-width = <0x10>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0xc>; | |
qcom,mdss-dsi-v-front-porch = <0xc>; | |
qcom,mdss-dsi-v-pulse-width = <0x8>; | |
qcom,mdss-dsi-h-left-border = <0x0>; | |
qcom,mdss-dsi-h-right-border = <0x0>; | |
qcom,mdss-dsi-v-top-border = <0x0>; | |
qcom,mdss-dsi-v-bottom-border = <0x0>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-color-order = <0x0>; | |
qcom,mdss-dsi-underflow-color = <0xff>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-on-command = <0x39010000 0x500037f 0x5a5a1501 0x0 0x2020115 0x1000000 0x23501 0x15010000 0x236 0x2150100 0x2 0x51001501 0x0 0x2532015 0x1000000 0x25706 0x15010000 0x25a 0x1050100 0x780002 0x11003901 0x0 0x3f05a5a 0x39010000 0x59ea 0x11000089 0x30800a00 0x5a00010 0x2d002d0 0x2000268 0x2001bb 0xa000c 0x66704c5 0x180010f0 0x30c2000 0x60b0b33 0xe1c2a38 0x46546269 0x7077797b 0x7d7e0102 0x1000940 0x9be19fc 0x19fa19f8 0x1a381a78 0x1ab62af6 0x2b342b74 0x3b746bf4 0x39010000 0x3f0 0x5a5a3901 0x0 0x3f15a5a 0x39010000 0x3f2 0x5a5a1501 0x0 0x2b00515 0x1000000 0x2e603 0x15010000 0x2b0 0xb390100 0x3 0xe3a92a39 0x1000000 0x3f25a 0x5a150100 0x2 0xb0041501 0x0 0x2e51105 0x1000000 0x22900>; | |
qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 80 00 02 10 00]; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-vr-on-command = [39 01 00 00 00 00 03 7f 5a 5a 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 03 f1 5a 5a 39 01 00 00 00 00 03 f2 5a 5a 15 01 00 00 00 00 02 bf b0 15 01 00 00 00 00 02 b0 0f 39 01 00 00 00 00 03 bf c9 90 15 01 00 00 00 00 02 51 01]; | |
qcom,mdss-dsi-vr-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-vr-off-command = [39 01 00 00 00 00 03 7f 5a 5a 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 03 f1 5a 5a 39 01 00 00 00 00 03 f2 5a 5a 15 01 00 00 00 00 02 bf b3 39 01 00 00 00 00 03 7f 5a 5a]; | |
qcom,mdss-dsi-vr-off-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-lp11-init; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-panel-timings = <0x1c0704 0x7140407 0x3030400>; | |
qcom,mdss-dsi-t-clk-post = <0x5>; | |
qcom,mdss-dsi-t-clk-pre = <0x1b>; | |
qcom,mdss-dsi-bl-min-level = <0x4>; | |
qcom,mdss-dsi-bl-max-level = <0xfe>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0x1 0x1 0x19>; | |
qcom,mdss-pan-physical-width-dimension = <0x44>; | |
qcom,mdss-pan-physical-height-dimension = <0x79>; | |
qcom,mdss-dsi-tx-eot-append; | |
qcom,esd-err-irq-gpio = <0x7c 0x34 0x2001>; | |
qcom,mdss-dsi-panel-orientation = "180"; | |
qcom,panel-supply-entries = <0x1d6>; | |
qcom,dispparam-enabled; | |
qcom,mdss-dsi-aod-mode; | |
qcom,mdss-dsi-aodon-command = [05 01 00 00 00 00 02 28 00 39 01 00 00 00 00 03 7f 5a 5a 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 03 f1 5a 5a 39 01 00 00 00 00 03 f2 5a 5a 39 01 00 00 00 00 02 b0 0b 39 01 00 00 00 00 02 c2 80 05 01 00 00 00 00 02 39 00 15 01 00 00 00 00 02 b0 19 15 01 00 00 00 00 02 e5 1f 39 01 00 00 00 00 06 e1 cc 14 14 24 24 15 01 00 00 00 00 02 51 00 05 01 00 00 05 00 02 29 00]; | |
qcom,mdss-dsi-aodon-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-aodoff-command = [05 01 00 00 00 00 02 28 00 39 01 00 00 05 00 03 7f 5a 5a 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 03 f1 5a 5a 39 01 00 00 00 00 03 f2 5a 5a 39 01 00 00 00 00 02 b0 0b 39 01 00 00 00 00 02 c2 40 05 01 00 00 00 00 02 38 00 39 01 00 00 00 00 02 b0 19 39 01 00 00 00 00 02 e5 00 39 01 00 00 00 00 06 e1 cc 14 14 0c 0a 15 01 00 00 00 00 02 51 00 05 01 00 00 40 00 02 29 00]; | |
qcom,mdss-dsi-aodoff-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-aod-byteclk = <0x1f9c800>; | |
qcom,mdss-dsi-aod-pclk = <0x2a26000>; | |
qcom,mdss-dsi-te-pin-select = <0x1>; | |
qcom,mdss-dsi-te-dcs-command = <0x1>; | |
qcom,mdss-dsi-te-check-enable; | |
qcom,mdss-dsi-te-using-te-pin; | |
qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
qcom,compression-mode = "dsc"; | |
qcom,config-select = <0x1d8>; | |
config0 { | |
qcom,lm-split = <0x2d0 0x2d0>; | |
qcom,mdss-dsc-encoders = <0x2>; | |
qcom,mdss-dsc-slice-height = <0x10>; | |
qcom,mdss-dsc-slice-width = <0x2d0>; | |
qcom,mdss-dsc-slice-per-pkt = <0x2>; | |
qcom,mdss-dsc-bit-per-component = <0x8>; | |
qcom,mdss-dsc-bit-per-pixel = <0x8>; | |
qcom,mdss-dsc-block-prediction-enable; | |
linux,phandle = <0x1d8>; | |
phandle = <0x1d8>; | |
}; | |
}; | |
qcom,mdss_dsi_jdi_fhd_nt35596s_video { | |
qcom,mdss-dsi-panel-name = "jdi fhd video dsi panel"; | |
qcom,mdss-dsi-panel-id = <0x0>; | |
qcom,mdss-dsi-panel-model = "JDI FHD NT35596S VIDEO PANEL"; | |
qcom,mdss-dsi-panel-sleepwrmod = <0x0>; | |
qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x438>; | |
qcom,mdss-dsi-panel-height = <0x870>; | |
qcom,mdss-dsi-h-front-porch = <0x10>; | |
qcom,mdss-dsi-h-back-porch = <0x28>; | |
qcom,mdss-dsi-h-pulse-width = <0x1c>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x18>; | |
qcom,mdss-dsi-v-front-porch = <0x7>; | |
qcom,mdss-dsi-v-pulse-width = <0x4>; | |
qcom,mdss-dsi-h-left-border = <0x0>; | |
qcom,mdss-dsi-h-right-border = <0x0>; | |
qcom,mdss-dsi-v-top-border = <0x0>; | |
qcom,mdss-dsi-v-bottom-border = <0x0>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-color-order = <0x0>; | |
qcom,mdss-dsi-underflow-color = <0x0>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-on-command = <0x15010000 0x2ff 0x24150000 0x2 0x9d341500 0x0 0x2fb0115 0x0 0x2c425 0x15000000 0x2d1 0x8150000 0x2 0xd2841501 0x0 0x2ff2615 0x0 0x2fb01 0x15000000 0x203 0x1c150000 0x2 0x3b081500 0x0 0x26b0815 0x0 0x29708 0x15000000 0x2c5 0x8150000 0x2 0xfb011501 0x0 0x2ff2315 0x0 0x2fb01 0x15000000 0x201 0x84150000 0x2 0x52d1500 0x0 0x2060015 0x0 0x23307 0x15000000 0x221 0xee150000 0x2 0x22ed1500 0x0 0x223ea15 0x0 0x224e8 0x15000000 0x225 0xe5150000 0x2 0x26e21500 0x0 0x227de15 0x0 0x228bb 0x15000000 0x229 0x87150000 0x2 0x2a771501 0x0 0x2320c15 0x0 0x2133f 0x15000000 0x214 0x34150000 0x2 0x152a1500 0x0 0x2162515 0x0 0x2179d 0x15000000 0x218 0x9a150000 0x2 0x19971500 0x0 0x21a9415 0x0 0x21b91 0x15000000 0x21c 0x8e150000 0x2 0x1d8b1500 0x0 0x21e8915 0x0 0x21f86 0x15000000 0x220 0x83150100 0x2 0xff221500 0x0 0x2000a15 0x0 0x20143 0x15000000 0x202 0x5b150000 0x2 0x36a1500 0x0 0x2047a15 0x0 0x20582 0x15000000 0x206 0x85150000 0x2 0x7801500 0x0 0x2087c15 0x0 0x2097c 0x15000000 0x20a 0x74150000 0x2 0xb711500 0x0 0x20c6e15 0x0 0x20d68 0x15000000 0x20e 0x65150100 0x2 0xf5c1500 0x0 0x2103215 0x0 0x21118 0x15000000 0x212 0x150000 0x2 0x13001500 0x0 0x21a0015 0x0 0x21b00 0x15000000 0x21c 0x150000 0x2 0x1d001500 0x0 0x21e0015 0x0 0x21f00 0x15000000 0x220 0x150000 0x2 0x21001500 0x0 0x2220015 0x0 0x22300 0x15000000 0x224 0x150100 0x2 0x25001500 0x0 0x2260015 0x0 0x22700 0x15000000 0x228 0x150000 0x2 0x29001500 0x0 0x22a0015 0x0 0x22b00 0x15000000 0x22f 0x150000 0x2 0x30001500 0x0 0x2310015 0x0 0x2320c 0x15000000 0x233 0xc150000 0x2 0x340c1500 0x0 0x2350b15 0x0 0x23609 0x15000000 0x237 0x9150100 0x2 0x38081500 0x0 0x2390515 0x0 0x23a03 0x15000000 0x23b 0x150000 0x2 0x3f001500 0x0 0x2400015 0x0 0x24100 0x15000000 0x242 0x150000 0x2 0x43001500 0x0 0x2440015 0x0 0x24500 0x15000000 0x246 0x150000 0x2 0x47001500 0x0 0x2480015 0x0 0x24903 0x15000000 0x24a 0x6150100 0x2 0x4b071500 0x0 0x24c0715 0x0 0x24d00 0x15000000 0x24e 0x150000 0x2 0x4f001500 0x0 0x2500015 0x0 0x25100 0x15000000 0x252 0x150000 0x2 0x53011500 0x0 0x2540115 0x0 0x25589 0x15000000 0x256 0x150000 0x2 0x58001500 0x0 0x2680015 0x0 0x284ff 0x15000000 0x285 0xff150100 0x2 0x86031500 0x0 0x2870015 0x0 0x28800 0x15000000 0x2a2 0x20150000 0x2 0xa9011500 0x0 0x2aa1215 0x0 0x2ab13 0x15000000 0x2ac 0xa150000 0x2 0xad741500 0x0 0x2af3315 0x0 0x2b003 0x15000000 0x2b1 0x14150000 0x2 0xb2421500 0x0 0x2b34015 0x0 0x2b4a5 0x15010000 0x2b6 0x44150000 0x2 0xb7041500 0x0 0x2b81415 0x0 0x2b942 0x15000000 0x2ba 0x40150000 0x2 0xbba51500 0x0 0x2bd4415 0x0 0x2be04 0x15000000 0x2bf 0x150000 0x2 0xc0751500 0x0 0x2c16a15 0x0 0x2c2a5 0x15000000 0x2c4 0x22150000 0x2 0xc5021500 0x0 0x2c60015 0x1000000 0x2c795 0x15000000 0x2c8 0x8a150000 0x2 0xc9a51500 0x0 0x2cb2215 0x0 0x2cc02 0x15000000 0x2cd 0x150000 0x2 0xceb51500 0x0 0x2cfaa15 0x0 0x2d0a5 0x15000000 0x2d2 0x22150000 0x2 0xd3021501 0x0 0x2fb0115 0x1000000 0x2ff10 0x15010000 0x226 0x2150000 0x2 0x35001500 0x0 0x251ff15 0x0 0x25324 0x15000000 0x255 0x150100 0x2 0xb0000501 0x5000 0x2110005 0x1000014 0x22900>; | |
qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 46 00 02 10 00]; | |
qcom,mdss-dsi-displayoff-command = [05 01 00 00 14 00 02 28 00]; | |
qcom,mdss-dsi-displayon-command = [05 01 00 00 14 00 02 29 00]; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-displayoff-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-displayon-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-h-sync-pulse = <0x1>; | |
qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-lp11-init; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-panel-timings = <0x220808 0x24240808 0x5030400>; | |
qcom,mdss-dsi-t-clk-post = <0xe>; | |
qcom,mdss-dsi-t-clk-pre = <0x34>; | |
qcom,mdss-dsi-bl-min-level = <0x1>; | |
qcom,mdss-dsi-bl-max-level = <0xfff>; | |
qcom,mdss-brightness-max-level = <0xfff>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
qcom,mdss-dsi-reset-sequence = <0x0 0xa 0x1 0xa>; | |
qcom,mdss-pan-physical-width-dimension = <0x44>; | |
qcom,mdss-pan-physical-height-dimension = <0x88>; | |
qcom,cont-splash-enabled; | |
qcom,mdss-dsi-tx-eot-append; | |
qcom,mdss-panel-on-dimming-delay = <0x78>; | |
qcom,esd-err-irq-gpio = <0x7c 0x34 0x2001>; | |
qcom,esd-panel-onoff-tpg; | |
qcom,mdss-dsi-min-refresh-rate = <0x37>; | |
qcom,mdss-dsi-max-refresh-rate = <0x3c>; | |
qcom,mdss-dsi-pan-enable-dynamic-fps; | |
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; | |
qcom,dispccbb-enabled; | |
qcom,dispblnotify-enabled; | |
qcom,dispparam-enabled; | |
qcom,disp-paneloff-disablecabc-enabled; | |
qcom,mdss-night-brightness = <0x7 0x19 0x2b 0x3d>; | |
qcom,mdss-dsi-panel-xy-coordinate = <0xa1 0xf 0x18>; | |
qcom,mdss-dsi-dispparam-skin-ce-command = [15 01 00 00 00 00 02 55 83]; | |
qcom,mdss-dsi-dispparam-skin-ce-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-cabcon-command = [15 01 00 00 00 00 02 55 03]; | |
qcom,mdss-dsi-dispparam-cabcon-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-cabcguion-command = [15 01 00 00 00 00 02 55 03]; | |
qcom,mdss-dsi-dispparam-cabcguion-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-cabcstillon-command = [15 00 00 00 00 00 02 55 01 15 01 00 00 00 00 03 68 01 01]; | |
qcom,mdss-dsi-dispparam-cabcstillon-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-cabcmovieon-command = [15 01 00 00 00 00 02 55 02]; | |
qcom,mdss-dsi-dispparam-cabcmovieon-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-cabcoff-command = [39 01 00 00 01 00 02 55 00]; | |
qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 2c]; | |
qcom,mdss-dsi-dispparam-idleon-command = [39 01 00 00 01 00 02 39 00]; | |
qcom,mdss-dsi-dispparam-idleoff-command = [39 01 00 00 01 00 02 38 00]; | |
qcom,mdss-dsi-dispparam-papermode2-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 10 00 02 26 01 15 01 00 00 00 00 02 ff 20 15 00 00 00 00 00 02 75 00 15 00 00 00 00 00 02 76 00 15 00 00 00 00 00 02 77 00 15 00 00 00 00 00 02 78 27 15 00 00 00 00 00 02 79 00 15 00 00 00 00 00 02 7a 67 15 00 00 00 00 00 02 7b 00 15 00 00 00 00 00 02 7c 94 15 00 00 00 00 00 02 7d 00 15 00 00 00 00 00 02 7e b8 15 00 00 00 00 00 02 7f 00 15 00 00 00 00 00 02 80 d4 15 00 00 00 00 00 02 81 00 15 00 00 00 00 00 02 82 ea 15 00 00 00 00 00 02 83 00 15 00 00 00 00 00 02 84 fc 15 00 00 00 00 00 02 85 01 15 00 00 00 00 00 02 86 0f 15 00 00 00 00 00 02 87 01 15 00 00 00 00 00 02 88 46 15 00 00 00 00 00 02 89 01 15 00 00 00 00 00 02 8a 70 15 00 00 00 00 00 02 8b 01 15 00 00 00 00 00 02 8c ad 15 00 00 00 00 00 02 8d 01 15 00 00 00 00 00 02 8e da 15 00 00 00 00 00 02 8f 02 15 00 00 00 00 00 02 90 1d 15 00 00 00 00 00 02 91 02 15 00 00 00 00 00 02 92 50 15 00 00 00 00 00 02 93 02 15 00 00 00 00 00 02 94 52 15 00 00 00 00 00 02 95 02 15 00 00 00 00 00 02 96 83 15 00 00 00 00 00 02 97 02 15 00 00 00 00 00 02 98 ba 15 00 00 00 00 00 02 99 02 15 00 00 00 00 00 02 9a de 15 00 00 00 00 00 02 9b 03 15 00 00 00 00 00 02 9c 12 15 00 00 00 00 00 02 9d 03 15 00 00 00 00 00 02 9e 2e 15 00 00 00 00 00 02 9f 03 15 00 00 00 00 00 02 a0 54 15 00 00 00 00 00 02 a2 03 15 00 00 00 00 00 02 a3 61 15 00 00 00 00 00 02 a4 03 15 00 00 00 00 00 02 a5 6f 15 00 00 00 00 00 02 a6 03 15 00 00 00 00 00 02 a7 7e 15 00 00 00 00 00 02 a9 03 15 00 00 00 00 00 02 aa 90 15 00 00 00 00 00 02 ab 03 15 00 00 00 00 00 02 ac a7 15 00 00 00 00 00 02 ad 03 15 00 00 00 00 00 02 ae c2 15 00 00 00 00 00 02 af 03 15 00 00 00 00 00 02 b0 d5 15 00 00 00 00 00 02 b1 03 15 01 00 00 00 00 02 b2 d8 15 00 00 00 00 00 02 b3 00 15 00 00 00 00 00 02 b4 00 15 00 00 00 00 00 02 b5 00 15 00 00 00 00 00 02 b6 27 15 00 00 00 00 00 02 b7 00 15 00 00 00 00 00 02 b8 67 15 00 00 00 00 00 02 b9 00 15 00 00 00 00 00 02 ba 94 15 00 00 00 00 00 02 bb 00 15 00 00 00 00 00 02 bc b8 15 00 00 00 00 00 02 bd 00 15 00 00 00 00 00 02 be d4 15 00 00 00 00 00 02 bf 00 15 00 00 00 00 00 02 c0 ea 15 00 00 00 00 00 02 c1 00 15 00 00 00 00 00 02 c2 fc 15 00 00 00 00 00 02 c3 01 15 00 00 00 00 00 02 c4 0f 15 00 00 00 00 00 02 c5 01 15 00 00 00 00 00 02 c6 46 15 00 00 00 00 00 02 c7 01 15 00 00 00 00 00 02 c8 70 15 00 00 00 00 00 02 c9 01 15 00 00 00 00 00 02 ca ad 15 00 00 00 00 00 02 cb 01 15 00 00 00 00 00 02 cc da 15 00 00 00 00 00 02 cd 02 15 00 00 00 00 00 02 ce 1d 15 00 00 00 00 00 02 cf 02 15 00 00 00 00 00 02 d0 50 15 00 00 00 00 00 02 d1 02 15 00 00 00 00 00 02 d2 52 15 00 00 00 00 00 02 d3 02 15 00 00 00 00 00 02 d4 83 15 00 00 00 00 00 02 d5 02 15 00 00 00 00 00 02 d6 ba 15 00 00 00 00 00 02 d7 02 15 00 00 00 00 00 02 d8 de 15 00 00 00 00 00 02 d9 03 15 00 00 00 00 00 02 da 12 15 00 00 00 00 00 02 db 03 15 00 00 00 00 00 02 dc 2e 15 00 00 00 00 00 02 dd 03 15 00 00 00 00 00 02 de 54 15 00 00 00 00 00 02 df 03 15 00 00 00 00 00 02 e0 61 15 00 00 00 00 00 02 e1 03 15 00 00 00 00 00 02 e2 6f 15 00 00 00 00 00 02 e3 03 15 00 00 00 00 00 02 e4 7e 15 00 00 00 00 00 02 e5 03 15 00 00 00 00 00 02 e6 90 15 00 00 00 00 00 02 e7 03 15 00 00 00 00 00 02 e8 a7 15 00 00 00 00 00 02 e9 03 15 00 00 00 00 00 02 ea c2 15 00 00 00 00 00 02 eb 03 15 00 00 00 00 00 02 ec d5 15 00 00 00 00 00 02 ed 03 15 00 00 00 00 00 02 ee d8 15 00 00 00 00 00 02 ef 00 15 00 00 00 00 00 02 f0 bc 15 00 00 00 00 00 02 f1 00 15 00 00 00 00 00 02 f2 cb 15 00 00 00 00 00 02 f3 00 15 00 00 00 00 00 02 f4 e4 15 00 00 00 00 00 02 f5 00 15 00 00 00 00 00 02 f6 f9 15 00 00 00 00 00 02 f7 01 15 00 00 00 00 00 02 f8 0b 15 00 00 00 00 00 02 f9 01 15 00 00 00 00 00 02 fa 1b 15 01 00 00 00 00 02 ff 21 15 00 00 00 00 00 02 00 01 15 00 00 00 00 00 02 01 2a 15 00 00 00 00 00 02 02 01 15 00 00 00 00 00 02 03 38 15 00 00 00 00 00 02 04 01 15 00 00 00 00 00 02 05 44 15 00 00 00 00 00 02 06 01 15 00 00 00 00 00 02 07 6e 15 00 00 00 00 00 02 08 01 15 00 00 00 00 00 02 09 8f 15 00 00 00 00 00 02 0a 01 15 00 00 00 00 00 02 0b c2 15 00 00 00 00 00 02 0c 01 15 00 00 00 00 00 02 0d e9 15 00 00 00 00 00 02 0e 02 15 00 00 00 00 00 02 0f 27 15 00 00 00 00 00 02 10 02 15 00 00 00 00 00 02 11 56 15 00 00 00 00 00 02 12 02 15 00 00 00 00 00 02 13 58 15 00 00 00 00 00 02 14 02 15 00 00 00 00 00 02 15 87 15 00 00 00 00 00 02 16 02 15 00 00 00 00 00 02 17 bd 15 00 00 00 00 00 02 18 02 15 00 00 00 00 00 02 19 e2 15 00 00 00 00 00 02 1a 03 15 00 00 00 00 00 02 1b 14 15 00 00 00 00 00 02 1c 03 15 00 00 00 00 00 02 1d 30 15 00 00 00 00 00 02 1e 03 15 00 00 00 00 00 02 1f 58 15 00 00 00 00 00 02 20 03 15 00 00 00 00 00 02 21 64 15 00 00 00 00 00 02 22 03 15 00 00 00 00 00 02 23 72 15 00 00 00 00 00 02 24 03 15 00 00 00 00 00 02 25 81 15 00 00 00 00 00 02 26 03 15 00 00 00 00 00 02 27 95 15 00 00 00 00 00 02 28 03 15 00 00 00 00 00 02 29 ad 15 00 00 00 00 00 02 2a 03 15 00 00 00 00 00 02 2b c6 15 00 00 00 00 00 02 2d 03 15 00 00 00 00 00 02 2f d6 15 00 00 00 00 00 02 30 03 15 01 00 00 00 00 02 31 d8 15 00 00 00 00 00 02 32 00 15 00 00 00 00 00 02 33 bc 15 00 00 00 00 00 02 34 00 15 00 00 00 00 00 02 35 cb 15 00 00 00 00 00 02 36 00 15 00 00 00 00 00 02 37 e4 15 00 00 00 00 00 02 38 00 15 00 00 00 00 00 02 39 f9 15 00 00 00 00 00 02 3a 01 15 00 00 00 00 00 02 3b 0b 15 00 00 00 00 00 02 3d 01 15 00 00 00 00 00 02 3f 1b 15 00 00 00 00 00 02 40 01 15 00 00 00 00 00 02 41 2a 15 00 00 00 00 00 02 42 01 15 00 00 00 00 00 02 43 38 15 00 00 00 00 00 02 44 01 15 00 00 00 00 00 02 45 44 15 00 00 00 00 00 02 46 01 15 00 00 00 00 00 02 47 6e 15 00 00 00 00 00 02 48 01 15 00 00 00 00 00 02 49 8f 15 00 00 00 00 00 02 4a 01 15 00 00 00 00 00 02 4b c2 15 00 00 00 00 00 02 4c 01 15 00 00 00 00 00 02 4d e9 15 00 00 00 00 00 02 4e 02 15 00 00 00 00 00 02 4f 27 15 00 00 00 00 00 02 50 02 15 00 00 00 00 00 02 51 56 15 00 00 00 00 00 02 52 02 15 00 00 00 00 00 02 53 58 15 00 00 00 00 00 02 54 02 15 00 00 00 00 00 02 55 87 15 00 00 00 00 00 02 56 02 15 00 00 00 00 00 02 58 bd 15 00 00 00 00 00 02 59 02 15 00 00 00 00 00 02 5a e2 15 00 00 00 00 00 02 5b 03 15 00 00 00 00 00 02 5c 14 15 00 00 00 00 00 02 5d 03 15 00 00 00 00 00 02 5e 30 15 00 00 00 00 00 02 5f 03 15 00 00 00 00 00 02 60 58 15 00 00 00 00 00 02 61 03 15 00 00 00 00 00 02 62 64 15 00 00 00 00 00 02 63 03 15 00 00 00 00 00 02 64 72 15 00 00 00 00 00 02 65 03 15 00 00 00 00 00 02 66 81 15 00 00 00 00 00 02 67 03 15 00 00 00 00 00 02 68 95 15 00 00 00 00 00 02 69 03 15 01 00 00 00 00 02 6a ad 15 00 00 00 00 00 02 6b 03 15 00 00 00 00 00 02 6c c6 15 00 00 00 00 00 02 6d 03 15 00 00 00 00 00 02 6e d6 15 00 00 00 00 00 02 6f 03 15 00 00 00 00 00 02 70 d8 15 00 00 00 00 00 02 71 01 15 00 00 00 00 00 02 72 7d 15 00 00 00 00 00 02 73 01 15 00 00 00 00 00 02 74 81 15 00 00 00 00 00 02 75 01 15 00 00 00 00 00 02 76 88 15 00 00 00 00 00 02 77 01 15 00 00 00 00 00 02 78 8f 15 00 00 00 00 00 02 79 01 15 00 00 00 00 00 02 7a 96 15 00 00 00 00 00 02 7b 01 15 00 00 00 00 00 02 7c 9d 15 00 00 00 00 00 02 7d 01 15 00 00 00 00 00 02 7e a3 15 00 00 00 00 00 02 7f 01 15 00 00 00 00 00 02 80 a8 15 00 00 00 00 00 02 81 01 15 00 00 00 00 00 02 82 ae 15 00 00 00 00 00 02 83 01 15 00 00 00 00 00 02 84 c3 15 00 00 00 00 00 02 85 01 15 00 00 00 00 00 02 86 d6 15 00 00 00 00 00 02 87 01 15 00 00 00 00 00 02 88 f5 15 00 00 00 00 00 02 89 02 15 00 00 00 00 00 02 8a 12 15 00 00 00 00 00 02 8b 02 15 00 00 00 00 00 02 8c 42 15 00 00 00 00 00 02 8d 02 15 00 00 00 00 00 02 8e 6b 15 00 00 00 00 00 02 8f 02 15 00 00 00 00 00 02 90 6c 15 00 00 00 00 00 02 91 02 15 00 00 00 00 00 02 92 98 15 00 00 00 00 00 02 93 02 15 00 00 00 00 00 02 94 cd 15 00 00 00 00 00 02 95 02 15 00 00 00 00 00 02 96 f2 15 00 00 00 00 00 02 97 03 15 00 00 00 00 00 02 98 20 15 00 00 00 00 00 02 99 03 15 00 00 00 00 00 02 9a 3c 15 00 00 00 00 00 02 9b 03 15 00 00 00 00 00 02 9c 61 15 00 00 00 00 00 02 9d 03 15 00 00 00 00 00 02 9e 6b 15 00 00 00 00 00 02 9f 03 15 00 00 00 00 00 02 a0 77 15 00 00 00 00 00 02 a2 03 15 00 00 00 00 00 02 a3 85 15 00 00 00 00 00 02 a4 03 15 00 00 00 00 00 02 a5 95 15 00 00 00 00 00 02 a6 03 15 00 00 00 00 00 02 a7 9f 15 00 00 00 00 00 02 a9 03 15 00 00 00 00 00 02 aa bf 15 00 00 00 00 00 02 ab 03 15 00 00 00 00 00 02 ac d6 15 00 00 00 00 00 02 ad 03 15 01 00 00 00 00 02 ae d8 15 00 00 00 00 00 02 af 01 15 00 00 00 00 00 02 b0 7d 15 00 00 00 00 00 02 b1 01 15 00 00 00 00 00 02 b2 81 15 00 00 00 00 00 02 b3 01 15 00 00 00 00 00 02 b4 88 15 00 00 00 00 00 02 b5 01 15 00 00 00 00 00 02 b6 8f 15 00 00 00 00 00 02 b7 01 15 00 00 00 00 00 02 b8 96 15 00 00 00 00 00 02 b9 01 15 00 00 00 00 00 02 ba 9d 15 00 00 00 00 00 02 bb 01 15 00 00 00 00 00 02 bc a3 15 00 00 00 00 00 02 bd 01 15 00 00 00 00 00 02 be a8 15 00 00 00 00 00 02 bf 01 15 00 00 00 00 00 02 c0 ae 15 00 00 00 00 00 02 c1 01 15 00 00 00 00 00 02 c2 c3 15 00 00 00 00 00 02 c3 01 15 00 00 00 00 00 02 c4 d6 15 00 00 00 00 00 02 c5 01 15 00 00 00 00 00 02 c6 f5 15 00 00 00 00 00 02 c7 02 15 00 00 00 00 00 02 c8 12 15 00 00 00 00 00 02 c9 02 15 00 00 00 00 00 02 ca 42 15 00 00 00 00 00 02 cb 02 15 00 00 00 00 00 02 cc 6b 15 00 00 00 00 00 02 cd 02 15 00 00 00 00 00 02 ce 6c 15 00 00 00 00 00 02 cf 02 15 00 00 00 00 00 02 d0 98 15 00 00 00 00 00 02 d1 02 15 00 00 00 00 00 02 d2 cd 15 00 00 00 00 00 02 d3 02 15 00 00 00 00 00 02 d4 f2 15 00 00 00 00 00 02 d5 03 15 00 00 00 00 00 02 d6 20 15 00 00 00 00 00 02 d7 03 15 00 00 00 00 00 02 d8 3c 15 00 00 00 00 00 02 d9 03 15 00 00 00 00 00 02 da 61 15 00 00 00 00 00 02 db 03 15 00 00 00 00 00 02 dc 6b 15 00 00 00 00 00 02 dd 03 15 00 00 00 00 00 02 de 77 15 00 00 00 00 00 02 df 03 15 00 00 00 00 00 02 e0 85 15 00 00 00 00 00 02 e1 03 15 00 00 00 00 00 02 e2 95 15 00 00 00 00 00 02 e3 03 15 00 00 00 00 00 02 e4 9f 15 00 00 00 00 00 02 e5 03 15 00 00 00 00 00 02 e6 bf 15 00 00 00 00 00 02 e7 03 15 00 00 00 00 00 02 e8 d6 15 00 00 00 00 00 02 e9 03 15 00 00 00 00 00 02 ea d8 15 01 00 00 00 00 02 ff 10]; | |
qcom,mdss-dsi-dispparam-papermode2-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-default-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 10 00 02 26 02]; | |
qcom,mdss-dsi-dispparam-default-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-normal1-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 10 00 02 26 01]; | |
qcom,mdss-dsi-dispparam-normal1-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-normal2-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 10 00 02 26 02]; | |
qcom,mdss-dsi-dispparam-normal2-command-state = "dsi_hs_mode"; | |
}; | |
qcom,mdss_dsi_jdi_fhd_nt35596s_pro_video { | |
qcom,mdss-dsi-panel-name = "jdi fhd video dsi panel"; | |
qcom,mdss-dsi-panel-id = <0x0>; | |
qcom,mdss-dsi-panel-model = "JDI FHD NT35596S VIDEO PANEL"; | |
qcom,mdss-dsi-panel-sleepwrmod = <0x0>; | |
qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x438>; | |
qcom,mdss-dsi-panel-height = <0x870>; | |
qcom,mdss-dsi-h-front-porch = <0xc>; | |
qcom,mdss-dsi-h-back-porch = <0x28>; | |
qcom,mdss-dsi-h-pulse-width = <0x18>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x18>; | |
qcom,mdss-dsi-v-front-porch = <0x6>; | |
qcom,mdss-dsi-v-pulse-width = <0x4>; | |
qcom,mdss-dsi-h-left-border = <0x0>; | |
qcom,mdss-dsi-h-right-border = <0x0>; | |
qcom,mdss-dsi-v-top-border = <0x0>; | |
qcom,mdss-dsi-v-bottom-border = <0x0>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-color-order = <0x0>; | |
qcom,mdss-dsi-underflow-color = <0x0>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-on-command = <0x15010000 0x2ff 0x24150000 0x2 0x9d341500 0x0 0x2fb0115 0x0 0x2c425 0x15000000 0x2d1 0x8150000 0x2 0xd2841501 0x0 0x2ff2615 0x0 0x2fb01 0x15000000 0x203 0x1c150000 0x2 0x3b081500 0x0 0x26b0815 0x0 0x29708 0x15000000 0x2c5 0x8150000 0x2 0xfb011501 0x0 0x2ff2315 0x0 0x2fb01 0x15000000 0x201 0x84150000 0x2 0x52d1500 0x0 0x2060015 0x0 0x23307 0x15000000 0x221 0xee150000 0x2 0x22ed1500 0x0 0x223ea15 0x0 0x224e8 0x15000000 0x225 0xe5150000 0x2 0x26e21500 0x0 0x227de15 0x0 0x228bb 0x15000000 0x229 0x87150000 0x2 0x2a771501 0x0 0x2320c15 0x0 0x2133f 0x15000000 0x214 0x34150000 0x2 0x152a1500 0x0 0x2162515 0x0 0x2179d 0x15000000 0x218 0x9a150000 0x2 0x19971500 0x0 0x21a9415 0x0 0x21b91 0x15000000 0x21c 0x8e150000 0x2 0x1d8b1500 0x0 0x21e8915 0x0 0x21f86 0x15000000 0x220 0x83150100 0x2 0xff221500 0x0 0x2000a15 0x0 0x20143 0x15000000 0x202 0x5b150000 0x2 0x36a1500 0x0 0x2047a15 0x0 0x20582 0x15000000 0x206 0x85150000 0x2 0x7801500 0x0 0x2087c15 0x0 0x2097c 0x15000000 0x20a 0x74150000 0x2 0xb711500 0x0 0x20c6e15 0x0 0x20d68 0x15000000 0x20e 0x65150100 0x2 0xf5c1500 0x0 0x2103215 0x0 0x21118 0x15000000 0x212 0x150000 0x2 0x13001500 0x0 0x21a0015 0x0 0x21b00 0x15000000 0x21c 0x150000 0x2 0x1d001500 0x0 0x21e0015 0x0 0x21f00 0x15000000 0x220 0x150000 0x2 0x21001500 0x0 0x2220015 0x0 0x22300 0x15000000 0x224 0x150100 0x2 0x25001500 0x0 0x2260015 0x0 0x22700 0x15000000 0x228 0x150000 0x2 0x29001500 0x0 0x22a0015 0x0 0x22b00 0x15000000 0x22f 0x150000 0x2 0x30001500 0x0 0x2310015 0x0 0x2320c 0x15000000 0x233 0xc150000 0x2 0x340c1500 0x0 0x2350b15 0x0 0x23609 0x15000000 0x237 0x9150100 0x2 0x38081500 0x0 0x2390515 0x0 0x23a03 0x15000000 0x23b 0x150000 0x2 0x3f001500 0x0 0x2400015 0x0 0x24100 0x15000000 0x242 0x150000 0x2 0x43001500 0x0 0x2440015 0x0 0x24500 0x15000000 0x246 0x150000 0x2 0x47001500 0x0 0x2480015 0x0 0x24903 0x15000000 0x24a 0x6150100 0x2 0x4b071500 0x0 0x24c0715 0x0 0x24d00 0x15000000 0x24e 0x150000 0x2 0x4f001500 0x0 0x2500015 0x0 0x25100 0x15000000 0x252 0x150000 0x2 0x53011500 0x0 0x2540115 0x0 0x25589 0x15000000 0x256 0x150000 0x2 0x58001500 0x0 0x2680015 0x0 0x284ff 0x15000000 0x285 0xff150100 0x2 0x86031500 0x0 0x2870015 0x0 0x28800 0x15000000 0x2a2 0x20150000 0x2 0xa9011500 0x0 0x2aa1215 0x0 0x2ab13 0x15000000 0x2ac 0xa150000 0x2 0xad741500 0x0 0x2af3315 0x0 0x2b003 0x15000000 0x2b1 0x14150000 0x2 0xb2421500 0x0 0x2b34015 0x0 0x2b4a5 0x15010000 0x2b6 0x44150000 0x2 0xb7041500 0x0 0x2b81415 0x0 0x2b942 0x15000000 0x2ba 0x40150000 0x2 0xbba51500 0x0 0x2bd4415 0x0 0x2be04 0x15000000 0x2bf 0x150000 0x2 0xc0751500 0x0 0x2c16a15 0x0 0x2c2a5 0x15000000 0x2c4 0x22150000 0x2 0xc5021500 0x0 0x2c60015 0x1000000 0x2c795 0x15000000 0x2c8 0x8a150000 0x2 0xc9a51500 0x0 0x2cb2215 0x0 0x2cc02 0x15000000 0x2cd 0x150000 0x2 0xceb51500 0x0 0x2cfaa15 0x0 0x2d0a5 0x15000000 0x2d2 0x22150000 0x2 0xd3021501 0x0 0x2fb0115 0x1000000 0x2ff10 0x15010000 0x226 0x2150000 0x2 0x35001500 0x0 0x251ff15 0x0 0x25324 0x15000000 0x255 0x150100 0x2 0xb0000501 0x5000 0x2110005 0x1000014 0x22900>; | |
qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 46 00 02 10 00]; | |
qcom,mdss-dsi-displayoff-command = [05 01 00 00 14 00 02 28 00]; | |
qcom,mdss-dsi-displayon-command = [05 01 00 00 14 00 02 29 00]; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-displayoff-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-displayon-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-h-sync-pulse = <0x1>; | |
qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-lp11-init; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-panel-timings = <0x1f0808 0x24220808 0x5030400>; | |
qcom,mdss-dsi-t-clk-post = <0xd>; | |
qcom,mdss-dsi-t-clk-pre = <0x30>; | |
qcom,mdss-dsi-bl-min-level = <0x1>; | |
qcom,mdss-dsi-bl-max-level = <0xfff>; | |
qcom,mdss-brightness-max-level = <0xfff>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
qcom,mdss-dsi-reset-sequence = <0x0 0xa 0x1 0xa>; | |
qcom,mdss-pan-physical-width-dimension = <0x44>; | |
qcom,mdss-pan-physical-height-dimension = <0x88>; | |
qcom,cont-splash-enabled; | |
qcom,mdss-dsi-tx-eot-append; | |
qcom,mdss-panel-on-dimming-delay = <0x78>; | |
qcom,esd-err-irq-gpio = <0x7c 0x34 0x2001>; | |
qcom,esd-panel-onoff-tpg; | |
qcom,mdss-dsi-min-refresh-rate = <0x37>; | |
qcom,mdss-dsi-max-refresh-rate = <0x3c>; | |
qcom,mdss-dsi-pan-enable-dynamic-fps; | |
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; | |
qcom,dispccbb-enabled; | |
qcom,dispblnotify-enabled; | |
qcom,dispparam-enabled; | |
qcom,disp-paneloff-disablecabc-enabled; | |
qcom,mdss-night-brightness = <0x7 0x19 0x2b 0x3d>; | |
qcom,mdss-dsi-panel-xy-coordinate = <0xa1 0xf 0x18>; | |
qcom,mdss-dsi-dispparam-skin-ce-command = [15 01 00 00 00 00 02 55 83]; | |
qcom,mdss-dsi-dispparam-skin-ce-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-cabcon-command = [15 01 00 00 00 00 02 55 03]; | |
qcom,mdss-dsi-dispparam-cabcon-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-cabcguion-command = [15 01 00 00 00 00 02 55 03]; | |
qcom,mdss-dsi-dispparam-cabcguion-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-cabcstillon-command = [15 00 00 00 00 00 02 55 01 15 01 00 00 00 00 03 68 01 01]; | |
qcom,mdss-dsi-dispparam-cabcstillon-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-cabcmovieon-command = [15 01 00 00 00 00 02 55 02]; | |
qcom,mdss-dsi-dispparam-cabcmovieon-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-cabcoff-command = [39 01 00 00 01 00 02 55 00]; | |
qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 2c]; | |
qcom,mdss-dsi-dispparam-idleon-command = [39 01 00 00 01 00 02 39 00]; | |
qcom,mdss-dsi-dispparam-idleoff-command = [39 01 00 00 01 00 02 38 00]; | |
qcom,mdss-dsi-dispparam-papermode2-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 10 00 02 26 01 15 01 00 00 00 00 02 ff 20 15 00 00 00 00 00 02 75 00 15 00 00 00 00 00 02 76 00 15 00 00 00 00 00 02 77 00 15 00 00 00 00 00 02 78 27 15 00 00 00 00 00 02 79 00 15 00 00 00 00 00 02 7a 67 15 00 00 00 00 00 02 7b 00 15 00 00 00 00 00 02 7c 94 15 00 00 00 00 00 02 7d 00 15 00 00 00 00 00 02 7e b8 15 00 00 00 00 00 02 7f 00 15 00 00 00 00 00 02 80 d4 15 00 00 00 00 00 02 81 00 15 00 00 00 00 00 02 82 ea 15 00 00 00 00 00 02 83 00 15 00 00 00 00 00 02 84 fc 15 00 00 00 00 00 02 85 01 15 00 00 00 00 00 02 86 0f 15 00 00 00 00 00 02 87 01 15 00 00 00 00 00 02 88 46 15 00 00 00 00 00 02 89 01 15 00 00 00 00 00 02 8a 70 15 00 00 00 00 00 02 8b 01 15 00 00 00 00 00 02 8c ad 15 00 00 00 00 00 02 8d 01 15 00 00 00 00 00 02 8e da 15 00 00 00 00 00 02 8f 02 15 00 00 00 00 00 02 90 1d 15 00 00 00 00 00 02 91 02 15 00 00 00 00 00 02 92 50 15 00 00 00 00 00 02 93 02 15 00 00 00 00 00 02 94 52 15 00 00 00 00 00 02 95 02 15 00 00 00 00 00 02 96 83 15 00 00 00 00 00 02 97 02 15 00 00 00 00 00 02 98 ba 15 00 00 00 00 00 02 99 02 15 00 00 00 00 00 02 9a de 15 00 00 00 00 00 02 9b 03 15 00 00 00 00 00 02 9c 12 15 00 00 00 00 00 02 9d 03 15 00 00 00 00 00 02 9e 2e 15 00 00 00 00 00 02 9f 03 15 00 00 00 00 00 02 a0 54 15 00 00 00 00 00 02 a2 03 15 00 00 00 00 00 02 a3 61 15 00 00 00 00 00 02 a4 03 15 00 00 00 00 00 02 a5 6f 15 00 00 00 00 00 02 a6 03 15 00 00 00 00 00 02 a7 7e 15 00 00 00 00 00 02 a9 03 15 00 00 00 00 00 02 aa 90 15 00 00 00 00 00 02 ab 03 15 00 00 00 00 00 02 ac a7 15 00 00 00 00 00 02 ad 03 15 00 00 00 00 00 02 ae c2 15 00 00 00 00 00 02 af 03 15 00 00 00 00 00 02 b0 d5 15 00 00 00 00 00 02 b1 03 15 01 00 00 00 00 02 b2 d8 15 00 00 00 00 00 02 b3 00 15 00 00 00 00 00 02 b4 00 15 00 00 00 00 00 02 b5 00 15 00 00 00 00 00 02 b6 27 15 00 00 00 00 00 02 b7 00 15 00 00 00 00 00 02 b8 67 15 00 00 00 00 00 02 b9 00 15 00 00 00 00 00 02 ba 94 15 00 00 00 00 00 02 bb 00 15 00 00 00 00 00 02 bc b8 15 00 00 00 00 00 02 bd 00 15 00 00 00 00 00 02 be d4 15 00 00 00 00 00 02 bf 00 15 00 00 00 00 00 02 c0 ea 15 00 00 00 00 00 02 c1 00 15 00 00 00 00 00 02 c2 fc 15 00 00 00 00 00 02 c3 01 15 00 00 00 00 00 02 c4 0f 15 00 00 00 00 00 02 c5 01 15 00 00 00 00 00 02 c6 46 15 00 00 00 00 00 02 c7 01 15 00 00 00 00 00 02 c8 70 15 00 00 00 00 00 02 c9 01 15 00 00 00 00 00 02 ca ad 15 00 00 00 00 00 02 cb 01 15 00 00 00 00 00 02 cc da 15 00 00 00 00 00 02 cd 02 15 00 00 00 00 00 02 ce 1d 15 00 00 00 00 00 02 cf 02 15 00 00 00 00 00 02 d0 50 15 00 00 00 00 00 02 d1 02 15 00 00 00 00 00 02 d2 52 15 00 00 00 00 00 02 d3 02 15 00 00 00 00 00 02 d4 83 15 00 00 00 00 00 02 d5 02 15 00 00 00 00 00 02 d6 ba 15 00 00 00 00 00 02 d7 02 15 00 00 00 00 00 02 d8 de 15 00 00 00 00 00 02 d9 03 15 00 00 00 00 00 02 da 12 15 00 00 00 00 00 02 db 03 15 00 00 00 00 00 02 dc 2e 15 00 00 00 00 00 02 dd 03 15 00 00 00 00 00 02 de 54 15 00 00 00 00 00 02 df 03 15 00 00 00 00 00 02 e0 61 15 00 00 00 00 00 02 e1 03 15 00 00 00 00 00 02 e2 6f 15 00 00 00 00 00 02 e3 03 15 00 00 00 00 00 02 e4 7e 15 00 00 00 00 00 02 e5 03 15 00 00 00 00 00 02 e6 90 15 00 00 00 00 00 02 e7 03 15 00 00 00 00 00 02 e8 a7 15 00 00 00 00 00 02 e9 03 15 00 00 00 00 00 02 ea c2 15 00 00 00 00 00 02 eb 03 15 00 00 00 00 00 02 ec d5 15 00 00 00 00 00 02 ed 03 15 00 00 00 00 00 02 ee d8 15 00 00 00 00 00 02 ef 00 15 00 00 00 00 00 02 f0 bc 15 00 00 00 00 00 02 f1 00 15 00 00 00 00 00 02 f2 cb 15 00 00 00 00 00 02 f3 00 15 00 00 00 00 00 02 f4 e4 15 00 00 00 00 00 02 f5 00 15 00 00 00 00 00 02 f6 f9 15 00 00 00 00 00 02 f7 01 15 00 00 00 00 00 02 f8 0b 15 00 00 00 00 00 02 f9 01 15 00 00 00 00 00 02 fa 1b 15 01 00 00 00 00 02 ff 21 15 00 00 00 00 00 02 00 01 15 00 00 00 00 00 02 01 2a 15 00 00 00 00 00 02 02 01 15 00 00 00 00 00 02 03 38 15 00 00 00 00 00 02 04 01 15 00 00 00 00 00 02 05 44 15 00 00 00 00 00 02 06 01 15 00 00 00 00 00 02 07 6e 15 00 00 00 00 00 02 08 01 15 00 00 00 00 00 02 09 8f 15 00 00 00 00 00 02 0a 01 15 00 00 00 00 00 02 0b c2 15 00 00 00 00 00 02 0c 01 15 00 00 00 00 00 02 0d e9 15 00 00 00 00 00 02 0e 02 15 00 00 00 00 00 02 0f 27 15 00 00 00 00 00 02 10 02 15 00 00 00 00 00 02 11 56 15 00 00 00 00 00 02 12 02 15 00 00 00 00 00 02 13 58 15 00 00 00 00 00 02 14 02 15 00 00 00 00 00 02 15 87 15 00 00 00 00 00 02 16 02 15 00 00 00 00 00 02 17 bd 15 00 00 00 00 00 02 18 02 15 00 00 00 00 00 02 19 e2 15 00 00 00 00 00 02 1a 03 15 00 00 00 00 00 02 1b 14 15 00 00 00 00 00 02 1c 03 15 00 00 00 00 00 02 1d 30 15 00 00 00 00 00 02 1e 03 15 00 00 00 00 00 02 1f 58 15 00 00 00 00 00 02 20 03 15 00 00 00 00 00 02 21 64 15 00 00 00 00 00 02 22 03 15 00 00 00 00 00 02 23 72 15 00 00 00 00 00 02 24 03 15 00 00 00 00 00 02 25 81 15 00 00 00 00 00 02 26 03 15 00 00 00 00 00 02 27 95 15 00 00 00 00 00 02 28 03 15 00 00 00 00 00 02 29 ad 15 00 00 00 00 00 02 2a 03 15 00 00 00 00 00 02 2b c6 15 00 00 00 00 00 02 2d 03 15 00 00 00 00 00 02 2f d6 15 00 00 00 00 00 02 30 03 15 01 00 00 00 00 02 31 d8 15 00 00 00 00 00 02 32 00 15 00 00 00 00 00 02 33 bc 15 00 00 00 00 00 02 34 00 15 00 00 00 00 00 02 35 cb 15 00 00 00 00 00 02 36 00 15 00 00 00 00 00 02 37 e4 15 00 00 00 00 00 02 38 00 15 00 00 00 00 00 02 39 f9 15 00 00 00 00 00 02 3a 01 15 00 00 00 00 00 02 3b 0b 15 00 00 00 00 00 02 3d 01 15 00 00 00 00 00 02 3f 1b 15 00 00 00 00 00 02 40 01 15 00 00 00 00 00 02 41 2a 15 00 00 00 00 00 02 42 01 15 00 00 00 00 00 02 43 38 15 00 00 00 00 00 02 44 01 15 00 00 00 00 00 02 45 44 15 00 00 00 00 00 02 46 01 15 00 00 00 00 00 02 47 6e 15 00 00 00 00 00 02 48 01 15 00 00 00 00 00 02 49 8f 15 00 00 00 00 00 02 4a 01 15 00 00 00 00 00 02 4b c2 15 00 00 00 00 00 02 4c 01 15 00 00 00 00 00 02 4d e9 15 00 00 00 00 00 02 4e 02 15 00 00 00 00 00 02 4f 27 15 00 00 00 00 00 02 50 02 15 00 00 00 00 00 02 51 56 15 00 00 00 00 00 02 52 02 15 00 00 00 00 00 02 53 58 15 00 00 00 00 00 02 54 02 15 00 00 00 00 00 02 55 87 15 00 00 00 00 00 02 56 02 15 00 00 00 00 00 02 58 bd 15 00 00 00 00 00 02 59 02 15 00 00 00 00 00 02 5a e2 15 00 00 00 00 00 02 5b 03 15 00 00 00 00 00 02 5c 14 15 00 00 00 00 00 02 5d 03 15 00 00 00 00 00 02 5e 30 15 00 00 00 00 00 02 5f 03 15 00 00 00 00 00 02 60 58 15 00 00 00 00 00 02 61 03 15 00 00 00 00 00 02 62 64 15 00 00 00 00 00 02 63 03 15 00 00 00 00 00 02 64 72 15 00 00 00 00 00 02 65 03 15 00 00 00 00 00 02 66 81 15 00 00 00 00 00 02 67 03 15 00 00 00 00 00 02 68 95 15 00 00 00 00 00 02 69 03 15 01 00 00 00 00 02 6a ad 15 00 00 00 00 00 02 6b 03 15 00 00 00 00 00 02 6c c6 15 00 00 00 00 00 02 6d 03 15 00 00 00 00 00 02 6e d6 15 00 00 00 00 00 02 6f 03 15 00 00 00 00 00 02 70 d8 15 00 00 00 00 00 02 71 01 15 00 00 00 00 00 02 72 7d 15 00 00 00 00 00 02 73 01 15 00 00 00 00 00 02 74 81 15 00 00 00 00 00 02 75 01 15 00 00 00 00 00 02 76 88 15 00 00 00 00 00 02 77 01 15 00 00 00 00 00 02 78 8f 15 00 00 00 00 00 02 79 01 15 00 00 00 00 00 02 7a 96 15 00 00 00 00 00 02 7b 01 15 00 00 00 00 00 02 7c 9d 15 00 00 00 00 00 02 7d 01 15 00 00 00 00 00 02 7e a3 15 00 00 00 00 00 02 7f 01 15 00 00 00 00 00 02 80 a8 15 00 00 00 00 00 02 81 01 15 00 00 00 00 00 02 82 ae 15 00 00 00 00 00 02 83 01 15 00 00 00 00 00 02 84 c3 15 00 00 00 00 00 02 85 01 15 00 00 00 00 00 02 86 d6 15 00 00 00 00 00 02 87 01 15 00 00 00 00 00 02 88 f5 15 00 00 00 00 00 02 89 02 15 00 00 00 00 00 02 8a 12 15 00 00 00 00 00 02 8b 02 15 00 00 00 00 00 02 8c 42 15 00 00 00 00 00 02 8d 02 15 00 00 00 00 00 02 8e 6b 15 00 00 00 00 00 02 8f 02 15 00 00 00 00 00 02 90 6c 15 00 00 00 00 00 02 91 02 15 00 00 00 00 00 02 92 98 15 00 00 00 00 00 02 93 02 15 00 00 00 00 00 02 94 cd 15 00 00 00 00 00 02 95 02 15 00 00 00 00 00 02 96 f2 15 00 00 00 00 00 02 97 03 15 00 00 00 00 00 02 98 20 15 00 00 00 00 00 02 99 03 15 00 00 00 00 00 02 9a 3c 15 00 00 00 00 00 02 9b 03 15 00 00 00 00 00 02 9c 61 15 00 00 00 00 00 02 9d 03 15 00 00 00 00 00 02 9e 6b 15 00 00 00 00 00 02 9f 03 15 00 00 00 00 00 02 a0 77 15 00 00 00 00 00 02 a2 03 15 00 00 00 00 00 02 a3 85 15 00 00 00 00 00 02 a4 03 15 00 00 00 00 00 02 a5 95 15 00 00 00 00 00 02 a6 03 15 00 00 00 00 00 02 a7 9f 15 00 00 00 00 00 02 a9 03 15 00 00 00 00 00 02 aa bf 15 00 00 00 00 00 02 ab 03 15 00 00 00 00 00 02 ac d6 15 00 00 00 00 00 02 ad 03 15 01 00 00 00 00 02 ae d8 15 00 00 00 00 00 02 af 01 15 00 00 00 00 00 02 b0 7d 15 00 00 00 00 00 02 b1 01 15 00 00 00 00 00 02 b2 81 15 00 00 00 00 00 02 b3 01 15 00 00 00 00 00 02 b4 88 15 00 00 00 00 00 02 b5 01 15 00 00 00 00 00 02 b6 8f 15 00 00 00 00 00 02 b7 01 15 00 00 00 00 00 02 b8 96 15 00 00 00 00 00 02 b9 01 15 00 00 00 00 00 02 ba 9d 15 00 00 00 00 00 02 bb 01 15 00 00 00 00 00 02 bc a3 15 00 00 00 00 00 02 bd 01 15 00 00 00 00 00 02 be a8 15 00 00 00 00 00 02 bf 01 15 00 00 00 00 00 02 c0 ae 15 00 00 00 00 00 02 c1 01 15 00 00 00 00 00 02 c2 c3 15 00 00 00 00 00 02 c3 01 15 00 00 00 00 00 02 c4 d6 15 00 00 00 00 00 02 c5 01 15 00 00 00 00 00 02 c6 f5 15 00 00 00 00 00 02 c7 02 15 00 00 00 00 00 02 c8 12 15 00 00 00 00 00 02 c9 02 15 00 00 00 00 00 02 ca 42 15 00 00 00 00 00 02 cb 02 15 00 00 00 00 00 02 cc 6b 15 00 00 00 00 00 02 cd 02 15 00 00 00 00 00 02 ce 6c 15 00 00 00 00 00 02 cf 02 15 00 00 00 00 00 02 d0 98 15 00 00 00 00 00 02 d1 02 15 00 00 00 00 00 02 d2 cd 15 00 00 00 00 00 02 d3 02 15 00 00 00 00 00 02 d4 f2 15 00 00 00 00 00 02 d5 03 15 00 00 00 00 00 02 d6 20 15 00 00 00 00 00 02 d7 03 15 00 00 00 00 00 02 d8 3c 15 00 00 00 00 00 02 d9 03 15 00 00 00 00 00 02 da 61 15 00 00 00 00 00 02 db 03 15 00 00 00 00 00 02 dc 6b 15 00 00 00 00 00 02 dd 03 15 00 00 00 00 00 02 de 77 15 00 00 00 00 00 02 df 03 15 00 00 00 00 00 02 e0 85 15 00 00 00 00 00 02 e1 03 15 00 00 00 00 00 02 e2 95 15 00 00 00 00 00 02 e3 03 15 00 00 00 00 00 02 e4 9f 15 00 00 00 00 00 02 e5 03 15 00 00 00 00 00 02 e6 bf 15 00 00 00 00 00 02 e7 03 15 00 00 00 00 00 02 e8 d6 15 00 00 00 00 00 02 e9 03 15 00 00 00 00 00 02 ea d8 15 01 00 00 00 00 02 ff 10]; | |
qcom,mdss-dsi-dispparam-papermode2-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-default-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 10 00 02 26 02]; | |
qcom,mdss-dsi-dispparam-default-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-normal1-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 10 00 02 26 01]; | |
qcom,mdss-dsi-dispparam-normal1-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-dispparam-normal2-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 10 00 02 26 02]; | |
qcom,mdss-dsi-dispparam-normal2-command-state = "dsi_hs_mode"; | |
}; | |
qcom,mdss_dsi_ebbg_fhd_ft8716_video { | |
qcom,mdss-dsi-panel-name = "ebbg fhd video dsi panel"; | |
qcom,mdss-dsi-panel-id = <0x0>; | |
qcom,mdss-dsi-panel-model = "EBBG FHD FT8716 VIDEO PANEL"; | |
qcom,mdss-dsi-panel-sleepwrmod = <0x0>; | |
qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
qcom,mdss-dsi-panel-framerate = <0x3c>; | |
qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
qcom,mdss-dsi-stream = <0x0>; | |
qcom,mdss-dsi-panel-width = <0x438>; | |
qcom,mdss-dsi-panel-height = <0x870>; | |
qcom,mdss-dsi-h-front-porch = <0x20>; | |
qcom,mdss-dsi-h-back-porch = <0x20>; | |
qcom,mdss-dsi-h-pulse-width = <0x2>; | |
qcom,mdss-dsi-h-sync-skew = <0x0>; | |
qcom,mdss-dsi-v-back-porch = <0x1a>; | |
qcom,mdss-dsi-v-front-porch = <0x10>; | |
qcom,mdss-dsi-v-pulse-width = <0x2>; | |
qcom,mdss-dsi-h-left-border = <0x0>; | |
qcom,mdss-dsi-h-right-border = <0x0>; | |
qcom,mdss-dsi-v-top-border = <0x0>; | |
qcom,mdss-dsi-v-bottom-border = <0x0>; | |
qcom,mdss-dsi-bpp = <0x18>; | |
qcom,mdss-dsi-color-order = <0x0>; | |
qcom,mdss-dsi-underflow-color = <0x0>; | |
qcom,mdss-dsi-border-color = <0x0>; | |
qcom,mdss-dsi-on-command = <0x15000000 0x200 0x290000 0x4 0xff871601 0x15000000 0x200 0x80290100 0x3 0xff871615 0x0 0x200b3 0x15000000 0x2ca 0x8c150000 0x2 0x2900 0x0 0x4ff0000 0x150000 0x2 0x802901 0x0 0x3ff0000 0x15000000 0x200 0x290000 0x5 0x2a000004 0x37150000 0x2 0x2901 0x0 0x52b0000 0x86f1500 0x0 0x251ff15 0x0 0x25324 0x15000000 0x255 0x50100 0x960002 0x11000501 0x0 0x2290005 0x1000000 0x23500>; | |
qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00 05 01 00 00 96 00 02 10 00]; | |
qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-displayoff-command = [05 01 00 00 16 00 02 28 00]; | |
qcom,mdss-dsi-displayon-command = [05 01 00 00 14 00 02 29 00]; | |
qcom,mdss-dsi-displayoff-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-displayon-command-state = "dsi_hs_mode"; | |
qcom,mdss-dsi-h-sync-pulse = <0x1>; | |
qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
qcom,mdss-dsi-bllp-eof-power-mode; | |
qcom,mdss-dsi-bllp-power-mode; | |
qcom,mdss-dsi-lp11-init; | |
qcom,mdss-dsi-lane-0-state; | |
qcom,mdss-dsi-lane-1-state; | |
qcom,mdss-dsi-lane-2-state; | |
qcom,mdss-dsi-lane-3-state; | |
qcom,mdss-dsi-panel-timings = <0x1c0606 0xb100607 0x5030400>; | |
qcom,mdss-dsi-t-clk-post = <0x7>; | |
qcom,mdss-dsi-t-clk-pre = <0x2a>; | |
qcom,mdss-dsi-bl-min-level = <0x1>; | |
qcom,mdss-dsi-bl-max-level = <0xfff>; | |
qcom,mdss-brightness-max-level = <0xfff>; | |
qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
qcom,mdss-dsi-mdp-trigger = "none"; | |
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
qcom,mdss-dsi-reset-sequence = <0x0 0xa 0x1 0xa>; | |
qcom,mdss-pan-physical-width-dimension = <0x40>; | |
qcom,mdss-pan-physical-height-dimension = <0x72>; | |
qcom,cont-splash-enabled; | |
qcom,mdss-dsi-tx-eot-append; | |
qcom,mdss-panel-on-dimming-delay = <0x78>; | |
qcom,dispparam-enabled; | |
qcom,mdss-night-brightness = <0x7 0x19 0x2b 0x3d>; | |
qcom,mdss-dsi-dispparam-cabcon-command = [15 01 00 00 00 00 02 55 02]; | |
qcom,mdss-dsi-dispparam-cabcguion-command = [15 01 00 00 01 00 02 55 01]; | |
qcom,mdss-dsi-dispparam-cabcstillon-command = [15 01 00 00 01 00 02 55 02]; | |
qcom,mdss-dsi-dispparam-cabcmovieon-command = [15 01 00 00 01 00 02 55 03]; | |
qcom,mdss-dsi-dispparam-cabcoff-command = [39 01 00 00 01 00 02 55 00]; | |
qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 2c]; | |
qcom,mdss-dsi-dispparam-idleon-command = [39 01 00 00 01 00 02 39 00]; | |
qcom,mdss-dsi-dispparam-idleoff-command = [39 01 00 00 01 00 02 38 00]; | |
}; | |
dsi_panel_pwr_supply { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
linux,phandle = <0x1b4>; | |
phandle = <0x1b4>; | |
qcom,panel-supply-entry@0 { | |
reg = <0x0>; | |
qcom,supply-name = "wqhd-vddio"; | |
qcom,supply-min-voltage = <0x1b7740>; | |
qcom,supply-max-voltage = <0x1b7740>; | |
qcom,supply-enable-load = <0x7d00>; | |
qcom,supply-disable-load = <0x50>; | |
qcom,supply-post-on-sleep = <0x1>; | |
qcom,supply-pre-off-sleep = <0xa>; | |
}; | |
qcom,panel-supply-entry@1 { | |
reg = <0x1>; | |
qcom,supply-name = "lab"; | |
qcom,supply-min-voltage = <0x4630c0>; | |
qcom,supply-max-voltage = <0x5b8d80>; | |
qcom,supply-enable-load = <0x186a0>; | |
qcom,supply-disable-load = <0x64>; | |
}; | |
qcom,panel-supply-entry@2 { | |
reg = <0x2>; | |
qcom,supply-name = "ibb"; | |
qcom,supply-min-voltage = <0x4630c0>; | |
qcom,supply-max-voltage = <0x5b8d80>; | |
qcom,supply-enable-load = <0x186a0>; | |
qcom,supply-disable-load = <0x64>; | |
qcom,supply-post-on-sleep = <0xa>; | |
qcom,supply-pre-off-sleep = <0x5>; | |
}; | |
}; | |
dsi_panel_pwr_supply_jdi_nt35596s { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
qcom,panel-supply-entry@0 { | |
reg = <0x0>; | |
qcom,supply-name = "wqhd-vddio"; | |
qcom,supply-min-voltage = <0x1b7740>; | |
qcom,supply-max-voltage = <0x1b7740>; | |
qcom,supply-enable-load = <0x7d00>; | |
qcom,supply-disable-load = <0x50>; | |
qcom,supply-post-on-sleep = <0x1>; | |
qcom,supply-pre-off-sleep = <0xf>; | |
}; | |
qcom,panel-supply-entry@1 { | |
reg = <0x1>; | |
qcom,supply-name = "lab"; | |
qcom,supply-min-voltage = <0x4630c0>; | |
qcom,supply-max-voltage = <0x5b8d80>; | |
qcom,supply-enable-load = <0x186a0>; | |
qcom,supply-disable-load = <0x64>; | |
}; | |
qcom,panel-supply-entry@2 { | |
reg = <0x2>; | |
qcom,supply-name = "ibb"; | |
qcom,supply-min-voltage = <0x4630c0>; | |
qcom,supply-max-voltage = <0x5b8d80>; | |
qcom,supply-enable-load = <0x186a0>; | |
qcom,supply-disable-load = <0x64>; | |
qcom,supply-pre-off-sleep = <0x5>; | |
}; | |
}; | |
dsi_panel_pwr_supply_ebbg_ft8716 { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
qcom,panel-supply-entry@0 { | |
reg = <0x0>; | |
qcom,supply-name = "wqhd-vddio"; | |
qcom,supply-min-voltage = <0x1b7740>; | |
qcom,supply-max-voltage = <0x1b7740>; | |
qcom,supply-enable-load = <0x7d00>; | |
qcom,supply-disable-load = <0x50>; | |
qcom,supply-post-on-sleep = <0xa>; | |
qcom,supply-pre-off-sleep = <0x5>; | |
}; | |
qcom,panel-supply-entry@1 { | |
reg = <0x1>; | |
qcom,supply-name = "lab"; | |
qcom,supply-min-voltage = <0x4630c0>; | |
qcom,supply-max-voltage = <0x5b8d80>; | |
qcom,supply-enable-load = <0x186a0>; | |
qcom,supply-disable-load = <0x64>; | |
qcom,supply-post-on-sleep = <0x2>; | |
}; | |
qcom,panel-supply-entry@2 { | |
reg = <0x2>; | |
qcom,supply-name = "ibb"; | |
qcom,supply-min-voltage = <0x4630c0>; | |
qcom,supply-max-voltage = <0x5b8d80>; | |
qcom,supply-enable-load = <0x186a0>; | |
qcom,supply-disable-load = <0x64>; | |
qcom,supply-pre-off-sleep = <0x1>; | |
}; | |
}; | |
dsi_panel_pwr_supply_amoled { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
linux,phandle = <0x1d6>; | |
phandle = <0x1d6>; | |
qcom,panel-supply-entry@0 { | |
reg = <0x0>; | |
qcom,supply-name = "wqhd-vddio"; | |
qcom,supply-min-voltage = <0x1b7740>; | |
qcom,supply-max-voltage = <0x1b7740>; | |
qcom,supply-enable-load = <0x7d00>; | |
qcom,supply-disable-load = <0x50>; | |
#qcom,supply-post-on-sleep = <0x5>; | |
}; | |
qcom,panel-supply-entry@1 { | |
reg = <0x0>; | |
qcom,supply-name = "vpnl"; | |
qcom,supply-min-voltage = <0x2dc6c0>; | |
qcom,supply-max-voltage = <0x2dc6c0>; | |
qcom,supply-enable-load = <0x7d00>; | |
qcom,supply-disable-load = <0x50>; | |
qcom,supply-post-on-sleep = <0x5>; | |
}; | |
}; | |
dsi_panel_pwr_supply_no_labibb { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
qcom,panel-supply-entry@0 { | |
reg = <0x0>; | |
qcom,supply-name = "wqhd-vddio"; | |
qcom,supply-min-voltage = <0x1cafc0>; | |
qcom,supply-max-voltage = <0x1cafc0>; | |
qcom,supply-enable-load = <0x7d00>; | |
qcom,supply-disable-load = <0x50>; | |
}; | |
}; | |
dsi_panel_pwr_supply_lgd_td4322 { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
linux,phandle = <0x1d5>; | |
phandle = <0x1d5>; | |
qcom,panel-supply-entry@0 { | |
reg = <0x0>; | |
qcom,supply-name = "wqhd-vddio"; | |
qcom,supply-min-voltage = <0x1b7740>; | |
qcom,supply-max-voltage = <0x1b7740>; | |
qcom,supply-enable-load = <0x7d00>; | |
qcom,supply-disable-load = <0x50>; | |
qcom,supply-post-on-sleep = <0xa>; | |
qcom,supply-pre-off-sleep = <0xa>; | |
}; | |
qcom,panel-supply-entry@1 { | |
reg = <0x1>; | |
qcom,supply-name = "lab"; | |
qcom,supply-min-voltage = <0x4630c0>; | |
qcom,supply-max-voltage = <0x5b8d80>; | |
qcom,supply-enable-load = <0x186a0>; | |
qcom,supply-disable-load = <0x64>; | |
}; | |
qcom,panel-supply-entry@2 { | |
reg = <0x2>; | |
qcom,supply-name = "ibb"; | |
qcom,supply-min-voltage = <0x4630c0>; | |
qcom,supply-max-voltage = <0x5b8d80>; | |
qcom,supply-enable-load = <0x186a0>; | |
qcom,supply-disable-load = <0x64>; | |
qcom,supply-post-on-sleep = <0xa>; | |
qcom,supply-pre-off-sleep = <0x5>; | |
}; | |
}; | |
qcom,mdss_dsi_pll@c994400 { | |
compatible = "qcom,mdss_dsi_pll_8998"; | |
status = "ok"; | |
label = "MDSS DSI 0 PLL"; | |
cell-index = <0x0>; | |
#clock-cells = <0x1>; | |
reg = <0xc994a00 0x1c0 0xc994400 0x7c0 0xc8c2300 0x8>; | |
reg-names = "pll_base", "phy_base", "gdsc_base"; | |
gdsc-supply = <0x2a>; | |
clocks = <0x27 0x85d37ab5>; | |
clock-names = "iface_clk"; | |
clock-rate = <0x0>; | |
qcom,dsi-pll-ssc-en; | |
qcom,dsi-pll-ssc-mode = "down-spread"; | |
linux,phandle = <0x59>; | |
phandle = <0x59>; | |
qcom,platform-supply-entries { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
qcom,platform-supply-entry@0 { | |
reg = <0x0>; | |
qcom,supply-name = "gdsc"; | |
qcom,supply-min-voltage = <0x0>; | |
qcom,supply-max-voltage = <0x0>; | |
qcom,supply-enable-load = <0x0>; | |
qcom,supply-disable-load = <0x0>; | |
}; | |
}; | |
}; | |
qcom,mdss_dsi_pll@c996400 { | |
compatible = "qcom,mdss_dsi_pll_8998"; | |
status = "disabled"; | |
label = "MDSS DSI 1 PLL"; | |
cell-index = <0x1>; | |
#clock-cells = <0x1>; | |
reg = <0xc996a00 0x1c0 0xc996400 0x7c0 0x8c2300 0x8>; | |
reg-names = "pll_base", "phy_base", "gdsc_base"; | |
gdsc-supply = <0x2a>; | |
clocks = <0x27 0x85d37ab5>; | |
clock-names = "iface_clk"; | |
clock-rate = <0x0>; | |
qcom,dsi-pll-ssc-en; | |
qcom,dsi-pll-ssc-mode = "down-spread"; | |
linux,phandle = <0x5a>; | |
phandle = <0x5a>; | |
qcom,platform-supply-entries { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
qcom,platform-supply-entry@0 { | |
reg = <0x0>; | |
qcom,supply-name = "gdsc"; | |
qcom,supply-min-voltage = <0x0>; | |
qcom,supply-max-voltage = <0x0>; | |
qcom,supply-enable-load = <0x0>; | |
qcom,supply-disable-load = <0x0>; | |
}; | |
}; | |
}; | |
qcom,mdss_dp_pll@c011000 { | |
compatible = "qcom,mdss_dp_pll_8998"; | |
status = "ok"; | |
label = "MDSS DP PLL"; | |
cell-index = <0x0>; | |
#clock-cells = <0x1>; | |
reg = <0xc011c00 0x190 0xc011000 0x910 0xc8c2300 0x8>; | |
reg-names = "pll_base", "phy_base", "gdsc_base"; | |
gdsc-supply = <0x2a>; | |
clocks = <0x27 0x85d37ab5 0x38 0xb867b147 0x38 0xb6cc8f00>; | |
clock-names = "iface_clk", "ref_clk_src", "ref_clk"; | |
clock-rate = <0x0>; | |
linux,phandle = <0x5b>; | |
phandle = <0x5b>; | |
qcom,platform-supply-entries { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
qcom,platform-supply-entry@0 { | |
reg = <0x0>; | |
qcom,supply-name = "gdsc"; | |
qcom,supply-min-voltage = <0x0>; | |
qcom,supply-max-voltage = <0x0>; | |
qcom,supply-enable-load = <0x0>; | |
qcom,supply-disable-load = <0x0>; | |
}; | |
}; | |
}; | |
qcom,mdss_hdmi_pll@0xc9a0600 { | |
compatible = "qcom,mdss_hdmi_pll_8998"; | |
label = "MDSS HDMI PLL"; | |
cell-index = <0x2>; | |
#clock-cells = <0x1>; | |
reg = <0xc9a0600 0xb10 0xc9a1200 0xe4 0xc8c2300 0x8>; | |
reg-names = "pll_base", "phy_base", "gdsc_base"; | |
gdsc-supply = <0x2a>; | |
vdda-pll-supply = <0x67>; | |
vdda-phy-supply = <0x69>; | |
clocks = <0x27 0x85d37ab5 0x38 0x4d4eec04 0x38 0xb867b147>; | |
clock-names = "iface_clk", "ref_clk", "ref_clk_src"; | |
clock-rate = <0x0>; | |
status = "disabled"; | |
linux,phandle = <0x5c>; | |
phandle = <0x5c>; | |
qcom,platform-supply-entries { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
qcom,platform-supply-entry@0 { | |
reg = <0x0>; | |
qcom,supply-name = "gdsc"; | |
qcom,supply-min-voltage = <0x0>; | |
qcom,supply-max-voltage = <0x0>; | |
qcom,supply-enable-load = <0x0>; | |
qcom,supply-disable-load = <0x0>; | |
}; | |
qcom,platform-supply-entry@1 { | |
reg = <0x1>; | |
qcom,supply-name = "vdda-pll"; | |
qcom,supply-min-voltage = <0x124f80>; | |
qcom,supply-max-voltage = <0x124f80>; | |
qcom,supply-enable-load = <0x3778>; | |
qcom,supply-disable-load = <0x1>; | |
}; | |
qcom,platform-supply-entry@2 { | |
reg = <0x2>; | |
qcom,supply-name = "vdda-phy"; | |
qcom,supply-min-voltage = <0x1b7740>; | |
qcom,supply-max-voltage = <0x1b7740>; | |
qcom,supply-enable-load = <0x332c>; | |
qcom,supply-disable-load = <0x4>; | |
}; | |
}; | |
}; | |
qcom,smp2pgpio-rdbg-2-in { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "rdbg"; | |
qcom,remote-pid = <0x2>; | |
qcom,is-inbound; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0x1d9>; | |
phandle = <0x1d9>; | |
}; | |
qcom,smp2pgpio_client_rdbg_2_in { | |
compatible = "qcom,smp2pgpio_client_rdbg_2_in"; | |
gpios = <0x1d9 0x0 0x0>; | |
}; | |
qcom,smp2pgpio-rdbg-2-out { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "rdbg"; | |
qcom,remote-pid = <0x2>; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0x1da>; | |
phandle = <0x1da>; | |
}; | |
qcom,smp2pgpio_client_rdbg_2_out { | |
compatible = "qcom,smp2pgpio_client_rdbg_2_out"; | |
gpios = <0x1da 0x0 0x0>; | |
}; | |
qcom,smp2pgpio-rdbg-1-in { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "rdbg"; | |
qcom,remote-pid = <0x1>; | |
qcom,is-inbound; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0x1db>; | |
phandle = <0x1db>; | |
}; | |
qcom,smp2pgpio_client_rdbg_1_in { | |
compatible = "qcom,smp2pgpio_client_rdbg_1_in"; | |
gpios = <0x1db 0x0 0x0>; | |
}; | |
qcom,smp2pgpio-rdbg-1-out { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "rdbg"; | |
qcom,remote-pid = <0x1>; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0x1dc>; | |
phandle = <0x1dc>; | |
}; | |
qcom,smp2pgpio_client_rdbg_1_out { | |
compatible = "qcom,smp2pgpio_client_rdbg_1_out"; | |
gpios = <0x1dc 0x0 0x0>; | |
}; | |
qcom,smp2pgpio-rdbg-5-in { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "rdbg"; | |
qcom,remote-pid = <0x5>; | |
qcom,is-inbound; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0x1dd>; | |
phandle = <0x1dd>; | |
}; | |
qcom,smp2pgpio_client_rdbg_5_in { | |
compatible = "qcom,smp2pgpio_client_rdbg_5_in"; | |
gpios = <0x1dd 0x0 0x0>; | |
}; | |
qcom,smp2pgpio-rdbg-5-out { | |
compatible = "qcom,smp2pgpio"; | |
qcom,entry-name = "rdbg"; | |
qcom,remote-pid = <0x5>; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
linux,phandle = <0x1de>; | |
phandle = <0x1de>; | |
}; | |
qcom,smp2pgpio_client_rdbg_5_out { | |
compatible = "qcom,smp2pgpio_client_rdbg_5_out"; | |
gpios = <0x1de 0x0 0x0>; | |
}; | |
qcom,sps-dma@0xc144000 { | |
#dma-cells = <0x4>; | |
compatible = "qcom,sps-dma"; | |
reg = <0xc144000 0x25000>; | |
interrupts = <0x0 0xee 0x0>; | |
qcom,summing-threshold = <0x10>; | |
linux,phandle = <0x1df>; | |
phandle = <0x1df>; | |
}; | |
qcom,sps-dma@0xc184000 { | |
#dma-cells = <0x4>; | |
compatible = "qcom,sps-dma"; | |
reg = <0xc184000 0x25000>; | |
interrupts = <0x0 0xef 0x0>; | |
qcom,summing-threshold = <0x10>; | |
linux,phandle = <0x1f5>; | |
phandle = <0x1f5>; | |
}; | |
i2c@c175000 { | |
compatible = "qcom,i2c-msm-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "qup_phys_addr"; | |
reg = <0xc175000 0x600>; | |
interrupt-names = "qup_irq"; | |
interrupts = <0x0 0x5f 0x0>; | |
dmas = <0x1df 0x6 0x40 0x20000020 0x20 0x1df 0x7 0x20 0x20000020 0x20>; | |
dma-names = "tx", "rx"; | |
qcom,master-id = <0x56>; | |
qcom,clk-freq-out = <0x61a80>; | |
qcom,clk-freq-in = <0x124f800>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8caa5b4f 0x38 0xc303fae9>; | |
pinctrl-names = "i2c_active", "i2c_sleep"; | |
pinctrl-0 = <0x1e0>; | |
pinctrl-1 = <0x1e1>; | |
status = "disabled"; | |
}; | |
i2c@c176000 { | |
compatible = "qcom,i2c-msm-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "qup_phys_addr"; | |
reg = <0xc176000 0x600>; | |
interrupt-names = "qup_irq"; | |
interrupts = <0x0 0x60 0x0>; | |
dmas = <0x1df 0x8 0x40 0x20000020 0x20 0x1df 0x9 0x20 0x20000020 0x20>; | |
dma-names = "tx", "rx"; | |
qcom,master-id = <0x56>; | |
qcom,clk-freq-out = <0x61a80>; | |
qcom,clk-freq-in = <0x124f800>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8caa5b4f 0x38 0x1076f220>; | |
pinctrl-names = "i2c_active", "i2c_sleep"; | |
pinctrl-0 = <0x1e2>; | |
pinctrl-1 = <0x1e3>; | |
status = "disabled"; | |
}; | |
i2c@c177000 { | |
compatible = "qcom,i2c-msm-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "qup_phys_addr"; | |
reg = <0xc177000 0x600>; | |
interrupt-names = "qup_irq"; | |
interrupts = <0x0 0x61 0x0>; | |
dmas = <0x1df 0xa 0x40 0x20000020 0x20 0x1df 0xb 0x20 0x20000020 0x20>; | |
dma-names = "tx", "rx"; | |
qcom,master-id = <0x56>; | |
qcom,clk-freq-out = <0x61a80>; | |
qcom,clk-freq-in = <0x124f800>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8caa5b4f 0x38 0x9e25ac82>; | |
pinctrl-names = "i2c_active", "i2c_sleep"; | |
pinctrl-0 = <0x1e4>; | |
pinctrl-1 = <0x1e5>; | |
status = "disabled"; | |
}; | |
i2c@c178000 { | |
compatible = "qcom,i2c-msm-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "qup_phys_addr"; | |
reg = <0xc178000 0x600>; | |
interrupt-names = "qup_irq"; | |
interrupts = <0x0 0x62 0x0>; | |
dmas = <0x1df 0xc 0x40 0x20000020 0x20 0x1df 0xd 0x20 0x20000020 0x20>; | |
dma-names = "tx", "rx"; | |
qcom,master-id = <0x56>; | |
qcom,clk-freq-out = <0x61a80>; | |
qcom,clk-freq-in = <0x124f800>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8caa5b4f 0x38 0xd7f40f6f>; | |
pinctrl-names = "i2c_active", "i2c_sleep"; | |
pinctrl-0 = <0x1e6>; | |
pinctrl-1 = <0x1e7>; | |
status = "disabled"; | |
}; | |
i2c@c179000 { | |
compatible = "qcom,i2c-msm-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "qup_phys_addr"; | |
reg = <0xc179000 0x600>; | |
interrupt-names = "qup_irq"; | |
interrupts = <0x0 0x63 0x0>; | |
dmas = <0x1df 0xe 0x40 0x20000020 0x20 0x1df 0xf 0x20 0x20000020 0x20>; | |
dma-names = "tx", "rx"; | |
qcom,master-id = <0x56>; | |
qcom,clk-freq-out = <0x61a80>; | |
qcom,clk-freq-in = <0x124f800>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8caa5b4f 0x38 0xacae5604>; | |
pinctrl-names = "i2c_active", "i2c_sleep"; | |
pinctrl-0 = <0x1e8>; | |
pinctrl-1 = <0x1e9>; | |
status = "okay"; | |
synaptics_dsi_i2c@20 { | |
compatible = "synaptics,dsx-i2c-force"; | |
reg = <0x20>; | |
interrupt-parent = <0x7c>; | |
interrupts = <0x7d 0x2008>; | |
vdd-supply = <0x1ea>; | |
lab-supply = <0x1c4>; | |
ibb-supply = <0x1c5>; | |
disp-supply = <0x68>; | |
avdd-supply = <0x1eb>; | |
synaptics,pwr-reg-name = "vdd"; | |
synaptics,lab-reg-name = "lab"; | |
synaptics,ibb-reg-name = "ibb"; | |
synaptics,disp-reg-name = "disp"; | |
synaptics,bus-reg-name = "avdd"; | |
synaptics,ub-i2c-addr = <0x2c>; | |
pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; | |
pinctrl-0 = <0x1ec>; | |
pinctrl-1 = <0x1ed 0x1ee>; | |
synaptics,mdss-dsi-reset = <0x7c 0x8 0x0>; | |
synaptics,reset-gpio = <0x7c 0x59 0x0>; | |
synaptics,irq-gpio = <0x7c 0x7d 0x2008>; | |
synaptics,reset-gpio-name = "dsx_reset"; | |
synaptics,irq-gpio-name = "dsx_irq"; | |
synaptics,irq-on-state = <0x0>; | |
synaptics,irq-flags = <0x2008>; | |
synaptics,power-delay-ms = <0x5>; | |
synaptics,reset-delay-ms = <0xc8>; | |
synaptics,reset-active-ms = <0x5>; | |
synaptics,power-on-state = <0x1>; | |
synaptics,reset-on-state = <0x0>; | |
synaptics,mdss-reset-state = <0x1>; | |
synaptics,panel-is-incell; | |
synaptics,cap-button-codes = <0x9e 0x8b 0x66>; | |
synaptics,short-jdi-25 = "000: 0xfb\n001: 0xef\n002: 0xff\n003: 0xff\n004: 0x18\n005: 0x00\n006: 0x00"; | |
synaptics,short-jdi-26 = "000: 0x03\n001: 0x00\n002: 0x00\n003: 0x00\n004: 0x00\n005: 0x00\n006: 0x00"; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8caa5b4f 0x38 0xacae5604>; | |
synaptics,guest-serialization-as-lockdown; | |
synaptics,tp-id-byte = [00]; | |
synaptics,config-array-size = <0x3>; | |
synaptics,cfg_1 { | |
synaptics,chip-id = <0x0>; | |
synaptics,chip-id-name = "S3330"; | |
synaptics,tp-id = [31]; | |
synaptics,fw-name = "synaptics_jdi_3330_c1.fw"; | |
}; | |
synaptics,cfg_2 { | |
synaptics,chip-id = <0x1>; | |
synaptics,chip-id-name = "S3331"; | |
synaptics,tp-id = [31]; | |
synaptics,fw-name = "synaptics_jdi_3331_c1.fw"; | |
}; | |
synaptics,cfg_3 { | |
synaptics,chip-id = <0x2>; | |
synaptics,chip-id-name = "TD4322"; | |
synaptics,chip-is-tddi; | |
synaptics,factory-param; | |
synaptics,tddi-short-limit_b = <0x96>; | |
synaptics,tddi-noise-limit = <0x3c>; | |
synaptics,tddi-extend-ee-short-reset-dur = <0x3c>; | |
synaptics,tddi-extend-ee-short-int_dur = <0x96>; | |
synaptics,tddi-extend-ee-short-tx-on-count = <0x92>; | |
synaptics,tddi-extend-ee-short-rx-on-count = <0x92>; | |
synaptics,tddi-extend-ee-short-test-limit-part1 = <0xb4>; | |
synaptics,tddi-extend-ee-short-test-limit-part2 = <0x0>; | |
synaptics,tddi-open-test-int-dur-one = <0x91>; | |
synaptics,tddi-open-test-int-dur-two = <0xf>; | |
synaptics,tddi-open-test-limit-phase2-lower = <0x32>; | |
synaptics,tddi-b7-open-test-int-dur-one = <0x17>; | |
synaptics,tddi-b7-open-test-int-dur-two = <0x1b>; | |
synaptics,tddi-b7-open-test-limit-phase2-lower = <0x0>; | |
synaptics,tddi-b7-open-test-limit-phase2-upper = <0x73>; | |
synaptics,button-count = <0x2>; | |
synaptics,abs-0d-open-factor = <0x9>; | |
synaptics,abs-0d-open-test-limit = <0x1e>; | |
synaptics,elec-open-test-tx-on-count = <0x2>; | |
synaptics,elec-open-test-rx-on-count = <0x2>; | |
synaptics,elec-open-int-dur-one = <0xa>; | |
synaptics,elec-open-int-dur-two = <0xf>; | |
synaptics,elec-open-test-limit-one = <0x0>; | |
synaptics,elec-open-test-limit-two = <0x32>; | |
synaptics,disp-pre-on-sleep = <0xa>; | |
synaptics,disp-post-on-sleep = <0xa>; | |
synaptics,disp-pre-off-sleep = <0xa>; | |
synaptics,disp-post-off-sleep = <0x0>; | |
synaptics,lab-pre-on-sleep = <0x0>; | |
synaptics,lab-post-on-sleep = <0xa>; | |
synaptics,lab-pre-off-sleep = <0xa>; | |
synaptics,lab-post-off-sleep = <0x0>; | |
synaptics,ibb-pre-on-sleep = <0x0>; | |
synaptics,ibb-post-on-sleep = <0xa>; | |
synaptics,ibb-pre-off-sleep = <0xa>; | |
synaptics,ibb-post-off-sleep = <0x0>; | |
synaptics,tp-id = [34]; | |
synaptics,fw-name = "synaptics_lgd_4322_c1.fw"; | |
}; | |
}; | |
}; | |
i2c@c17a000 { | |
compatible = "qcom,i2c-msm-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "qup_phys_addr"; | |
reg = <0xc17a000 0x600>; | |
interrupt-names = "qup_irq"; | |
interrupts = <0x0 0x64 0x0>; | |
dmas = <0x1df 0x10 0x40 0x20000020 0x20 0x1df 0x11 0x20 0x20000020 0x20>; | |
dma-names = "tx", "rx"; | |
qcom,master-id = <0x56>; | |
qcom,clk-freq-out = <0x61a80>; | |
qcom,clk-freq-in = <0x124f800>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8caa5b4f 0x38 0x5c6ad820>; | |
pinctrl-names = "i2c_active", "i2c_sleep"; | |
pinctrl-0 = <0x1ef>; | |
pinctrl-1 = <0x1f0>; | |
status = "okay"; | |
nq@28 { | |
compatible = "qcom,nq-nci"; | |
reg = <0x28>; | |
qcom,nq-irq = <0x7c 0x5c 0x0>; | |
qcom,nq-ven = <0x7c 0xc 0x0>; | |
qcom,nq-firm = <0x7c 0x5d 0x0>; | |
qcom,nq-clkreq = <0x8f 0x15 0x0>; | |
qcom,nq-esepwr = <0x7c 0x74 0x0>; | |
interrupt-parent = <0x7c>; | |
qcom,clk-src = "BBCLK3"; | |
interrupts = <0x5c 0x0>; | |
interrupt-names = "nfc_irq"; | |
pinctrl-names = "nfc_active", "nfc_suspend"; | |
pinctrl-0 = <0x1f1 0x1f2>; | |
pinctrl-1 = <0x1f3 0x1f4>; | |
clocks = <0x38 0xc4de7dad>; | |
clock-names = "ref_clk"; | |
}; | |
}; | |
i2c@c1b5000 { | |
compatible = "qcom,i2c-msm-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "qup_phys_addr"; | |
reg = <0xc1b5000 0x600>; | |
interrupt-names = "qup_irq"; | |
interrupts = <0x0 0x65 0x0>; | |
dmas = <0x1f5 0x6 0x40 0x20000020 0x20 0x1f5 0x7 0x20 0x20000020 0x20>; | |
dma-names = "tx", "rx"; | |
qcom,master-id = <0x54>; | |
qcom,clk-freq-out = <0x61a80>; | |
qcom,clk-freq-in = <0x124f800>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8f283c1d 0x38 0x9ace11dd>; | |
pinctrl-names = "i2c_active", "i2c_sleep"; | |
pinctrl-0 = <0x1f6>; | |
pinctrl-1 = <0x1f7>; | |
status = "okay"; | |
qcom,smb138x@8 { | |
compatible = "qcom,i2c-pmic"; | |
reg = <0x8>; | |
#address-cells = <0x2>; | |
#size-cells = <0x0>; | |
interrupt-parent = <0x1f8>; | |
interrupts = <0x0 0xd1 0x0 0x8>; | |
interrupt_names = "smb138x"; | |
interrupt-controller; | |
#interrupt-cells = <0x3>; | |
qcom,periph-map = <0x10 0x11 0x12 0x13 0x14 0x16 0x36>; | |
linux,phandle = <0x1f9>; | |
phandle = <0x1f9>; | |
qcom,revid@100 { | |
compatible = "qcom,qpnp-revid"; | |
reg = <0x100 0x100>; | |
linux,phandle = <0x1fa>; | |
phandle = <0x1fa>; | |
}; | |
qcom,tadc@3600 { | |
compatible = "qcom,tadc"; | |
reg = <0x3600 0x100>; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
#io-channel-cells = <0x1>; | |
interrupt-parent = <0x1f9>; | |
interrupts = <0x36 0x0 0x3>; | |
interrupt-names = "eoc"; | |
linux,phandle = <0x1fb>; | |
phandle = <0x1fb>; | |
batt_temp@0 { | |
reg = <0x0>; | |
qcom,rbias = <0x10a04>; | |
qcom,rtherm-at-25degc = <0x109a0>; | |
qcom,beta-coefficient = <0xd7a>; | |
}; | |
skin_temp@1 { | |
reg = <0x1>; | |
qcom,rbias = <0x80e8>; | |
qcom,rtherm-at-25degc = <0x109a0>; | |
qcom,beta-coefficient = <0xd7a>; | |
}; | |
die_temp@2 { | |
reg = <0x2>; | |
qcom,scale = <0xfffffae6>; | |
qcom,offset = <0x61250>; | |
}; | |
batt_i@3 { | |
reg = <0x3>; | |
qcom,channel = <0x3>; | |
qcom,scale = <0xfeced300>; | |
}; | |
batt_v@4 { | |
reg = <0x4>; | |
qcom,scale = <0x4c4b40>; | |
}; | |
input_i@5 { | |
reg = <0x5>; | |
qcom,scale = <0xd9fb92>; | |
}; | |
input_v@6 { | |
reg = <0x6>; | |
qcom,scale = <0x17d7840>; | |
}; | |
otg_i@7 { | |
reg = <0x7>; | |
qcom,scale = <0x57316e>; | |
}; | |
}; | |
qcom,smb138x-parallel-slave@1000 { | |
compatible = "qcom,smb138x-parallel-slave"; | |
qcom,pmic-revid = <0x1fa>; | |
reg = <0x1000 0x700>; | |
#address-cells = <0x1>; | |
#size-cells = <0x1>; | |
interrupt-parent = <0x1f9>; | |
io-channels = <0x1fb 0x1 0x1fb 0x2 0x1fb 0x3 0x1fb 0xe 0x1fb 0xf 0x1fb 0x10 0x1fb 0x11>; | |
io-channel-names = "connector_temp", "charger_temp", "batt_i", "connector_temp_thr1", "connector_temp_thr2", "connector_temp_thr3", "charger_temp_max"; | |
qcom,chgr@1000 { | |
reg = <0x1000 0x100>; | |
interrupts = <0x10 0x1 0x1>; | |
interrupt-names = "chg-state-change"; | |
}; | |
qcom,chgr-misc@1600 { | |
reg = <0x1600 0x100>; | |
interrupts = <0x16 0x1 0x1 0x16 0x6 0x1>; | |
interrupt-names = "wdog-bark", "temperature-change"; | |
}; | |
qcom,smb138x-vbus { | |
status = "disabled"; | |
regulator-name = "smb138x-vbus"; | |
}; | |
}; | |
}; | |
}; | |
i2c@c1b6000 { | |
compatible = "qcom,i2c-msm-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "qup_phys_addr"; | |
reg = <0xc1b6000 0x600>; | |
interrupt-names = "qup_irq"; | |
interrupts = <0x0 0x66 0x0>; | |
dmas = <0x1f5 0x8 0x40 0x20000020 0x20 0x1f5 0x9 0x20 0x20000020 0x20>; | |
dma-names = "tx", "rx"; | |
qcom,master-id = <0x54>; | |
qcom,clk-freq-out = <0x61a80>; | |
qcom,clk-freq-in = <0x124f800>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8f283c1d 0x38 0x1bf9a57e>; | |
pinctrl-names = "i2c_active", "i2c_sleep"; | |
pinctrl-0 = <0x1fc>; | |
pinctrl-1 = <0x1fd>; | |
status = "disabled"; | |
}; | |
i2c@c1b7000 { | |
compatible = "qcom,i2c-msm-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "qup_phys_addr"; | |
reg = <0xc1b7000 0x600>; | |
interrupt-names = "qup_irq"; | |
interrupts = <0x0 0x67 0x0>; | |
dmas = <0x1f5 0xa 0x40 0x20000020 0x20 0x1f5 0xb 0x20 0x20000020 0x20>; | |
dma-names = "tx", "rx"; | |
qcom,master-id = <0x54>; | |
qcom,clk-freq-out = <0x61a80>; | |
qcom,clk-freq-in = <0x124f800>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8f283c1d 0x38 0x336d4170>; | |
pinctrl-names = "i2c_active", "i2c_sleep"; | |
pinctrl-0 = <0x1fe>; | |
pinctrl-1 = <0x1ff>; | |
status = "disabled"; | |
}; | |
i2c@c1b8000 { | |
compatible = "qcom,i2c-msm-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "qup_phys_addr"; | |
reg = <0xc1b8000 0x600>; | |
interrupt-names = "qup_irq"; | |
interrupts = <0x0 0x68 0x0>; | |
dmas = <0x1f5 0xc 0x40 0x20000020 0x20 0x1f5 0xd 0x20 0x20000020 0x20>; | |
dma-names = "tx", "rx"; | |
qcom,master-id = <0x54>; | |
qcom,clk-freq-out = <0x61a80>; | |
qcom,clk-freq-in = <0x124f800>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8f283c1d 0x38 0xbd22539d>; | |
pinctrl-names = "i2c_active", "i2c_sleep"; | |
pinctrl-0 = <0x200>; | |
pinctrl-1 = <0x201>; | |
status = "okay"; | |
tfa98xx@34 { | |
compatible = "nxp,tfa98xx"; | |
reg = <0x34>; | |
reset-gpio = <0x7c 0x29 0x0>; | |
irq-gpio = <0x7c 0x2a 0x0>; | |
spk-id = <0x202>; | |
}; | |
}; | |
i2c@c1b9000 { | |
compatible = "qcom,i2c-msm-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "qup_phys_addr"; | |
reg = <0xc1b9000 0x600>; | |
interrupt-names = "qup_irq"; | |
interrupts = <0x0 0x69 0x0>; | |
dmas = <0x1f5 0xe 0x40 0x20000020 0x20 0x1f5 0xf 0x20 0x20000020 0x20>; | |
dma-names = "tx", "rx"; | |
qcom,master-id = <0x54>; | |
qcom,clk-freq-out = <0x61a80>; | |
qcom,clk-freq-in = <0x124f800>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8f283c1d 0x38 0xe2b2ce1d>; | |
pinctrl-names = "i2c_active", "i2c_sleep"; | |
pinctrl-0 = <0x203>; | |
pinctrl-1 = <0x204>; | |
status = "disabled"; | |
}; | |
i2c@c1ba000 { | |
compatible = "qcom,i2c-msm-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "qup_phys_addr"; | |
reg = <0xc1ba000 0x600>; | |
interrupt-names = "qup_irq"; | |
interrupts = <0x0 0x6a 0x0>; | |
dmas = <0x1f5 0x10 0x40 0x20000020 0x20 0x1f5 0x11 0x20 0x20000020 0x20>; | |
dma-names = "tx", "rx"; | |
qcom,master-id = <0x54>; | |
qcom,clk-freq-out = <0x61a80>; | |
qcom,clk-freq-in = <0x124f800>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8f283c1d 0x38 0x894bcea4>; | |
pinctrl-names = "i2c_active", "i2c_sleep"; | |
pinctrl-0 = <0x205>; | |
pinctrl-1 = <0x206>; | |
status = "disabled"; | |
}; | |
spi@c175000 { | |
compatible = "qcom,spi-qup-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "spi_physical", "spi_bam_physical"; | |
reg = <0xc175000 0x600 0xc144000 0x25000>; | |
interrupt-names = "spi_irq", "spi_bam_irq"; | |
interrupts = <0x0 0x5f 0x0 0x0 0xee 0x0>; | |
spi-max-frequency = <0x2faf080>; | |
qcom,use-bam; | |
qcom,ver-reg-exists; | |
qcom,bam-consumer-pipe-index = <0x6>; | |
qcom,bam-producer-pipe-index = <0x7>; | |
qcom,master-id = <0x56>; | |
qcom,use-pinctrl; | |
pinctrl-names = "spi_default", "spi_sleep"; | |
pinctrl-0 = <0x207>; | |
pinctrl-1 = <0x208>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8caa5b4f 0x38 0x759a76b0>; | |
status = "disabled"; | |
}; | |
spi@c176000 { | |
compatible = "qcom,spi-qup-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "spi_physical", "spi_bam_physical"; | |
reg = <0xc176000 0x600 0xc144000 0x25000>; | |
interrupt-names = "spi_irq", "spi_bam_irq"; | |
interrupts = <0x0 0x60 0x0 0x0 0xee 0x0>; | |
spi-max-frequency = <0x124f800>; | |
qcom,use-bam; | |
qcom,ver-reg-exists; | |
qcom,bam-consumer-pipe-index = <0x8>; | |
qcom,bam-producer-pipe-index = <0x9>; | |
qcom,master-id = <0x56>; | |
qcom,use-pinctrl; | |
pinctrl-names = "spi_default", "spi_sleep"; | |
pinctrl-0 = <0x209>; | |
pinctrl-1 = <0x20a>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8caa5b4f 0x38 0x3e77d48f>; | |
status = "ok"; | |
peel_ir@0 { | |
compatible = "peel_ir"; | |
reg = <0x0>; | |
spi-max-frequency = <0x124f800>; | |
peel_ir,lr-gpio = <0x49>; | |
peel_ir,lr-gpio-valid = <0x1>; | |
peel_ir,spi-bpw = <0x20>; | |
peel_ir,spi-clk-speed = <0xea600>; | |
peel_ir,spi-mode = <0x0>; | |
peel_ir,peel-field = <0x929>; | |
status = "ok"; | |
}; | |
}; | |
spi@c177000 { | |
compatible = "qcom,spi-qup-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "spi_physical", "spi_bam_physical"; | |
reg = <0xc177000 0x600 0xc144000 0x25000>; | |
interrupt-names = "spi_irq", "spi_bam_irq"; | |
interrupts = <0x0 0x61 0x0 0x0 0xee 0x0>; | |
spi-max-frequency = <0x2faf080>; | |
qcom,use-bam; | |
qcom,ver-reg-exists; | |
qcom,bam-consumer-pipe-index = <0xa>; | |
qcom,bam-producer-pipe-index = <0xb>; | |
qcom,master-id = <0x56>; | |
qcom,use-pinctrl; | |
pinctrl-names = "spi_default", "spi_sleep"; | |
pinctrl-0 = <0x20b>; | |
pinctrl-1 = <0x20c>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8caa5b4f 0x38 0xfb978880>; | |
status = "disabled"; | |
}; | |
spi@c178000 { | |
compatible = "qcom,spi-qup-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "spi_physical", "spi_bam_physical"; | |
reg = <0xc178000 0x600 0xc144000 0x25000>; | |
interrupt-names = "spi_irq", "spi_bam_irq"; | |
interrupts = <0x0 0x62 0x0 0x0 0xee 0x0>; | |
spi-max-frequency = <0x2faf080>; | |
qcom,use-bam; | |
qcom,ver-reg-exists; | |
qcom,bam-consumer-pipe-index = <0xc>; | |
qcom,bam-producer-pipe-index = <0xd>; | |
qcom,master-id = <0x56>; | |
qcom,use-pinctrl; | |
pinctrl-names = "spi_default", "spi_sleep"; | |
pinctrl-0 = <0x20d>; | |
pinctrl-1 = <0x20e>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8caa5b4f 0x38 0x80f8722f>; | |
status = "disabled"; | |
}; | |
spi@c179000 { | |
compatible = "qcom,spi-qup-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "spi_physical", "spi_bam_physical"; | |
reg = <0xc179000 0x600 0xc144000 0x25000>; | |
interrupt-names = "spi_irq", "spi_bam_irq"; | |
interrupts = <0x0 0x63 0x0 0x0 0xee 0x0>; | |
spi-max-frequency = <0x2faf080>; | |
qcom,use-bam; | |
qcom,ver-reg-exists; | |
qcom,bam-consumer-pipe-index = <0xe>; | |
qcom,bam-producer-pipe-index = <0xf>; | |
qcom,master-id = <0x56>; | |
qcom,use-pinctrl; | |
pinctrl-names = "spi_default", "spi_sleep"; | |
pinctrl-0 = <0x20f>; | |
pinctrl-1 = <0x210>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8caa5b4f 0x38 0xbf3e15d7>; | |
status = "disabled"; | |
}; | |
spi@c17a000 { | |
compatible = "qcom,spi-qup-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "spi_physical", "spi_bam_physical"; | |
reg = <0xc17a000 0x600 0xc144000 0x25000>; | |
interrupt-names = "spi_irq", "spi_bam_irq"; | |
interrupts = <0x0 0x64 0x0 0x0 0xee 0x0>; | |
spi-max-frequency = <0x2faf080>; | |
qcom,use-bam; | |
qcom,ver-reg-exists; | |
qcom,bam-consumer-pipe-index = <0x10>; | |
qcom,bam-producer-pipe-index = <0x11>; | |
qcom,master-id = <0x56>; | |
qcom,use-pinctrl; | |
pinctrl-names = "spi_default", "spi_sleep"; | |
pinctrl-0 = <0x211>; | |
pinctrl-1 = <0x212>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8caa5b4f 0x38 0x780d9f85>; | |
status = "disabled"; | |
}; | |
spi@c1b5000 { | |
compatible = "qcom,spi-qup-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "spi_physical", "spi_bam_physical"; | |
reg = <0xc1b5000 0x600 0xc184000 0x25000>; | |
interrupt-names = "spi_irq", "spi_bam_irq"; | |
interrupts = <0x0 0x65 0x0 0x0 0xef 0x0>; | |
spi-max-frequency = <0x2faf080>; | |
qcom,use-bam; | |
qcom,ver-reg-exists; | |
qcom,bam-consumer-pipe-index = <0x6>; | |
qcom,bam-producer-pipe-index = <0x7>; | |
qcom,master-id = <0x54>; | |
qcom,use-pinctrl; | |
pinctrl-names = "spi_default", "spi_sleep"; | |
pinctrl-0 = <0x213>; | |
pinctrl-1 = <0x214>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8f283c1d 0x38 0xa32604cc>; | |
status = "disabled"; | |
}; | |
spi@c1b6000 { | |
compatible = "qcom,spi-qup-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "spi_physical", "spi_bam_physical"; | |
reg = <0xc1b6000 0x600 0xc184000 0x25000>; | |
interrupt-names = "spi_irq", "spi_bam_irq"; | |
interrupts = <0x0 0x66 0x0 0x0 0xef 0x0>; | |
spi-max-frequency = <0x2faf080>; | |
qcom,use-bam; | |
qcom,ver-reg-exists; | |
qcom,bam-consumer-pipe-index = <0x8>; | |
qcom,bam-producer-pipe-index = <0x9>; | |
qcom,master-id = <0x54>; | |
qcom,use-pinctrl; | |
pinctrl-names = "spi_default", "spi_sleep"; | |
pinctrl-0 = <0x215>; | |
pinctrl-1 = <0x216>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8f283c1d 0x38 0xbf54ca6d>; | |
status = "disabled"; | |
}; | |
spi@c1b7000 { | |
compatible = "qcom,spi-qup-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "spi_physical", "spi_bam_physical"; | |
reg = <0xc1b7000 0x600 0xc184000 0x25000>; | |
interrupt-names = "spi_irq", "spi_bam_irq"; | |
interrupts = <0x0 0x67 0x0 0x0 0xef 0x0>; | |
spi-max-frequency = <0x2faf080>; | |
qcom,use-bam; | |
qcom,ver-reg-exists; | |
qcom,bam-consumer-pipe-index = <0xa>; | |
qcom,bam-producer-pipe-index = <0xb>; | |
qcom,master-id = <0x54>; | |
qcom,use-pinctrl; | |
pinctrl-names = "spi_default", "spi_sleep"; | |
pinctrl-0 = <0x217>; | |
pinctrl-1 = <0x218>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8f283c1d 0x38 0xc68509d6>; | |
status = "disabled"; | |
}; | |
spi@c1b8000 { | |
compatible = "qcom,spi-qup-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "spi_physical", "spi_bam_physical"; | |
reg = <0xc1b8000 0x600 0xc184000 0x25000>; | |
interrupt-names = "spi_irq", "spi_bam_irq"; | |
interrupts = <0x0 0x68 0x0 0x0 0xef 0x0>; | |
spi-max-frequency = <0x2faf080>; | |
qcom,use-bam; | |
qcom,ver-reg-exists; | |
qcom,bam-consumer-pipe-index = <0xc>; | |
qcom,bam-producer-pipe-index = <0xd>; | |
qcom,master-id = <0x54>; | |
qcom,use-pinctrl; | |
pinctrl-names = "spi_default", "spi_sleep"; | |
pinctrl-0 = <0x219>; | |
pinctrl-1 = <0x21a>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8f283c1d 0x38 0x1a72b93>; | |
status = "ok"; | |
}; | |
spi@c1b9000 { | |
compatible = "qcom,spi-qup-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "spi_physical", "spi_bam_physical"; | |
reg = <0xc1b9000 0x600 0xc184000 0x25000>; | |
interrupt-names = "spi_irq", "spi_bam_irq"; | |
interrupts = <0x0 0x69 0x0 0x0 0xef 0x0>; | |
spi-max-frequency = <0x2faf080>; | |
qcom,use-bam; | |
qcom,ver-reg-exists; | |
qcom,bam-consumer-pipe-index = <0xe>; | |
qcom,bam-producer-pipe-index = <0xf>; | |
qcom,master-id = <0x54>; | |
qcom,use-pinctrl; | |
pinctrl-names = "spi_default", "spi_sleep"; | |
pinctrl-0 = <0x21b>; | |
pinctrl-1 = <0x21c>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8f283c1d 0x38 0xf40999cd>; | |
status = "disabled"; | |
}; | |
spi@c1ba000 { | |
compatible = "qcom,spi-qup-v2"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg-names = "spi_physical", "spi_bam_physical"; | |
reg = <0xc1ba000 0x600 0xc184000 0x25000>; | |
interrupt-names = "spi_irq", "spi_bam_irq"; | |
interrupts = <0x0 0x6a 0x0 0x0 0xef 0x0>; | |
spi-max-frequency = <0x2faf080>; | |
qcom,use-bam; | |
qcom,ver-reg-exists; | |
qcom,bam-consumer-pipe-index = <0x10>; | |
qcom,bam-producer-pipe-index = <0x11>; | |
qcom,master-id = <0x54>; | |
qcom,use-pinctrl; | |
pinctrl-names = "spi_default", "spi_sleep"; | |
pinctrl-0 = <0x21d>; | |
pinctrl-1 = <0x21e>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8f283c1d 0x38 0xfe1bd34a>; | |
status = "disabled"; | |
}; | |
uart@c16f000 { | |
compatible = "qcom,msm-hsuart-v14"; | |
reg = <0xc16f000 0x200 0xc144000 0x25000>; | |
reg-names = "core_mem", "bam_mem"; | |
interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; | |
#address-cells = <0x0>; | |
interrupt-parent = <0x21f>; | |
interrupts = <0x0 0x1 0x2>; | |
#interrupt-cells = <0x1>; | |
interrupt-map-mask = <0xffffffff>; | |
interrupt-map = <0x0 0x1 0x0 0x0 0x6b 0x0 0x1 0x1 0x0 0x0 0xee 0x0 0x2 0x7c 0x1 0x0>; | |
qcom,inject-rx-on-wakeup; | |
qcom,rx-char-to-inject = <0xfd>; | |
qcom,bam-tx-ep-pipe-index = <0x0>; | |
qcom,bam-rx-ep-pipe-index = <0x1>; | |
qcom,master-id = <0x56>; | |
clock-names = "core_clk", "iface_clk"; | |
clocks = <0x38 0xc7c62f90 0x38 0x8caa5b4f>; | |
pinctrl-names = "sleep", "default"; | |
pinctrl-0 = <0x220>; | |
pinctrl-1 = <0x221>; | |
qcom,msm-bus,name = "buart1"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x56 0x200 0x0 0x0 0x56 0x200 0x1f4 0x320>; | |
status = "disabled"; | |
linux,phandle = <0x21f>; | |
phandle = <0x21f>; | |
}; | |
uart@c170000 { | |
compatible = "qcom,msm-hsuart-v14"; | |
reg = <0xc170000 0x200 0xc144000 0x25000>; | |
reg-names = "core_mem", "bam_mem"; | |
interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; | |
#address-cells = <0x0>; | |
interrupt-parent = <0x222>; | |
interrupts = <0x0 0x1 0x2>; | |
#interrupt-cells = <0x1>; | |
interrupt-map-mask = <0xffffffff>; | |
interrupt-map = <0x0 0x1 0x0 0x0 0x6c 0x0 0x1 0x1 0x0 0x0 0xee 0x0 0x2 0x7c 0x22 0x0>; | |
qcom,inject-rx-on-wakeup; | |
qcom,rx-char-to-inject = <0xfd>; | |
qcom,bam-tx-ep-pipe-index = <0x2>; | |
qcom,bam-rx-ep-pipe-index = <0x3>; | |
qcom,master-id = <0x56>; | |
clock-names = "core_clk", "iface_clk"; | |
clocks = <0x38 0xf8a61c96 0x38 0x8caa5b4f>; | |
pinctrl-names = "sleep", "default"; | |
pinctrl-0 = <0x223>; | |
pinctrl-1 = <0x224>; | |
qcom,msm-bus,name = "buart2"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x56 0x200 0x0 0x0 0x56 0x200 0x1f4 0x320>; | |
status = "disabled"; | |
linux,phandle = <0x222>; | |
phandle = <0x222>; | |
}; | |
uart@c171000 { | |
compatible = "qcom,msm-hsuart-v14"; | |
reg = <0xc171000 0x200 0xc144000 0x25000>; | |
reg-names = "core_mem", "bam_mem"; | |
interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; | |
#address-cells = <0x0>; | |
interrupt-parent = <0x225>; | |
interrupts = <0x0 0x1 0x2>; | |
#interrupt-cells = <0x1>; | |
interrupt-map-mask = <0xffffffff>; | |
interrupt-map = <0x0 0x1 0x0 0x0 0x6d 0x0 0x1 0x1 0x0 0x0 0xee 0x0 0x2 0x7c 0x2e 0x0>; | |
qcom,inject-rx-on-wakeup; | |
qcom,rx-char-to-inject = <0xfd>; | |
qcom,bam-tx-ep-pipe-index = <0x4>; | |
qcom,bam-rx-ep-pipe-index = <0x5>; | |
qcom,master-id = <0x56>; | |
clock-names = "core_clk", "iface_clk"; | |
clocks = <0x38 0xc3298bd7 0x38 0x8caa5b4f>; | |
pinctrl-names = "sleep", "default"; | |
pinctrl-0 = <0x226 0x227 0x228>; | |
pinctrl-1 = <0x229 0x22a 0x22b>; | |
qcom,msm-bus,name = "buart3"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x56 0x200 0x0 0x0 0x56 0x200 0x1f4 0x320>; | |
status = "ok"; | |
linux,phandle = <0x225>; | |
phandle = <0x225>; | |
}; | |
uart@c1af000 { | |
compatible = "qcom,msm-hsuart-v14"; | |
reg = <0xc1af000 0x200 0xc184000 0x25000>; | |
reg-names = "core_mem", "bam_mem"; | |
interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; | |
#address-cells = <0x0>; | |
interrupt-parent = <0x22c>; | |
interrupts = <0x0 0x1 0x2>; | |
#interrupt-cells = <0x1>; | |
interrupt-map-mask = <0xffffffff>; | |
interrupt-map = <0x0 0x1 0x0 0x0 0x71 0x0 0x1 0x1 0x0 0x0 0xef 0x0 0x2 0x7c 0x36 0x0>; | |
qcom,inject-rx-on-wakeup; | |
qcom,rx-char-to-inject = <0xfd>; | |
qcom,bam-tx-ep-pipe-index = <0x0>; | |
qcom,bam-rx-ep-pipe-index = <0x1>; | |
qcom,master-id = <0x54>; | |
clock-names = "core_clk", "iface_clk"; | |
clocks = <0x38 0x8c3512ff 0x38 0x8f283c1d>; | |
pinctrl-names = "sleep", "default"; | |
pinctrl-0 = <0x22d>; | |
pinctrl-1 = <0x22e>; | |
qcom,msm-bus,name = "buart1"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x56 0x200 0x0 0x0 0x56 0x200 0x1f4 0x320>; | |
status = "disabled"; | |
linux,phandle = <0x22c>; | |
phandle = <0x22c>; | |
}; | |
uart@c1b0000 { | |
compatible = "qcom,msm-hsuart-v14"; | |
reg = <0xc1b0000 0x200 0xc184000 0x25000>; | |
reg-names = "core_mem", "bam_mem"; | |
interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; | |
#address-cells = <0x0>; | |
interrupt-parent = <0x22f>; | |
interrupts = <0x0 0x1 0x2>; | |
#interrupt-cells = <0x1>; | |
interrupt-map-mask = <0xffffffff>; | |
interrupt-map = <0x0 0x1 0x0 0x0 0x72 0x0 0x1 0x1 0x0 0x0 0xef 0x0 0x2 0x7c 0x5 0x0>; | |
qcom,inject-rx-on-wakeup; | |
qcom,rx-char-to-inject = <0xfd>; | |
qcom,bam-tx-ep-pipe-index = <0x2>; | |
qcom,bam-rx-ep-pipe-index = <0x3>; | |
qcom,master-id = <0x54>; | |
clock-names = "core_clk", "iface_clk"; | |
clocks = <0x38 0x1e1965a3 0x38 0x8f283c1d>; | |
pinctrl-names = "sleep", "default"; | |
pinctrl-0 = <0x230>; | |
pinctrl-1 = <0x231>; | |
qcom,msm-bus,name = "buart2"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x56 0x200 0x0 0x0 0x56 0x200 0x1f4 0x320>; | |
status = "disabled"; | |
linux,phandle = <0x22f>; | |
phandle = <0x22f>; | |
}; | |
uart@c1b1000 { | |
compatible = "qcom,msm-hsuart-v14"; | |
reg = <0xc1b1000 0x200 0xc184000 0x25000>; | |
reg-names = "core_mem", "bam_mem"; | |
interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; | |
#address-cells = <0x0>; | |
interrupt-parent = <0x232>; | |
interrupts = <0x0 0x1 0x2>; | |
#interrupt-cells = <0x1>; | |
interrupt-map-mask = <0xffffffff>; | |
interrupt-map = <0x0 0x1 0x0 0x0 0x73 0x0 0x1 0x1 0x0 0x0 0xef 0x0 0x2 0x7c 0x32 0x0>; | |
qcom,inject-rx-on-wakeup; | |
qcom,rx-char-to-inject = <0xfd>; | |
qcom,bam-tx-ep-pipe-index = <0x4>; | |
qcom,bam-rx-ep-pipe-index = <0x5>; | |
qcom,master-id = <0x54>; | |
clock-names = "core_clk", "iface_clk"; | |
clocks = <0x38 0x382415ab 0x38 0x8f283c1d>; | |
pinctrl-names = "sleep", "default"; | |
pinctrl-0 = <0x233>; | |
pinctrl-1 = <0x234>; | |
qcom,msm-bus,name = "buart3"; | |
qcom,msm-bus,num-cases = <0x2>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,vectors-KBps = <0x56 0x200 0x0 0x0 0x56 0x200 0x1f4 0x320>; | |
status = "disabled"; | |
linux,phandle = <0x232>; | |
phandle = <0x232>; | |
}; | |
qcom,avtimer@170f7000 { | |
compatible = "qcom,avtimer"; | |
reg = <0x170f700c 0x4 0x170f7010 0x4>; | |
reg-names = "avtimer_lsb_addr", "avtimer_msb_addr"; | |
qcom,clk-div = <0x1b>; | |
}; | |
sound-9335 { | |
compatible = "qcom,msm8998-asoc-snd-tasha"; | |
qcom,model = "msm8998-tasha-snd-card"; | |
qcom,ext-disp-audio-rx; | |
qcom,wcn-btfm; | |
qcom,mi2s-audio-intf; | |
qcom,auxpcm-audio-intf; | |
qcom,msm-mi2s-master = <0x1 0x1 0x1 0x1>; | |
reg = <0x1711a000 0x4 0x1711b000 0x4 0x1711c000 0x4 0x1711d000 0x4>; | |
reg-names = "lpaif_pri_mode_muxsel", "lpaif_sec_mode_muxsel", "lpaif_tert_mode_muxsel", "lpaif_quat_mode_muxsel"; | |
qcom,audio-routing = "AIF4 VI", "MCLK", "RX_BIAS", "MCLK", "MADINPUT", "MCLK", "AMIC1", "MIC BIAS2", "MIC BIAS2", "Handset Mic", "AMIC2", "MIC BIAS2", "MIC BIAS2", "Headset Mic", "AMIC3", "MIC BIAS1", "MIC BIAS1", "ANCRight Headset Mic", "AMIC4", "MIC BIAS1", "MIC BIAS1", "ANCLeft Headset Mic", "AMIC5", "MIC BIAS4", "MIC BIAS4", "Handset Mic", "AMIC6", "MIC BIAS4", "MIC BIAS4", "Analog Mic6"; | |
qcom,msm-mbhc-hphl-swh = <0x1>; | |
qcom,msm-mbhc-gnd-swh = <0x0>; | |
qcom,hph-en0-gpio = <0x235>; | |
qcom,hph-en1-gpio = <0x236>; | |
qcom,tasha-mclk-clk-freq = <0x927c00>; | |
asoc-platform = <0x237 0x238 0x239 0x23a 0x23b 0x23c 0x23d 0x23e 0x23f 0x240 0x241 0x242 0x243 0x244 0x245 0x246>; | |
asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", "msm-pcm-dsp.2", "msm-voip-dsp", "msm-pcm-voice", "msm-pcm-loopback", "msm-compress-dsp", "msm-pcm-hostless", "msm-pcm-afe", "msm-lsm-client", "msm-pcm-routing", "msm-cpe-lsm", "msm-compr-dsp", "msm-pcm-dsp-noirq", "msm-cpe-lsm.3", "msm-transcode-loopback"; | |
asoc-cpu = <0x247 0x248 0x249 0x24a 0x24b 0x24c 0x24d 0x24e 0x24f 0x250 0x251 0x252 0x253 0x254 0x255 0x256 0x257 0x258 0x259 0x25a 0x25b 0x25c 0x25d 0x25e 0x25f 0x260 0x261 0x262 0x263 0x264 0x265 0x266 0x267 0x268 0x269 0x26a 0x249 0x24a 0x24b 0x24c 0x26b 0x26c 0x26d 0x26e 0x26f 0x270 0x271 0x272>; | |
asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3"; | |
asoc-codec = <0x273 0x274>; | |
asoc-codec-names = "msm-stub-codec.1", "msm-ext-disp-audio-codec-rx"; | |
qcom,wsa-max-devs = <0x0>; | |
qcom,wsa-devs = <0x275 0x276 0x277 0x278>; | |
qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", "SpkrLeft", "SpkrRight"; | |
qcom,us-euro-gpios = <0x279>; | |
qcom,asel-gpio = <0x27a 0x3 0x0>; | |
qcom,hsdet-gpio = <0x7c 0x8 0x1>; | |
qcom,spk-id-pin = <0x202>; | |
qcom,rcv-id-pin = <0x27b>; | |
msm_cdc_pinctrl@67 { | |
compatible = "qcom,msm-cdc-pinctrl"; | |
pinctrl-names = "aud_active", "aud_sleep"; | |
pinctrl-0 = <0x27c>; | |
pinctrl-1 = <0x27d>; | |
linux,phandle = <0x235>; | |
phandle = <0x235>; | |
}; | |
msm_cdc_pinctrl@68 { | |
compatible = "qcom,msm-cdc-pinctrl"; | |
pinctrl-names = "aud_active", "aud_sleep"; | |
pinctrl-0 = <0x27e>; | |
pinctrl-1 = <0x27f>; | |
linux,phandle = <0x236>; | |
phandle = <0x236>; | |
}; | |
}; | |
sound-tavil { | |
compatible = "qcom,msm8998-asoc-snd-tavil"; | |
qcom,model = "msm8998-tavil-snd-card"; | |
qcom,ext-disp-audio-rx; | |
qcom,wcn-btfm; | |
qcom,mi2s-audio-intf; | |
qcom,auxpcm-audio-intf; | |
qcom,msm-mi2s-master = <0x1 0x1 0x1 0x1>; | |
reg = <0x1711a000 0x4 0x1711b000 0x4 0x1711c000 0x4 0x1711d000 0x4>; | |
reg-names = "lpaif_pri_mode_muxsel", "lpaif_sec_mode_muxsel", "lpaif_tert_mode_muxsel", "lpaif_quat_mode_muxsel"; | |
qcom,audio-routing = "AIF4 VI", "MCLK", "RX_BIAS", "MCLK", "MADINPUT", "MCLK", "hifi amp", "LINEOUT1", "hifi amp", "LINEOUT2", "AMIC2", "MIC BIAS2", "MIC BIAS2", "Headset Mic", "AMIC3", "MIC BIAS2", "MIC BIAS2", "ANCRight Headset Mic", "AMIC4", "MIC BIAS2", "MIC BIAS2", "ANCLeft Headset Mic", "AMIC5", "MIC BIAS3", "MIC BIAS3", "Handset Mic", "DMIC0", "MIC BIAS1", "MIC BIAS1", "Digital Mic0", "DMIC1", "MIC BIAS1", "MIC BIAS1", "Digital Mic1", "DMIC2", "MIC BIAS3", "MIC BIAS3", "Digital Mic2", "DMIC3", "MIC BIAS3", "MIC BIAS3", "Digital Mic3", "DMIC4", "MIC BIAS4", "MIC BIAS4", "Digital Mic4", "DMIC5", "MIC BIAS4", "MIC BIAS4", "Digital Mic5", "SpkrLeft IN", "SPK1 OUT", "SpkrRight IN", "SPK2 OUT"; | |
qcom,msm-mbhc-hphl-swh = <0x0>; | |
qcom,msm-mbhc-gnd-swh = <0x0>; | |
qcom,us-euro-gpios = <0x280>; | |
qcom,hph-en0-gpio = <0x281>; | |
qcom,hph-en1-gpio = <0x282>; | |
qcom,tavil-mclk-clk-freq = <0x927c00>; | |
asoc-platform = <0x237 0x238 0x239 0x23a 0x23b 0x23c 0x23d 0x23e 0x23f 0x240 0x241 0x242 0x243 0x244 0x246>; | |
asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", "msm-pcm-dsp.2", "msm-voip-dsp", "msm-pcm-voice", "msm-pcm-loopback", "msm-compress-dsp", "msm-pcm-hostless", "msm-pcm-afe", "msm-lsm-client", "msm-pcm-routing", "msm-cpe-lsm", "msm-compr-dsp", "msm-pcm-dsp-noirq", "msm-transcode-loopback"; | |
asoc-cpu = <0x247 0x248 0x249 0x24a 0x24b 0x24c 0x24d 0x24e 0x24f 0x250 0x251 0x252 0x253 0x254 0x255 0x256 0x257 0x258 0x259 0x25a 0x25b 0x25c 0x25d 0x25e 0x25f 0x260 0x261 0x262 0x263 0x264 0x265 0x266 0x267 0x268 0x269 0x26a 0x26b 0x26c 0x26d 0x26e 0x26f 0x270 0x271 0x272>; | |
asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913"; | |
asoc-codec = <0x273 0x274>; | |
asoc-codec-names = "msm-stub-codec.1", "msm-ext-disp-audio-codec-rx"; | |
qcom,wsa-max-devs = <0x2>; | |
qcom,wsa-devs = <0x283 0x284 0x285 0x286>; | |
qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", "SpkrLeft", "SpkrRight"; | |
status = "disabled"; | |
}; | |
qcom,msm-cpe-lsm { | |
compatible = "qcom,msm-cpe-lsm"; | |
qcom,msm-cpe-lsm-id = <0x1>; | |
linux,phandle = <0x242>; | |
phandle = <0x242>; | |
}; | |
qcom,msm-cpe-lsm@3 { | |
compatible = "qcom,msm-cpe-lsm"; | |
qcom,msm-cpe-lsm-id = <0x3>; | |
linux,phandle = <0x245>; | |
phandle = <0x245>; | |
}; | |
qcom,wcd-dsp-mgr { | |
compatible = "qcom,wcd-dsp-mgr"; | |
qcom,wdsp-components = <0x287 0x0 0x288 0x1 0x289 0x2>; | |
qcom,img-filename = "cpe_9340"; | |
}; | |
msm_cdc_pinctrl@75 { | |
compatible = "qcom,msm-cdc-pinctrl"; | |
pinctrl-names = "aud_active", "aud_sleep"; | |
pinctrl-0 = <0x28a>; | |
pinctrl-1 = <0x28b>; | |
linux,phandle = <0x279>; | |
phandle = <0x279>; | |
}; | |
wcd9xxx-irq { | |
status = "ok"; | |
compatible = "qcom,wcd9xxx-irq"; | |
interrupt-controller; | |
#interrupt-cells = <0x1>; | |
interrupt-parent = <0x7c>; | |
qcom,gpio-connect = <0x7c 0x36 0x0>; | |
pinctrl-names = "default"; | |
pinctrl-0 = <0x28c>; | |
linux,phandle = <0x3a>; | |
phandle = <0x3a>; | |
}; | |
audio_ext_clk { | |
status = "ok"; | |
compatible = "qcom,audio-ref-clk"; | |
qcom,audio-ref-clk-gpio = <0x8f 0xd 0x0>; | |
clock-names = "osr_clk"; | |
clocks = <0x38 0xaa1157a6>; | |
qcom,node_has_rpm_clock; | |
#clock-cells = <0x1>; | |
pinctrl-names = "sleep", "active"; | |
pinctrl-0 = <0x28d>; | |
pinctrl-1 = <0x28e>; | |
linux,phandle = <0x3c>; | |
phandle = <0x3c>; | |
}; | |
audio_ext_clk_lnbb { | |
status = "ok"; | |
compatible = "qcom,audio-ref-clk"; | |
clock-names = "osr_clk"; | |
clocks = <0x38 0xf83e6387>; | |
qcom,node_has_rpm_clock; | |
#clock-cells = <0x1>; | |
linux,phandle = <0x44>; | |
phandle = <0x44>; | |
}; | |
msm_cdc_pinctrl@64 { | |
compatible = "qcom,msm-cdc-pinctrl"; | |
qcom,cdc-rst-n-gpio = <0x7c 0x40 0x0>; | |
pinctrl-names = "aud_active", "aud_sleep"; | |
pinctrl-0 = <0x28f>; | |
pinctrl-1 = <0x290>; | |
linux,phandle = <0x3b>; | |
phandle = <0x3b>; | |
}; | |
qocm,wcd-dsp-glink { | |
compatible = "qcom,wcd-dsp-glink"; | |
}; | |
qcom,sde_kms@c900000 { | |
compatible = "qcom,sde-kms"; | |
reg = <0xc900000 0x90000 0xc9b0000 0x2008>; | |
reg-names = "mdp_phys", "vbif_phys"; | |
clocks = <0x38 0xdb4b31e6 0x27 0x49a394f4 0x27 0x4825baf4 0x27 0xc365ac39 0x27 0x49a394f4 0x27 0x85d37ab5 0x27 0xdf04fc1d 0x27 0x6dc1f8f1 0x27 0x43539b0e 0x27 0x629b36dc 0x27 0x627b2b>; | |
clock-names = "mmss_noc_axi_clk", "mmss_noc_ahb_clk", "mmss_smmu_ahb_clk", "mmss_smmu_axi_clk", "mnoc_clk", "iface_clk", "bus_clk", "core_clk_src", "core_clk", "vsync_clk", "lut_clk"; | |
clock-rate = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x13ab6680 0x0 0x0 0x0 0x0>; | |
clock-max-rate = <0x0 0x0 0x0 0x0 0x0 0x0 0x18964020 0x18964020 0x0 0x0 0x0 0x0>; | |
qcom,sde-max-bw-low-kbps = <0x663be0>; | |
qcom,sde-max-bw-high-kbps = <0x663be0>; | |
interrupt-parent = <0x1>; | |
interrupts = <0x0 0x53 0x0>; | |
interrupt-controller; | |
#interrupt-cells = <0x1>; | |
iommus = <0xd4 0x0>; | |
gpus = <0x5d>; | |
qcom,sde-off = <0x1000>; | |
qcom,sde-len = <0x458>; | |
qcom,sde-ctl-off = <0x2000 0x2200 0x2400 0x2600 0x2800>; | |
qcom,sde-ctl-size = <0x94>; | |
qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000 0x49000 0x4a000>; | |
qcom,sde-mixer-size = <0x31c>; | |
qcom,sde-dspp-off = <0x55000 0x57000>; | |
qcom,sde-dspp-size = <0x17e0>; | |
qcom,sde-wb-off = <0x66000>; | |
qcom,sde-wb-size = <0x2dc>; | |
qcom,sde-wb-id = <0x2>; | |
qcom,sde-wb-xin-id = <0x6>; | |
qcom,sde-wb-clk-ctrl = <0x2bc 0x10>; | |
qcom,sde-intf-off = <0x6b000 0x6b800 0x6c000 0x6c800>; | |
qcom,sde-intf-size = <0x280>; | |
qcom,sde-intf-type = "dp", "dsi", "dsi", "hdmi"; | |
qcom,sde-pp-off = <0x71000 0x71800 0x72000 0x72800 0x73000>; | |
qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x1>; | |
qcom,sde-pp-size = <0xd4>; | |
qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0 0x0>; | |
qcom,sde-cdm-off = <0x7a200>; | |
qcom,sde-cdm-size = <0x224>; | |
qcom,sde-dsc-off = <0x81000 0x81400>; | |
qcom,sde-dsc-size = <0x140>; | |
qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>; | |
qcom,sde-sspp-type = "vig", "vig", "vig", "vig", "dma", "dma", "dma", "dma", "cursor", "cursor"; | |
qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 0x25000 0x27000 0x29000 0x2b000 0x35000 0x37000>; | |
qcom,sde-sspp-src-size = <0x1ac>; | |
qcom,sde-sspp-xin-id = <0x0 0x4 0x8 0xc 0x1 0x5 0x9 0xd 0x2 0xa>; | |
qcom,sde-sspp-clk-ctrl = <0x2ac 0x8 0x2b4 0x8 0x2c4 0x8 0x2c4 0xc 0x3a8 0x10 0x3b0 0x10>; | |
qcom,sde-qseed-type = "qseedv3"; | |
qcom,sde-mixer-linewidth = <0xa00>; | |
qcom,sde-sspp-linewidth = <0xa00>; | |
qcom,sde-mixer-blendstages = <0x7>; | |
qcom,sde-highest-bank-bit = <0x2>; | |
qcom,sde-panic-per-pipe; | |
qcom,sde-has-cdp; | |
qcom,sde-has-src-split; | |
qcom,sde-sspp-danger-lut = <0xf 0xffff 0x0>; | |
qcom,sde-sspp-safe-lut = <0xfffc 0xff00 0xffff>; | |
qcom,sde-vbif-off = <0x0>; | |
qcom,sde-vbif-id = <0x0>; | |
qcom,sde-vbif-default-ot-rd-limit = <0x20>; | |
qcom,sde-vbif-default-ot-wr-limit = <0x20>; | |
qcom,sde-vbif-dynamic-ot-rd-limit = <0x3b53800 0x2 0x76a7000 0x4 0xed4e000 0x10>; | |
qcom,sde-vbif-dynamic-ot-wr-limit = <0x3b53800 0x2 0x76a7000 0x4 0xed4e000 0x10>; | |
vdd-supply = <0x2a>; | |
gdsc-mmagic-mdss-supply = <0x28>; | |
qcom,sde-csc-type = "csc-10bit"; | |
connectors = <0x291 0x292 0x293>; | |
linux,phandle = <0x294>; | |
phandle = <0x294>; | |
qcom,sde-sspp-vig-blocks { | |
qcom,sde-vig-csc-off = <0x1a00>; | |
qcom,sde-vig-qseed-off = <0xa00>; | |
qcom,sde-vig-qseed-size = <0xa0>; | |
}; | |
qcom,platform-supply-entries { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
qcom,platform-supply-entry@0 { | |
reg = <0x0>; | |
qcom,supply-name = "gdsc-mmagic-mdss"; | |
qcom,supply-min-voltage = <0x0>; | |
qcom,supply-max-voltage = <0x0>; | |
qcom,supply-enable-load = <0x0>; | |
qcom,supply-disable-load = <0x0>; | |
}; | |
qcom,platform-supply-entry@1 { | |
reg = <0x1>; | |
qcom,supply-name = "vdd"; | |
qcom,supply-min-voltage = <0x0>; | |
qcom,supply-max-voltage = <0x0>; | |
qcom,supply-enable-load = <0x0>; | |
qcom,supply-disable-load = <0x0>; | |
}; | |
}; | |
qcom,smmu_kms_unsec_cb { | |
compatible = "qcom,smmu_sde_unsec"; | |
iommus = <0xd4 0x0>; | |
}; | |
qcom,smmu_kms_sec_cb { | |
compatible = "qcom,smmu_sde_sec"; | |
iommus = <0xd4 0x1>; | |
}; | |
qcom,sde-data-bus { | |
qcom,msm-bus,name = "mdss_sde"; | |
qcom,msm-bus,num-cases = <0x3>; | |
qcom,msm-bus,num-paths = <0x2>; | |
qcom,msm-bus,vectors-KBps = <0x16 0x200 0x0 0x0 0x17 0x200 0x0 0x0 0x16 0x200 0x0 0x61a800 0x17 0x200 0x0 0x61a800 0x16 0x200 0x0 0x61a800 0x17 0x200 0x0 0x61a800>; | |
}; | |
qcom,sde-reg-bus { | |
qcom,msm-bus,name = "mdss_reg"; | |
qcom,msm-bus,num-cases = <0x4>; | |
qcom,msm-bus,num-paths = <0x1>; | |
qcom,msm-bus,active-only; | |
qcom,msm-bus,vectors-KBps = <0x1 0x24e 0x0 0x0 0x1 0x24e 0x0 0x12c00 0x1 0x24e 0x0 0x27100 0x1 0x24e 0x0 0x4e200>; | |
}; | |
}; | |
qcom,hdmi_tx_8998@c9a0000 { | |
cell-index = <0x0>; | |
compatible = "qcom,hdmi-tx-8998"; | |
reg = <0xc9a0000 0x50c 0x780000 0x621c 0xc9e0000 0x28>; | |
reg-names = "core_physical", "qfprom_physical", "hdcp_physical"; | |
interrupt-parent = <0x294>; | |
interrupts = <0x8 0x0>; | |
interrupt-controller; | |
#interrupt-cells = <0x1>; | |
qcom,hdmi-tx-ddc-clk-gpio = <0x7c 0x20 0x0>; | |
qcom,hdmi-tx-ddc-data-gpio = <0x7c 0x21 0x0>; | |
qcom,hdmi-tx-hpd-gpio = <0x7c 0x22 0x0>; | |
qcom,hdmi-tx-hpd5v-gpio = <0x7c 0x85 0x0>; | |
pinctrl-names = "default", "sleep"; | |
pinctrl-0 = <0x1ce 0x1d1 0x1cd>; | |
pinctrl-1 = <0x1d4 0x1cf 0x1d3>; | |
hpd-gdsc-supply = <0x2a>; | |
qcom,supply-names = "hpd-gdsc"; | |
qcom,min-voltage-level = <0x0>; | |
qcom,max-voltage-level = <0x0>; | |
qcom,enable-load = <0x0>; | |
qcom,disable-load = <0x0>; | |
clocks = <0x27 0x49a394f4 0x27 0x85d37ab5 0x27 0x28460a6d 0x27 0x43539b0e 0x27 0x5448519f 0x27 0x74d5a954 0x27 0x49a394f4 0x27 0xea30b0e7 0x27 0xdf04fc1d>; | |
clock-names = "hpd_mnoc_clk", "hpd_iface_clk", "hpd_core_clk", "hpd_mdp_core_clk", "hpd_alt_iface_clk", "core_extp_clk", "mnoc_clk", "hpd_misc_ahb_clk", "hpd_bus_clk"; | |
qcom,pluggable; | |
linux,phandle = <0x291>; | |
phandle = <0x291>; | |
}; | |
qcom,wb-display@0 { | |
compatible = "qcom,wb-display"; | |
cell-index = <0x0>; | |
label = "wb_display"; | |
linux,phandle = <0x293>; | |
phandle = <0x293>; | |
}; | |
qcom,hdmi-display { | |
compatible = "qcom,hdmi-display"; | |
label = "sde_hdmi"; | |
qcom,display-type = "secondary"; | |
qcom,msm_ext_disp = <0x1ca>; | |
linux,phandle = <0x292>; | |
phandle = <0x292>; | |
}; | |
qcom,hdmi-cec@c9a0000 { | |
compatible = "qcom,hdmi-cec"; | |
label = "sde_hdmi_cec"; | |
qcom,hdmi-dev = <0x292>; | |
interrupt-parent = <0x291>; | |
interrupts = <0x1 0x0>; | |
reg = <0xc9a0000 0x50c>; | |
reg-names = "hdmi_cec"; | |
clocks = <0x27 0x49a394f4 0x27 0x85d37ab5 0x27 0x28460a6d>; | |
clock-names = "cec_mnoc_clk", "cec_iface_clk", "cec_core_clk"; | |
pinctrl-names = "cec_active", "cec_sleep"; | |
pinctrl-0 = <0x1d2>; | |
pinctrl-1 = <0x1d0>; | |
cec-gdsc-supply = <0x2a>; | |
qcom,platform-supply-entries { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
qcom,platform-supply-entry@0 { | |
reg = <0x0>; | |
qcom,supply-name = "cec-gdsc"; | |
qcom,supply-min-voltage = <0x0>; | |
qcom,supply-max-voltage = <0x0>; | |
qcom,supply-enable-load = <0x0>; | |
qcom,supply-disable-load = <0x0>; | |
}; | |
}; | |
}; | |
qcom,camera-flash@0 { | |
cell-index = <0x0>; | |
compatible = "qcom,camera-flash"; | |
qcom,flash-source = <0x295 0x296>; | |
qcom,torch-source = <0x297 0x298>; | |
qcom,switch-source = <0x299>; | |
status = "ok"; | |
linux,phandle = <0xec>; | |
phandle = <0xec>; | |
}; | |
qcom,camera-flash@1 { | |
cell-index = <0x1>; | |
compatible = "qcom,camera-flash"; | |
qcom,flash-source = <0x29a>; | |
qcom,torch-source = <0x29b>; | |
qcom,switch-source = <0x29c>; | |
status = "disable"; | |
}; | |
vaf_gpio_supply { | |
compatible = "regulator-fixed"; | |
regulator-name = "vaf_gpio_supply"; | |
regulator-min-microvolt = <0x2ab980>; | |
regulator-max-microvolt = <0x2ab980>; | |
startup-delay-us = <0xfa0>; | |
enable-active-high; | |
gpio = <0x7c 0x1d 0x0>; | |
linux,phandle = <0xe0>; | |
phandle = <0xe0>; | |
}; | |
vana_gpio_supply { | |
compatible = "regulator-fixed"; | |
regulator-name = "vana_gpio_supply"; | |
regulator-min-microvolt = <0x2ab980>; | |
regulator-max-microvolt = <0x2ab980>; | |
startup-delay-us = <0xfa0>; | |
enable-active-high; | |
gpio = <0x7c 0x50 0x0>; | |
linux,phandle = <0xe2>; | |
phandle = <0xe2>; | |
}; | |
vdig_gpio_supply { | |
compatible = "regulator-fixed"; | |
regulator-name = "vdig_gpio_supply"; | |
regulator-min-microvolt = <0x10c8e0>; | |
regulator-max-microvolt = <0x10c8e0>; | |
startup-delay-us = <0xfa0>; | |
enable-active-high; | |
gpio = <0x8f 0x14 0x0>; | |
linux,phandle = <0xe1>; | |
phandle = <0xe1>; | |
}; | |
spk-id-pin@100 { | |
compatible = "audio,speaker-id"; | |
audio,speaker-id-gpio = <0x7c 0x64 0x0>; | |
pinctrl-names = "pull_down", "pull_up", "no_pull"; | |
pinctrl-0 = <0x29d>; | |
pinctrl-1 = <0x29e>; | |
pinctrl-2 = <0x29f>; | |
linux,phandle = <0x202>; | |
phandle = <0x202>; | |
}; | |
rcv-id-pin@11 { | |
compatible = "audio,speaker-id"; | |
audio,speaker-id-gpio = <0x7c 0xb 0x0>; | |
pinctrl-names = "pull_down", "pull_up", "no_pull"; | |
pinctrl-0 = <0x2a0>; | |
pinctrl-1 = <0x2a1>; | |
pinctrl-2 = <0x2a2>; | |
linux,phandle = <0x27b>; | |
phandle = <0x27b>; | |
}; | |
snfuse@0x786134 { | |
compatible = "qcom,sn-fuse"; | |
reg = <0x786134 0x4>; | |
reg-names = "sn-base"; | |
}; | |
gpio_keys { | |
compatible = "gpio-keys"; | |
input-name = "gpio-keys"; | |
status = "okay"; | |
vol_up { | |
label = "volume_up"; | |
gpios = <0x8f 0x6 0x1>; | |
linux,input-type = <0x1>; | |
linux,code = <0x73>; | |
gpio-key,wakeup; | |
debounce-interval = <0xf>; | |
}; | |
cam_snapshot { | |
label = "cam_snapshot"; | |
gpios = <0x8f 0x7 0x1>; | |
linux,input-type = <0x1>; | |
linux,code = <0x2fe>; | |
gpio-key,wakeup; | |
debounce-interval = <0xf>; | |
}; | |
cam_focus { | |
label = "cam_focus"; | |
gpios = <0x8f 0x8 0x1>; | |
linux,input-type = <0x1>; | |
linux,code = <0x210>; | |
gpio-key,wakeup; | |
debounce-interval = <0xf>; | |
}; | |
hall_key0 { | |
label = "hall_key0"; | |
gpios = <0x7c 0x7c 0x1>; | |
linux,input-type = <0x5>; | |
linux,code = <0x0>; | |
gpio-key,wakeup; | |
debounce-interval = <0xf>; | |
}; | |
}; | |
gpio_rf { | |
pinctrl-names = "tlmm_gpio_rf_active", "tlmm_gpio_rf_suspend"; | |
pinctrl-0 = <0x2a3>; | |
pinctrl-1 = <0x2a4>; | |
compatible = "gpio_rf"; | |
gpios = <0x7c 0x77 0x1>; | |
debounce-interval = <0xf>; | |
}; | |
fingerprint_fpc { | |
status = "ok"; | |
compatible = "fpc,fpc1020"; | |
interrupt-parent = <0x7c>; | |
interrupts = <0x79 0x0>; | |
fpc,gpio_rst = <0x7c 0x25 0x0>; | |
fpc,gpio_irq = <0x7c 0x79 0x0>; | |
vdd_ana-supply = <0x2a5>; | |
pinctrl-names = "fpc1020_reset_reset", "fpc1020_reset_active", "fpc1020_irq_active"; | |
pinctrl-0 = <0x2a6>; | |
pinctrl-1 = <0x2a7>; | |
pinctrl-2 = <0x2a8>; | |
}; | |
fingerprint_goodix { | |
compatible = "goodix,fingerprint"; | |
fp-gpio-reset = <0x7c 0x25 0x0>; | |
fp-gpio-irq = <0x7c 0x79 0x0>; | |
pinctrl-names = "pmx_fp_active", "pmx_fp_suspend"; | |
pinctrl-0 = <0x2a9>; | |
pinctrl-1 = <0x2aa>; | |
clock-names = "iface_clk", "core_clk"; | |
clocks = <0x38 0x8f283c1d 0x38 0xfe1bd34a>; | |
status = "ok"; | |
}; | |
}; | |
chosen { | |
stdout-path = "serial0"; | |
bootargs = "rcupdate.rcu_expedited=1"; | |
}; | |
aliases { | |
serial0 = "/soc/serial@0c1b0000"; | |
pci-domain0 = "/soc/qcom,pcie@01c00000"; | |
sdhc2 = "/soc/sdhci@c0a4900"; | |
i2c1 = "/soc/i2c@c175000"; | |
i2c2 = "/soc/i2c@c176000"; | |
i2c3 = "/soc/i2c@c177000"; | |
i2c4 = "/soc/i2c@c178000"; | |
i2c5 = "/soc/i2c@c179000"; | |
i2c6 = "/soc/i2c@c17a000"; | |
i2c7 = "/soc/i2c@c1b5000"; | |
i2c8 = "/soc/i2c@c1b6000"; | |
i2c9 = "/soc/i2c@c1b7000"; | |
i2c10 = "/soc/i2c@c1b8000"; | |
i2c11 = "/soc/i2c@c1b9000"; | |
i2c12 = "/soc/i2c@c1ba000"; | |
spi1 = "/soc/spi@c175000"; | |
spi2 = "/soc/spi@c176000"; | |
spi3 = "/soc/spi@c177000"; | |
spi4 = "/soc/spi@c178000"; | |
spi5 = "/soc/spi@c179000"; | |
spi6 = "/soc/spi@c17a000"; | |
spi7 = "/soc/spi@c1b5000"; | |
spi8 = "/soc/spi@c1b6000"; | |
spi9 = "/soc/spi@c1b7000"; | |
spi10 = "/soc/spi@c1b8000"; | |
spi11 = "/soc/spi@c1b9000"; | |
spi12 = "/soc/spi@c1ba000"; | |
}; | |
memory { | |
device_type = "memory"; | |
reg = <0x0 0x0 0x0 0x0>; | |
}; | |
psci { | |
compatible = "arm,psci-1.0"; | |
method = "smc"; | |
}; | |
vendor { | |
#address-cells = <0x1>; | |
#size-cells = <0x1>; | |
ranges = <0x0 0x0 0x0 0xffffffff>; | |
compatible = "simple-bus"; | |
}; | |
firmware { | |
android { | |
compatible = "android,firmware"; | |
fstab { | |
compatible = "android,fstab"; | |
system { | |
compatible = "android,system"; | |
dev = "/dev/block/platform/soc/1da4000.ufshc/by-name/system"; | |
type = "ext4"; | |
mnt_flags = "ro,barrier=1,discard"; | |
fsmgr_flags = "wait,verify"; | |
status = "ok"; | |
}; | |
}; | |
}; | |
}; | |
reserved-memory { | |
#address-cells = <0x2>; | |
#size-cells = <0x2>; | |
ranges; | |
removed_regions@85800000 { | |
compatible = "removed-dma-pool"; | |
no-map; | |
reg = <0x0 0x85800000 0x0 0x3700000>; | |
}; | |
pil_ipa_gpu_region@95600000 { | |
compatible = "removed-dma-pool"; | |
no-map; | |
reg = <0x0 0x95600000 0x0 0x100000>; | |
}; | |
pil_slpi_region@94700000 { | |
compatible = "removed-dma-pool"; | |
no-map; | |
reg = <0x0 0x94700000 0x0 0xf00000>; | |
linux,phandle = <0xa3>; | |
phandle = <0xa3>; | |
}; | |
pil_mba_region@94500000 { | |
compatible = "removed-dma-pool"; | |
no-map; | |
reg = <0x0 0x94500000 0x0 0x200000>; | |
linux,phandle = <0x8e>; | |
phandle = <0x8e>; | |
}; | |
pil_video_region@94000000 { | |
compatible = "removed-dma-pool"; | |
no-map; | |
reg = <0x0 0x94000000 0x0 0x500000>; | |
linux,phandle = <0xa7>; | |
phandle = <0xa7>; | |
}; | |
modem_region@8d000000 { | |
compatible = "removed-dma-pool"; | |
no-map; | |
reg = <0x0 0x8d000000 0x0 0x7000000>; | |
linux,phandle = <0x8b>; | |
phandle = <0x8b>; | |
}; | |
pil_adsp_region@0x8b200000 { | |
compatible = "removed-dma-pool"; | |
no-map; | |
reg = <0x0 0x8b200000 0x0 0x1e00000>; | |
linux,phandle = <0x88>; | |
phandle = <0x88>; | |
}; | |
spss_region@8ab00000 { | |
compatible = "removed-dma-pool"; | |
no-map; | |
reg = <0x0 0x8ab00000 0x0 0x700000>; | |
linux,phandle = <0xa8>; | |
phandle = <0xa8>; | |
}; | |
adsp_region { | |
compatible = "shared-dma-pool"; | |
alloc-ranges = <0x0 0x0 0x0 0xffffffff>; | |
reusable; | |
alignment = <0x0 0x400000>; | |
size = <0x0 0x800000>; | |
linux,phandle = <0x64>; | |
phandle = <0x64>; | |
}; | |
qseecom_region { | |
compatible = "shared-dma-pool"; | |
alloc-ranges = <0x0 0x0 0x0 0xffffffff>; | |
reusable; | |
alignment = <0x0 0x400000>; | |
size = <0x0 0x1400000>; | |
linux,phandle = <0xd5>; | |
phandle = <0xd5>; | |
}; | |
sp_region { | |
compatible = "shared-dma-pool"; | |
alloc-ranges = <0x0 0x0 0x0 0xffffffff>; | |
reusable; | |
alignment = <0x0 0x100000>; | |
size = <0x0 0x800000>; | |
linux,phandle = <0xd6>; | |
phandle = <0xd6>; | |
}; | |
secure_region { | |
compatible = "shared-dma-pool"; | |
alloc-ranges = <0x0 0x0 0x0 0xffffffff>; | |
reusable; | |
alignment = <0x0 0x200000>; | |
size = <0x0 0x5c00000>; | |
linux,phandle = <0xd7>; | |
phandle = <0xd7>; | |
}; | |
linux,cma { | |
compatible = "shared-dma-pool"; | |
alloc-ranges = <0x0 0x0 0x0 0xffffffff>; | |
reusable; | |
alignment = <0x0 0x400000>; | |
size = <0x0 0x2000000>; | |
linux,cma-default; | |
}; | |
splash_region@9d600000 { | |
reg = <0x0 0x9d600000 0x0 0x2400000>; | |
label = "cont_splash_mem"; | |
linux,phandle = <0x1b0>; | |
phandle = <0x1b0>; | |
}; | |
}; | |
regulator-gfx-stub { | |
compatible = "qcom,stub-regulator"; | |
regulator-name = "gfx_stub_corner"; | |
qcom,hpm-min-load = <0x186a0>; | |
regulator-min-microvolt = <0x1>; | |
regulator-max-microvolt = <0x6>; | |
status = "disabled"; | |
}; | |
bt_wcn3990 { | |
compatible = "qca,wcn3990"; | |
qca,bt-vdd-io-supply = <0x2ab>; | |
qca,bt-vdd-xtal-supply = <0xcb>; | |
qca,bt-vdd-core-supply = <0x2ac>; | |
qca,bt-vdd-pa-supply = <0x2ad>; | |
qca,bt-vdd-ldo-supply = <0x2ae>; | |
qca,bt-chip-pwd-supply = <0x2af>; | |
clocks = <0x38 0xa7c5602a>; | |
clock-names = "rf_clk2"; | |
qca,bt-vdd-io-voltage-level = <0x14a140 0x14a140>; | |
qca,bt-vdd-xtal-voltage-level = <0x1f20c0 0x1f20c0>; | |
qca,bt-vdd-core-voltage-level = <0x1b7740 0x1b7740>; | |
qca,bt-vdd-pa-voltage-level = <0x13e5c0 0x13e5c0>; | |
qca,bt-vdd-ldo-voltage-level = <0x328980 0x328980>; | |
qca,bt-chip-pwd-voltage-level = <0x36ee80 0x36ee80>; | |
qca,bt-vdd-io-current-level = <0x1>; | |
qca,bt-vdd-xtal-current-level = <0x1>; | |
qca,bt-vdd-core-current-level = <0x1>; | |
qca,bt-vdd-pa-current-level = <0x1>; | |
qca,bt-vdd-ldo-current-level = <0x1>; | |
}; | |
qcom,battery-data { | |
qcom,batt-id-range-pct = <0xf>; | |
qcom,c1_atl_3350mah { | |
qcom,max-voltage-uv = <0x432380>; | |
qcom,nom-batt-capacity-mah = <0xd16>; | |
qcom,fg-cc-cv-threshold-mv = <0x1126>; | |
qcom,batt-id-kohm = <0x44>; | |
qcom,battery-beta = <0xd6b>; | |
qcom,battery-type = "c1_atl"; | |
qcom,checksum = <0x23eb>; | |
qcom,gui-version = "PMI8998GUI - 2.0.0.54"; | |
qcom,fg-profile-data = <0x661fb605 0x700a9dfc 0x731d37f5 0x41122b14 0xbf18d722 0xad459652 0x57000000 0xf000000 0x8cc4 0x9ccd72cb 0x22000800 0x41e3a107 0x4dfd6ff3 0x45e48f12 0xfc0c2333 0x19060920 0x27001400 0xf91f4e05 0xa90a2706 0x2b1d4301 0x45009904 0x3819ca22 0x9845cf52 0x59000000 0xc000000 0x82cc 0x20c257ad 0x1c000000 0x29f2a107 0x2707a3eb 0xfbe4fd02 0x59d5d21a 0xad33ccff 0x7100000 0x150d6646 0x1c004000 0x7e010afa 0xff000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; | |
}; | |
qcom,c1_sdi_3440mah { | |
qcom,max-voltage-uv = <0x432380>; | |
qcom,nom-batt-capacity-mah = <0xd16>; | |
qcom,fg-cc-cv-threshold-mv = <0x1126>; | |
qcom,batt-id-kohm = <0x1e>; | |
qcom,battery-beta = <0xd6b>; | |
qcom,battery-type = "c1_sdi"; | |
qcom,checksum = <0x623e>; | |
qcom,gui-version = "PMI8998GUI - 2.0.0.54"; | |
qcom,fg-profile-data = <0xa81f6805 0xb20a09fc 0x4f1d2ce2 0x270a460c 0x8a184f23 0xf744cb53 0x5b000000 0xe000000 0x8b5 0x30c485ac 0x2e000800 0x2200e1ed 0x100679fa 0x3704ec03 0xbee53322 0x36060920 0x27001400 0xee1f4805 0xc40af905 0x701de7d2 0x4e0ba914 0xee190722 0xfc3c064b 0x52000000 0x13000000 0xc3cc 0x41aa41c3 0x21000000 0x6600e1ed 0xf7062af2 0xf6f4fffa 0x9bf51b1a 0x9933ccff 0x7100000 0x1a0d6646 0x21004000 0x6c010afa 0xff000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; | |
}; | |
qcom,itech-3020mah { | |
qcom,max-voltage-uv = <0x432380>; | |
qcom,v-cutoff-uv = <0x33e140>; | |
qcom,chg-term-ua = <0x186a0>; | |
qcom,batt-id-kohm = <0x96>; | |
qcom,battery-type = "itech_3020mah"; | |
qcom,fg-profile-data = <0xe8830c7d 0xe980b276 0x20834073 0xd76c597e 0xfb815893 0xdae02b1 0x5b12d782 0x8678f376 0x4a710c83 0x1b80738d 0x49890782 0xd89979bc 0xaac87c17 0xf80bf45b 0xce6e71fd 0x92e7944 0x52430000 0xde3d2a37 0xd3460000 0x0 0x0 0x3a6bb769 0xdd6c8383 0x4276ca68 0x7875ef80 0xd474565b 0x0 0xaa55ad2 0x54a0710c 0x2800ff36 0xf0113003 0x0>; | |
}; | |
}; | |
}; |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment