delay.hs

module Test where

import Clash.Prelude
import Clash.Explicit.Testbench


delay2 :: (KnownNat n, HiddenClockReset domain gated synchronous) => DSignal domain n Int -> DSignal domain (n + 2) Int
delay2 = delayedI


add1 ::
    (Num a , KnownNat n, HiddenClockReset domain gated synchronous)
    => DSignal domain n (Maybe a)
    -> DSignal domain (n + 1) (Maybe a)
add1 a =
    delayedI $ fmap (fmap (1 +)) a


add1Module :: (HiddenClockReset domain gated synchronous) =>
    Signal domain (Unsigned 8) -> Signal domain (Maybe (Unsigned 8))
add1Module input =
    toSignal $ add1 $ fromSignal $ fmap Just input

{-# ANN topEntity
  (Synthesize
    { t_name   = "PlTest"
    , t_inputs = [ PortName "clk"
                 , PortName "rst"
                 , PortName "data_in"
                 ]
    , t_output = PortName "data_out"
    }) #-}
topEntity
  :: Clock System Source
  -> Reset System Asynchronous
  -> Signal System (Unsigned 8)
  -> Signal System (Maybe (Unsigned 8))
topEntity = exposeClockReset add1Module