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CPU Flags (created from https://github.com/torvalds/linux/blob/master/arch/x86/include/asm/cpufeatures.h)
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CLASS|FLAG|DESC | |
AMD-EXTENDED|3dnowprefetch|3DNow prefetch instructions | |
AMD-EXTENDED|abm|Advanced bit manipulation | |
AMD-EXTENDED|bpext|Data breakpoint extension | |
AMD-EXTENDED|cmp_legacy|If yes HyperThreading not valid | |
AMD-EXTENDED|cr8_legacy|CR8 in | |
AMD-EXTENDED|extapic|Extended APIC space | |
AMD-EXTENDED|fma4|4 operands MAC instructions | |
AMD-EXTENDED|ibs|Instruction Based Sampling | |
AMD-EXTENDED|lahf_lm|LAHF/SAHF in long mode | |
AMD-EXTENDED|lwp|Light Weight Profiling | |
AMD-EXTENDED|misalignsse|Misaligned SSE mode | |
AMD-EXTENDED|mwaitx|MWAIT extension (MONITORX/MWAITX instructions) | |
AMD-EXTENDED|nodeid_msr|NodeId MSR | |
AMD-EXTENDED|osvw|OS Visible Workaround | |
AMD-EXTENDED|perfctr_core|Core performance counter extensions | |
AMD-EXTENDED|perfctr_llc|Last Level Cache performance counter extensions | |
AMD-EXTENDED|perfctr_nb|NB performance counter extensions | |
AMD-EXTENDED|ptsc|Performance time-stamp counter | |
AMD-EXTENDED|skinit|SKINIT/STGI instructions | |
AMD-EXTENDED|sse4a|SSE-4A | |
AMD-EXTENDED|svm|Secure Virtual Machine | |
AMD-EXTENDED|tbm|Trailing Bit Manipulations | |
AMD-EXTENDED|tce|Translation Cache Extension | |
AMD-EXTENDED|topoext|Topology extensions CPUID leafs | |
AMD-EXTENDED|wdt|Watchdog timer | |
AMD-EXTENDED|xop|extended AVX instructions | |
AMD-SVM|avic13|Virtual Interrupt Controller | |
AMD-SVM|decodeassists|Decode Assists support | |
AMD-SVM|flushbyasid|flush-by-ASID support | |
AMD-SVM|lbrv|LBR Virtualization support | |
AMD-SVM|npt|Nested Page Table support | |
AMD-SVM|nrips|"nrip_save" SVM next_rip save | |
AMD-SVM|pausefilter10|filtered pause intercept | |
AMD-SVM|pfthreshold12|pause filter threshold | |
AMD-SVM|svml|"svm_lock" SVM locking MSR | |
AMD-SVM|tscratemsr|"tsc_scale" TSC scaling support | |
AMD-SVM|vgif16|Virtual GIF | |
AMD-SVM|vmcbclean|"vmcb_clean" VMCB clean bits support | |
AMD-SVM|v_vmsave_vmload15|Virtual VMSAVE VMLOAD | |
AMD|amd_ibpb12|Indirect Branch Prediction Barrier | |
AMD|amd_ibrs14|Indirect Branch Restricted Speculation | |
AMD|amd_ssbd24|Speculative Store Bypass Disable | |
AMD|amd_ssb_no26|Speculative Store Bypass is fixed in hardware. | |
AMD|amd_stibp15|Single Thread Indirect Branch Predictors | |
AMD|clzero|CLZERO instruction | |
AMD|irperf|Instructions Retired Count | |
AMD|overflow_recov|MCA overflow recovery support | |
AMD|smca|Scalable MCA | |
AMD|succor|Uncorrectable error containment and recovery | |
AMD|virt_ssbd25|Virtualized Speculative Store Bypass Disable | |
AMD|xsaveerptr|Always save/restore FP error pointers | |
AUX|cat_l2|Cache Allocation Technology L2 | |
AUX|cat_l3|Cache Allocation Technology L3 | |
AUX|cdp_l2|Code and Data Prioritization L2 | |
AUX|cdp_l3|Code and Data Prioritization L3 | |
AUX|cpb|AMD Core Performance Boost | |
AUX|cpuid_fault|Intel CPUID faulting | |
AUX|epb|IA32_ENERGY_PERF_BIAS support | |
AUX|hw_pstate|AMD HW-PState | |
AUX|ibpb|Indirect Branch Prediction Barrier | |
AUX|ibrs_enhanced|Enhanced IBRS | |
AUX|ibrs|Indirect Branch Restricted Speculation | |
AUX|intel_ppin|Intel Processor Inventory Number | |
AUX|invpcid_single|Effectively INVPCID && CR4.PCIDE=1 | |
AUX|l1tf_pteinv|L1TF workaround PTE inversion | |
AUX|ls_cfg_ssbd|AMD SSBD implementation via LS_CFG MSR | |
AUX|mba|Memory Bandwidth Allocation | |
AUX|msr_spec_ctrl|MSR SPEC_CTRL is implemented | |
AUX|proc_feedback|AMD ProcFeedbackInterface | |
AUX|pti|Kernel Page Table Isolation enabled | |
AUX|retpoline_amd|AMD Retpoline mitigation for Spectre variant | |
AUX|retpoline|Generic Retpoline mitigation for Spectre variant | |
AUX|ring3mwait|Ring | |
AUX|rsb_ctxsw|Fill RSB on context switches | |
AUX|sev|AMD Secure Encrypted Virtualization | |
AUX|sme|AMD Secure Memory Encryption | |
AUX|spec_store_bypass_disable|Disable Speculative Store Bypass. | |
AUX|ssbd|Speculative Store Bypass Disable | |
AUX|stibp|Single Thread Indirect Branch Predictors | |
AUX|use_ibpb|Indirect Branch Prediction Barrier enabled | |
AUX|use_ibrs_fw|Use IBRS during runtime firmware calls | |
AUX|zen|CPU is AMD family | |
CPU-TYPE|acc_power|AMD Accumulated Power Mechanism | |
CPU-TYPE|always|Always-present feature | |
CPU-TYPE|amd_dcm|AMD multi-node processor | |
CPU-TYPE|aperfmperf|P-State hardware coordination feedback capability (APERF/MPERF MSRs) | |
CPU-TYPE|arch_perfmon|Intel Architectural PerfMon | |
CPU-TYPE|art|Always running timer (ART) | |
CPU-TYPE|bts|Branch Trace Store | |
CPU-TYPE|constant_tsc|TSC ticks at a constant rate | |
CPU-TYPE|cpuid|CPU has CPUID instruction itself | |
CPU-TYPE|extd_apicid|Extended APICID (8 bits) | |
CPU-TYPE|k7|Athlon | |
CPU-TYPE|k8|Opteron, Athlon64 | |
CPU-TYPE|lfence_rdtsc|LFENCE synchronizes RDTSC | |
CPU-TYPE|mfence_rdtsc|MFENCE synchronizes RDTSC | |
CPU-TYPE|nonstop_tsc_s3|TSC doesn't stop in S3 state | |
CPU-TYPE|nonstop_tsc|TSC does not stop in C states | |
CPU-TYPE|nopl|The NOPL (0F | |
CPU-TYPE|p3|P3 | |
CPU-TYPE|p4|P4 | |
CPU-TYPE|pebs|Precise-Event Based Sampling | |
CPU-TYPE|rep_good|REP microcode works well | |
CPU-TYPE|syscall32|syscall in IA32 userspace | |
CPU-TYPE|sysenter32|sysenter in IA32 userspace | |
CPU-TYPE|tsc_known_freq|TSC has known frequency | |
CPU-TYPE|tsc_reliable|TSC is known to be reliable | |
CPU-TYPE|up|SMP kernel running on UP | |
CPU-TYPE|xtopology|CPU topology enum extensions | |
EXTENDED|xgetbv1|XGETBV with ECX = | |
EXTENDED|xsavec|XSAVEC instruction | |
EXTENDED|xsaveopt|XSAVEOPT instruction | |
EXTENDED|xsaves|XSAVES/XRSTORS instructions | |
INTEL-QoS|cqm_llc|LLC QoS if | |
INTEL-QoS|cqm_mbm_local|LLC Local MBM monitoring | |
INTEL-QoS|cqm_mbm_total|LLC Total MBM monitoring | |
INTEL-QoS|cqm_occup_llc|LLC occupancy monitoring | |
INTEL|3dnowext|AMD 3dnowext support in Intel | |
INTEL|3dnow|AMD 3dnow support on Intel | |
INTEL|acc|"tm" Automatic clock control | |
INTEL|acpi|ACPI via MSR | |
INTEL|adx|ADCX and ADOX instructions | |
INTEL|aes|AES instructions | |
INTEL|apic|Onboard APIC | |
INTEL|arch_capabilities29|IA32_ARCH_CAPABILITIES MSR (Intel) | |
INTEL|avx2|AVX2 instructions | |
INTEL|avx512bw|AVX-512 BW (Byte/Word granular) Instructions | |
INTEL|avx512cd|AVX-512 Conflict Detection | |
INTEL|avx512dq|AVX-512 DQ (Double/Quad granular) Instructions | |
INTEL|avx512er|AVX-512 Exponential and Reciprocal | |
INTEL|avx512f|AVX-512 Foundation | |
INTEL|avx512ifma|AVX-512 Integer Fused Multiply-Add instructions | |
INTEL|avx512pf|AVX-512 Prefetch | |
INTEL|avx512vbmi|AVX512 Vector Bit Manipulation instructions | |
INTEL|avx512vl|AVX-512 VL (128/256 Vector Length) Extensions | |
INTEL|avx512_4fmaps|AVX-512 Multiply Accumulation Single precision | |
INTEL|avx512_4vnniw|AVX-512 Neural Network Instructions | |
INTEL|avx512_bitalg12|Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions | |
INTEL|avx512_vbmi2|Additional AVX512 Vector Bit Manipulation Instructions | |
INTEL|avx512_vnni11|Vector Neural Network Instructions | |
INTEL|avx512_vpopcntdq14|POPCNT for vectors of DW/QW | |
INTEL|avx|Advanced Vector Extensions | |
INTEL|bmi1|1st group bit manipulation extensions | |
INTEL|bmi2|2nd group bit manipulation extensions | |
INTEL|cid|Context ID | |
INTEL|cldemote25|CLDEMOTE instruction | |
INTEL|clflushopt|CLFLUSHOPT instruction | |
INTEL|clflush|CLFLUSH instruction | |
INTEL|clwb|CLWB instruction | |
INTEL|cmov|CMOV instructions (plus FCMOVcc, FCOMI with FPU) | |
INTEL|cqm|Cache QoS Monitoring | |
INTEL|cx8|CMPXCHG8 instruction | |
INTEL|cx16|CMPXCHG16B instruction | |
INTEL|dca|Direct Cache Access | |
INTEL|de|Debugging Extensions | |
INTEL|dscpl|"ds_cpl" CPL-qualified (filtered) Debug Store | |
INTEL|ds|"dts" Debug Store | |
INTEL|dtes64|64-bit Debug Store | |
INTEL|erms|Enhanced REP MOVSB/STOSB instructions | |
INTEL|est|Enhanced SpeedStep | |
INTEL|f16c|16-bit FP conversions | |
INTEL|flush_l1d28|Flush L1D cache | |
INTEL|fma|Fused multiply-add | |
INTEL|fpu|Onboard FPU | |
INTEL|fsgsbase|RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions | |
INTEL|fxsr_opt|AMD | |
INTEL|fxsr|FXSAVE/FXRSTOR, CR4.OSFXSR | |
INTEL|gbpages|AMD | |
INTEL|gfni|Galois Field New Instructions | |
INTEL|hle|Hardware Lock Elision | |
INTEL|ht|Hyper-Threading | |
INTEL|hypervisor|Running on a hypervisor | |
INTEL|ia64|IA-64 processor | |
INTEL|intel_pt|Intel Processor Trace | |
INTEL|intel_stibp27|Single Thread Indirect Branch Predictors | |
INTEL|invpcid|Invalidate Processor Context ID | |
INTEL|la5716|5-level page tables | |
INTEL|lm|AMD | |
INTEL|mca|Machine Check Architecture | |
INTEL|mce|Machine Check Exception | |
INTEL|mmxext|AMD | |
INTEL|mmx|Multimedia Extensions | |
INTEL|movbe|MOVBE instruction | |
INTEL|movdir64b28|MOVDIR64B instruction | |
INTEL|movdiri27|MOVDIRI instruction | |
INTEL|mpx|Memory Protection Extension | |
INTEL|mp|AMD | |
INTEL|msr|Model-Specific Registers | |
INTEL|mtrr|Memory Type Range Registers | |
INTEL|mwait|"monitor" MONITOR/MWAIT support | |
INTEL|nx|AMD | |
INTEL|ospke|OS Protection Keys Enable | |
INTEL|osxsave|XSAVE instruction enabled in the OS | |
INTEL|pae|Physical Address Extensions | |
INTEL|pat|Page Attribute Table | |
INTEL|pbe|Pending Break Enable | |
INTEL|pcid|Process Context Identifiers | |
INTEL|pclmulqdq|PCLMULQDQ instruction | |
INTEL|pconfig18|Intel PCONFIG | |
INTEL|pdcm|Perf/Debug Capabilities MSR | |
INTEL|pge|Page Global Enable | |
INTEL|pku|Protection Keys for Userspace | |
INTEL|pn|Processor serial number | |
INTEL|popcnt|POPCNT instruction | |
INTEL|pse36|36-bit PSEs | |
INTEL|pse|Page Size Extensions | |
INTEL|rdpid22|RDPID instruction | |
INTEL|rdrand|RDRAND instruction | |
INTEL|rdseed|RDSEED instruction | |
INTEL|rdtscp|AMD | |
INTEL|rdt_a|Resource Director Technology Allocation | |
INTEL|rtm|Restricted Transactional Memory | |
INTEL|sdbg|Silicon Debug | |
INTEL|selfsnoop|"ss" CPU self snoop | |
INTEL|sep|SYSENTER/SYSEXIT | |
INTEL|sha_ni|SHA1/SHA256 Instruction Extensions | |
INTEL|smap|Supervisor Mode Access Prevention | |
INTEL|smep|Supervisor Mode Execution Protection | |
INTEL|smx|Safer Mode eXtensions | |
INTEL|spec_ctrl26|Speculation Control (IBRS + IBPB) | |
INTEL|spec_ctrl_ssbd31|Speculative Store Bypass Disable | |
INTEL|ssse3|Supplemental SSE-3 | |
INTEL|syscall|AMD | |
INTEL|tm2|Thermal Monitor | |
INTEL|tme13|Intel Total Memory Encryption | |
INTEL|tsc_adjust|TSC adjustment MSR | |
INTEL|tsc_deadline_timer|TSC deadline timer | |
INTEL|tsc|Time Stamp Counter | |
INTEL|umip|User Mode Instruction Protection | |
INTEL|vaes|Vector AES | |
INTEL|vme|Virtual Mode Extensions | |
INTEL|vmx|Hardware virtualization | |
INTEL|vpclmulqdq10|Carry-Less Multiplication Double Quadword | |
INTEL|x2apic|X2APIC | |
INTEL|xmm2|"sse2" | |
INTEL|xmm3|"pni" SSE-3 | |
INTEL|xmm4_1|"sse4_1" SSE-4.1 | |
INTEL|xmm4_2|"sse4_2" SSE-4.2 | |
INTEL|xmm|"sse" | |
INTEL|xsave|XSAVE/XRSTOR/XSETBV/XGETBV instructions | |
INTEL|xtpr|Send Task Priority Messages | |
OTHER|centaur_mcr|Centaur MCRs (= MTRRs) | |
OTHER|cxmmx|Cyrix MMX extensions | |
OTHER|cyrix_arr|Cyrix ARRs (= MTRRs) | |
OTHER|k6_mtrr|AMD K6 nonstandard MTRRs | |
THERMAL|arat|Always Running APIC Timer | |
THERMAL|dtherm|Digital Thermal Sensor | |
THERMAL|hwp_act_window|HWP Activity Window | |
THERMAL|hwp_epp10|HWP Energy Perf. Preference | |
THERMAL|hwp_notify|HWP Notification | |
THERMAL|hwp_pkg_req11|HWP Package Level Request | |
THERMAL|hwp|Intel Hardware P-states | |
THERMAL|ida|Intel Dynamic Acceleration | |
THERMAL|pln|Intel Power Limit Notification | |
THERMAL|pts|Intel Package Thermal Status | |
TRANSMETA|longrun|Longrun power control | |
TRANSMETA|lrti|LongRun table interface | |
TRANSMETA|recovery|CPU in recovery mode | |
V12N|ept_ad|Intel Extended Page Table access-dirty bit | |
V12N|ept|Intel Extended Page Table | |
V12N|flexpriority|Intel FlexPriority | |
V12N|tpr_shadow|Intel TPR Shadow | |
V12N|vmmcall|Prefer VMMCALL to VMCALL | |
V12N|vnmi|Intel Virtual NMI | |
V12N|vpid|Intel Virtual Processor ID | |
V12N|xenpv|Xen paravirtual guest | |
VIA|ace2_en|ACE v2 enabled | |
VIA|ace2|Advanced Cryptography Engine v2 | |
VIA|phe_en|PHE enabled | |
VIA|phe|PadLock Hash Engine | |
VIA|pmm_en|PMM enabled | |
VIA|pmm|PadLock Montgomery Multiplier | |
VIA|xcrypt_en|"ace_en" on-CPU crypto enabled | |
VIA|xcrypt|"ace" on-CPU crypto (xcrypt) | |
VIA|xstore_en|"rng_en" RNG enabled | |
VIA|xstore|"rng" RNG present (xstore) |
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