Created
September 5, 2022 14:44
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TPS950 MSM8953 DTS
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| /dts-v1/; | |
| / { | |
| model = "Qualcomm Technologies, Inc. SDM450"; | |
| compatible = "qcom,sdm450", "qcom,msm8953"; | |
| #address-cells = <0x02>; | |
| qcom,msm-id = <0x152 0x00>; | |
| qcom,board-id = <0x08 0x00>; | |
| #size-cells = <0x02>; | |
| interrupt-parent = <0x01>; | |
| soc { | |
| compatible = "simple-bus"; | |
| ranges = <0x00 0x00 0x00 0xffffffff>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| cti@6010000 { | |
| reg = <0x6010000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti0"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| phandle = <0x48>; | |
| coresight-nr-inports = <0x00>; | |
| linux,phandle = <0x48>; | |
| coresight-id = <0x14>; | |
| }; | |
| cti@6011000 { | |
| reg = <0x6011000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti1"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x15>; | |
| }; | |
| cti@6012000 { | |
| reg = <0x6012000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti2"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x16>; | |
| }; | |
| cti@6013000 { | |
| reg = <0x6013000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti3"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x17>; | |
| }; | |
| cti@6014000 { | |
| reg = <0x6014000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti4"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x18>; | |
| }; | |
| cti@6015000 { | |
| reg = <0x6015000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti5"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x19>; | |
| }; | |
| cti@6016000 { | |
| reg = <0x6016000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti6"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x1a>; | |
| }; | |
| cti@6017000 { | |
| reg = <0x6017000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti7"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x1b>; | |
| }; | |
| cti@6018000 { | |
| reg = <0x6018000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti8"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| phandle = <0x49>; | |
| coresight-nr-inports = <0x00>; | |
| linux,phandle = <0x49>; | |
| coresight-id = <0x1c>; | |
| }; | |
| cti@6019000 { | |
| reg = <0x6019000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti9"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x1d>; | |
| }; | |
| qcom,smp2p-adsp@0x0b011008 { | |
| reg = <0xb011008 0x04>; | |
| interrupts = <0x00 0x123 0x01>; | |
| qcom,irq-bitmask = <0x400>; | |
| qcom,remote-pid = <0x02>; | |
| compatible = "qcom,smp2p"; | |
| }; | |
| funnel@6021000 { | |
| reg = <0x6021000 0x1000>; | |
| reg-names = "funnel-base"; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-funnel-in0"; | |
| compatible = "arm,coresight-funnel"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-child-ports = <0x00>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| phandle = <0x70>; | |
| coresight-child-list = <0x6f>; | |
| coresight-nr-inports = <0x08>; | |
| linux,phandle = <0x70>; | |
| coresight-id = <0x04>; | |
| }; | |
| cti@601a000 { | |
| reg = <0x601a000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti10"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x1e>; | |
| }; | |
| cti@601b000 { | |
| reg = <0x601b000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti11"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x1f>; | |
| }; | |
| cti@601c000 { | |
| reg = <0x601c000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti12"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x20>; | |
| }; | |
| cti@601d000 { | |
| reg = <0x601d000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti13"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x21>; | |
| }; | |
| cti@601e000 { | |
| reg = <0x601e000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti14"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x22>; | |
| }; | |
| cti@601f000 { | |
| reg = <0x601f000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti15"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x23>; | |
| }; | |
| qcom,msm-imem@8600000 { | |
| reg = <0x8600000 0x1000>; | |
| compatible = "qcom,msm-imem"; | |
| ranges = <0x00 0x8600000 0x1000>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| restart_reason@65c { | |
| reg = <0x65c 0x04>; | |
| compatible = "qcom,msm-imem-restart_reason"; | |
| }; | |
| dload_type@18 { | |
| reg = <0x18 0x04>; | |
| compatible = "qcom,msm-imem-dload-type"; | |
| }; | |
| boot_stats@6b0 { | |
| reg = <0x6b0 0x20>; | |
| compatible = "qcom,msm-imem-boot_stats"; | |
| }; | |
| pil@94c { | |
| reg = <0x94c 0xc8>; | |
| compatible = "qcom,msm-imem-pil"; | |
| }; | |
| mem_dump_table@10 { | |
| reg = <0x10 0x08>; | |
| compatible = "qcom,msm-imem-mem_dump_table"; | |
| }; | |
| }; | |
| cti@6124000 { | |
| reg = <0x6124000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-modem-cpu1"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x2d>; | |
| }; | |
| funnel@6100000 { | |
| reg = <0x6100000 0x1000>; | |
| reg-names = "funnel-base"; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-funnel-center"; | |
| compatible = "arm,coresight-funnel"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-child-ports = <0x03>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| phandle = <0x74>; | |
| coresight-child-list = <0x70>; | |
| coresight-nr-inports = <0x08>; | |
| linux,phandle = <0x74>; | |
| coresight-id = <0x05>; | |
| }; | |
| cti@6128000 { | |
| reg = <0x6128000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-modem-cpu0"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x2c>; | |
| }; | |
| cti@6134000 { | |
| reg = <0x6134000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-video-cpu0"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x2e>; | |
| }; | |
| cti@6139000 { | |
| reg = <0x6139000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-wcn-cpu0"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x2f>; | |
| }; | |
| funnel@6120000 { | |
| reg = <0x6120000 0x1000>; | |
| reg-names = "funnel-base"; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-funnel-right"; | |
| compatible = "arm,coresight-funnel"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-child-ports = <0x04>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| phandle = <0x71>; | |
| coresight-child-list = <0x70>; | |
| coresight-nr-inports = <0x08>; | |
| linux,phandle = <0x71>; | |
| coresight-id = <0x06>; | |
| }; | |
| cti@610c000 { | |
| reg = <0x610c000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-rpm-cpu0"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x31>; | |
| }; | |
| funnel@6130000 { | |
| reg = <0x6130000 0x1000>; | |
| reg-names = "funnel-base"; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coesight-funnel-mm"; | |
| compatible = "arm,coresight-funnel"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-child-ports = <0x05>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| phandle = <0x3c>; | |
| coresight-child-list = <0x70>; | |
| coresight-nr-inports = <0x08>; | |
| linux,phandle = <0x3c>; | |
| coresight-id = <0x07>; | |
| }; | |
| funnel@6132000 { | |
| reg = <0x6132000 0x1000>; | |
| reg-names = "funnel-base"; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-funnel-cam"; | |
| compatible = "arm,coresight-funnel"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-child-ports = <0x04>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-child-list = <0x3c>; | |
| coresight-nr-inports = <0x08>; | |
| coresight-id = <0x08>; | |
| }; | |
| cti@613c000 { | |
| reg = <0x613c000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-audio-cpu0"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x30>; | |
| }; | |
| qcom,irqrouter@1b00000 { | |
| reg = <0x1b00000 0x100>; | |
| reg-names = "irqrouter"; | |
| compatible = "qcom,irqrouter"; | |
| cell-index = <0x00>; | |
| status = "ok"; | |
| }; | |
| cti@6198000 { | |
| reg = <0x6198000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu0"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-cti-cpu = <0x02>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x24>; | |
| }; | |
| cti@6199000 { | |
| reg = <0x6199000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu1"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-cti-cpu = <0x03>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x25>; | |
| }; | |
| qcom,kgsl-busmon { | |
| label = "kgsl-busmon"; | |
| compatible = "qcom,kgsl-busmon"; | |
| }; | |
| cti@619a000 { | |
| reg = <0x619a000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu2"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-cti-cpu = <0x04>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x26>; | |
| }; | |
| cti@619b000 { | |
| reg = <0x619b000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu3"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-cti-cpu = <0x05>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x27>; | |
| }; | |
| qcom,vfe1@1b14000 { | |
| reg = <0x1b14000 0x1000 0x1ba0000 0x200>; | |
| interrupts = <0x00 0x1d 0x00>; | |
| reg-names = "vfe\0vfe_vbif"; | |
| ds-regs = <0x988 0x98c 0x990 0x994 0x998 0x99c 0x9a0 0x9a4 0x9a8 0x9ac 0x9b0 0x9b4 0x9b8 0x9bc 0x9c0 0x9c4 0x9c8>; | |
| compatible = "qcom,vfe40"; | |
| clock-names = "camss_top_ahb_clk\0camss_ahb_clk\0vfe_clk_src\0camss_vfe_vfe_clk\0camss_csi_vfe_clk\0iface_clk\0bus_clk\0iface_ahb_clk"; | |
| max-clk-turbo = <0x1bb75640>; | |
| interrupt-names = "vfe"; | |
| vbif-settings = <0x03>; | |
| max-clk-nominal = <0x1bb75640>; | |
| clocks = <0x37 0x4e814a78 0x37 0x9894b414 0x37 0x4e357366 0x37 0xcaf20d99 0x37 0xb1ef6e8b 0x37 0x634a738a 0x37 0xaf7463b3 0x37 0x3c0a858f>; | |
| vbif-entries = <0x01>; | |
| vbif-regs = <0x124>; | |
| ds-settings = <0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0x110>; | |
| cell-index = <0x01>; | |
| qos-settings = <0xaa55aa55 0xaa55aa55 0xaa55aa55 0xaa55aa55 0xaa55aa55 0xaa55aa55 0xaa55aa55 0xaa55aa55>; | |
| ds-entries = <0x11>; | |
| vdd-supply = <0x175>; | |
| qos-entries = <0x08>; | |
| qos-regs = <0x2c4 0x2c8 0x2cc 0x2d0 0x2d4 0x2d8 0x2dc 0x2e0>; | |
| qcom,clock-rates = <0x00 0x00 0xfe50fb0 0x00 0x00 0x00 0x00 0x00>; | |
| }; | |
| qcom,rmtfs_sharedmem@00000000 { | |
| reg = <0x00 0x180000>; | |
| qcom,client-id = <0x01>; | |
| reg-names = "rmtfs"; | |
| compatible = "qcom,sharedmem-uio"; | |
| }; | |
| cpu-pmu { | |
| interrupts = <0x01 0x07 0xff00>; | |
| compatible = "arm,armv8-pmuv3"; | |
| }; | |
| fuse@a601c { | |
| reg = <0xa601c 0x08 0xa6004 0x04 0xa600c 0x04>; | |
| reg-names = "fuse-base\0nidnt-fuse-base\0qpdi-fuse-base"; | |
| coresight-name = "coresight-fuse"; | |
| compatible = "arm,coresight-fuse-v2"; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x3c>; | |
| }; | |
| qcom,wdt@b017000 { | |
| reg = <0xb017000 0x1000>; | |
| interrupts = <0x00 0x03 0x00 0x00 0x04 0x00>; | |
| qcom,pet-time = <0x2710>; | |
| reg-names = "wdt-base"; | |
| qcom,wakeup-enable; | |
| compatible = "qcom,msm-watchdog"; | |
| qcom,ipi-ping; | |
| qcom,bark-time = <0x2af8>; | |
| }; | |
| cti@61b8000 { | |
| reg = <0x61b8000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu4"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-cti-cpu = <0x06>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x28>; | |
| }; | |
| cti@61b9000 { | |
| reg = <0x61b9000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu5"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-cti-cpu = <0x07>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x29>; | |
| }; | |
| funnel@61a1000 { | |
| reg = <0x61a1000 0x1000>; | |
| reg-names = "funnel-base"; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-funnel-apss0"; | |
| compatible = "arm,coresight-funnel"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-child-ports = <0x00>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| phandle = <0x73>; | |
| coresight-child-list = <0x72>; | |
| coresight-nr-inports = <0x08>; | |
| linux,phandle = <0x73>; | |
| coresight-id = <0x0a>; | |
| }; | |
| cti@61ba000 { | |
| reg = <0x61ba000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu6"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-cti-cpu = <0x08>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x2a>; | |
| }; | |
| cti@61bb000 { | |
| reg = <0x61bb000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu7"; | |
| compatible = "arm,coresight-cti"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-cti-cpu = <0x09>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x2b>; | |
| }; | |
| funnel@61d0000 { | |
| reg = <0x61d0000 0x1000>; | |
| reg-names = "funnel-base"; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-funnel-apss1"; | |
| compatible = "arm,coresight-funnel"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-child-ports = <0x03>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| phandle = <0x72>; | |
| coresight-child-list = <0x71>; | |
| coresight-nr-inports = <0x08>; | |
| linux,phandle = <0x72>; | |
| coresight-id = <0x09>; | |
| }; | |
| qcom,msm-cpe-lsm { | |
| compatible = "qcom,msm-cpe-lsm"; | |
| phandle = <0x163>; | |
| linux,phandle = <0x163>; | |
| }; | |
| uart@78b0000 { | |
| reg = <0x78b0000 0x200 0x7884000 0x1f000>; | |
| qcom,msm-bus,vectors-KBps = <0x56 0x200 0x00 0x00 0x56 0x200 0x1f4 0x320>; | |
| interrupts = <0x00 0x01 0x02>; | |
| pinctrl-0 = <0xce>; | |
| pinctrl-1 = <0xcf>; | |
| reg-names = "core_mem\0bam_mem"; | |
| qcom,bam-tx-ep-pipe-index = <0x02>; | |
| compatible = "qcom,msm-hsuart-v14"; | |
| clock-names = "core_clk\0iface_clk"; | |
| qcom,msm-bus,name = "blsp1_uart1"; | |
| interrupt-names = "core_irq\0bam_irq\0wakeup_irq"; | |
| clocks = <0x37 0xf8a61c96 0x37 0x8caa5b4f>; | |
| #interrupt-cells = <0x01>; | |
| qcom,rx-char-to-inject = <0xfd>; | |
| qcom,bam-rx-ep-pipe-index = <0x03>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| status = "okay"; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| #address-cells = <0x00>; | |
| interrupt-map = <0x00 0x01 0x00 0x6c 0x00 0x01 0x01 0x00 0xee 0x00 0x02 0xbe 0x0d 0x00>; | |
| interrupt-map-mask = <0xffffffff>; | |
| qcom,master-id = <0x56>; | |
| phandle = <0xcd>; | |
| pinctrl-names = "sleep\0default"; | |
| qcom,inject-rx-on-wakeup; | |
| linux,phandle = <0xcd>; | |
| interrupt-parent = <0xcd>; | |
| }; | |
| usb_detect { | |
| interrupts = <0x00 0xc6 0x00>; | |
| compatible = "qcom,gpio-usbdetect"; | |
| interrupt-names = "vbus_det_irq"; | |
| interrupt-parent = <0x113>; | |
| }; | |
| qcom,camera-flash { | |
| compatible = "qcom,camera-flash"; | |
| qcom,torch-source = <0x19f>; | |
| qcom,flash-type = <0x03>; | |
| qcom,switch-source = <0x19f>; | |
| cell-index = <0x00>; | |
| qcom,flash-source = <0x19f>; | |
| }; | |
| qcom,msm-dai-fe { | |
| compatible = "qcom,msm-dai-fe"; | |
| }; | |
| qcom,msm-dai-q6 { | |
| compatible = "qcom,msm-dai-q6"; | |
| qcom,msm-dai-q6-incall-music-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x8005>; | |
| phandle = <0x15d>; | |
| linux,phandle = <0x15d>; | |
| }; | |
| qcom,msm-dai-q6-sb-0-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4000>; | |
| phandle = <0x14b>; | |
| linux,phandle = <0x14b>; | |
| }; | |
| qcom,msm-dai-q6-sb-0-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4001>; | |
| phandle = <0x14c>; | |
| linux,phandle = <0x14c>; | |
| }; | |
| qcom,msm-dai-q6-sb-1-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4002>; | |
| phandle = <0x14d>; | |
| linux,phandle = <0x14d>; | |
| }; | |
| qcom,msm-dai-q6-sb-1-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4003>; | |
| phandle = <0x14e>; | |
| linux,phandle = <0x14e>; | |
| }; | |
| qcom,msm-dai-q6-sb-2-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4004>; | |
| phandle = <0x164>; | |
| linux,phandle = <0x164>; | |
| }; | |
| qcom,msm-dai-q6-sb-2-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4005>; | |
| phandle = <0x165>; | |
| linux,phandle = <0x165>; | |
| }; | |
| qcom,msm-dai-q6-sb-3-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4006>; | |
| phandle = <0x14f>; | |
| linux,phandle = <0x14f>; | |
| }; | |
| qcom,msm-dai-q6-sb-3-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4007>; | |
| phandle = <0x150>; | |
| linux,phandle = <0x150>; | |
| }; | |
| qcom,msm-dai-q6-sb-4-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4008>; | |
| phandle = <0x151>; | |
| linux,phandle = <0x151>; | |
| }; | |
| qcom,msm-dai-q6-sb-4-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4009>; | |
| phandle = <0x152>; | |
| linux,phandle = <0x152>; | |
| }; | |
| qcom,msm-dai-q6-sb-5-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x400a>; | |
| phandle = <0x167>; | |
| linux,phandle = <0x167>; | |
| }; | |
| qcom,msm-dai-q6-sb-5-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x400b>; | |
| phandle = <0x166>; | |
| linux,phandle = <0x166>; | |
| }; | |
| qcom,msm-dai-q6-sb-6-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x400c>; | |
| phandle = <0x168>; | |
| linux,phandle = <0x168>; | |
| }; | |
| qcom,msm-dai-q6-afe-proxy-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0xf1>; | |
| phandle = <0x159>; | |
| linux,phandle = <0x159>; | |
| }; | |
| qcom,msm-dai-q6-afe-proxy-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0xf0>; | |
| phandle = <0x15a>; | |
| linux,phandle = <0x15a>; | |
| }; | |
| qcom,msm-dai-q6-incall-record-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x8003>; | |
| phandle = <0x15b>; | |
| linux,phandle = <0x15b>; | |
| }; | |
| qcom,msm-dai-q6-incall-record-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x8004>; | |
| phandle = <0x15c>; | |
| linux,phandle = <0x15c>; | |
| }; | |
| qcom,msm-dai-q6-be-afe-pcm-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0xe0>; | |
| phandle = <0x157>; | |
| linux,phandle = <0x157>; | |
| }; | |
| qcom,msm-dai-q6-be-afe-pcm-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0xe1>; | |
| phandle = <0x158>; | |
| linux,phandle = <0x158>; | |
| }; | |
| qcom,msm-dai-q6-int-fm-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x3004>; | |
| phandle = <0x155>; | |
| linux,phandle = <0x155>; | |
| }; | |
| qcom,msm-dai-q6-int-fm-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x3005>; | |
| phandle = <0x156>; | |
| linux,phandle = <0x156>; | |
| }; | |
| qcom,msm-dai-q6-incall-music-2-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x8002>; | |
| phandle = <0x15e>; | |
| linux,phandle = <0x15e>; | |
| }; | |
| qcom,msm-dai-q6-bt-sco-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x3000>; | |
| phandle = <0x153>; | |
| linux,phandle = <0x153>; | |
| }; | |
| qcom,msm-dai-q6-bt-sco-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x3001>; | |
| phandle = <0x154>; | |
| linux,phandle = <0x154>; | |
| }; | |
| }; | |
| qcom,msm-audio-ion { | |
| qcom,smmu-enabled; | |
| compatible = "qcom,msm-audio-ion"; | |
| qcom,smmu-version = <0x01>; | |
| iommus = <0x12c 0x01>; | |
| }; | |
| serial@78af000 { | |
| reg = <0x78af000 0x200>; | |
| interrupts = <0x00 0x6b 0x00>; | |
| pinctrl-0 = <0xca>; | |
| compatible = "qcom,msm-lsuart-v14"; | |
| clock-names = "core_clk\0iface_clk"; | |
| clocks = <0x37 0xc7c62f90 0x37 0x8caa5b4f>; | |
| status = "ok"; | |
| pinctrl-names = "default"; | |
| }; | |
| qcom,kgsl-iommu@1c40000 { | |
| reg = <0x1c40000 0x10000>; | |
| qcom,retention; | |
| qcom,protect = <0x40000 0x10000>; | |
| compatible = "qcom,kgsl-smmu-v2"; | |
| clock-names = "gpu_ahb_clk\0gcc_bimc_gfx_clk"; | |
| qcom,micro-mmu-control = <0x6000>; | |
| clocks = <0x38 0xd15c8a00 0x38 0x3edd69ad>; | |
| qcom,secure_align_mask = <0xfff>; | |
| gfx3d_secure { | |
| compatible = "qcom,smmu-kgsl-cb"; | |
| iommus = <0x3d 0x02>; | |
| memory-region = <0x3e>; | |
| }; | |
| gfx3d_user { | |
| label = "gfx3d_user"; | |
| compatible = "qcom,smmu-kgsl-cb"; | |
| iommus = <0x3d 0x00>; | |
| qcom,gpu-offset = <0x48000>; | |
| }; | |
| }; | |
| qcom,ipc_router_wcnss_xprt { | |
| qcom,fragmented-data; | |
| qcom,ch-name = "IPCRTR"; | |
| compatible = "qcom,ipc_router_smd_xprt"; | |
| qcom,xprt-linkid = <0x01>; | |
| qcom,xprt-remote = "wcnss"; | |
| qcom,xprt-version = <0x01>; | |
| }; | |
| qcom,msm-cpufreq { | |
| compatible = "qcom,msm-cpufreq"; | |
| clock-names = "l2_clk\0cpu0_clk\0cpu1_clk\0cpu2_clk\0cpu3_clk\0cpu4_clk\0cpu5_clk\0cpu6_clk\0cpu7_clk"; | |
| clocks = <0xb3 0x96854074 0xb3 0x2e6af930 0xb3 0x2e6af930 0xb3 0x2e6af930 0xb3 0x2e6af930 0xb3 0x2e6af930 0xb3 0x2e6af930 0xb3 0x2e6af930 0xb3 0x2e6af930>; | |
| qcom,cpufreq-table = <0x9f600 0xfd200 0x156300 0x19c800 0x1b8a00 0x1de200 0x1ec300 0x20d000 0x21b100>; | |
| }; | |
| qcom,venus@1de0000 { | |
| reg = <0x1de0000 0x4000>; | |
| qcom,msm-bus,vectors-KBps = <0x3f 0x200 0x00 0x00 0x3f 0x200 0x00 0x4a380>; | |
| qcom,firmware-name = "venus"; | |
| compatible = "qcom,pil-tz-generic"; | |
| clock-names = "core_clk\0iface_clk\0bus_clk\0scm_core_clk\0scm_iface_clk\0scm_bus_clk\0scm_core_clk_src"; | |
| qcom,msm-bus,name = "pil-venus"; | |
| clocks = <0x37 0xf76a02bb 0x37 0x8d778c6 0x37 0xcdf4c8f6 0x37 0xd390d2 0x37 0x94de4919 0x37 0xd4415c9b 0x37 0x37a21414>; | |
| qcom,proxy-reg-names = "vdd"; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,proxy-timeout-ms = <0x64>; | |
| qcom,scm_core_clk_src-freq = <0x4c4b400>; | |
| qcom,pas-id = <0x09>; | |
| vdd-supply = <0xb8>; | |
| memory-region = <0x11c>; | |
| qcom,proxy-clock-names = "core_clk\0iface_clk\0bus_clk\0scm_core_clk\0scm_iface_clk\0scm_bus_clk\0scm_core_clk_src"; | |
| }; | |
| qcom,msm-pcm-hostless { | |
| compatible = "qcom,msm-pcm-hostless"; | |
| phandle = <0x13f>; | |
| linux,phandle = <0x13f>; | |
| }; | |
| qcom,memshare { | |
| compatible = "qcom,memshare"; | |
| qcom,client_1 { | |
| qcom,client-id = <0x00>; | |
| label = "modem"; | |
| qcom,allocate-boot-time; | |
| compatible = "qcom,memshare-peripheral"; | |
| qcom,peripheral-size = <0x200000>; | |
| }; | |
| qcom,client_2 { | |
| qcom,client-id = <0x02>; | |
| label = "modem"; | |
| compatible = "qcom,memshare-peripheral"; | |
| qcom,peripheral-size = <0x300000>; | |
| }; | |
| qcom,client_3 { | |
| qcom,client-id = <0x01>; | |
| label = "modem"; | |
| compatible = "qcom,memshare-peripheral"; | |
| qcom,peripheral-size = <0x500000>; | |
| }; | |
| }; | |
| qcom,rpm-log@29fc00 { | |
| reg = <0x29fc00 0x4000>; | |
| compatible = "qcom,rpm-log"; | |
| qcom,offset-log-len = <0x28>; | |
| qcom,offset-page-buffer-addr = <0x24>; | |
| qcom,offset-log-len-mask = <0x2c>; | |
| qcom,offset-version = <0x04>; | |
| qcom,rpm-addr-phys = <0x200000>; | |
| qcom,offset-page-indices = <0x38>; | |
| }; | |
| qcom,pronto@a21b000 { | |
| reg = <0xa21b000 0x3000>; | |
| vdd_pronto_pll-uV-uA = <0x1b7740 0x4650>; | |
| interrupts = <0x00 0x95 0x01>; | |
| qcom,firmware-name = "wcnss"; | |
| qcom,gpio-err-fatal = <0x11d 0x00 0x00>; | |
| qcom,gpio-err-ready = <0x11d 0x01 0x00>; | |
| compatible = "qcom,pil-tz-generic"; | |
| clock-names = "xo\0scm_core_clk\0scm_iface_clk\0scm_bus_clk\0scm_core_clk_src"; | |
| vdd_pronto_pll-supply = <0xf5>; | |
| qcom,gpio-force-stop = <0x11e 0x00 0x00>; | |
| qcom,gpio-stop-ack = <0x11d 0x03 0x00>; | |
| clocks = <0x37 0x89dae6d0 0x37 0xd390d2 0x37 0x94de4919 0x37 0xd4415c9b 0x37 0x37a21414>; | |
| qcom,smem-id = <0x1a6>; | |
| qcom,ssctl-instance-id = <0x13>; | |
| qcom,sysmon-id = <0x06>; | |
| qcom,proxy-timeout-ms = <0x2710>; | |
| qcom,gpio-proxy-unvote = <0x11d 0x02 0x00>; | |
| proxy-reg-names = "vdd_pronto_pll"; | |
| qcom,pas-id = <0x06>; | |
| memory-region = <0x11f>; | |
| qcom,scm_core_clk_src = <0x4c4b400>; | |
| qcom,proxy-clock-names = "xo\0scm_core_clk\0scm_iface_clk\0scm_bus_clk\0scm_core_clk_src"; | |
| }; | |
| qcom,gdsc@185701c { | |
| reg = <0x185701c 0x04>; | |
| regulator-name = "gdsc_jpeg"; | |
| compatible = "qcom,gdsc"; | |
| clock-names = "core_clk\0bus_clk"; | |
| clocks = <0x37 0x1ed3f032 0x37 0x3e278896>; | |
| status = "okay"; | |
| phandle = <0x177>; | |
| linux,phandle = <0x177>; | |
| }; | |
| qcom,gdsc@1858034 { | |
| reg = <0x1858034 0x04>; | |
| regulator-name = "gdsc_vfe"; | |
| compatible = "qcom,gdsc"; | |
| clock-names = "core_clk\0bus_clk\0micro_clk\0csi_clk"; | |
| clocks = <0x37 0xaaa3cd97 0x37 0x77fe2384 0x37 0xfbbee8cf 0x37 0xcc73453c>; | |
| status = "okay"; | |
| phandle = <0x174>; | |
| linux,phandle = <0x174>; | |
| }; | |
| qcom,gdsc@1858078 { | |
| reg = <0x1858078 0x04>; | |
| regulator-name = "gdsc_cpp"; | |
| compatible = "qcom,gdsc"; | |
| clock-names = "core_clk\0bus_clk"; | |
| clocks = <0x37 0x7118a0de 0x37 0xbbf73861>; | |
| status = "okay"; | |
| phandle = <0x178>; | |
| linux,phandle = <0x178>; | |
| }; | |
| qcom,gdsc@185806c { | |
| reg = <0x185806c 0x04>; | |
| regulator-name = "gdsc_vfe1"; | |
| compatible = "qcom,gdsc"; | |
| clock-names = "core_clk\0bus_clk\0micro_clk\0csi_clk"; | |
| clocks = <0x37 0xcaf20d99 0x37 0xaf7463b3 0x37 0xfbbee8cf 0x37 0xb1ef6e8b>; | |
| status = "okay"; | |
| phandle = <0x175>; | |
| linux,phandle = <0x175>; | |
| }; | |
| qcom,gdsc@185901c { | |
| reg = <0x185901c 0x04>; | |
| regulator-name = "gdsc_oxili_gx"; | |
| compatible = "qcom,gdsc"; | |
| clock-names = "core_root_clk"; | |
| qcom,force-enable-root-clk; | |
| clocks = <0x38 0x917f76ef>; | |
| status = "okay"; | |
| parent-supply = <0xc8>; | |
| phandle = <0x3b>; | |
| linux,phandle = <0x3b>; | |
| }; | |
| qcom,gdsc@185904c { | |
| reg = <0x185904c 0x04>; | |
| regulator-name = "gdsc_oxili_cx"; | |
| compatible = "qcom,gdsc"; | |
| clock-names = "core_clk"; | |
| clocks = <0x38 0x49a51fd9>; | |
| status = "okay"; | |
| phandle = <0x3a>; | |
| linux,phandle = <0x3a>; | |
| }; | |
| qcom,gdsc@183f078 { | |
| reg = <0x183f078 0x04>; | |
| regulator-name = "gdsc_usb30"; | |
| compatible = "qcom,gdsc"; | |
| status = "okay"; | |
| phandle = <0x120>; | |
| linux,phandle = <0x120>; | |
| }; | |
| qcom,gdsc@184c018 { | |
| reg = <0x184c018 0x04>; | |
| regulator-name = "gdsc_venus"; | |
| compatible = "qcom,gdsc"; | |
| clock-names = "bus_clk\0core_clk"; | |
| clocks = <0x37 0xcdf4c8f6 0x37 0xf76a02bb>; | |
| status = "okay"; | |
| phandle = <0xb8>; | |
| linux,phandle = <0xb8>; | |
| }; | |
| qcom,gdsc@184c028 { | |
| reg = <0x184c028 0x04>; | |
| regulator-name = "gdsc_venus_core0"; | |
| compatible = "qcom,gdsc"; | |
| clock-names = "core0_clk"; | |
| qcom,support-hw-trigger; | |
| clocks = <0x37 0x83a7f549>; | |
| status = "okay"; | |
| phandle = <0xb9>; | |
| linux,phandle = <0xb9>; | |
| }; | |
| qcom,gdsc@184c030 { | |
| reg = <0x184c030 0x04>; | |
| regulator-name = "gdsc_venus_core1"; | |
| compatible = "qcom,gdsc"; | |
| status = "disabled"; | |
| }; | |
| qcom,gdsc@184d078 { | |
| reg = <0x184d078 0x04>; | |
| proxy-supply = <0x172>; | |
| regulator-name = "gdsc_mdss"; | |
| compatible = "qcom,gdsc"; | |
| clock-names = "core_clk\0bus_clk"; | |
| clocks = <0x37 0x22f3521f 0x37 0x668f51de>; | |
| qcom,proxy-consumer-enable; | |
| status = "okay"; | |
| phandle = <0x172>; | |
| linux,phandle = <0x172>; | |
| }; | |
| ssusb@7000000 { | |
| reg = <0x7000000 0xfc000 0x7e000 0x400>; | |
| vbus_dwc3-supply = <0x121>; | |
| qcom,msm-bus,vectors-KBps = <0x3d 0x200 0x00 0x00 0x3d 0x200 0x3a980 0xc3500 0x3d 0x200 0x3a980 0xc3500>; | |
| interrupts = <0x00 0x88 0x00 0x00 0xdc 0x00 0x00 0x86 0x00>; | |
| otg,id_det_pin = <0xbe 0x8c 0x00>; | |
| reg-names = "core_base\0ahb2phy_base"; | |
| compatible = "qcom,dwc-usb3-msm"; | |
| clock-names = "core_clk\0iface_clk\0utmi_clk\0sleep_clk\0xo\0cfg_ahb_clk"; | |
| qcom,msm-bus,name = "usb3"; | |
| interrupt-names = "hs_phy_irq\0ss_phy_irq\0pwr_event_irq"; | |
| clocks = <0x37 0xb3b4e2cb 0x37 0xf7f4b314 0x37 0xa800b65a 0x37 0xd0b65c92 0x37 0xfad488ce 0x37 0xccb7e26f>; | |
| ranges; | |
| qcom,msm-bus,num-cases = <0x03>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,dwc-usb3-msm-tx-fifo-size = <0x5328>; | |
| #address-cells = <0x01>; | |
| qcom,usb-dbm = <0x122>; | |
| USB3_GDSC-supply = <0x120>; | |
| #size-cells = <0x01>; | |
| dwc3@7000000 { | |
| reg = <0x7000000 0xc8d0>; | |
| interrupts = <0x00 0x8c 0x00>; | |
| compatible = "snps,dwc3"; | |
| snps,usb3-u1u2-disable; | |
| snps,is-utmi-l1-suspend; | |
| tx-fifo-resize; | |
| snps,hird-threshold = [00]; | |
| usb-phy = <0x123 0x124>; | |
| interrupt-parent = <0x01>; | |
| snps,nominal-elastic-buffer; | |
| }; | |
| qcom,usbbam@7104000 { | |
| reg = <0x7104000 0x1a934>; | |
| qcom,usb-bam-fifo-baseaddr = "\b`P"; | |
| interrupts = <0x00 0x87 0x00>; | |
| qcom,usb-bam-override-threshold = <0x4001>; | |
| compatible = "qcom,usb-bam-msm"; | |
| qcom,ignore-core-reset-ack; | |
| qcom,disable-clk-gating; | |
| qcom,reset-bam-on-connect; | |
| qcom,usb-bam-max-mbps-superspeed = <0xe10>; | |
| qcom,usb-bam-num-pipes = <0x08>; | |
| qcom,usb-bam-max-mbps-highspeed = <0x190>; | |
| qcom,bam-type = <0x00>; | |
| interrupt-parent = <0x01>; | |
| qcom,pipe0 { | |
| qcom,src-bam-pipe-index = <0x01>; | |
| label = "ssusb-ipa-out-0"; | |
| qcom,dir = <0x00>; | |
| qcom,usb-bam-mem-type = <0x01>; | |
| qcom,pipe-num = <0x00>; | |
| qcom,data-fifo-size = <0x8000>; | |
| qcom,peer-bam = <0x01>; | |
| qcom,descriptor-fifo-size = <0x2000>; | |
| }; | |
| qcom,pipe1 { | |
| qcom,dst-bam-pipe-index = <0x00>; | |
| label = "ssusb-ipa-in-0"; | |
| qcom,dir = <0x01>; | |
| qcom,usb-bam-mem-type = <0x01>; | |
| qcom,pipe-num = <0x00>; | |
| qcom,data-fifo-size = <0x8000>; | |
| qcom,peer-bam = <0x01>; | |
| qcom,descriptor-fifo-size = <0x2000>; | |
| }; | |
| qcom,pipe2 { | |
| qcom,dst-bam-pipe-index = <0x02>; | |
| qcom,peer-bam-physical-address = <0x6044000>; | |
| qcom,src-bam-pipe-index = <0x00>; | |
| label = "ssusb-qdss-in-0"; | |
| qcom,dir = <0x01>; | |
| qcom,usb-bam-mem-type = <0x02>; | |
| qcom,pipe-num = <0x00>; | |
| qcom,data-fifo-size = <0xe00>; | |
| qcom,data-fifo-offset = <0x00>; | |
| qcom,descriptor-fifo-offset = <0xe00>; | |
| qcom,peer-bam = <0x00>; | |
| qcom,descriptor-fifo-size = <0x200>; | |
| }; | |
| qcom,pipe3 { | |
| qcom,dst-bam-pipe-index = <0x02>; | |
| label = "ssusb-dpl-ipa-in-1"; | |
| qcom,dir = <0x01>; | |
| qcom,usb-bam-mem-type = <0x01>; | |
| qcom,pipe-num = <0x01>; | |
| qcom,data-fifo-size = <0x8000>; | |
| qcom,peer-bam = <0x01>; | |
| qcom,descriptor-fifo-size = <0x2000>; | |
| }; | |
| }; | |
| }; | |
| eldo2 { | |
| gpio = <0xbe 0x32 0x00>; | |
| regulator-name = "eldo2_8953"; | |
| compatible = "regulator-fixed"; | |
| enable-active-high; | |
| regulator-always-on; | |
| phandle = <0xec>; | |
| startup-delay-us = <0x00>; | |
| linux,phandle = <0xec>; | |
| }; | |
| tpda@6003000 { | |
| reg = <0x6003000 0x1000>; | |
| reg-names = "tpda-base"; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-tpda"; | |
| compatible = "qcom,coresight-tpda"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| qcom,cmb-elem-size = <0x00 0x20>; | |
| coresight-child-ports = <0x06>; | |
| qcom,tpda-atid = <0x40>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| phandle = <0x75>; | |
| coresight-child-list = <0x70>; | |
| coresight-nr-inports = <0x02>; | |
| linux,phandle = <0x75>; | |
| coresight-id = <0x39>; | |
| }; | |
| qcom,avtimer@c0a300c { | |
| reg = <0xc0a300c 0x04 0xc0a3010 0x04>; | |
| reg-names = "avtimer_lsb_addr\0avtimer_msb_addr"; | |
| qcom,clk-div = <0x1b>; | |
| compatible = "qcom,avtimer"; | |
| }; | |
| qcom,iris-fm { | |
| compatible = "qcom,iris_fm"; | |
| }; | |
| sdcc1ice@7803000 { | |
| reg = <0x7803000 0x8000>; | |
| qcom,msm-bus,vectors-KBps = <0x4e 0x200 0x00 0x00 0x4e 0x200 0x3e8 0x00>; | |
| interrupts = <0x00 0x138 0x00 0x00 0x139 0x00>; | |
| compatible = "qcom,ice"; | |
| clock-names = "ice_core_clk_src\0ice_core_clk\0bus_clk\0iface_clk"; | |
| qcom,msm-bus,name = "sdcc_ice_noc"; | |
| interrupt-names = "sdcc_ice_nonsec_level_irq\0sdcc_ice_sec_level_irq"; | |
| qcom,enable-ice-clk; | |
| clocks = <0x37 0xfd6a4301 0x37 0xfd5680a 0x37 0x9ad6fb96 0x37 0x691e0caa>; | |
| qcom,bus-vector-names = "MIN\0MAX"; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,op-freq-hz = <0x1017df80 0x00 0x00 0x00>; | |
| phandle = <0xff>; | |
| qcom,instance-type = "sdcc"; | |
| linux,phandle = <0xff>; | |
| }; | |
| i2c@7af5000 { | |
| reg = <0x7af5000 0x600>; | |
| dmas = <0xe4 0x04 0x40 0x20000020 0x20 0xe4 0x05 0x20 0x20000020 0x20>; | |
| interrupts = <0x00 0x12b 0x00>; | |
| pinctrl-0 = <0xe2>; | |
| pinctrl-1 = <0xe3>; | |
| reg-names = "qup_phys_addr"; | |
| compatible = "qcom,i2c-msm-v2"; | |
| clock-names = "iface_clk\0core_clk"; | |
| qcom,clk-freq-in = <0x124f800>; | |
| interrupt-names = "qup_irq"; | |
| clocks = <0x37 0x8f283c1d 0x37 0x9ace11dd>; | |
| qcom,clk-freq-out = <0x61a80>; | |
| qcom,noise-rjct-scl = <0x00>; | |
| qcom,noise-rjct-sda = <0x00>; | |
| #address-cells = <0x01>; | |
| qcom,master-id = <0x54>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| pinctrl-names = "i2c_active\0i2c_sleep"; | |
| }; | |
| i2c@7af8000 { | |
| reg = <0x7af8000 0x600>; | |
| dmas = <0xe4 0x0a 0x40 0x20000020 0x20 0xe4 0x0b 0x20 0x20000020 0x20>; | |
| interrupts = <0x00 0x12e 0x00>; | |
| pinctrl-0 = <0xe5>; | |
| pinctrl-1 = <0xe6>; | |
| reg-names = "qup_phys_addr"; | |
| compatible = "qcom,i2c-msm-v2"; | |
| clock-names = "iface_clk\0core_clk"; | |
| qcom,clk-freq-in = <0x124f800>; | |
| interrupt-names = "qup_irq"; | |
| clocks = <0x37 0x8f283c1d 0x37 0xbd22539d>; | |
| qcom,clk-freq-out = <0x186a0>; | |
| qcom,noise-rjct-scl = <0x00>; | |
| qcom,noise-rjct-sda = <0x00>; | |
| #address-cells = <0x01>; | |
| qcom,master-id = <0x54>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| pinctrl-names = "i2c_active\0i2c_sleep"; | |
| gsl@40 { | |
| reg = <0x40>; | |
| interrupts = <0x41 0x2008>; | |
| vcc-i2c-supply = <0xe8>; | |
| compatible = "silead,gsl-tp"; | |
| gsl,irq-gpio = <0xbe 0x41 0x2002>; | |
| gsl,post-hard-reset-delay-ms = <0xc8>; | |
| gsl,name = "gsl"; | |
| gsl,hard-reset-delay-ms = <0x14>; | |
| gsl,button-map = <0x8b 0xac 0x9e>; | |
| gsl,panel-coords = <0x00 0x00 0x2d0 0x500>; | |
| gsl,reset-gpio = <0xbe 0x40 0x00>; | |
| gsl,display-coords = <0x00 0x00 0x21c 0x3c0>; | |
| vdd-supply = <0xe7>; | |
| gsl,num-max-touches = <0x05>; | |
| interrupt-parent = <0xbe>; | |
| }; | |
| }; | |
| qcom,csid@1b30000 { | |
| reg = <0x1b30000 0x400>; | |
| interrupts = <0x00 0x33 0x00>; | |
| reg-names = "csid"; | |
| compatible = "qcom,csid-v3.5.1\0qcom,csid"; | |
| clock-names = "camss_top_ahb_clk\0ispif_ahb_clk\0csi_ahb_clk\0csi_src_clk\0csi0_phy_clk\0csi_clk\0csi_pix_clk\0csi_rdi_clk\0camss_ahb_clk"; | |
| qcom,csi-vdd-voltage = <0x12b128>; | |
| interrupt-names = "csid"; | |
| clocks = <0x37 0x4e814a78 0x37 0x3c0a858f 0x37 0x175d672a 0x37 0x227e65bc 0x37 0x6a41ff7 0x37 0x6b01b3e1 0x37 0x61a8a930 0x37 0x7053c7ae 0x37 0x9894b414>; | |
| cell-index = <0x00>; | |
| status = "ok"; | |
| qcom,mipi-csi-vdd-supply = <0x173>; | |
| qcom,clock-rates = <0x00 0x3ab06a0 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x00>; | |
| }; | |
| qcom,csid@1b30400 { | |
| reg = <0x1b30400 0x400>; | |
| interrupts = <0x00 0x34 0x00>; | |
| reg-names = "csid"; | |
| compatible = "qcom,csid-v3.5.1\0qcom,csid"; | |
| clock-names = "camss_top_ahb_clk\0ispif_ahb_clk\0csi_ahb_clk\0csi_src_clk\0csi1_phy_clk\0csi_clk\0csi_pix_clk\0csi_rdi_clk\0camss_ahb_clk"; | |
| qcom,csi-vdd-voltage = <0x12b128>; | |
| interrupt-names = "csid"; | |
| clocks = <0x37 0x4e814a78 0x37 0x3c0a858f 0x37 0x2c2dc261 0x37 0x6a2a6c36 0x37 0xfd1d1fa 0x37 0x1aba4a8c 0x37 0x87fc98d8 0x37 0x6ac996fe 0x37 0x9894b414>; | |
| cell-index = <0x01>; | |
| status = "ok"; | |
| qcom,mipi-csi-vdd-supply = <0x173>; | |
| qcom,clock-rates = <0x00 0x3ab06a0 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x00>; | |
| }; | |
| qcom,csid@1b30800 { | |
| reg = <0x1b30800 0x400>; | |
| interrupts = <0x00 0x99 0x00>; | |
| reg-names = "csid"; | |
| compatible = "qcom,csid-v3.5.1\0qcom,csid"; | |
| clock-names = "camss_top_ahb_clk\0ispif_ahb_clk\0csi_ahb_clk\0csi_src_clk\0csi2_phy_clk\0csi_clk\0csi_pix_clk\0csi_rdi_clk\0camss_ahb_clk"; | |
| qcom,csi-vdd-voltage = <0x12b128>; | |
| interrupt-names = "csid"; | |
| clocks = <0x37 0x4e814a78 0x37 0x3c0a858f 0x37 0xf3f25940 0x37 0x4113589f 0x37 0xbeeffbcd 0x37 0xb6857fa2 0x37 0xa619561a 0x37 0x19fd3f1 0x37 0x9894b414>; | |
| cell-index = <0x02>; | |
| status = "ok"; | |
| qcom,mipi-csi-vdd-supply = <0x173>; | |
| qcom,clock-rates = <0x00 0x3ab06a0 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x00>; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_1_in { | |
| gpios = <0x42 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_1_in"; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_2_in { | |
| gpios = <0x46 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_2_in"; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_4_in { | |
| gpios = <0x44 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_4_in"; | |
| }; | |
| sound { | |
| reg = <0xc051000 0x04 0xc051004 0x04 0xc055000 0x04 0xc052000 0x04>; | |
| pinctrl-10 = <0x12d 0x15f 0x12f 0x135 0x131 0x132>; | |
| pinctrl-11 = <0x133 0x15f 0x134 0x135 0x131 0x132>; | |
| pinctrl-12 = <0x12d 0x15f 0x12f 0x130 0x136 0x137>; | |
| pinctrl-13 = <0x133 0x15f 0x134 0x130 0x136 0x137>; | |
| pinctrl-14 = <0x12d 0x15f 0x12f 0x135 0x136 0x137>; | |
| pinctrl-15 = <0x133 0x15f 0x134 0x135 0x136 0x137>; | |
| pinctrl-0 = <0x12d 0x12e 0x12f 0x130 0x131 0x132>; | |
| pinctrl-1 = <0x133 0x12e 0x134 0x130 0x131 0x132>; | |
| pinctrl-2 = <0x12d 0x12e 0x12f 0x135 0x131 0x132>; | |
| pinctrl-3 = <0x133 0x12e 0x134 0x135 0x131 0x132>; | |
| pinctrl-4 = <0x12d 0x12e 0x12f 0x130 0x136 0x137>; | |
| pinctrl-5 = <0x133 0x12e 0x134 0x130 0x136 0x137>; | |
| pinctrl-6 = <0x12d 0x12e 0x12f 0x135 0x136 0x137>; | |
| pinctrl-7 = <0x133 0x12e 0x134 0x135 0x136 0x137>; | |
| pinctrl-8 = <0x12d 0x15f 0x12f 0x130 0x131 0x132>; | |
| pinctrl-9 = <0x133 0x15f 0x134 0x130 0x131 0x132>; | |
| reg-names = "csr_gp_io_mux_mic_ctl\0csr_gp_io_mux_spkr_ctl\0csr_gp_io_lpaif_pri_pcm_pri_mode_muxsel\0csr_gp_io_mux_quin_ctl"; | |
| qcom,pinctrl-names = "all_off\0pri_i2s_act\0us_eu_gpio_act\0pri_i2s_us_eu_gpio_act\0quin_act\0quin_pri_i2s_act\0quin_us_eu_gpio_act\0quin_us_eu_gpio_pri_i2s_act\0comp_gpio_act\0comp_gpio_pri_i2s_act\0comp_gpio_us_eu_gpio_act\0comp_gpio_pri_i2s_us_eu_gpio_act\0comp_gpio_quin_act\0comp_gpio_quin_pri_i2s_act\0comp_gpio_quin_us_eu_gpio_act\0comp_gpio_quin_us_eu_gpio_pri_i2s_act"; | |
| qcom,msm-ext-pa = "primary"; | |
| asoc-platform-names = "msm-pcm-dsp.0\0msm-pcm-dsp.1\0msm-pcm-dsp.2\0msm-voip-dsp\0msm-pcm-voice\0msm-pcm-loopback\0msm-compress-dsp\0msm-pcm-hostless\0msm-pcm-afe\0msm-lsm-client\0msm-pcm-routing\0msm-pcm-lpa"; | |
| qcom,msm-micbias1-ext-cap; | |
| qcom,msm-mclk-freq = <0x927c00>; | |
| compatible = "qcom,msm8952-audio-codec"; | |
| qcom,msm-spk-ext-pa = <0xbe 0x16 0x00>; | |
| asoc-platform = <0x138 0x139 0x13a 0x13b 0x13c 0x13d 0x13e 0x13f 0x140 0x141 0x142 0x143>; | |
| qcom,msm-mbhc-gnd-swh = <0x00>; | |
| qcom,audio-routing = "RX_BIAS\0MCLK\0SPK_RX_BIAS\0MCLK\0INT_LDO_H\0MCLK\0MIC BIAS Internal1\0Handset Mic\0MIC BIAS External2\0Headset Mic\0MIC BIAS Internal1\0Secondary Mic\0AMIC1\0MIC BIAS Internal1\0AMIC2\0MIC BIAS External2\0AMIC3\0MIC BIAS Internal1\0Lineout_1 amp\0LINEOUT"; | |
| qcom,msm-hs-micbias-type = "internal"; | |
| asoc-cpu-names = "msm-dai-q6-auxpcm.1\0msm-dai-q6-mi2s.0\0msm-dai-q6-mi2s.1\0msm-dai-q6-mi2s.2\0msm-dai-q6-mi2s.3\0msm-dai-q6-mi2s.5\0msm-dai-q6-mi2s.6\0msm-dai-q6-dev.16384\0msm-dai-q6-dev.16385\0msm-dai-q6-dev.16386\0msm-dai-q6-dev.16387\0msm-dai-q6-dev.16390\0msm-dai-q6-dev.16391\0msm-dai-q6-dev.16392\0msm-dai-q6-dev.16393\0msm-dai-q6-dev.12288\0msm-dai-q6-dev.12289\0msm-dai-q6-dev.12292\0msm-dai-q6-dev.12293\0msm-dai-q6-dev.224\0msm-dai-q6-dev.225\0msm-dai-q6-dev.241\0msm-dai-q6-dev.240\0msm-dai-q6-dev.32771\0msm-dai-q6-dev.32772\0msm-dai-q6-dev.32773\0msm-dai-q6-dev.32770"; | |
| asoc-codec = <0x160 0x161 0x162>; | |
| status = "okay"; | |
| qcom,cdc-us-euro-gpios = <0xbe 0x12 0x00>; | |
| qcom,msm-gpios = "pri_i2s\0us_eu_gpio\0quin_i2s\0comp_gpio"; | |
| asoc-cpu = <0x144 0x145 0x146 0x147 0x148 0x149 0x14a 0x14b 0x14c 0x14d 0x14e 0x14f 0x150 0x151 0x152 0x153 0x154 0x155 0x156 0x157 0x158 0x159 0x15a 0x15b 0x15c 0x15d 0x15e>; | |
| qcom,msm-mbhc-hphl-swh = <0x01>; | |
| qcom,hdmi-dba-codec-rx; | |
| pinctrl-names = "all_off\0pri_i2s_act\0us_eu_gpio_act\0pri_i2s_us_eu_gpio_act\0quin_act\0quin_pri_i2s_act\0quin_us_eu_gpio_act\0quin_us_eu_gpio_pri_i2s_act\0comp_gpio_act\0comp_gpio_pri_i2s_act\0comp_gpio_us_eu_gpio_act\0comp_gpio_pri_i2s_us_eu_gpio_act\0comp_gpio_quin_act\0comp_gpio_quin_pri_i2s_act\0comp_gpio_quin_us_eu_gpio_act\0comp_gpio_quin_us_eu_gpio_pri_i2s_act"; | |
| asoc-codec-names = "msm-stub-codec.1\0cajon_codec\0msm-hdmi-dba-codec-rx"; | |
| qcom,model = "msm8953-snd-card-mtp"; | |
| }; | |
| timer { | |
| interrupts = <0x01 0x02 0xff08 0x01 0x03 0xff08 0x01 0x04 0xff08 0x01 0x01 0xff08>; | |
| compatible = "arm,armv8-timer"; | |
| clock-frequency = <0x124f800>; | |
| }; | |
| qcom,smp2p-wcnss@0x0b011008 { | |
| reg = <0xb011008 0x04>; | |
| interrupts = <0x00 0x8f 0x01>; | |
| qcom,irq-bitmask = <0x40000>; | |
| qcom,remote-pid = <0x04>; | |
| compatible = "qcom,smp2p"; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-1-out { | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x01>; | |
| compatible = "qcom,smp2pgpio"; | |
| #interrupt-cells = <0x02>; | |
| qcom,entry-name = "master-kernel"; | |
| phandle = <0x117>; | |
| interrupt-controller; | |
| gpio-controller; | |
| linux,phandle = <0x117>; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-2-out { | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x02>; | |
| compatible = "qcom,smp2pgpio"; | |
| #interrupt-cells = <0x02>; | |
| qcom,entry-name = "master-kernel"; | |
| phandle = <0x11a>; | |
| interrupt-controller; | |
| gpio-controller; | |
| linux,phandle = <0x11a>; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-4-out { | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x04>; | |
| compatible = "qcom,smp2pgpio"; | |
| #interrupt-cells = <0x02>; | |
| qcom,entry-name = "master-kernel"; | |
| phandle = <0x11e>; | |
| interrupt-controller; | |
| gpio-controller; | |
| linux,phandle = <0x11e>; | |
| }; | |
| tmc@6027000 { | |
| reg = <0x6027000 0x1000>; | |
| reg-names = "tmc-base"; | |
| coresight-outports = <0x00>; | |
| coresight-ctis = <0x48 0x49>; | |
| coresight-name = "coresight-tmc-etf"; | |
| compatible = "arm,coresight-tmc"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-child-ports = <0x00>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| qcom,force-reg-dump; | |
| phandle = <0x6f>; | |
| coresight-child-list = <0x6e>; | |
| coresight-default-sink; | |
| coresight-nr-inports = <0x01>; | |
| linux,phandle = <0x6f>; | |
| coresight-id = <0x03>; | |
| }; | |
| tmc@6028000 { | |
| reg = <0x6028000 0x1000 0x6044000 0x15000>; | |
| interrupts = <0x00 0xa6 0x00>; | |
| reg-names = "tmc-base\0bam-base"; | |
| coresight-ctis = <0x48 0x49>; | |
| coresight-name = "coresight-tmc-etr"; | |
| compatible = "arm,coresight-tmc"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| interrupt-names = "byte-cntr-irq"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| qcom,sg-enable; | |
| qcom,memory-size = <0x100000>; | |
| qcom,force-reg-dump; | |
| phandle = <0x6c>; | |
| coresight-nr-inports = <0x01>; | |
| linux,phandle = <0x6c>; | |
| coresight-id = <0x00>; | |
| }; | |
| qcom,mpm2-sleep-counter@4a3000 { | |
| reg = <0x4a3000 0x1000>; | |
| compatible = "qcom,mpm2-sleep-counter"; | |
| clock-frequency = <0x8000>; | |
| }; | |
| qcom,spm@b1d2000 { | |
| reg = <0xb1d2000 0x1000>; | |
| qcom,pfm-port = <0x02>; | |
| reg-names = "saw-base"; | |
| qcom,vctl-port = <0x00>; | |
| compatible = "qcom,spm-v2"; | |
| qcom,saw2-cfg = <0x14>; | |
| qcom,name = "system-cci"; | |
| qcom,saw2-spm-ctl = <0x0e>; | |
| qcom,saw2-spm-dly = <0x3c102800>; | |
| qcom,cpu-vctl-list = <0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09>; | |
| qcom,phase-port = <0x01>; | |
| #address-cells = <0x01>; | |
| qcom,saw2-ver-reg = <0xfd0>; | |
| qcom,vctl-timeout-us = <0x1f4>; | |
| #size-cells = <0x01>; | |
| qcom,saw2-avs-ctl = <0x10>; | |
| }; | |
| qcom,bcl { | |
| compatible = "qcom,bcl"; | |
| qcom,bcl-freq-control-list = <0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09>; | |
| qcom,bcl-framework-interface; | |
| qcom,bcl-enable; | |
| qcom,bcl-hotplug-list = <0x08 0x09>; | |
| qcom,bcl-soc-hotplug-list = <0x06 0x07 0x08 0x09>; | |
| qcom,ibat-monitor { | |
| qcom,low-threshold-uamp = <0x33e140>; | |
| qcom,soc-low-threshold = <0x0a>; | |
| qcom,thermal-handle = <0xc9>; | |
| qcom,vph-high-threshold-uv = <0x3567e0>; | |
| qcom,mitigation-freq-khz = <0x19c800>; | |
| qcom,vph-low-threshold-uv = <0x30d400>; | |
| qcom,high-threshold-uamp = <0x401640>; | |
| }; | |
| }; | |
| qcom,chd { | |
| compatible = "qcom,core-hang-detect"; | |
| qcom,config-arr = <0xb1880b8 0xb1980b8 0xb1a80b8 0xb1b80b8 0xb0880b8 0xb0980b8 0xb0a80b8 0xb0b80b8>; | |
| qcom,threshold-arr = <0xb1880b0 0xb1980b0 0xb1a80b0 0xb1b80b0 0xb0880b0 0xb0980b0 0xb0a80b0 0xb0b80b0>; | |
| }; | |
| qcom,ion { | |
| compatible = "qcom,msm-ion"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,ion-heap@25 { | |
| reg = <0x19>; | |
| qcom,ion-heap-type = "SYSTEM"; | |
| }; | |
| qcom,ion-heap@27 { | |
| reg = <0x1b>; | |
| qcom,ion-heap-type = "DMA"; | |
| memory-region = <0x3f>; | |
| }; | |
| qcom,ion-heap@8 { | |
| reg = <0x08>; | |
| qcom,ion-heap-type = "SECURE_DMA"; | |
| memory-region = <0x3e>; | |
| }; | |
| }; | |
| qcom,sps { | |
| compatible = "qcom,msm_sps_4k"; | |
| qcom,pipe-attr-ee; | |
| }; | |
| qcom,vfe { | |
| compatible = "qcom,vfe"; | |
| num_child = <0x02>; | |
| }; | |
| qcom,msm-compress-dsp { | |
| compatible = "qcom,msm-compress-dsp"; | |
| phandle = <0x13e>; | |
| linux,phandle = <0x13e>; | |
| }; | |
| qcom,rpm-stats@200000 { | |
| reg = <0x200000 0x1000 0x290014 0x04 0x29001c 0x04>; | |
| reg-names = "phys_addr_base\0offset_addr\0heap_phys_addrbase"; | |
| qcom,sleep-stats-version = <0x02>; | |
| compatible = "qcom,rpm-stats"; | |
| }; | |
| qcom,mpm@601d4 { | |
| reg = <0x601d4 0x1000 0xb011008 0x04>; | |
| qcom,gic-parent = <0x01>; | |
| interrupts = <0x00 0xab 0x01>; | |
| qcom,gpio-map = <0x03 0x26 0x04 0x01 0x05 0x05 0x06 0x09 0x08 0x25 0x09 0x24 0x0a 0x0d 0x0b 0x23 0x0c 0x11 0x0d 0x15 0x0e 0x36 0x0f 0x22 0x10 0x1f 0x11 0x3a 0x12 0x1c 0x13 0x2a 0x14 0x19 0x15 0x0c 0x16 0x2b 0x17 0x2c 0x18 0x2d 0x19 0x2e 0x1a 0x30 0x1b 0x41 0x1c 0x5d 0x1d 0x61 0x1e 0x3f 0x1f 0x46 0x20 0x47 0x21 0x48 0x22 0x51 0x23 0x55 0x24 0x5a 0x32 0x43 0x33 0x49 0x34 0x4a 0x35 0x3e 0x3b 0x3b 0x3c 0x3c 0x3d 0x3d 0x3e 0x56 0x3f 0x57 0x40 0x5b 0x41 0x81 0x42 0x82 0x43 0x83 0x44 0x84 0x45 0x85 0x46 0x89 0x47 0x8a 0x48 0x8b 0x49 0x8c 0x4a 0x8d 0xff 0x58>; | |
| reg-names = "vmpm\0ipc"; | |
| compatible = "qcom,mpm-v2"; | |
| clock-names = "xo"; | |
| clocks = <0x37 0x2be48257>; | |
| qcom,ipc-bit-offset = <0x01>; | |
| qcom,gpio-parent = <0xbe>; | |
| qcom,num-mpm-irqs = <0x60>; | |
| qcom,gic-map = <0x02 0xd8 0x3a 0xa8 0x31 0xa8 0x25 0xfc 0x35 0x68 0x58 0xde 0xff 0x12 0xff 0x13 0xff 0x14 0xff 0x17 0xff 0x23 0xff 0x27 0xff 0x28 0xff 0x2f 0xff 0x36 0xff 0x38 0xff 0x39 0xff 0x3a 0xff 0x3b 0xff 0x3c 0xff 0x3d 0xff 0x41 0xff 0x45 0xff 0x49 0xff 0x4a 0xff 0x4b 0xff 0x4e 0xff 0x4f 0xff 0x55 0xff 0x56 0xff 0x5a 0xff 0x5c 0xff 0x5d 0xff 0x61 0xff 0x66 0xff 0x6c 0xff 0x6d 0xff 0x70 0xff 0x72 0xff 0x7e 0xff 0x80 0xff 0x83 0xff 0x88 0xff 0x89 0xff 0x8a 0xff 0x8b 0xff 0x8c 0xff 0x8d 0xff 0x8e 0xff 0x8f 0xff 0x90 0xff 0x91 0xff 0x92 0xff 0x93 0xff 0x94 0xff 0x95 0xff 0x96 0xff 0x97 0xff 0x98 0xff 0x99 0xff 0x9b 0xff 0x9d 0xff 0xa6 0xff 0xa7 0xff 0xaa 0xff 0xac 0xff 0xad 0xff 0xae 0xff 0xaf 0xff 0xb0 0xff 0xb1 0xff 0xb2 0xff 0xb3 0xff 0xb5 0xff 0xbc 0xff 0xbd 0xff 0xbe 0xff 0xbf 0xff 0xc0 0xff 0xc1 0xff 0xc2 0xff 0xc3 0xff 0xc4 0xff 0xc5 0xff 0xc6 0xff 0xc8 0xff 0xc9 0xff 0xca 0xff 0xcb 0xff 0xcc 0xff 0xcd 0xff 0xce 0xff 0xcf 0xff 0xd4 0xff 0xd7 0xff 0xe0 0xff 0xe7 0xff 0xef 0xff 0xf0 0xff 0xfd 0xff 0x101 0xff 0x104 0xff 0x106 0xff 0x107 0xff 0x108 0xff 0x10d 0xff 0x10e 0xff 0x111 0xff 0x112 0xff 0x113 0xff 0x114 0xff 0x11d 0xff 0x11e 0xff 0x11f 0xff 0x131 0xff 0x132 0xff 0x133 0xff 0x134 0xff 0x13a 0xff 0x141 0xff 0x142 0xff 0x143 0xff 0x145 0xff 0x158 0xff 0x15a>; | |
| }; | |
| apm@b111000 { | |
| reg = <0xb111000 0x1000>; | |
| reg-names = "pm-apcc-glb"; | |
| qcom,apm-resume-clk-delay = <0x10>; | |
| qcom,apm-halt-clk-delay = <0x11>; | |
| compatible = "qcom,msm8953-apm"; | |
| qcom,apm-post-halt-delay = <0x02>; | |
| phandle = <0x126>; | |
| qcom,apm-sel-switch-delay = <0x01>; | |
| linux,phandle = <0x126>; | |
| }; | |
| qcom,smp2p-modem@0x0b011008 { | |
| reg = <0xb011008 0x04>; | |
| interrupts = <0x00 0x1b 0x01>; | |
| qcom,irq-bitmask = <0x4000>; | |
| qcom,remote-pid = <0x01>; | |
| compatible = "qcom,smp2p"; | |
| }; | |
| devfreq_spdm_cpu { | |
| qcom,msm-bus,vectors-KBps = <0x01 0x200 0x00 0x00 0x01 0x200 0x00 0x00>; | |
| qcom,up-step-multp = <0x02>; | |
| qcom,spdm-client = <0x00>; | |
| qcom,msm-bus,active-only; | |
| qcom,spdm-interval = <0x1e>; | |
| qcom,pl-freqs = <0x38270 0xbbfd0>; | |
| compatible = "qcom,devfreq_spdm"; | |
| qcom,reject-rate = <0x1388 0x1388 0x1388 0x1388 0x1388 0x1388>; | |
| clock-names = "cci_clk"; | |
| qcom,msm-bus,name = "devfreq_spdm"; | |
| qcom,bw-dwnstep = <0x1068>; | |
| qcom,alpha-down = <0x0f>; | |
| clocks = <0xb3 0x96854074>; | |
| qcom,bucket-size = <0x08>; | |
| qcom,cci-response-time-us = <0xfa0 0xfa0 0xbb8 0xbb8 0x7d0 0x7d0>; | |
| qcom,max-vote = <0x1068>; | |
| qcom,bw-upstep = <0x190>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,max-cci-freq = <0xd4670>; | |
| qcom,response-time-us = <0x1770 0x1770 0xfa0 0xfa0 0x7d0 0x7d0>; | |
| qcom,ports = <0x0b>; | |
| qcom,alpha-up = <0x08>; | |
| }; | |
| devfreq_spdm_gov { | |
| interrupts = <0x00 0xc0 0x00>; | |
| compatible = "qcom,gov_spdm_hyp"; | |
| interrupt-names = "spdm-irq"; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_15_out { | |
| gpios = <0x41 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_15_out"; | |
| }; | |
| interrupt-controller@b000000 { | |
| reg = <0xb000000 0x1000 0xb002000 0x1000>; | |
| compatible = "qcom,msm-qgic2"; | |
| #interrupt-cells = <0x03>; | |
| phandle = <0x01>; | |
| interrupt-controller; | |
| linux,phandle = <0x01>; | |
| }; | |
| qcom,msm-lsm-client { | |
| compatible = "qcom,msm-lsm-client"; | |
| phandle = <0x141>; | |
| linux,phandle = <0x141>; | |
| }; | |
| qcom,lpm-levels { | |
| compatible = "qcom,lpm-levels"; | |
| clock-names = "l2_clk\0cpu0_clk\0cpu1_clk\0cpu2_clk\0cpu3_clk\0cpu4_clk\0cpu5_clk\0cpu6_clk\0cpu7_clk"; | |
| clocks = <0xb3 0x96854074 0xb3 0x2e6af930 0xb3 0x2e6af930 0xb3 0x2e6af930 0xb3 0x2e6af930 0xb3 0x2e6af930 0xb3 0x2e6af930 0xb3 0x2e6af930 0xb3 0x2e6af930>; | |
| #address-cells = <0x01>; | |
| qcom,use-psci; | |
| #size-cells = <0x00>; | |
| qcom,pm-cluster@0 { | |
| reg = <0x00>; | |
| label = "system"; | |
| qcom,default-level = <0x00>; | |
| qcom,psci-mode-shift = <0x08>; | |
| qcom,psci-mode-mask = <0x0f>; | |
| qcom,spm-device-names = "cci"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,pm-cluster-level@0 { | |
| reg = <0x00>; | |
| qcom,latency-us = <0x1a7>; | |
| label = "system-active"; | |
| qcom,time-overhead = <0x2cf>; | |
| qcom,energy-overhead = <0x49066>; | |
| qcom,psci-mode = <0x00>; | |
| qcom,ss-power = <0x15d>; | |
| }; | |
| qcom,pm-cluster-level@1 { | |
| reg = <0x01>; | |
| qcom,latency-us = <0x1e0>; | |
| label = "system-wfi"; | |
| qcom,min-child-idx = <0x03>; | |
| qcom,time-overhead = <0x2f1>; | |
| qcom,energy-overhead = <0x4ca85>; | |
| qcom,psci-mode = <0x01>; | |
| qcom,ss-power = <0x15c>; | |
| }; | |
| qcom,pm-cluster-level@2 { | |
| reg = <0x02>; | |
| qcom,reset-level = <0x03>; | |
| qcom,notify-rpm; | |
| qcom,latency-us = <0x2b13>; | |
| label = "system-pc"; | |
| qcom,min-child-idx = <0x03>; | |
| qcom,time-overhead = <0x5d7>; | |
| qcom,energy-overhead = <0x96663>; | |
| qcom,psci-mode = <0x03>; | |
| qcom,is-reset; | |
| qcom,ss-power = <0x154>; | |
| }; | |
| qcom,pm-cluster@0 { | |
| reg = <0x00>; | |
| label = "pwr"; | |
| qcom,cpu = <0x02 0x03 0x04 0x05>; | |
| qcom,default-level = <0x00>; | |
| qcom,psci-mode-shift = <0x04>; | |
| qcom,psci-mode-mask = <0x0f>; | |
| qcom,spm-device-names = "l2"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,pm-cluster-level@0 { | |
| reg = <0x00>; | |
| qcom,latency-us = <0xb4>; | |
| label = "pwr-l2-wfi"; | |
| qcom,time-overhead = <0x10e>; | |
| qcom,energy-overhead = <0x1ba3f>; | |
| qcom,psci-mode = <0x01>; | |
| qcom,ss-power = <0x169>; | |
| }; | |
| qcom,pm-cluster-level@1 { | |
| reg = <0x01>; | |
| qcom,reset-level = <0x01>; | |
| qcom,latency-us = <0xbc>; | |
| label = "pwr-l2-retention"; | |
| qcom,min-child-idx = <0x01>; | |
| qcom,time-overhead = <0x133>; | |
| qcom,energy-overhead = <0x1d9b7>; | |
| qcom,psci-mode = <0x03>; | |
| qcom,ss-power = <0x168>; | |
| }; | |
| qcom,pm-cluster-level@2 { | |
| reg = <0x02>; | |
| qcom,reset-level = <0x02>; | |
| qcom,latency-us = <0xd4>; | |
| label = "pwr-l2-gdhs"; | |
| qcom,min-child-idx = <0x01>; | |
| qcom,time-overhead = <0x16b>; | |
| qcom,energy-overhead = <0x24cdc>; | |
| qcom,psci-mode = <0x04>; | |
| qcom,ss-power = <0x162>; | |
| }; | |
| qcom,pm-cluster-level@3 { | |
| reg = <0x03>; | |
| qcom,reset-level = <0x03>; | |
| qcom,latency-us = <0x1a5>; | |
| label = "pwr-l2-pc"; | |
| qcom,min-child-idx = <0x01>; | |
| qcom,time-overhead = <0x2b2>; | |
| qcom,energy-overhead = <0x43be7>; | |
| qcom,psci-mode = <0x05>; | |
| qcom,is-reset; | |
| qcom,ss-power = <0x15e>; | |
| }; | |
| qcom,pm-cpu { | |
| qcom,psci-mode-shift = <0x00>; | |
| qcom,psci-mode-mask = <0x0f>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,pm-cpu-level@0 { | |
| reg = <0x00>; | |
| qcom,spm-cpu-mode = "wfi"; | |
| qcom,latency-us = <0x01>; | |
| qcom,time-overhead = <0x3d>; | |
| qcom,energy-overhead = <0x76d8>; | |
| qcom,psci-cpu-mode = <0x01>; | |
| qcom,ss-power = <0x18b>; | |
| }; | |
| qcom,pm-cpu-level@1 { | |
| reg = <0x01>; | |
| qcom,reset-level = <0x03>; | |
| qcom,spm-cpu-mode = "pc"; | |
| qcom,latency-us = <0xb4>; | |
| qcom,use-broadcast-timer; | |
| qcom,time-overhead = <0x10e>; | |
| qcom,energy-overhead = <0x1ba3f>; | |
| qcom,psci-cpu-mode = <0x03>; | |
| qcom,is-reset; | |
| qcom,ss-power = <0x169>; | |
| }; | |
| }; | |
| }; | |
| qcom,pm-cluster@1 { | |
| reg = <0x01>; | |
| label = "perf"; | |
| qcom,cpu = <0x06 0x07 0x08 0x09>; | |
| qcom,default-level = <0x00>; | |
| qcom,psci-mode-shift = <0x04>; | |
| qcom,psci-mode-mask = <0x0f>; | |
| qcom,spm-device-names = "l2"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,pm-cluster-level@0 { | |
| reg = <0x00>; | |
| qcom,latency-us = <0xb3>; | |
| label = "perf-l2-wfi"; | |
| qcom,time-overhead = <0x10c>; | |
| qcom,energy-overhead = <0x1ba5a>; | |
| qcom,psci-mode = <0x01>; | |
| qcom,ss-power = <0x16a>; | |
| }; | |
| qcom,pm-cluster-level@1 { | |
| reg = <0x01>; | |
| qcom,reset-level = <0x01>; | |
| qcom,latency-us = <0xba>; | |
| label = "perf-l2-retention"; | |
| qcom,min-child-idx = <0x01>; | |
| qcom,time-overhead = <0x132>; | |
| qcom,energy-overhead = <0x1ec1e>; | |
| qcom,psci-mode = <0x03>; | |
| qcom,ss-power = <0x169>; | |
| }; | |
| qcom,pm-cluster-level@2 { | |
| reg = <0x02>; | |
| qcom,reset-level = <0x02>; | |
| qcom,latency-us = <0xd2>; | |
| label = "perf-l2-gdhs"; | |
| qcom,min-child-idx = <0x01>; | |
| qcom,time-overhead = <0x169>; | |
| qcom,energy-overhead = <0x26050>; | |
| qcom,psci-mode = <0x04>; | |
| qcom,ss-power = <0x163>; | |
| }; | |
| qcom,pm-cluster-level@3 { | |
| reg = <0x03>; | |
| qcom,reset-level = <0x03>; | |
| qcom,latency-us = <0x1a7>; | |
| label = "perf-l2-pc"; | |
| qcom,min-child-idx = <0x01>; | |
| qcom,time-overhead = <0x2cf>; | |
| qcom,energy-overhead = <0x49066>; | |
| qcom,psci-mode = <0x05>; | |
| qcom,is-reset; | |
| qcom,ss-power = <0x15d>; | |
| }; | |
| qcom,pm-cpu { | |
| qcom,psci-mode-shift = <0x00>; | |
| qcom,psci-mode-mask = <0x0f>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,pm-cpu-level@0 { | |
| reg = <0x00>; | |
| qcom,spm-cpu-mode = "wfi"; | |
| qcom,latency-us = <0x01>; | |
| qcom,time-overhead = <0x3d>; | |
| qcom,energy-overhead = <0x76d8>; | |
| qcom,psci-cpu-mode = <0x01>; | |
| qcom,ss-power = <0x18d>; | |
| }; | |
| qcom,pm-cpu-level@1 { | |
| reg = <0x01>; | |
| qcom,reset-level = <0x03>; | |
| qcom,spm-cpu-mode = "pc"; | |
| qcom,latency-us = <0xb3>; | |
| qcom,use-broadcast-timer; | |
| qcom,time-overhead = <0x10c>; | |
| qcom,energy-overhead = <0x1ba5a>; | |
| qcom,psci-cpu-mode = <0x03>; | |
| qcom,is-reset; | |
| qcom,ss-power = <0x16a>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| }; | |
| arm,smmu-kgsl@1c40000 { | |
| reg = <0x1c40000 0x10000>; | |
| interrupts = <0x00 0xc7 0x00 0x00 0xe1 0x00 0x00 0xe8 0x00 0x00 0xe9 0x00 0x00 0xea 0x00>; | |
| #clock-cells = <0x01>; | |
| qcom,deferred-regulator-disable-delay = <0x50>; | |
| compatible = "qcom,smmu-v2"; | |
| clock-names = "gpu_ahb_clk\0gcc_bimc_gfx_clk"; | |
| qcom,enable-static-cb; | |
| attach-impl-defs = <0x6000 0x270 0x6060 0x1055 0x6800 0x06 0x6900 0x3ff 0x6924 0x204 0x6928 0x10800 0x6930 0x400 0x6960 0xffffffff 0x6b64 0xa0000 0x6b68 0xaaab92a>; | |
| clocks = <0x38 0xd15c8a00 0x38 0x3edd69ad>; | |
| qcom,dynamic; | |
| #iommu-cells = <0x01>; | |
| qcom,enable-smmu-halt; | |
| status = "ok"; | |
| qcom,skip-init; | |
| #global-interrupts = <0x01>; | |
| phandle = <0x3d>; | |
| vdd-supply = <0x3a>; | |
| qcom,no-smr-check; | |
| qcom,register-save; | |
| qcom,tz-device-id = "GPU"; | |
| linux,phandle = <0x3d>; | |
| }; | |
| regulator@0194415c { | |
| reg = <0x194415c 0x04>; | |
| regulator-name = "gfx_mem_acc_corner"; | |
| reg-names = "acc-sel-l1"; | |
| compatible = "qcom,mem-acc-regulator"; | |
| regulator-min-microvolt = <0x01>; | |
| qcom,acc-sel-l1-bit-size = <0x01>; | |
| regulator-max-microvolt = <0x02>; | |
| qcom,acc-sel-l1-bit-pos = <0x00>; | |
| phandle = <0x12a>; | |
| linux,phandle = <0x12a>; | |
| qcom,corner-acc-map = <0x01 0x00>; | |
| }; | |
| regulator@019461d4 { | |
| reg = <0x19461d4 0x04 0x19461d8 0x04>; | |
| regulator-name = "apc_mem_acc_corner"; | |
| reg-names = "acc-sel-l1\0acc-sel-l2"; | |
| compatible = "qcom,mem-acc-regulator"; | |
| qcom,acc-sel-l2-bit-pos = <0x00>; | |
| regulator-min-microvolt = <0x01>; | |
| qcom,acc-sel-l1-bit-size = <0x01>; | |
| qcom,acc-sel-l2-bit-size = <0x01>; | |
| regulator-max-microvolt = <0x02>; | |
| qcom,acc-sel-l1-bit-pos = <0x00>; | |
| phandle = <0x129>; | |
| linux,phandle = <0x129>; | |
| qcom,corner-acc-map = <0x01 0x00>; | |
| }; | |
| qcom,cpu-sleep-status { | |
| compatible = "qcom,cpu-sleep-status"; | |
| }; | |
| qcom,ipc_router_modem_xprt { | |
| qcom,fragmented-data; | |
| qcom,ch-name = "IPCRTR"; | |
| compatible = "qcom,ipc_router_smd_xprt"; | |
| qcom,xprt-linkid = <0x01>; | |
| qcom,xprt-remote = "modem"; | |
| qcom,disable-pil-loading; | |
| qcom,xprt-version = <0x01>; | |
| }; | |
| qcom,cpu-clock-8953@b116000 { | |
| reg = <0xb114000 0x68 0xb014000 0x68 0xb116000 0x400 0xb111050 0x08 0xb011050 0x08 0xb1d1050 0x08 0xa4124 0x08>; | |
| vdd-mx-supply = <0xf1>; | |
| qcom,speed2-bin-v0-cci = <0x00 0x00 0xf906000 0x01 0x18b82000 0x02 0x216ab000 0x03 0x28488000 0x04 0x2b07a000 0x05 0x2eb12000 0x06 0x3010b000 0x07>; | |
| qcom,speed7-bin-v0-cl = <0x00 0x00 0x26e8f000 0x01 0x3dcc5000 0x02 0x538ab800 0x03 0x64b54000 0x04 0x6b931000 0x05 0x74bad000 0x06 0x7829b800 0x07 0x802c8000 0x08 0x839b6800 0x09>; | |
| #clock-cells = <0x01>; | |
| vdd-cl-supply = <0xf2>; | |
| reg-names = "rcgwr-c0-base\0rcgwr-c1-base\0c0-pll\0c0-mux\0c1-mux\0cci-mux\0efuse"; | |
| compatible = "qcom,cpu-clock-8953"; | |
| clock-names = "xo_a"; | |
| qcom,num-clusters = <0x02>; | |
| qcom,speed6-bin-v0-cl = <0x00 0x00 0x26e8f000 0x01 0x3dcc5000 0x02 0x538ab800 0x03 0x64b54000 0x04 0x6b931000 0x05>; | |
| qcom,speed2-bin-v0-cl = <0x00 0x00 0x26e8f000 0x01 0x3dcc5000 0x02 0x538ab800 0x03 0x64b54000 0x04 0x6b931000 0x05 0x74bad000 0x06 0x7829b800 0x07>; | |
| clocks = <0x37 0x2fdd2c7c>; | |
| qcom,speed6-bin-v0-cci = <0x00 0x00 0xf906000 0x01 0x18b82000 0x02 0x216ab000 0x03 0x28488000 0x04 0x2b07a000 0x05>; | |
| qcom,speed7-bin-v0-cci = <0x00 0x00 0xf906000 0x01 0x18b82000 0x02 0x216ab000 0x03 0x28488000 0x04 0x2b07a000 0x05 0x2eb12000 0x06 0x3010b000 0x07 0x33450000 0x08 0x34a49000 0x09>; | |
| qcom,speed0-bin-v0-cci = <0x00 0x00 0xf906000 0x01 0x18b82000 0x02 0x216ab000 0x03 0x28488000 0x04 0x2b07a000 0x05 0x2eb12000 0x06 0x3010b000 0x07>; | |
| phandle = <0xb3>; | |
| qcom,speed0-bin-v0-cl = <0x00 0x00 0x26e8f000 0x01 0x3dcc5000 0x02 0x538ab800 0x03 0x64b54000 0x04 0x6b931000 0x05 0x74bad000 0x06 0x7829b800 0x07>; | |
| linux,phandle = <0xb3>; | |
| }; | |
| qcom,ipc_router_q6_xprt { | |
| qcom,fragmented-data; | |
| qcom,ch-name = "IPCRTR"; | |
| compatible = "qcom,ipc_router_smd_xprt"; | |
| qcom,xprt-linkid = <0x01>; | |
| qcom,xprt-remote = "adsp"; | |
| qcom,xprt-version = <0x01>; | |
| }; | |
| qcom,kgsl-hyp { | |
| qcom,firmware-name = "a506_zap"; | |
| compatible = "qcom,pil-tz-generic"; | |
| clock-names = "scm_core_clk\0scm_iface_clk\0scm_bus_clk\0scm_core_clk_src"; | |
| clocks = <0x37 0xd390d2 0x37 0x94de4919 0x37 0xd4415c9b 0x37 0x37a21414>; | |
| qcom,scm_core_clk_src-freq = <0x4c4b400>; | |
| qcom,pas-id = <0x0d>; | |
| memory-region = <0x36>; | |
| qcom,proxy-clock-names = "scm_core_clk\0scm_iface_clk\0scm_bus_clk\0scm_core_clk_src"; | |
| }; | |
| dbgui@6108000 { | |
| reg = <0x6108000 0x1000>; | |
| qcom,dbgui-size = <0x40>; | |
| qcom,dbgui-data-offset = <0x130>; | |
| reg-names = "dbgui-base"; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-dbgui"; | |
| compatible = "qcom,coresight-dbgui"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-child-ports = <0x02>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| qcom,dbgui-addr-offset = <0x30>; | |
| coresight-child-list = <0x74>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x38>; | |
| }; | |
| qcom,ipc-spinlock@1905000 { | |
| reg = <0x1905000 0x8000>; | |
| compatible = "qcom,ipc-spinlock-sfpb"; | |
| qcom,num-locks = <0x08>; | |
| }; | |
| hwevent@6101000 { | |
| reg = <0x6101000 0x148 0x6101fb0 0x04 0x6121000 0x148 0x6121fb0 0x04 0x6131000 0x148 0x6131fb0 0x04 0x7105010 0x04 0x7885010 0x04>; | |
| reg-names = "center-wrapper-mux\0center-wrapper-lockaccess\0right-wrapper-mux\0right-wrapper-lockaccess\0mm-wrapper-mux\0mm-wrapper-lockaccess\0usbbam-mux\0blsp-mux"; | |
| coresight-name = "coresight-hwevent"; | |
| compatible = "qcom,coresight-hwevent"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x3b>; | |
| }; | |
| qcom,mdss_dsi@0 { | |
| qcom,msm-bus,vectors-KBps = <0x16 0x200 0x00 0x00 0x16 0x200 0x00 0x3e8>; | |
| compatible = "qcom,mdss-dsi"; | |
| clock-names = "mdp_core_clk\0iface_clk\0bus_clk\0ext_byte0_clk\0ext_byte1_clk\0ext_pixel0_clk\0ext_pixel1_clk"; | |
| qcom,mdss-fb-map-sec = <0x195>; | |
| qcom,msm-bus,name = "mdss_dsi"; | |
| hw-config = "single_dsi"; | |
| gdsc-supply = <0x172>; | |
| clocks = <0x18e 0x588460a4 0x37 0xbfb92ed3 0x37 0x668f51de 0x18e 0xfb32f31e 0x18e 0x585ef6d4 0x18e 0x87c1612 0x18e 0x8067c5a3>; | |
| vdda-supply = <0x173>; | |
| qcom,mmss-phyreset-ctrl-offset = <0x24>; | |
| qcom,mdss-fb-map-prim = <0x194>; | |
| ranges = <0x1a94000 0x1a94000 0x400 0x1a94400 0x1a94400 0x588 0x193e000 0x193e000 0x30 0x1a96000 0x1a96000 0x400 0x1a96400 0x1a96400 0x588 0x193e000 0x193e000 0x30>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,mmss-ulp-clamp-ctrl-offset = <0x20>; | |
| vcca-supply = <0x125>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| qcom,phy-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,phy-supply-entry@0 { | |
| reg = <0x00>; | |
| qcom,supply-disable-load = <0x20>; | |
| qcom,supply-max-voltage = <0xe1d48>; | |
| qcom,supply-min-voltage = <0xe1d48>; | |
| qcom,supply-name = "vcca"; | |
| qcom,supply-enable-load = <0x4268>; | |
| }; | |
| }; | |
| qcom,ctrl-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,ctrl-supply-entry@0 { | |
| reg = <0x00>; | |
| qcom,supply-disable-load = <0x01>; | |
| qcom,supply-max-voltage = <0x12b128>; | |
| qcom,supply-min-voltage = <0x12b128>; | |
| qcom,supply-name = "vdda"; | |
| qcom,supply-enable-load = <0x46f0>; | |
| }; | |
| }; | |
| qcom,core-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,core-supply-entry@0 { | |
| reg = <0x00>; | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-max-voltage = <0x00>; | |
| qcom,supply-min-voltage = <0x00>; | |
| qcom,supply-name = "gdsc"; | |
| qcom,supply-enable-load = <0x00>; | |
| }; | |
| }; | |
| qcom,mdss_dsi_ctrl1@1a96000 { | |
| reg = <0x1a96000 0x400 0x1a96400 0x588 0x193e000 0x30>; | |
| qcom,mdss-mdp = <0x196>; | |
| qcom,dsi-pref-prim-pan = <0x19b>; | |
| pinctrl-0 = <0x197 0x198>; | |
| pinctrl-1 = <0x199 0x19a>; | |
| reg-names = "dsi_ctrl\0dsi_phy\0mmss_misc_phys"; | |
| vddio-supply = <0x17a>; | |
| qcom,platform-reset-gpio = <0xbe 0x88 0x00>; | |
| label = "MDSS DSI CTRL->1"; | |
| compatible = "qcom,mdss-dsi-ctrl"; | |
| clock-names = "byte_clk\0pixel_clk\0core_clk\0byte_clk_rcg\0pixel_clk_rcg\0pll_byte_clk_mux\0pll_pixel_clk_mux\0pll_byte_clk_src\0pll_pixel_clk_src\0pll_shadow_byte_clk_src\0pll_shadow_pixel_clk_src"; | |
| qcom,platform-te-gpio = <0xbe 0x18 0x00>; | |
| qcom,pluggable; | |
| qcom,timing-db-mode; | |
| clocks = <0x18e 0x41f97fd8 0x18e 0x9a9c430d 0x37 0x34653cc7 0x18e 0x63c2c955 0x18e 0x90f68ac 0xf0 0xb5a42b7b 0xf0 0x36458019 0xf0 0x63930a8f 0xf0 0xe4c9b56 0xf0 0xfc021ce5 0xf0 0xdcca3ffc>; | |
| qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; | |
| cell-index = <0x01>; | |
| qcom,platform-lane-config = <0x100f 0x100f 0x100f 0x100f 0x108f>; | |
| qcom,platform-strength-ctrl = [ff 06 ff 06 ff 06 ff 06 ff 00]; | |
| phandle = <0x193>; | |
| vdd-supply = <0x179>; | |
| pinctrl-names = "mdss_default\0mdss_sleep"; | |
| linux,phandle = <0x193>; | |
| }; | |
| qcom,mdss_dsi_ctrl0@1a94000 { | |
| reg = <0x1a94000 0x400 0x1a94400 0x580 0x193e000 0x30>; | |
| qcom,mdss-mdp = <0x196>; | |
| pinctrl-0 = <0x197 0x198>; | |
| pinctrl-1 = <0x199 0x19a>; | |
| reg-names = "dsi_ctrl\0dsi_phy\0mmss_misc_phys"; | |
| vddio-supply = <0x17a>; | |
| qcom,platform-reset-gpio = <0xbe 0x3d 0x00>; | |
| label = "MDSS DSI CTRL->0"; | |
| compatible = "qcom,mdss-dsi-ctrl"; | |
| clock-names = "byte_clk\0pixel_clk\0core_clk\0byte_clk_rcg\0pixel_clk_rcg\0pll_byte_clk_mux\0pll_pixel_clk_mux\0pll_byte_clk_src\0pll_pixel_clk_src\0pll_shadow_byte_clk_src\0pll_shadow_pixel_clk_src"; | |
| qcom,platform-te-gpio = <0xbe 0x89 0x00>; | |
| qcom,timing-db-mode; | |
| clocks = <0x18e 0x35da7862 0x18e 0xcc5c5c77 0x37 0xaec5cb25 0x18e 0x75cc885b 0x18e 0xccac1f35 0xef 0x60e83f06 0xef 0x792379e1 0xef 0xbbaa30be 0xef 0x45b3260f 0xef 0x177c029c 0xef 0x98ae3c92>; | |
| qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; | |
| cell-index = <0x00>; | |
| qcom,platform-lane-config = <0x100f 0x100f 0x100f 0x100f 0x108f>; | |
| qcom,platform-strength-ctrl = [ff 06 ff 06 ff 06 ff 06 ff 00]; | |
| phandle = <0x190>; | |
| vdd-supply = <0x179>; | |
| pinctrl-names = "mdss_default\0mdss_sleep"; | |
| linux,phandle = <0x190>; | |
| }; | |
| }; | |
| tsens@4a8000 { | |
| reg = <0x4a8000 0x2000 0xa4000 0x1000>; | |
| interrupts = <0x00 0xb8 0x00 0x00 0x13a 0x00>; | |
| qcom,client-id = <0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f>; | |
| reg-names = "tsens_physical\0tsens_eeprom_physical"; | |
| compatible = "qcom,msm8953-tsens"; | |
| interrupt-names = "tsens-upper-lower\0tsens-critical"; | |
| qcom,sensors = <0x0f>; | |
| qcom,valid-status-check; | |
| qcom,sensor-id = <0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f>; | |
| qcom,slope = <0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80>; | |
| }; | |
| qcom,sps-dma@7ac4000 { | |
| reg = <0x7ac4000 0x1f000>; | |
| interrupts = <0x00 0xef 0x00>; | |
| compatible = "qcom,sps-dma"; | |
| #dma-cells = <0x04>; | |
| phandle = <0xe4>; | |
| qcom,summing-threshold = <0x0a>; | |
| linux,phandle = <0xe4>; | |
| }; | |
| wcd_gpio_ctrl { | |
| pinctrl-0 = <0x16e>; | |
| pinctrl-1 = <0x16f>; | |
| compatible = "qcom,wcd-gpio-ctrl"; | |
| status = "disabled"; | |
| phandle = <0xea>; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| linux,phandle = <0xea>; | |
| qcom,cdc-rst-n-gpio = <0xbe 0x43 0x00>; | |
| }; | |
| qcom,adsprpc_domains { | |
| compatible = "qcom,msm-fastrpc-legacy-compute-cb"; | |
| qcom,msm_fastrpc_compute_cb { | |
| qcom,adsp-shared-phandle = <0xfe>; | |
| qcom,adsp-shared-sids = <0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f>; | |
| qcom,virtual-addr-pool = <0x80000000 0x7fffffff>; | |
| }; | |
| }; | |
| qcom,msm-ssc-sensors { | |
| compatible = "qcom,msm-ssc-sensors"; | |
| }; | |
| qcom,smp2pgpio-smp2p-15-out { | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x0f>; | |
| compatible = "qcom,smp2pgpio"; | |
| #interrupt-cells = <0x02>; | |
| qcom,entry-name = "smp2p"; | |
| phandle = <0x41>; | |
| interrupt-controller; | |
| gpio-controller; | |
| linux,phandle = <0x41>; | |
| }; | |
| qcom,msm-pri-auxpcm { | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| qcom,msm-auxpcm-interface = "primary"; | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; | |
| qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; | |
| qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; | |
| qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; | |
| phandle = <0x144>; | |
| qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; | |
| linux,phandle = <0x144>; | |
| }; | |
| qcom,msm-gladiator@b1c0000 { | |
| reg = <0xb1c0000 0x4000>; | |
| interrupts = <0x00 0x16 0x00>; | |
| reg-names = "gladiator_base"; | |
| compatible = "qcom,msm-gladiator"; | |
| }; | |
| qcom,gcc@1800000 { | |
| reg = <0x1800000 0x80000 0xa4124 0x08>; | |
| #clock-cells = <0x01>; | |
| reg-names = "cc_base\0efuse"; | |
| compatible = "qcom,gcc-8953"; | |
| vdd_dig-supply = <0xee>; | |
| phandle = <0x37>; | |
| linux,phandle = <0x37>; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-1-in { | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x01>; | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,is-inbound; | |
| #interrupt-cells = <0x02>; | |
| qcom,entry-name = "slave-kernel"; | |
| phandle = <0x116>; | |
| interrupt-controller; | |
| gpio-controller; | |
| linux,phandle = <0x116>; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-2-in { | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x02>; | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,is-inbound; | |
| #interrupt-cells = <0x02>; | |
| qcom,entry-name = "slave-kernel"; | |
| phandle = <0x119>; | |
| interrupt-controller; | |
| gpio-controller; | |
| linux,phandle = <0x119>; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-4-in { | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x04>; | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,is-inbound; | |
| #interrupt-cells = <0x02>; | |
| qcom,entry-name = "slave-kernel"; | |
| phandle = <0x11d>; | |
| interrupt-controller; | |
| gpio-controller; | |
| linux,phandle = <0x11d>; | |
| }; | |
| qrng@e3000 { | |
| reg = <0xe3000 0x1000>; | |
| qcom,msm-bus,vectors-KBps = <0x01 0x26a 0x00 0x00 0x01 0x26a 0x00 0x320>; | |
| compatible = "qcom,msm-rng"; | |
| clock-names = "iface_clk"; | |
| qcom,msm-bus,name = "msm-rng-noc"; | |
| clocks = <0x37 0x397e7eaa>; | |
| qcom,no-qrng-config; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-rng-iface-clk; | |
| }; | |
| qcom,msm-voip-dsp { | |
| compatible = "qcom,msm-voip-dsp"; | |
| phandle = <0x13b>; | |
| linux,phandle = <0x13b>; | |
| }; | |
| qcom,mss@4080000 { | |
| reg = <0x4080000 0x100 0x194f000 0x10 0x1950000 0x08 0x1951000 0x08 0x4020000 0x40 0x1871000 0x04>; | |
| vdd_mx-uV = <0x180>; | |
| interrupts = <0x00 0x18 0x01>; | |
| vdd_cx-supply = <0xee>; | |
| qcom,firmware-name = "modem"; | |
| qcom,gpio-err-fatal = <0x116 0x00 0x00>; | |
| reg-names = "qdsp6_base\0halt_q6\0halt_modem\0halt_nc\0rmb_base\0restart_reg"; | |
| qcom,gpio-err-ready = <0x116 0x01 0x00>; | |
| qcom,pil-self-auth; | |
| qcom,gpio-shutdown-ack = <0x116 0x07 0x00>; | |
| compatible = "qcom,pil-q6v55-mss"; | |
| clock-names = "xo\0iface_clk\0bus_clk\0mem_clk"; | |
| qcom,gpio-force-stop = <0x117 0x00 0x00>; | |
| qcom,gpio-stop-ack = <0x116 0x03 0x00>; | |
| vdd_pll-supply = <0xf5>; | |
| clocks = <0x37 0xe97a8354 0x37 0x111cde81 0x37 0x67544d62 0x37 0xde2adeb1>; | |
| qcom,qdsp6v56-1-10; | |
| qcom,pil-mss-memsetup; | |
| qcom,ssctl-instance-id = <0x12>; | |
| vdd_cx-voltage = <0x180>; | |
| qcom,sysmon-id = <0x00>; | |
| vdd_mx-supply = <0xf1>; | |
| qcom,active-clock-names = "iface_clk\0bus_clk\0mem_clk"; | |
| qcom,gpio-proxy-unvote = <0x116 0x02 0x00>; | |
| qcom,pas-id = <0x05>; | |
| qcom,vdd_pll = <0x1b7740>; | |
| memory-region = <0x118>; | |
| vdd_mss-supply = <0x115>; | |
| qcom,proxy-clock-names = "xo"; | |
| }; | |
| cpuss_dump { | |
| compatible = "qcom,cpuss-dump"; | |
| qcom,l1_i_cache0 { | |
| qcom,dump-id = <0x60>; | |
| qcom,dump-node = <0x26>; | |
| }; | |
| qcom,l1_i_cache1 { | |
| qcom,dump-id = <0x61>; | |
| qcom,dump-node = <0x27>; | |
| }; | |
| qcom,l1_i_cache2 { | |
| qcom,dump-id = <0x62>; | |
| qcom,dump-node = <0x28>; | |
| }; | |
| qcom,l1_i_cache3 { | |
| qcom,dump-id = <0x63>; | |
| qcom,dump-node = <0x29>; | |
| }; | |
| qcom,l1_i_cache100 { | |
| qcom,dump-id = <0x64>; | |
| qcom,dump-node = <0x2a>; | |
| }; | |
| qcom,l1_i_cache101 { | |
| qcom,dump-id = <0x65>; | |
| qcom,dump-node = <0x2b>; | |
| }; | |
| qcom,l1_i_cache102 { | |
| qcom,dump-id = <0x66>; | |
| qcom,dump-node = <0x2c>; | |
| }; | |
| qcom,l1_i_cache103 { | |
| qcom,dump-id = <0x67>; | |
| qcom,dump-node = <0x2d>; | |
| }; | |
| qcom,l1_d_cache0 { | |
| qcom,dump-id = <0x80>; | |
| qcom,dump-node = <0x2e>; | |
| }; | |
| qcom,l1_d_cache1 { | |
| qcom,dump-id = <0x81>; | |
| qcom,dump-node = <0x2f>; | |
| }; | |
| qcom,l1_d_cache2 { | |
| qcom,dump-id = <0x82>; | |
| qcom,dump-node = <0x30>; | |
| }; | |
| qcom,l1_d_cache3 { | |
| qcom,dump-id = <0x83>; | |
| qcom,dump-node = <0x31>; | |
| }; | |
| qcom,l1_d_cache100 { | |
| qcom,dump-id = <0x84>; | |
| qcom,dump-node = <0x32>; | |
| }; | |
| qcom,l1_d_cache101 { | |
| qcom,dump-id = <0x85>; | |
| qcom,dump-node = <0x33>; | |
| }; | |
| qcom,l1_d_cache102 { | |
| qcom,dump-id = <0x86>; | |
| qcom,dump-node = <0x34>; | |
| }; | |
| qcom,l1_d_cache103 { | |
| qcom,dump-id = <0x87>; | |
| qcom,dump-node = <0x35>; | |
| }; | |
| qcom,l2_dump0 { | |
| qcom,dump-id = <0xc0>; | |
| qcom,dump-node = <0x0d>; | |
| }; | |
| qcom,l2_dump1 { | |
| qcom,dump-id = <0xc1>; | |
| qcom,dump-node = <0x1b>; | |
| }; | |
| }; | |
| qusb@79000 { | |
| reg = <0x79000 0x180 0x1841030 0x04 0x193f044 0x04 0x193f020 0x04>; | |
| reg-names = "qusb_phy_base\0ref_clk_addr\0tcsr_phy_clk_scheme_sel\0tcsr_phy_level_shift_keeper"; | |
| compatible = "qcom,qusb2phy"; | |
| qcom,qusb-phy-init-seq = <0xf8 0x80 0xb3 0x84 0x83 0x88 0xc0 0x8c 0x14 0x9c 0x30 0x08 0x79 0x0c 0x21 0x10 0x00 0x90 0x9f 0x1c 0x00 0x18>; | |
| clock-names = "ref_clk_src\0ref_clk\0cfg_ahb_clk\0phy_reset\0iface_clk\0core_clk"; | |
| vdda18-supply = <0xf5>; | |
| qcom,vdd-voltage-level = <0x00 0xe1d48 0xe1d48>; | |
| vdda33-supply = <0xed>; | |
| clocks = <0x37 0xf5304268 0x37 0x16e35a90 0x37 0xccb7e26f 0x37 0x3ce5fa84 0x37 0xf7f4b314 0x37 0xb3b4e2cb>; | |
| phy_type = "utmi"; | |
| phandle = <0x123>; | |
| vdd-supply = <0x125>; | |
| USB3_GDSC-supply = <0x120>; | |
| linux,phandle = <0x123>; | |
| }; | |
| qcom,cci@1b0c000 { | |
| reg = <0x1b0c000 0x4000>; | |
| interrupts = <0x00 0x32 0x00>; | |
| reg-names = "cci"; | |
| qcom,gpio-tbl-flags = <0x01 0x01>; | |
| qcom,gpio-tbl-label = "CCI_I2C_DATA0\0CCI_I2C_CLK0"; | |
| compatible = "qcom,cci"; | |
| clock-names = "ispif_ahb_clk\0cci_src_clk\0cci_ahb_clk\0camss_cci_clk\0camss_ahb_clk\0camss_top_ahb_clk"; | |
| interrupt-names = "cci"; | |
| clocks = <0x37 0x3c0a858f 0x37 0x822f3d97 0x37 0xa81c11ba 0x37 0xb7dd8824 0x37 0x9894b414 0x37 0x4e814a78>; | |
| cell-index = <0x00>; | |
| status = "ok"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,gpio-tbl-num = <0x00 0x01>; | |
| qcom,clock-rates = <0x3ab06a0 0x124f800 0x00 0x00 0x00 0x00 0x3ab06a0 0x23c3460 0x00 0x00 0x00 0x00>; | |
| qcom,i2c_standard_mode { | |
| qcom,hw-trdhld = <0x06>; | |
| qcom,hw-tsu-sta = <0x1c>; | |
| qcom,hw-tsu-sto = <0x1c>; | |
| qcom,hw-scl-stretch-en = <0x00>; | |
| status = "disabled"; | |
| qcom,hw-tsp = <0x01>; | |
| qcom,hw-thigh = <0x4e>; | |
| qcom,hw-thd-dat = <0x0a>; | |
| qcom,hw-thd-sta = <0x4d>; | |
| qcom,hw-tbuf = <0x76>; | |
| qcom,hw-tlow = <0x72>; | |
| }; | |
| qcom,i2c_custom_mode { | |
| qcom,hw-trdhld = <0x06>; | |
| qcom,hw-tsu-sta = <0x15>; | |
| qcom,hw-tsu-sto = <0x15>; | |
| qcom,hw-scl-stretch-en = <0x01>; | |
| status = "ok"; | |
| qcom,hw-tsp = <0x03>; | |
| qcom,hw-thigh = <0x0f>; | |
| qcom,hw-thd-dat = <0x0d>; | |
| qcom,hw-thd-sta = <0x12>; | |
| qcom,hw-tbuf = <0x19>; | |
| qcom,hw-tlow = <0x1c>; | |
| }; | |
| qcom,i2c_fast_mode { | |
| qcom,hw-trdhld = <0x06>; | |
| qcom,hw-tsu-sta = <0x15>; | |
| qcom,hw-tsu-sto = <0x15>; | |
| qcom,hw-scl-stretch-en = <0x00>; | |
| status = "ok"; | |
| qcom,hw-tsp = <0x03>; | |
| qcom,hw-thigh = <0x14>; | |
| qcom,hw-thd-dat = <0x0d>; | |
| qcom,hw-thd-sta = <0x12>; | |
| qcom,hw-tbuf = <0x20>; | |
| qcom,hw-tlow = <0x1c>; | |
| }; | |
| qcom,i2c_fast_plus_mode { | |
| qcom,hw-trdhld = <0x03>; | |
| qcom,hw-tsu-sta = <0x12>; | |
| qcom,hw-tsu-sto = <0x11>; | |
| qcom,hw-scl-stretch-en = <0x01>; | |
| qcom,cci-clk-src = <0x23c3460>; | |
| status = "ok"; | |
| qcom,hw-tsp = <0x03>; | |
| qcom,hw-thigh = <0x10>; | |
| qcom,hw-thd-dat = <0x10>; | |
| qcom,hw-thd-sta = <0x0f>; | |
| qcom,hw-tbuf = <0x13>; | |
| qcom,hw-tlow = <0x16>; | |
| }; | |
| qcom,eeprom@0 { | |
| reg = <0x00>; | |
| qcom,gpio-standby = <0x02>; | |
| pinctrl-0 = <0x17c 0x17d 0x17e>; | |
| pinctrl-1 = <0x17f 0x180 0x181>; | |
| qcom,cam-vreg-op-mode = <0x00 0x19a28 0x186a0>; | |
| gpios = <0xbe 0x1a 0x00 0xbe 0x28 0x00 0xbe 0x27 0x00 0xbe 0x86 0x00>; | |
| qcom,cci-master = <0x00>; | |
| compatible = "qcom,eeprom"; | |
| clock-names = "cam_src_clk\0cam_clk"; | |
| qcom,gpio-req-tbl-flags = <0x01 0x00 0x00 0x00>; | |
| qcom,gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; | |
| qcom,gpio-req-tbl-label = "CAMIF_MCLK0\0CAM_RESET0\0CAM_STANDBY0\0CAM_VANA"; | |
| qcom,cam-vreg-name = "cam_vio\0cam_vdig\0cam_vaf"; | |
| cam_vio-supply = <0x17a>; | |
| qcom,gpio-reset = <0x01>; | |
| clocks = <0x37 0x266b3853 0x37 0x80902deb>; | |
| cam_vaf-supply = <0x179>; | |
| qcom,cam-vreg-max-voltage = <0x00 0x10c8e0 0x2b7cd0>; | |
| cam_vdig-supply = <0x17b>; | |
| cell-index = <0x00>; | |
| status = "ok"; | |
| qcom,cam-vreg-min-voltage = <0x00 0x10c8e0 0x2b7cd0>; | |
| qcom,gpio-vana = <0x03>; | |
| pinctrl-names = "cam_default\0cam_suspend"; | |
| qcom,clock-rates = <0x124f800 0x00>; | |
| }; | |
| qcom,eeprom@2 { | |
| reg = <0x02>; | |
| qcom,gpio-standby = <0x02>; | |
| cam_vana-supply = <0x183>; | |
| pinctrl-0 = <0x184 0x185>; | |
| pinctrl-1 = <0x186 0x187>; | |
| qcom,cam-vreg-op-mode = <0x30d40 0x00 0x13880 0x186a0>; | |
| gpios = <0xbe 0x1c 0x00 0xbe 0x83 0x00 0xbe 0x84 0x00>; | |
| qcom,cci-master = <0x01>; | |
| compatible = "qcom,eeprom"; | |
| clock-names = "cam_src_clk\0cam_clk"; | |
| qcom,gpio-req-tbl-flags = <0x01 0x00 0x00>; | |
| qcom,gpio-req-tbl-num = <0x00 0x01 0x02>; | |
| qcom,gpio-req-tbl-label = "CAMIF_MCLK1\0CAM_RESET1\0CAM_STANDBY1"; | |
| qcom,cam-vreg-name = "cam_vdig\0cam_vio\0cam_vana\0cam_vaf"; | |
| cam_vio-supply = <0x17a>; | |
| qcom,gpio-reset = <0x01>; | |
| clocks = <0x37 0x42545468 0x37 0x222f8fff>; | |
| cam_vaf-supply = <0x179>; | |
| qcom,cam-vreg-max-voltage = <0x124f80 0x00 0x2ab980 0x2b7cd0>; | |
| cam_vdig-supply = <0x182>; | |
| cell-index = <0x02>; | |
| status = "ok"; | |
| qcom,cam-vreg-min-voltage = <0x124f80 0x00 0x2ab980 0x2b7cd0>; | |
| phandle = <0x188>; | |
| pinctrl-names = "cam_default\0cam_suspend"; | |
| qcom,clock-rates = <0x124f800 0x00>; | |
| linux,phandle = <0x188>; | |
| }; | |
| qcom,camera@1 { | |
| reg = <0x01>; | |
| qcom,gpio-standby = <0x02>; | |
| cam_vana-supply = <0x183>; | |
| pinctrl-0 = <0x184 0x185>; | |
| pinctrl-1 = <0x186 0x187>; | |
| qcom,cam-vreg-op-mode = <0x30d40 0x00 0x13880 0x186a0>; | |
| gpios = <0xbe 0x1c 0x00 0xbe 0x83 0x00 0xbe 0x84 0x00>; | |
| qcom,cci-master = <0x01>; | |
| qcom,eeprom-src = <0x188>; | |
| compatible = "qcom,camera"; | |
| clock-names = "cam_src_clk\0cam_clk"; | |
| qcom,gpio-req-tbl-flags = <0x01 0x00 0x00>; | |
| qcom,gpio-req-tbl-num = <0x00 0x01 0x02>; | |
| qcom,gpio-req-tbl-label = "CAMIF_MCLK1\0CAM_RESET1\0CAM_STANDBY1"; | |
| qcom,sensor-position = <0x100>; | |
| qcom,sensor-mode = <0x01>; | |
| qcom,csiphy-sd-index = <0x01>; | |
| qcom,cam-vreg-name = "cam_vdig\0cam_vio\0cam_vana\0cam_vaf"; | |
| cam_vio-supply = <0x17a>; | |
| qcom,gpio-reset = <0x01>; | |
| clocks = <0x37 0x42545468 0x37 0x222f8fff>; | |
| qcom,mount-angle = <0x5a>; | |
| cam_vaf-supply = <0x179>; | |
| qcom,cam-vreg-max-voltage = <0x124f80 0x00 0x2ab980 0x2b7cd0>; | |
| cam_vdig-supply = <0x182>; | |
| cell-index = <0x01>; | |
| status = "ok"; | |
| qcom,cam-vreg-min-voltage = <0x124f80 0x00 0x2ab980 0x2b7cd0>; | |
| qcom,csid-sd-index = <0x01>; | |
| qcom,actuator-src = <0x189>; | |
| pinctrl-names = "cam_default\0cam_suspend"; | |
| qcom,clock-rates = <0x16e3600 0x00>; | |
| }; | |
| qcom,camera@2 { | |
| reg = <0x02>; | |
| qcom,gpio-standby = <0x02>; | |
| cam_vana-supply = <0x183>; | |
| pinctrl-0 = <0x18a 0x18b>; | |
| pinctrl-1 = <0x18c 0x18d>; | |
| qcom,cam-vreg-op-mode = <0x19a28 0x00 0x13880 0x186a0>; | |
| gpios = <0xbe 0x1b 0x00 0xbe 0x81 0x00 0xbe 0x82 0x00>; | |
| qcom,cci-master = <0x00>; | |
| compatible = "qcom,camera"; | |
| clock-names = "cam_src_clk\0cam_clk"; | |
| qcom,gpio-req-tbl-flags = <0x01 0x00 0x00>; | |
| qcom,gpio-req-tbl-num = <0x00 0x01 0x02>; | |
| qcom,gpio-req-tbl-label = "CAMIF_MCLK2\0CAM_RESET2\0CAM_STANDBY2"; | |
| qcom,sensor-position = <0x01>; | |
| qcom,sensor-mode = <0x00>; | |
| qcom,csiphy-sd-index = <0x02>; | |
| qcom,cam-vreg-name = "cam_vdig\0cam_vio\0cam_vana\0cam_vaf"; | |
| cam_vio-supply = <0x17a>; | |
| qcom,gpio-reset = <0x01>; | |
| clocks = <0x37 0xa73cad0c 0x37 0x5002d85f>; | |
| qcom,mount-angle = <0x5a>; | |
| cam_vaf-supply = <0x179>; | |
| qcom,cam-vreg-max-voltage = <0x11edd8 0x00 0x2ab980 0x2b7cd0>; | |
| qcom,gpio-no-mux = <0x00>; | |
| cam_vdig-supply = <0x182>; | |
| cell-index = <0x02>; | |
| status = "ok"; | |
| qcom,cam-vreg-min-voltage = <0x11edd8 0x00 0x2ab980 0x2b7cd0>; | |
| qcom,csid-sd-index = <0x02>; | |
| pinctrl-names = "cam_default\0cam_suspend"; | |
| qcom,clock-rates = <0x16e3600 0x00>; | |
| }; | |
| qcom,actuator@0 { | |
| reg = <0x00>; | |
| qcom,cam-vreg-op-mode = <0x13880>; | |
| qcom,cci-master = <0x00>; | |
| compatible = "qcom,actuator"; | |
| qcom,cam-vreg-name = "cam_vaf"; | |
| cam_vaf-supply = <0x179>; | |
| qcom,cam-vreg-max-voltage = <0x2b7cd0>; | |
| cell-index = <0x00>; | |
| qcom,cam-vreg-min-voltage = <0x2b7cd0>; | |
| }; | |
| qcom,actuator@1 { | |
| reg = <0x01>; | |
| qcom,cam-vreg-op-mode = <0x13880>; | |
| qcom,cci-master = <0x00>; | |
| compatible = "qcom,actuator"; | |
| qcom,cam-vreg-name = "cam_vaf"; | |
| cam_vaf-supply = <0x179>; | |
| qcom,cam-vreg-max-voltage = <0x2b7cd0>; | |
| cell-index = <0x01>; | |
| qcom,cam-vreg-min-voltage = <0x2b7cd0>; | |
| phandle = <0x189>; | |
| linux,phandle = <0x189>; | |
| }; | |
| }; | |
| qcom,iommu@1e00000 { | |
| reg = <0x1e00000 0x40000>; | |
| interrupts = <0x00 0x29 0x00 0x00 0x26 0x00>; | |
| reg-names = "iommu_base"; | |
| label = "apps_iommu"; | |
| compatible = "qcom,msm-smmu-v2\0qcom,msm-mmu-500"; | |
| clock-names = "iface_clk\0core_clk"; | |
| interrupt-names = "global_cfg_NS_irq\0global_cfg_S_irq"; | |
| clocks = <0x37 0x75eaefa5 0x37 0x8fbc51da>; | |
| #iommu-cells = <0x01>; | |
| qcom,iommu-secure-id = <0x11>; | |
| ranges; | |
| status = "ok"; | |
| #address-cells = <0x01>; | |
| qcom,cb-base-offset = <0x20000>; | |
| phandle = <0x176>; | |
| #size-cells = <0x01>; | |
| linux,phandle = <0x176>; | |
| qcom,iommu-ctx@1e20000 { | |
| reg = <0x1e20000 0x1000>; | |
| interrupts = <0x00 0xfd 0x00 0x00 0xfd 0x00>; | |
| label = "adsp_elf"; | |
| compatible = "qcom,msm-smmu-v2-ctx"; | |
| qcom,secure-context; | |
| qcom,iommu-sid-mask = <0x3f0>; | |
| qcom,iommu-ctx-sids = <0x2400>; | |
| }; | |
| qcom,iommu-ctx@1e21000 { | |
| reg = <0x1e21000 0x1000>; | |
| interrupts = <0x00 0xfe 0x00 0x00 0xfe 0x00>; | |
| label = "adsp_sec_pixel"; | |
| compatible = "qcom,msm-smmu-v2-ctx"; | |
| qcom,secure-context; | |
| qcom,iommu-sid-mask = <0x3f1>; | |
| qcom,iommu-ctx-sids = <0x2402>; | |
| }; | |
| qcom,iommu-ctx@1e22000 { | |
| reg = <0x1e22000 0x1000>; | |
| interrupts = <0x00 0xff 0x00 0x00 0xff 0x00>; | |
| label = "mdp_1"; | |
| compatible = "qcom,msm-smmu-v2-ctx"; | |
| qcom,secure-context; | |
| qcom,iommu-ctx-sids = <0xc01>; | |
| }; | |
| qcom,iommu-ctx@1e23000 { | |
| reg = <0x1e23000 0x1000>; | |
| interrupts = <0x00 0x35 0x00 0x00 0x35 0x00>; | |
| label = "venus_fw"; | |
| compatible = "qcom,msm-smmu-v2-ctx"; | |
| qcom,secure-context; | |
| qcom,iommu-sid-mask = <0x200 0x200 0x220>; | |
| qcom,iommu-ctx-sids = <0x980 0x986 0x903>; | |
| qcom,report-error-on-fault; | |
| }; | |
| qcom,iommu-ctx@1e24000 { | |
| reg = <0x1e24000 0x1000>; | |
| interrupts = <0x00 0x36 0x00 0x00 0x36 0x00>; | |
| label = "venus_sec_non_pixel"; | |
| compatible = "qcom,msm-smmu-v2-ctx"; | |
| qcom,secure-context; | |
| qcom,iommu-sid-mask = <0x200 0x20a 0x208 0x200>; | |
| qcom,iommu-ctx-sids = <0x908 0x905 0x925 0x928>; | |
| phandle = <0xb7>; | |
| qcom,report-error-on-fault; | |
| linux,phandle = <0xb7>; | |
| }; | |
| qcom,iommu-ctx@1e25000 { | |
| reg = <0x1e25000 0x1000>; | |
| interrupts = <0x00 0x3a 0x00 0x00 0x3a 0x00>; | |
| label = "venus_sec_bitstream"; | |
| compatible = "qcom,msm-smmu-v2-ctx"; | |
| qcom,secure-context; | |
| qcom,iommu-sid-mask = <0x200 0x208 0x202 0x200 0x200 0x202>; | |
| qcom,iommu-ctx-sids = <0x900 0x902 0x909 0x90e 0x926 0x929>; | |
| phandle = <0xb5>; | |
| qcom,report-error-on-fault; | |
| linux,phandle = <0xb5>; | |
| }; | |
| qcom,iommu-ctx@1e26000 { | |
| reg = <0x1e26000 0x1000>; | |
| interrupts = <0x00 0x3c 0x00 0x00 0x3c 0x00>; | |
| label = "venus_sec_pixel"; | |
| compatible = "qcom,msm-smmu-v2-ctx"; | |
| qcom,secure-context; | |
| qcom,iommu-sid-mask = <0x208 0x200 0x200>; | |
| qcom,iommu-ctx-sids = <0x904 0x910 0x92c>; | |
| phandle = <0xb6>; | |
| qcom,report-error-on-fault; | |
| linux,phandle = <0xb6>; | |
| }; | |
| qcom,iommu-ctx@1e28000 { | |
| reg = <0x1e28000 0x1000>; | |
| interrupts = <0x00 0x4c 0x00>; | |
| label = "pronto_pil"; | |
| compatible = "qcom,msm-smmu-v2-ctx"; | |
| qcom,iommu-sid-mask = <0x3f2 0x3f0 0x3f0>; | |
| qcom,iommu-ctx-sids = <0x1401 0x1402 0x1404>; | |
| }; | |
| qcom,iommu-ctx@1e29000 { | |
| reg = <0x1e29000 0x1000>; | |
| interrupts = <0x00 0x4d 0x00>; | |
| label = "q6"; | |
| compatible = "qcom,msm-smmu-v2-ctx"; | |
| qcom,iommu-sid-mask = <0x3fe>; | |
| qcom,iommu-ctx-sids = <0x1000>; | |
| }; | |
| qcom,iommu-ctx@1e30000 { | |
| reg = <0x1e30000 0x1000>; | |
| interrupts = <0x00 0x69 0x00>; | |
| label = "adsp_opendsp"; | |
| compatible = "qcom,msm-smmu-v2-ctx"; | |
| qcom,iommu-sid-mask = <0x3f0>; | |
| qcom,iommu-ctx-sids = <0x2404>; | |
| }; | |
| qcom,iommu-ctx@1e31000 { | |
| reg = <0x1e31000 0x1000>; | |
| interrupts = <0x00 0x6a 0x00>; | |
| label = "adsp_shared"; | |
| compatible = "qcom,msm-smmu-v2-ctx"; | |
| qcom,iommu-sid-mask = <0x3f7>; | |
| qcom,iommu-ctx-sids = <0x2408>; | |
| phandle = <0xfe>; | |
| linux,phandle = <0xfe>; | |
| }; | |
| qcom,iommu-ctx@1e32000 { | |
| reg = <0x1e32000 0x1000>; | |
| interrupts = <0x00 0x6d 0x00>; | |
| label = "cpp"; | |
| compatible = "qcom,msm-smmu-v2-ctx"; | |
| qcom,iommu-sid-mask = <0x3fc>; | |
| qcom,iommu-ctx-sids = <0x1c00>; | |
| }; | |
| qcom,iommu-ctx@1e33000 { | |
| reg = <0x1e33000 0x1000>; | |
| interrupts = <0x00 0x6e 0x00>; | |
| label = "jpeg_enc0"; | |
| compatible = "qcom,msm-smmu-v2-ctx"; | |
| qcom,iommu-sid-mask = <0x3fe>; | |
| qcom,iommu-ctx-sids = <0x1800>; | |
| }; | |
| qcom,iommu-ctx@1e34000 { | |
| reg = <0x1e34000 0x1000>; | |
| interrupts = <0x00 0x6f 0x00>; | |
| label = "vfe"; | |
| compatible = "qcom,msm-smmu-v2-ctx"; | |
| qcom,iommu-sid-mask = <0x3fc 0x3fc>; | |
| qcom,iommu-ctx-sids = <0x400 0x2800>; | |
| }; | |
| qcom,iommu-ctx@1e35000 { | |
| reg = <0x1e35000 0x1000>; | |
| interrupts = <0x00 0x70 0x00>; | |
| label = "mdp_0"; | |
| compatible = "qcom,msm-smmu-v2-ctx"; | |
| qcom,iommu-sid-mask = <0x3fe>; | |
| qcom,iommu-ctx-sids = <0xc00>; | |
| }; | |
| qcom,iommu-ctx@1e36000 { | |
| reg = <0x1e36000 0x1000>; | |
| interrupts = <0x00 0x71 0x00>; | |
| label = "venus_ns"; | |
| compatible = "qcom,msm-smmu-v2-ctx"; | |
| qcom,iommu-sid-mask = <0x201 0x200 0x207 0x201 0x203 0x201 0x210>; | |
| qcom,iommu-ctx-sids = <0x800 0x807 0x808 0x810 0x828 0x82c 0x821>; | |
| phandle = <0xb4>; | |
| qcom,report-error-on-fault; | |
| linux,phandle = <0xb4>; | |
| }; | |
| qcom,iommu-ctx@1e37000 { | |
| reg = <0x1e37000 0x1000>; | |
| interrupts = <0x00 0x72 0x00>; | |
| label = "access_control"; | |
| compatible = "qcom,msm-smmu-v2-ctx"; | |
| qcom,iommu-sid-mask = <0x3f1 0x3f3 0x3f1 0x7f 0x01 0x01 0x3f>; | |
| qcom,iommu-ctx-sids = <0x1406 0x1408 0x140c 0x100 0x1d4 0x1e6 0x340>; | |
| }; | |
| qcom,iommu-ctx@1e38000 { | |
| reg = <0x1e38000 0x1000>; | |
| interrupts = <0x00 0x73 0x00>; | |
| label = "ipa"; | |
| compatible = "qcom,msm-smmu-v2-ctx"; | |
| qcom,iommu-sid-mask = <0x3fa 0x3f8>; | |
| qcom,iommu-ctx-sids = <0x2000 0x2004>; | |
| }; | |
| qcom,iommu-ctx@1e2a000 { | |
| reg = <0x1e2a000 0x1000>; | |
| interrupts = <0x00 0x50 0x00>; | |
| label = "periph_rpm"; | |
| compatible = "qcom,msm-smmu-v2-ctx"; | |
| qcom,iommu-sid-mask = <0x3f>; | |
| qcom,iommu-ctx-sids = <0x40>; | |
| }; | |
| qcom,iommu-ctx@1e2b000 { | |
| reg = <0x1e2b000 0x1000>; | |
| interrupts = <0x00 0x5e 0x00>; | |
| label = "lpass"; | |
| compatible = "qcom,msm-smmu-v2-ctx"; | |
| qcom,iommu-sid-mask = <0x07 0x01 0x03 0x03 0x01 0x07 0x03 0x01 0x07 0x01>; | |
| qcom,iommu-ctx-sids = <0x1c0 0x1ca 0x1cc 0x1d0 0x1d6 0x1d8 0x1e0 0x1e4 0x1e8 0x1f0>; | |
| }; | |
| qcom,iommu-ctx@1e2f000 { | |
| reg = <0x1e2f000 0x1000>; | |
| interrupts = <0x00 0x68 0x00>; | |
| label = "adsp_io"; | |
| compatible = "qcom,msm-smmu-v2-ctx"; | |
| qcom,iommu-sid-mask = <0x3f0>; | |
| #iommu-cells = <0x01>; | |
| qcom,iommu-ctx-sids = <0x2401>; | |
| qcom,virtual-addr-pool = <0x10000000 0xfffffff>; | |
| phandle = <0x12c>; | |
| linux,phandle = <0x12c>; | |
| }; | |
| }; | |
| qcom,msm-pcm-voice { | |
| compatible = "qcom,msm-pcm-voice"; | |
| qcom,destroy-cvd; | |
| phandle = <0x13c>; | |
| linux,phandle = <0x13c>; | |
| }; | |
| qcom,msm-core@a0000 { | |
| reg = <0xa0000 0x1000>; | |
| compatible = "qcom,apss-core-ea"; | |
| qcom,high-hyst-temp = <0x64>; | |
| qcom,low-hyst-temp = <0x64>; | |
| ea0 { | |
| sensor = <0xbf>; | |
| phandle = <0x0c>; | |
| linux,phandle = <0x0c>; | |
| }; | |
| ea1 { | |
| sensor = <0xc0>; | |
| phandle = <0x11>; | |
| linux,phandle = <0x11>; | |
| }; | |
| ea2 { | |
| sensor = <0xc1>; | |
| phandle = <0x14>; | |
| linux,phandle = <0x14>; | |
| }; | |
| ea3 { | |
| sensor = <0xc2>; | |
| phandle = <0x17>; | |
| linux,phandle = <0x17>; | |
| }; | |
| ea4 { | |
| sensor = <0xc3>; | |
| phandle = <0x1a>; | |
| linux,phandle = <0x1a>; | |
| }; | |
| ea5 { | |
| sensor = <0xc4>; | |
| phandle = <0x1f>; | |
| linux,phandle = <0x1f>; | |
| }; | |
| ea6 { | |
| sensor = <0xc5>; | |
| phandle = <0x22>; | |
| linux,phandle = <0x22>; | |
| }; | |
| ea7 { | |
| sensor = <0xc6>; | |
| phandle = <0x25>; | |
| linux,phandle = <0x25>; | |
| }; | |
| }; | |
| ad-hoc-bus@580000 { | |
| reg = <0x580000 0x16080 0x580000 0x16080 0x400000 0x5a000 0x500000 0x12080>; | |
| reg-names = "snoc-base\0snoc-mm-base\0bimc-base\0pcnoc-base"; | |
| compatible = "qcom,msm-bus-device"; | |
| fab-bimc { | |
| label = "fab-bimc"; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-bimc"; | |
| clock-names = "bus_clk\0bus_a_clk"; | |
| qcom,util-fact = <0x99>; | |
| qcom,base-name = "bimc-base"; | |
| coresight-child-ports = <0x02>; | |
| clocks = <0x37 0xd212feea 0x37 0x71d1a499>; | |
| qcom,fab-dev; | |
| phandle = <0x78>; | |
| coresight-child-list = <0x70>; | |
| qcom,bus-type = <0x02>; | |
| cell-id = <0x00>; | |
| coresight-nr-inports = <0x00>; | |
| linux,phandle = <0x78>; | |
| coresight-id = <0xcb>; | |
| }; | |
| fab-snoc { | |
| label = "fab-snoc"; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-snoc"; | |
| clock-names = "bus_clk\0bus_a_clk"; | |
| qcom,qos-off = <0x1000>; | |
| qcom,base-name = "snoc-base"; | |
| coresight-child-ports = <0x04>; | |
| clocks = <0x37 0xe6900bb6 0x37 0x5d4683bd>; | |
| qcom,fab-dev; | |
| phandle = <0x7f>; | |
| coresight-child-list = <0x74>; | |
| qcom,base-offset = <0x7000>; | |
| qcom,bus-type = <0x01>; | |
| cell-id = <0x400>; | |
| coresight-nr-inports = <0x00>; | |
| linux,phandle = <0x7f>; | |
| coresight-id = <0xc8>; | |
| }; | |
| slv-lpass { | |
| label = "slv-lpass"; | |
| qcom,bus-dev = <0x7f>; | |
| qcom,slv-rpm-id = <0x15>; | |
| qcom,ap-owned; | |
| phandle = <0xa6>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x20a>; | |
| linux,phandle = <0xa6>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-bimc-snoc { | |
| label = "slv-bimc-snoc"; | |
| qcom,bus-dev = <0x78>; | |
| qcom,slv-rpm-id = <0x02>; | |
| qcom,connections = <0xad>; | |
| phandle = <0x77>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2721>; | |
| linux,phandle = <0x77>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| slv-crypto-0-cfg { | |
| label = "slv-crypto-0-cfg"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x34>; | |
| qcom,ap-owned; | |
| phandle = <0xa0>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x271>; | |
| linux,phandle = <0xa0>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-qdss-stm { | |
| label = "slv-qdss-stm"; | |
| qcom,bus-dev = <0x7f>; | |
| qcom,slv-rpm-id = <0x1e>; | |
| phandle = <0xa9>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x24c>; | |
| linux,phandle = <0xa9>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| fab-pcnoc { | |
| label = "fab-pcnoc"; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-pcnoc"; | |
| clock-names = "bus_clk\0bus_a_clk"; | |
| qcom,qos-off = <0x1000>; | |
| qcom,base-name = "pcnoc-base"; | |
| coresight-child-ports = <0x03>; | |
| clocks = <0x37 0x2b53b688 0x37 0x9753a54f>; | |
| qcom,fab-dev; | |
| phandle = <0x7a>; | |
| coresight-child-list = <0x74>; | |
| qcom,base-offset = <0x7000>; | |
| qcom,bus-type = <0x01>; | |
| cell-id = <0x1000>; | |
| coresight-nr-inports = <0x00>; | |
| linux,phandle = <0x7a>; | |
| coresight-id = <0xc9>; | |
| qcom,node-qos-clks { | |
| clock-names = "pcnoc-usb3-axi-no-rate"; | |
| clocks = <0x37 0xf7f4b314>; | |
| }; | |
| }; | |
| mas-qdss-bam { | |
| qcom,qos-mode = "fixed"; | |
| label = "mas-qdss-bam"; | |
| qcom,bus-dev = <0x7f>; | |
| qcom,connections = <0x7e>; | |
| qcom,mas-rpm-id = <0x13>; | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x35>; | |
| qcom,buswidth = <0x04>; | |
| qcom,prio0 = <0x01>; | |
| qcom,prio1 = <0x01>; | |
| qcom,qport = <0x0b>; | |
| }; | |
| mas-qdss-etr { | |
| qcom,qos-mode = "fixed"; | |
| label = "mas-qdss-etr"; | |
| qcom,bus-dev = <0x7f>; | |
| qcom,connections = <0x7e>; | |
| qcom,mas-rpm-id = <0x1f>; | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x3c>; | |
| qcom,buswidth = <0x08>; | |
| qcom,prio0 = <0x01>; | |
| qcom,prio1 = <0x01>; | |
| qcom,qport = <0x0a>; | |
| }; | |
| slv-kpss-ahb { | |
| label = "slv-kpss-ahb"; | |
| qcom,bus-dev = <0x7f>; | |
| qcom,slv-rpm-id = <0x14>; | |
| qcom,ap-owned; | |
| phandle = <0xa8>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2a1>; | |
| linux,phandle = <0xa8>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-bimc-snoc { | |
| label = "mas-bimc-snoc"; | |
| qcom,bus-dev = <0x7f>; | |
| qcom,connections = <0x80 0x81 0x82>; | |
| qcom,mas-rpm-id = <0x15>; | |
| phandle = <0xad>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2720>; | |
| linux,phandle = <0xad>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| slv-camera-ss-cfg { | |
| label = "slv-camera-ss-cfg"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x03>; | |
| qcom,ap-owned; | |
| phandle = <0x9d>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x24d>; | |
| linux,phandle = <0x9d>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-snoc-bimc-0 { | |
| label = "slv-snoc-bimc-0"; | |
| qcom,bus-dev = <0x84>; | |
| qcom,slv-rpm-id = <0x18>; | |
| qcom,connections = <0xaf>; | |
| qcom,ap-owned; | |
| phandle = <0x85>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2729>; | |
| linux,phandle = <0x85>; | |
| qcom,buswidth = <0x10>; | |
| }; | |
| slv-snoc-bimc-1 { | |
| label = "slv-snoc-bimc-1"; | |
| qcom,bus-dev = <0x7f>; | |
| qcom,slv-rpm-id = <0x68>; | |
| qcom,connections = <0xb0>; | |
| phandle = <0x86>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x272a>; | |
| linux,phandle = <0x86>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| slv-snoc-bimc-2 { | |
| label = "slv-snoc-bimc-2"; | |
| qcom,bus-dev = <0x84>; | |
| qcom,slv-rpm-id = <0x89>; | |
| qcom,connections = <0xb1>; | |
| qcom,ap-owned; | |
| phandle = <0x83>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x273e>; | |
| linux,phandle = <0x83>; | |
| qcom,buswidth = <0x10>; | |
| }; | |
| slv-blsp-1 { | |
| label = "slv-blsp-1"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x27>; | |
| phandle = <0x9a>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x265>; | |
| linux,phandle = <0x9a>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-blsp-2 { | |
| label = "slv-blsp-2"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x25>; | |
| phandle = <0x9b>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x263>; | |
| linux,phandle = <0x9b>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-cats-0 { | |
| label = "slv-cats-0"; | |
| qcom,bus-dev = <0x84>; | |
| qcom,slv-rpm-id = <0x6a>; | |
| qcom,ap-owned; | |
| phandle = <0xab>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x297>; | |
| linux,phandle = <0xab>; | |
| qcom,buswidth = <0x10>; | |
| }; | |
| slv-cats-1 { | |
| label = "slv-cats-1"; | |
| qcom,bus-dev = <0x7f>; | |
| qcom,slv-rpm-id = <0x6b>; | |
| qcom,ap-owned; | |
| phandle = <0xac>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x298>; | |
| linux,phandle = <0xac>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| snoc-int-0 { | |
| label = "snoc-int-0"; | |
| qcom,bus-dev = <0x7f>; | |
| qcom,slv-rpm-id = <0x82>; | |
| qcom,connections = <0xa6 0xa7 0xa8>; | |
| qcom,mas-rpm-id = <0x63>; | |
| qcom,ap-owned; | |
| phandle = <0x80>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2714>; | |
| linux,phandle = <0x80>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| snoc-int-1 { | |
| label = "snoc-int-1"; | |
| qcom,bus-dev = <0x7f>; | |
| qcom,slv-rpm-id = <0x83>; | |
| qcom,connections = <0xa9 0xaa 0x87>; | |
| qcom,mas-rpm-id = <0x64>; | |
| phandle = <0x81>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2715>; | |
| linux,phandle = <0x81>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| snoc-int-2 { | |
| label = "snoc-int-2"; | |
| qcom,bus-dev = <0x7f>; | |
| qcom,slv-rpm-id = <0xc5>; | |
| qcom,connections = <0xab 0xac>; | |
| qcom,mas-rpm-id = <0x86>; | |
| qcom,ap-owned; | |
| phandle = <0x82>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2752>; | |
| linux,phandle = <0x82>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| mas-cpp { | |
| qcom,qos-mode = "bypass"; | |
| label = "mas-cpp"; | |
| qcom,bus-dev = <0x84>; | |
| qcom,connections = <0x83>; | |
| qcom,mas-rpm-id = <0x73>; | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x6a>; | |
| qcom,buswidth = <0x10>; | |
| qcom,qport = <0x0c>; | |
| }; | |
| mas-ipa { | |
| qcom,qos-mode = "fixed"; | |
| label = "mas-ipa"; | |
| qcom,bus-dev = <0x7f>; | |
| qcom,connections = <0x80 0x81 0x86>; | |
| qcom,mas-rpm-id = <0x3b>; | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x5a>; | |
| qcom,buswidth = <0x08>; | |
| qcom,prio0 = <0x00>; | |
| qcom,prio1 = <0x00>; | |
| qcom,qport = <0x0e>; | |
| }; | |
| mas-mdp { | |
| qcom,qos-mode = "bypass"; | |
| label = "mas-mdp"; | |
| qcom,bus-dev = <0x84>; | |
| qcom,connections = <0x85>; | |
| qcom,mas-rpm-id = <0x08>; | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x16>; | |
| qcom,buswidth = <0x10>; | |
| qcom,qport = <0x07>; | |
| }; | |
| mas-pcnoc-snoc { | |
| qcom,qos-mode = "fixed"; | |
| label = "mas-pcnoc-snoc"; | |
| qcom,bus-dev = <0x7f>; | |
| qcom,blacklist = <0x87>; | |
| qcom,connections = <0x80 0x81 0x86>; | |
| qcom,mas-rpm-id = <0x1d>; | |
| phandle = <0xae>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x271a>; | |
| linux,phandle = <0xae>; | |
| qcom,buswidth = <0x08>; | |
| qcom,qport = <0x05>; | |
| }; | |
| slv-ebi { | |
| label = "slv-ebi"; | |
| qcom,bus-dev = <0x78>; | |
| qcom,slv-rpm-id = <0x00>; | |
| phandle = <0x76>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x200>; | |
| linux,phandle = <0x76>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| slv-pdm { | |
| label = "slv-pdm"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x29>; | |
| phandle = <0x94>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x267>; | |
| linux,phandle = <0x94>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-tcu { | |
| label = "slv-tcu"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x85>; | |
| qcom,ap-owned; | |
| phandle = <0x91>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2a0>; | |
| linux,phandle = <0x91>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| slv-message-ram { | |
| label = "slv-message-ram"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x37>; | |
| phandle = <0x9c>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x274>; | |
| linux,phandle = <0x9c>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-jpeg { | |
| qcom,qos-mode = "bypass"; | |
| label = "mas-jpeg"; | |
| qcom,bus-dev = <0x84>; | |
| qcom,connections = <0x83>; | |
| qcom,mas-rpm-id = <0x07>; | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x3e>; | |
| qcom,buswidth = <0x10>; | |
| qcom,qport = <0x06>; | |
| }; | |
| mas-spdm { | |
| label = "mas-spdm"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,connections = <0x79>; | |
| qcom,mas-rpm-id = <0x32>; | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x24>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-vfe0 { | |
| qcom,qos-mode = "bypass"; | |
| label = "mas-vfe0"; | |
| qcom,bus-dev = <0x84>; | |
| qcom,connections = <0x85>; | |
| qcom,mas-rpm-id = <0x0b>; | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x1d>; | |
| qcom,buswidth = <0x10>; | |
| qcom,qport = <0x09>; | |
| }; | |
| mas-vfe1 { | |
| qcom,qos-mode = "bypass"; | |
| label = "mas-vfe1"; | |
| qcom,bus-dev = <0x84>; | |
| qcom,connections = <0x85>; | |
| qcom,mas-rpm-id = <0x85>; | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x6d>; | |
| qcom,buswidth = <0x10>; | |
| qcom,qport = <0x0d>; | |
| }; | |
| mas-usb3 { | |
| qcom,qos-mode = "fixed"; | |
| label = "mas-usb3"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,connections = <0x7c>; | |
| qcom,mas-rpm-id = <0x20>; | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x3d>; | |
| qcom,buswidth = <0x08>; | |
| qcom,prio0 = <0x01>; | |
| qcom,prio1 = <0x01>; | |
| qcom,qport = <0x0b>; | |
| }; | |
| qdss-int { | |
| label = "qdss-int"; | |
| qcom,bus-dev = <0x7f>; | |
| qcom,slv-rpm-id = <0x80>; | |
| qcom,connections = <0x81 0x86>; | |
| qcom,mas-rpm-id = <0x62>; | |
| qcom,ap-owned; | |
| phandle = <0x7e>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2719>; | |
| linux,phandle = <0x7e>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| slv-sdcc-1 { | |
| label = "slv-sdcc-1"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x1f>; | |
| phandle = <0xa2>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x25e>; | |
| linux,phandle = <0xa2>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-sdcc-2 { | |
| label = "slv-sdcc-2"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x21>; | |
| phandle = <0xa1>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x260>; | |
| linux,phandle = <0xa1>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-snoc-pcnoc { | |
| qcom,qos-mode = "fixed"; | |
| label = "mas-snoc-pcnoc"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,connections = <0x7d>; | |
| qcom,mas-rpm-id = <0x4d>; | |
| phandle = <0xb2>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2739>; | |
| linux,phandle = <0xb2>; | |
| qcom,buswidth = <0x08>; | |
| qcom,qport = <0x09>; | |
| }; | |
| slv-disp-ss-cfg { | |
| label = "slv-disp-ss-cfg"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x04>; | |
| qcom,ap-owned; | |
| phandle = <0x9e>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x24e>; | |
| linux,phandle = <0x9e>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-oxili { | |
| qcom,qos-mode = "fixed"; | |
| label = "mas-oxili"; | |
| qcom,prio-rd = <0x00>; | |
| qcom,prio-wr = <0x00>; | |
| qcom,bus-dev = <0x78>; | |
| qcom,connections = <0x76 0x77>; | |
| qcom,mas-rpm-id = <0x06>; | |
| qcom,ap-owned; | |
| qcom,prio-lvl = <0x00>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x1a>; | |
| qcom,buswidth = <0x08>; | |
| qcom,qport = <0x02>; | |
| }; | |
| mas-tcu-0 { | |
| qcom,qos-mode = "fixed"; | |
| label = "mas-tcu-0"; | |
| qcom,prio-rd = <0x02>; | |
| qcom,bus-dev = <0x78>; | |
| qcom,connections = <0x76 0x77>; | |
| qcom,mas-rpm-id = <0x66>; | |
| qcom,ap-owned; | |
| qcom,prio-lvl = <0x02>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x68>; | |
| qcom,buswidth = <0x08>; | |
| qcom,qport = <0x06>; | |
| }; | |
| mas-venus { | |
| qcom,qos-mode = "bypass"; | |
| label = "mas-venus"; | |
| qcom,bus-dev = <0x84>; | |
| qcom,connections = <0x83>; | |
| qcom,mas-rpm-id = <0x09>; | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x3f>; | |
| qcom,buswidth = <0x10>; | |
| qcom,qport = <0x08>; | |
| }; | |
| mas-apps-proc { | |
| qcom,qos-mode = "fixed"; | |
| label = "mas-apps-proc"; | |
| qcom,prio-rd = <0x00>; | |
| qcom,prio-wr = <0x00>; | |
| qcom,bus-dev = <0x78>; | |
| qcom,connections = <0x76 0x77>; | |
| qcom,mas-rpm-id = <0x00>; | |
| qcom,ap-owned; | |
| qcom,prio-lvl = <0x00>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x01>; | |
| qcom,buswidth = <0x08>; | |
| qcom,qport = <0x00>; | |
| }; | |
| slv-venus-cfg { | |
| label = "slv-venus-cfg"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x0a>; | |
| qcom,ap-owned; | |
| phandle = <0x9f>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x254>; | |
| linux,phandle = <0x9f>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-snoc-bimc-0 { | |
| qcom,qos-mode = "bypass"; | |
| label = "mas-snoc-bimc-0"; | |
| qcom,bus-dev = <0x78>; | |
| qcom,connections = <0x76 0x77>; | |
| qcom,mas-rpm-id = <0x03>; | |
| qcom,ap-owned; | |
| phandle = <0xaf>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2717>; | |
| linux,phandle = <0xaf>; | |
| qcom,buswidth = <0x08>; | |
| qcom,qport = <0x03>; | |
| }; | |
| mas-snoc-bimc-1 { | |
| qcom,qos-mode = "bypass"; | |
| label = "mas-snoc-bimc-1"; | |
| qcom,bus-dev = <0x78>; | |
| qcom,connections = <0x76>; | |
| qcom,mas-rpm-id = <0x4c>; | |
| phandle = <0xb0>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2718>; | |
| linux,phandle = <0xb0>; | |
| qcom,buswidth = <0x08>; | |
| qcom,qport = <0x05>; | |
| }; | |
| mas-snoc-bimc-2 { | |
| qcom,qos-mode = "bypass"; | |
| label = "mas-snoc-bimc-2"; | |
| qcom,bus-dev = <0x78>; | |
| qcom,connections = <0x76 0x77>; | |
| qcom,mas-rpm-id = <0x6c>; | |
| qcom,ap-owned; | |
| phandle = <0xb1>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x273d>; | |
| linux,phandle = <0xb1>; | |
| qcom,buswidth = <0x08>; | |
| qcom,qport = <0x04>; | |
| }; | |
| slv-gpu-cfg { | |
| label = "slv-gpu-cfg"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x0b>; | |
| qcom,ap-owned; | |
| phandle = <0x92>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x256>; | |
| linux,phandle = <0x92>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| slv-pmic-arb { | |
| label = "slv-pmic-arb"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x3b>; | |
| phandle = <0xa3>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x278>; | |
| linux,phandle = <0xa3>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-pcnoc-snoc { | |
| label = "slv-pcnoc-snoc"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x2d>; | |
| qcom,connections = <0xae>; | |
| phandle = <0x88>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x271b>; | |
| linux,phandle = <0x88>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| slv-snoc-cfg { | |
| label = "slv-snoc-cfg"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x46>; | |
| phandle = <0x97>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x282>; | |
| linux,phandle = <0x97>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| pcnoc-m-0 { | |
| qcom,qos-mode = "fixed"; | |
| label = "pcnoc-m-0"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x74>; | |
| qcom,connections = <0x7c>; | |
| qcom,mas-rpm-id = <0x57>; | |
| qcom,ap-owned; | |
| phandle = <0x79>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x271e>; | |
| linux,phandle = <0x79>; | |
| qcom,buswidth = <0x04>; | |
| qcom,prio0 = <0x01>; | |
| qcom,prio1 = <0x01>; | |
| qcom,qport = <0x05>; | |
| }; | |
| pcnoc-m-1 { | |
| qcom,qos-mode = "fixed"; | |
| label = "pcnoc-m-1"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x75>; | |
| qcom,connections = <0x7c>; | |
| qcom,mas-rpm-id = <0x58>; | |
| phandle = <0x7b>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x271f>; | |
| linux,phandle = <0x7b>; | |
| qcom,buswidth = <0x04>; | |
| qcom,qport = <0x06>; | |
| }; | |
| pcnoc-s-0 { | |
| label = "pcnoc-s-0"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x76>; | |
| qcom,connections = <0x94 0x95>; | |
| qcom,mas-rpm-id = <0x59>; | |
| phandle = <0x8b>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2722>; | |
| linux,phandle = <0x8b>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| pcnoc-s-1 { | |
| label = "pcnoc-s-1"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x77>; | |
| qcom,connections = <0x96>; | |
| qcom,mas-rpm-id = <0x5a>; | |
| phandle = <0x89>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2723>; | |
| linux,phandle = <0x89>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| pcnoc-s-2 { | |
| label = "pcnoc-s-2"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x78>; | |
| qcom,connections = <0x97>; | |
| qcom,mas-rpm-id = <0x5b>; | |
| phandle = <0x8a>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2724>; | |
| linux,phandle = <0x8a>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| pcnoc-s-3 { | |
| label = "pcnoc-s-3"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x79>; | |
| qcom,connections = <0x98 0x99 0x9a 0x9b 0x9c>; | |
| qcom,mas-rpm-id = <0x5c>; | |
| phandle = <0x93>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2725>; | |
| linux,phandle = <0x93>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| pcnoc-s-4 { | |
| label = "pcnoc-s-4"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x7a>; | |
| qcom,connections = <0x9d 0x9e 0x9f>; | |
| qcom,mas-rpm-id = <0x5d>; | |
| qcom,ap-owned; | |
| phandle = <0x8c>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2726>; | |
| linux,phandle = <0x8c>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| pcnoc-s-6 { | |
| label = "pcnoc-s-6"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x7b>; | |
| qcom,connections = <0xa0 0xa1 0xa2>; | |
| qcom,mas-rpm-id = <0x5e>; | |
| phandle = <0x8d>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2d1>; | |
| linux,phandle = <0x8d>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| pcnoc-s-7 { | |
| label = "pcnoc-s-7"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x7c>; | |
| qcom,connections = <0xa3>; | |
| qcom,mas-rpm-id = <0x5f>; | |
| phandle = <0x8e>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2740>; | |
| linux,phandle = <0x8e>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| pcnoc-s-8 { | |
| label = "pcnoc-s-8"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x7d>; | |
| qcom,connections = <0xa4>; | |
| qcom,mas-rpm-id = <0x60>; | |
| qcom,ap-owned; | |
| phandle = <0x8f>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2727>; | |
| linux,phandle = <0x8f>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| pcnoc-s-9 { | |
| label = "pcnoc-s-9"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x7e>; | |
| qcom,connections = <0xa5>; | |
| qcom,mas-rpm-id = <0x61>; | |
| qcom,ap-owned; | |
| phandle = <0x90>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2728>; | |
| linux,phandle = <0x90>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-blsp-1 { | |
| label = "mas-blsp-1"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,connections = <0x7b>; | |
| qcom,mas-rpm-id = <0x29>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x56>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-blsp-2 { | |
| label = "mas-blsp-2"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,connections = <0x7b>; | |
| qcom,mas-rpm-id = <0x27>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x54>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-crypto { | |
| qcom,qos-mode = "fixed"; | |
| label = "mas-crypto"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,connections = <0x7c>; | |
| qcom,mas-rpm-id = <0x17>; | |
| qcom,ap-owned; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x37>; | |
| qcom,buswidth = <0x08>; | |
| qcom,prio0 = <0x01>; | |
| qcom,prio1 = <0x01>; | |
| qcom,qport = <0x00>; | |
| }; | |
| fab-snoc-mm { | |
| label = "fab-snoc-mm"; | |
| clock-names = "bus_clk\0bus_a_clk"; | |
| qcom,util-fact = <0x99>; | |
| qcom,qos-off = <0x1000>; | |
| qcom,base-name = "snoc-mm-base"; | |
| clocks = <0x37 0xd61e5721 0x37 0x50600f1b>; | |
| qcom,fab-dev; | |
| phandle = <0x84>; | |
| qcom,base-offset = <0x7000>; | |
| qcom,bus-type = <0x01>; | |
| cell-id = <0x800>; | |
| linux,phandle = <0x84>; | |
| }; | |
| slv-imem { | |
| label = "slv-imem"; | |
| qcom,bus-dev = <0x7f>; | |
| qcom,slv-rpm-id = <0x1a>; | |
| phandle = <0xaa>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x249>; | |
| linux,phandle = <0xaa>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| slv-prng { | |
| label = "slv-prng"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x2c>; | |
| phandle = <0x99>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x26a>; | |
| linux,phandle = <0x99>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-tcsr { | |
| label = "slv-tcsr"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x32>; | |
| phandle = <0x96>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x26f>; | |
| linux,phandle = <0x96>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-spdm { | |
| label = "slv-spdm"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x3c>; | |
| qcom,ap-owned; | |
| phandle = <0x95>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x279>; | |
| linux,phandle = <0x95>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-tlmm { | |
| label = "slv-tlmm"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x33>; | |
| phandle = <0x98>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x270>; | |
| linux,phandle = <0x98>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-usb3 { | |
| label = "slv-usb3"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x16>; | |
| qcom,ap-owned; | |
| phandle = <0xa4>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x247>; | |
| linux,phandle = <0xa4>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-wcss { | |
| label = "slv-wcss"; | |
| qcom,bus-dev = <0x7f>; | |
| qcom,slv-rpm-id = <0x17>; | |
| qcom,ap-owned; | |
| phandle = <0xa7>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x248>; | |
| linux,phandle = <0xa7>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| pcnoc-int-1 { | |
| label = "pcnoc-int-1"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0x73>; | |
| qcom,connections = <0x7d 0x88>; | |
| qcom,mas-rpm-id = <0x56>; | |
| phandle = <0x7c>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x271d>; | |
| linux,phandle = <0x7c>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| pcnoc-int-2 { | |
| label = "pcnoc-int-2"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0xb8>; | |
| qcom,connections = <0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93>; | |
| qcom,mas-rpm-id = <0x7c>; | |
| phandle = <0x7d>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2741>; | |
| linux,phandle = <0x7d>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| slv-snoc-pcnoc { | |
| label = "slv-snoc-pcnoc"; | |
| qcom,bus-dev = <0x7f>; | |
| qcom,slv-rpm-id = <0x1c>; | |
| qcom,connections = <0xb2>; | |
| phandle = <0x87>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x273a>; | |
| linux,phandle = <0x87>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| mas-sdcc-1 { | |
| qcom,qos-mode = "fixed"; | |
| label = "mas-sdcc-1"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,connections = <0x7c>; | |
| qcom,mas-rpm-id = <0x21>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x4e>; | |
| qcom,buswidth = <0x08>; | |
| qcom,qport = <0x07>; | |
| }; | |
| mas-sdcc-2 { | |
| qcom,qos-mode = "fixed"; | |
| label = "mas-sdcc-2"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,connections = <0x7c>; | |
| qcom,mas-rpm-id = <0x23>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x51>; | |
| qcom,buswidth = <0x08>; | |
| qcom,qport = <0x08>; | |
| }; | |
| slv-ipa-cfg { | |
| label = "slv-ipa-cfg"; | |
| qcom,bus-dev = <0x7a>; | |
| qcom,slv-rpm-id = <0xb7>; | |
| qcom,ap-owned; | |
| phandle = <0xa5>; | |
| qcom,agg-ports = <0x01>; | |
| cell-id = <0x2a4>; | |
| linux,phandle = <0xa5>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| }; | |
| clock-controller@b011000 { | |
| reg = <0xb011000 0x1000>; | |
| compatible = "qcom,8953-l2ccc"; | |
| phandle = <0x1c>; | |
| linux,phandle = <0x1c>; | |
| }; | |
| pinctrl@1000000 { | |
| reg = <0x1000000 0x300000>; | |
| interrupts = <0x00 0xd0 0x00>; | |
| #gpio-cells = <0x02>; | |
| compatible = "qcom,msm8953-pinctrl"; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0xbe>; | |
| interrupt-controller; | |
| gpio-controller; | |
| linux,phandle = <0xbe>; | |
| pmx_ts_release { | |
| ts_release { | |
| mux { | |
| pins = "gpio65\0gpio64"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio65\0gpio64"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| pmx_ts_int_suspend { | |
| ts_int_suspend { | |
| mux { | |
| pins = "gpio65"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio65"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| default { | |
| phandle = <0xcf>; | |
| linux,phandle = <0xcf>; | |
| mux { | |
| pins = "gpio12\0gpio13"; | |
| function = "blsp_uart4"; | |
| }; | |
| config { | |
| pins = "gpio12\0gpio13"; | |
| bias-disable; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| cdc-pdm-comp-lines { | |
| pdm_comp_lines_on { | |
| phandle = <0x15f>; | |
| linux,phandle = <0x15f>; | |
| mux { | |
| pins = "gpio67\0gpio68"; | |
| function = "cdc_pdm0"; | |
| }; | |
| config { | |
| pins = "gpio67\0gpio68"; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| pdm_comp_lines_off { | |
| phandle = <0x12e>; | |
| linux,phandle = <0x12e>; | |
| mux { | |
| pins = "gpio67\0gpio68"; | |
| function = "cdc_pdm0"; | |
| }; | |
| config { | |
| pins = "gpio67\0gpio68"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| pmx_ts_reset_suspend { | |
| ts_reset_suspend { | |
| mux { | |
| pins = "gpio64"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio64"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| wcnss_pmux_gpio { | |
| wcnss_gpio_default { | |
| phandle = <0xfa>; | |
| linux,phandle = <0xfa>; | |
| mux { | |
| pins = "gpio76\0gpio77\0gpio78\0gpio79\0gpio80"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio76\0gpio77\0gpio78\0gpio79\0gpio80"; | |
| bias-pull-up; | |
| drive-strength = <0x06>; | |
| }; | |
| }; | |
| }; | |
| sdc1_data_off { | |
| phandle = <0x107>; | |
| linux,phandle = <0x107>; | |
| config { | |
| pins = "sdc1_data"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| sdc2_clk_off { | |
| phandle = <0x10d>; | |
| linux,phandle = <0x10d>; | |
| config { | |
| pins = "sdc2_clk"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| sdc2_cmd_off { | |
| phandle = <0x10e>; | |
| linux,phandle = <0x10e>; | |
| config { | |
| pins = "sdc2_cmd"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| sdc2_data_on { | |
| phandle = <0x10b>; | |
| linux,phandle = <0x10b>; | |
| config { | |
| pins = "sdc2_data"; | |
| bias-pull-up; | |
| drive-strength = <0x0a>; | |
| }; | |
| }; | |
| SY7803_pins { | |
| en_default { | |
| phandle = <0x19e>; | |
| linux,phandle = <0x19e>; | |
| mux { | |
| pins = "gpio90\0gpio91"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio90\0gpio91"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| cd_on { | |
| phandle = <0x10c>; | |
| linux,phandle = <0x10c>; | |
| mux { | |
| pins = "gpio133"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio133"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| i2c_2 { | |
| i2c_2_active { | |
| phandle = <0xd0>; | |
| linux,phandle = <0xd0>; | |
| mux { | |
| pins = "gpio6\0gpio7"; | |
| function = "blsp_i2c2"; | |
| }; | |
| config { | |
| pins = "gpio6\0gpio7"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| i2c_2_sleep { | |
| phandle = <0xd1>; | |
| linux,phandle = <0xd1>; | |
| mux { | |
| pins = "gpio6\0gpio7"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio6\0gpio7"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| i2c_4 { | |
| i2c_4_active { | |
| phandle = <0xdc>; | |
| linux,phandle = <0xdc>; | |
| mux { | |
| pins = "gpio14\0gpio15"; | |
| function = "blsp_i2c4"; | |
| }; | |
| config { | |
| pins = "gpio14\0gpio15"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| i2c_4_sleep { | |
| phandle = <0xdd>; | |
| linux,phandle = <0xdd>; | |
| mux { | |
| pins = "gpio14\0gpio15"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio14\0gpio15"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| i2c_5 { | |
| i2c_5_sleep { | |
| phandle = <0xe3>; | |
| linux,phandle = <0xe3>; | |
| mux { | |
| pins = "gpio18\0gpio19"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio18\0gpio19"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| i2c_5_active { | |
| phandle = <0xe2>; | |
| linux,phandle = <0xe2>; | |
| mux { | |
| pins = "gpio18\0gpio19"; | |
| function = "blsp_i2c5"; | |
| }; | |
| config { | |
| pins = "gpio18\0gpio19"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| i2c_8 { | |
| i2c_8_active { | |
| phandle = <0xe5>; | |
| linux,phandle = <0xe5>; | |
| mux { | |
| pins = "gpio98\0gpio99"; | |
| function = "blsp_i2c8"; | |
| }; | |
| config { | |
| pins = "gpio98\0gpio99"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| i2c_8_sleep { | |
| phandle = <0xe6>; | |
| linux,phandle = <0xe6>; | |
| mux { | |
| pins = "gpio98\0gpio99"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio98\0gpio99"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| sleep { | |
| phandle = <0xce>; | |
| linux,phandle = <0xce>; | |
| mux { | |
| pins = "gpio12\0gpio13"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio12\0gpio13"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| cam_sensor_front1_sleep { | |
| phandle = <0x18d>; | |
| linux,phandle = <0x18d>; | |
| mux { | |
| pins = "gpio129\0gpio130"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio129\0gpio130"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| cam_sensor_rear_default { | |
| phandle = <0x17d>; | |
| linux,phandle = <0x17d>; | |
| mux { | |
| pins = "gpio40\0gpio39"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio40\0gpio39"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| cam_sensor_mclk1_default { | |
| phandle = <0x18a>; | |
| linux,phandle = <0x18a>; | |
| mux { | |
| pins = "gpio27"; | |
| function = "cam_mclk"; | |
| }; | |
| config { | |
| pins = "gpio27"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| pmx_nfc_reset { | |
| pins = "gpio59"; | |
| label = "pmx_nfc_disable"; | |
| qcom,num-grp-pins = <0x01>; | |
| qcom,pin-func = <0x00>; | |
| active { | |
| bias-pull-up; | |
| drive-strength = <0x06>; | |
| phandle = <0xdf>; | |
| linux,phandle = <0xdf>; | |
| }; | |
| suspend { | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| phandle = <0xe1>; | |
| linux,phandle = <0xe1>; | |
| }; | |
| }; | |
| pmx_mdss { | |
| mdss_dsi_active { | |
| phandle = <0x197>; | |
| linux,phandle = <0x197>; | |
| mux { | |
| pins = "gpio61"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio61"; | |
| bias-disable = <0x00>; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| mdss_dsi_suspend { | |
| phandle = <0x199>; | |
| linux,phandle = <0x199>; | |
| mux { | |
| pins = "gpio61"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio61"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| wsa_reset { | |
| wsa_reset_off { | |
| phandle = <0xd7>; | |
| linux,phandle = <0xd7>; | |
| mux { | |
| pins = "gpio96"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio96"; | |
| output-low; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| wsa_reset_on { | |
| phandle = <0xda>; | |
| linux,phandle = <0xda>; | |
| mux { | |
| pins = "gpio96"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio96"; | |
| output-high; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_front1_default { | |
| phandle = <0x18b>; | |
| linux,phandle = <0x18b>; | |
| mux { | |
| pins = "gpio129\0gpio130"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio129\0gpio130"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| pmx-uart5console { | |
| uart_console_active { | |
| phandle = <0xcb>; | |
| linux,phandle = <0xcb>; | |
| mux { | |
| pins = "gpio16\0gpio17"; | |
| function = "blsp_uart5"; | |
| }; | |
| config { | |
| pins = "gpio16\0gpio17"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| uart5_console_sleep { | |
| mux { | |
| pins = "gpio16\0gpio17"; | |
| function = "blsp_uart5"; | |
| }; | |
| config { | |
| pins = "gpio16\0gpio17"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_rear_vdig { | |
| phandle = <0x17e>; | |
| linux,phandle = <0x17e>; | |
| mux { | |
| pins = "gpio134"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio134"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| pmx_rd_nfc_int { | |
| pins = "gpio44"; | |
| label = "pmx_nfc_int"; | |
| qcom,num-grp-pins = <0x01>; | |
| qcom,pin-func = <0x00>; | |
| active { | |
| bias-pull-up; | |
| drive-strength = <0x06>; | |
| phandle = <0xde>; | |
| linux,phandle = <0xde>; | |
| }; | |
| suspend { | |
| bias-pull-up; | |
| drive-strength = <0x06>; | |
| phandle = <0xe0>; | |
| linux,phandle = <0xe0>; | |
| }; | |
| }; | |
| cam_sensor_mclk0_sleep { | |
| phandle = <0x17f>; | |
| linux,phandle = <0x17f>; | |
| mux { | |
| pins = "gpio26"; | |
| function = "cam_mclk"; | |
| }; | |
| config { | |
| pins = "gpio26"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| pmx-uartconsole { | |
| uart_console_active { | |
| phandle = <0xca>; | |
| linux,phandle = <0xca>; | |
| mux { | |
| pins = "gpio4\0gpio5"; | |
| function = "blsp_uart2"; | |
| }; | |
| config { | |
| pins = "gpio4\0gpio5"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| uart_console_sleep { | |
| mux { | |
| pins = "gpio4\0gpio5"; | |
| function = "blsp_uart2"; | |
| }; | |
| config { | |
| pins = "gpio4\0gpio5"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| sdc2_data_off { | |
| phandle = <0x10f>; | |
| linux,phandle = <0x10f>; | |
| config { | |
| pins = "sdc2_data"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| pmx_adv7533_int { | |
| adv7533_int_active { | |
| phandle = <0xd3>; | |
| linux,phandle = <0xd3>; | |
| mux { | |
| pins = "gpio91"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio91"; | |
| bias-disable; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| adv7533_int_suspend { | |
| phandle = <0xd4>; | |
| linux,phandle = <0xd4>; | |
| mux { | |
| pins = "gpio91"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio91"; | |
| bias-disable; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_front_sleep { | |
| phandle = <0x187>; | |
| linux,phandle = <0x187>; | |
| mux { | |
| pins = "gpio131\0gpio132"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio131\0gpio132"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| cross-conn-det { | |
| lines_off { | |
| phandle = <0x130>; | |
| linux,phandle = <0x130>; | |
| mux { | |
| pins = "gpio63"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio63"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| lines_on { | |
| phandle = <0x135>; | |
| linux,phandle = <0x135>; | |
| mux { | |
| pins = "gpio63"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio63"; | |
| output-low; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| pmx_ts_int_active { | |
| ts_int_active { | |
| mux { | |
| pins = "gpio65"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio65"; | |
| bias-pull-up; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| wcd9xxx_intr { | |
| wcd_intr_default { | |
| phandle = <0x16d>; | |
| linux,phandle = <0x16d>; | |
| mux { | |
| pins = "gpio73"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio73"; | |
| input-enable; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| telpo_gpio { | |
| telpo_gpio_active { | |
| phandle = <0x1a2>; | |
| linux,phandle = <0x1a2>; | |
| mux { | |
| pins = "gpio0\0gpio11\0gpio136\0gpio48\0gpio1\0gpio2\0gpio3\0gpio24\0gpio31\0gpio32\0gpio45\0gpio42\0gpio43\0gpio135\0gpio90"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio0\0gpio11\0gpio136\0gpio48\0gpio1\0gpio2\0gpio3\0gpio24\0gpio31\0gpio32\0gpio45\0gpio42\0gpio43\0gpio135\0gpio90"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| telpo_gpio_suspend { | |
| phandle = <0x1a3>; | |
| linux,phandle = <0x1a3>; | |
| mux { | |
| pins = "gpio0\0gpio11\0gpio136\0gpio48\0gpio1\0gpio2\0gpio3\0gpio24\0gpio31\0gpio32\0gpio45\0gpio42\0gpio43\0gpio135\0gpio90"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio0\0gpio11\0gpio136\0gpio48\0gpio1\0gpio2\0gpio3\0gpio24\0gpio31\0gpio32\0gpio45\0gpio42\0gpio43\0gpio135\0gpio90"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| cdc_reset_ctrl { | |
| cdc_reset_sleep { | |
| phandle = <0x16f>; | |
| linux,phandle = <0x16f>; | |
| mux { | |
| pins = "gpio67"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio67"; | |
| bias-disable; | |
| output-low; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| cdc_reset_active { | |
| phandle = <0x16e>; | |
| linux,phandle = <0x16e>; | |
| mux { | |
| pins = "gpio67"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio67"; | |
| output-high; | |
| drive-strength = <0x10>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| cd_off { | |
| mux { | |
| pins = "gpio133"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio133"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| pri-tlmm-lines { | |
| pri_tlmm_lines_act { | |
| phandle = <0x136>; | |
| linux,phandle = <0x136>; | |
| mux { | |
| pins = "gpio91"; | |
| function = "pri_mi2s"; | |
| }; | |
| config { | |
| pins = "gpio91"; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| pri_tlmm_lines_sus { | |
| phandle = <0x131>; | |
| linux,phandle = <0x131>; | |
| mux { | |
| pins = "gpio91"; | |
| function = "pri_mi2s"; | |
| }; | |
| config { | |
| pins = "gpio91"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| sdc2_clk_on { | |
| phandle = <0x109>; | |
| linux,phandle = <0x109>; | |
| config { | |
| pins = "sdc2_clk"; | |
| bias-disable; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| sdc2_cmd_on { | |
| phandle = <0x10a>; | |
| linux,phandle = <0x10a>; | |
| config { | |
| pins = "sdc2_cmd"; | |
| bias-pull-up; | |
| drive-strength = <0x0a>; | |
| }; | |
| }; | |
| cam_sensor_mclk1_sleep { | |
| phandle = <0x18c>; | |
| linux,phandle = <0x18c>; | |
| mux { | |
| pins = "gpio27"; | |
| function = "cam_mclk"; | |
| }; | |
| config { | |
| pins = "gpio27"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| pmx_ts_reset_active { | |
| ts_reset_active { | |
| mux { | |
| pins = "gpio64"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio64"; | |
| bias-pull-up; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| typec_ssmux_config { | |
| phandle = <0x112>; | |
| linux,phandle = <0x112>; | |
| mux { | |
| pins = "gpio139"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio139"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| pri-tlmm-ws-lines { | |
| pri_tlmm_ws_act { | |
| phandle = <0x137>; | |
| linux,phandle = <0x137>; | |
| mux { | |
| pins = "gpio92"; | |
| function = "pri_mi2s_ws"; | |
| }; | |
| config { | |
| pins = "gpio92"; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| pri_tlmm_ws_sus { | |
| phandle = <0x132>; | |
| linux,phandle = <0x132>; | |
| mux { | |
| pins = "gpio92"; | |
| function = "pri_mi2s_ws"; | |
| }; | |
| config { | |
| pins = "gpio92"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| sdc1_clk_off { | |
| phandle = <0x105>; | |
| linux,phandle = <0x105>; | |
| config { | |
| pins = "sdc1_clk"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| sdc1_cmd_off { | |
| phandle = <0x106>; | |
| linux,phandle = <0x106>; | |
| config { | |
| pins = "sdc1_cmd"; | |
| num-grp-pins = <0x01>; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| sdc1_data_on { | |
| phandle = <0x103>; | |
| linux,phandle = <0x103>; | |
| config { | |
| pins = "sdc1_data"; | |
| bias-pull-up; | |
| drive-strength = <0x0a>; | |
| }; | |
| }; | |
| cam_sensor_mclk0_default { | |
| phandle = <0x17c>; | |
| linux,phandle = <0x17c>; | |
| mux { | |
| pins = "gpio26"; | |
| function = "cam_mclk"; | |
| }; | |
| config { | |
| pins = "gpio26"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| cam_sensor_mclk2_sleep { | |
| phandle = <0x186>; | |
| linux,phandle = <0x186>; | |
| mux { | |
| pins = "gpio28"; | |
| function = "cam_mclk"; | |
| }; | |
| config { | |
| pins = "gpio28"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| sdc1_rclk_on { | |
| phandle = <0x104>; | |
| linux,phandle = <0x104>; | |
| config { | |
| pins = "sdc1_rclk"; | |
| bias-pull-down; | |
| }; | |
| }; | |
| tlmm_gpio_key { | |
| gpio_key_active { | |
| phandle = <0x1a0>; | |
| linux,phandle = <0x1a0>; | |
| mux { | |
| pins = "gpio85\0gpio86\0gpio87\0gpio135\0gpio140"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio85\0gpio86\0gpio87\0gpio135\0gpio140"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| gpio_key_suspend { | |
| phandle = <0x1a1>; | |
| linux,phandle = <0x1a1>; | |
| mux { | |
| pins = "gpio85\0gpio86\0gpio87\0gpio135\0gpio140"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio85\0gpio86\0gpio87\0gpio135\0gpio140"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| pmx_qdsd_clk { | |
| clk_sdcard { | |
| phandle = <0x4a>; | |
| linux,phandle = <0x4a>; | |
| config { | |
| pins = "qdsd_clk"; | |
| bias-disable; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| clk_swdtrc { | |
| phandle = <0x5b>; | |
| linux,phandle = <0x5b>; | |
| config { | |
| pins = "qdsd_clk"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| clk_trace { | |
| phandle = <0x50>; | |
| linux,phandle = <0x50>; | |
| config { | |
| pins = "qdsd_clk"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| clk_spmi { | |
| phandle = <0x66>; | |
| linux,phandle = <0x66>; | |
| config { | |
| pins = "qdsd_clk"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| pmx_qdsd_cmd { | |
| cmd_jtag { | |
| phandle = <0x61>; | |
| linux,phandle = <0x61>; | |
| config { | |
| pins = "qdsd_cmd"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| cmd_spmi { | |
| phandle = <0x67>; | |
| linux,phandle = <0x67>; | |
| config { | |
| pins = "qdsd_cmd"; | |
| drive-strength = <0x0a>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| cmd_uart { | |
| phandle = <0x56>; | |
| linux,phandle = <0x56>; | |
| config { | |
| pins = "qdsd_cmd"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| cmd_sdcard { | |
| phandle = <0x4b>; | |
| linux,phandle = <0x4b>; | |
| config { | |
| pins = "qdsd_cmd"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| cmd_swdtrc { | |
| phandle = <0x5c>; | |
| linux,phandle = <0x5c>; | |
| config { | |
| pins = "qdsd_cmd"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| cmd_trace { | |
| phandle = <0x51>; | |
| linux,phandle = <0x51>; | |
| config { | |
| pins = "qdsd_cmd"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| pmx_mdss_te { | |
| mdss_te_suspend { | |
| phandle = <0x19a>; | |
| linux,phandle = <0x19a>; | |
| mux { | |
| pins = "gpio137"; | |
| function = "mdp_vsync"; | |
| }; | |
| config { | |
| pins = "gpio137"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| mdss_te_active { | |
| phandle = <0x198>; | |
| linux,phandle = <0x198>; | |
| mux { | |
| pins = "gpio137"; | |
| function = "mdp_vsync"; | |
| }; | |
| config { | |
| pins = "gpio137"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| pmx_qdsd_data0 { | |
| data0_trace { | |
| phandle = <0x52>; | |
| linux,phandle = <0x52>; | |
| config { | |
| pins = "qdsd_data0"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| data0_sdcard { | |
| phandle = <0x4c>; | |
| linux,phandle = <0x4c>; | |
| config { | |
| pins = "qdsd_data0"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| data0_swdtrc { | |
| phandle = <0x5d>; | |
| linux,phandle = <0x5d>; | |
| config { | |
| pins = "qdsd_data0"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| data0_jtag { | |
| phandle = <0x62>; | |
| linux,phandle = <0x62>; | |
| config { | |
| pins = "qdsd_data0"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| data0_spmi { | |
| phandle = <0x68>; | |
| linux,phandle = <0x68>; | |
| config { | |
| pins = "qdsd_data0"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| data0_uart { | |
| phandle = <0x57>; | |
| linux,phandle = <0x57>; | |
| config { | |
| pins = "qdsd_data0"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| pmx_qdsd_data1 { | |
| data1_trace { | |
| phandle = <0x53>; | |
| linux,phandle = <0x53>; | |
| config { | |
| pins = "qdsd_data1"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| data1_sdcard { | |
| phandle = <0x4d>; | |
| linux,phandle = <0x4d>; | |
| config { | |
| pins = "qdsd_data1"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| data1_swdtrc { | |
| phandle = <0x5e>; | |
| linux,phandle = <0x5e>; | |
| config { | |
| pins = "qdsd_data1"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| data1_jtag { | |
| phandle = <0x63>; | |
| linux,phandle = <0x63>; | |
| config { | |
| pins = "qdsd_data1"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| data1_uart { | |
| phandle = <0x58>; | |
| linux,phandle = <0x58>; | |
| config { | |
| pins = "qdsd_data1"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| pmx_qdsd_data2 { | |
| data2_trace { | |
| phandle = <0x54>; | |
| linux,phandle = <0x54>; | |
| config { | |
| pins = "qdsd_data2"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| data2_sdcard { | |
| phandle = <0x4e>; | |
| linux,phandle = <0x4e>; | |
| config { | |
| pins = "qdsd_data2"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| data2_swdtrc { | |
| phandle = <0x5f>; | |
| linux,phandle = <0x5f>; | |
| config { | |
| pins = "qdsd_data2"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| data2_jtag { | |
| phandle = <0x64>; | |
| linux,phandle = <0x64>; | |
| config { | |
| pins = "qdsd_data2"; | |
| bias-pull-up; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| data2_uart { | |
| phandle = <0x59>; | |
| linux,phandle = <0x59>; | |
| config { | |
| pins = "qdsd_data2"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| pmx_qdsd_data3 { | |
| data3_sdcard { | |
| phandle = <0x4f>; | |
| linux,phandle = <0x4f>; | |
| config { | |
| pins = "qdsd_data3"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| data3_swdtrc { | |
| phandle = <0x60>; | |
| linux,phandle = <0x60>; | |
| config { | |
| pins = "qdsd_data3"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| data3_trace { | |
| phandle = <0x55>; | |
| linux,phandle = <0x55>; | |
| config { | |
| pins = "qdsd_data3"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| data3_jtag { | |
| phandle = <0x65>; | |
| linux,phandle = <0x65>; | |
| config { | |
| pins = "qdsd_data3"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| data3_spmi { | |
| phandle = <0x69>; | |
| linux,phandle = <0x69>; | |
| config { | |
| pins = "qdsd_data3"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| data3_uart { | |
| phandle = <0x5a>; | |
| linux,phandle = <0x5a>; | |
| config { | |
| pins = "qdsd_data3"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_rear_vdig_sleep { | |
| phandle = <0x181>; | |
| linux,phandle = <0x181>; | |
| mux { | |
| pins = "gpio134"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio134"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| cdc_mclk2_pin { | |
| cdc_mclk2_sleep { | |
| phandle = <0x170>; | |
| linux,phandle = <0x170>; | |
| mux { | |
| pins = "gpio66"; | |
| function = "pri_mi2s"; | |
| }; | |
| config { | |
| pins = "gpio66"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| cdc_mclk2_active { | |
| phandle = <0x171>; | |
| linux,phandle = <0x171>; | |
| mux { | |
| pins = "gpio66"; | |
| function = "pri_mi2s"; | |
| }; | |
| config { | |
| pins = "gpio66"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| wsa-vi { | |
| wsa_vi_on { | |
| phandle = <0xdb>; | |
| linux,phandle = <0xdb>; | |
| mux { | |
| pins = "gpio94\0gpio95"; | |
| function = "wsa_io"; | |
| }; | |
| config { | |
| pins = "gpio94\0gpio95"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| wsa_vi_off { | |
| phandle = <0xd8>; | |
| linux,phandle = <0xd8>; | |
| mux { | |
| pins = "gpio94\0gpio95"; | |
| function = "wsa_io"; | |
| }; | |
| config { | |
| pins = "gpio94\0gpio95"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_mclk2_default { | |
| phandle = <0x184>; | |
| linux,phandle = <0x184>; | |
| mux { | |
| pins = "gpio28"; | |
| function = "cam_mclk"; | |
| }; | |
| config { | |
| pins = "gpio28"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| sdc1_rclk_off { | |
| phandle = <0x108>; | |
| linux,phandle = <0x108>; | |
| config { | |
| pins = "sdc1_rclk"; | |
| bias-pull-down; | |
| }; | |
| }; | |
| cdc-pdm-lines { | |
| pdm_lines_off { | |
| phandle = <0x12d>; | |
| linux,phandle = <0x12d>; | |
| mux { | |
| pins = "gpio69\0gpio73\0gpio74"; | |
| function = "cdc_pdm0"; | |
| }; | |
| config { | |
| pins = "gpio69\0gpio73\0gpio74"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| pdm_lines_on { | |
| phandle = <0x133>; | |
| linux,phandle = <0x133>; | |
| mux { | |
| pins = "gpio69\0gpio73\0gpio74"; | |
| function = "cdc_pdm0"; | |
| }; | |
| config { | |
| pins = "gpio69\0gpio73\0gpio74"; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| pmx-uart6console { | |
| uart_console_active { | |
| phandle = <0xcc>; | |
| linux,phandle = <0xcc>; | |
| mux { | |
| pins = "gpio20\0gpio21"; | |
| function = "blsp_uart6"; | |
| }; | |
| config { | |
| pins = "gpio20\0gpio21"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| uart6_console_sleep { | |
| mux { | |
| pins = "gpio20\0gpio21"; | |
| function = "blsp_uart5"; | |
| }; | |
| config { | |
| pins = "gpio20\0gpio21"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| }; | |
| sdc1_clk_on { | |
| phandle = <0x101>; | |
| linux,phandle = <0x101>; | |
| config { | |
| pins = "sdc1_clk"; | |
| bias-disable; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| sdc1_cmd_on { | |
| phandle = <0x102>; | |
| linux,phandle = <0x102>; | |
| config { | |
| pins = "sdc1_cmd"; | |
| bias-pull-up; | |
| drive-strength = <0x0a>; | |
| }; | |
| }; | |
| wcnss_pmux_5wire { | |
| wcnss_sleep { | |
| phandle = <0xf9>; | |
| linux,phandle = <0xf9>; | |
| wcss_wlan { | |
| pins = "gpio79\0gpio80"; | |
| function = "wcss_wlan"; | |
| }; | |
| config { | |
| pins = "gpio76\0gpio77\0gpio78\0gpio79\0gpio80"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| wcss_wlan0 { | |
| pins = "gpio78"; | |
| function = "wcss_wlan0"; | |
| }; | |
| wcss_wlan1 { | |
| pins = "gpio77"; | |
| function = "wcss_wlan1"; | |
| }; | |
| wcss_wlan2 { | |
| pins = "gpio76"; | |
| function = "wcss_wlan2"; | |
| }; | |
| }; | |
| wcnss_default { | |
| phandle = <0xf8>; | |
| linux,phandle = <0xf8>; | |
| wcss_wlan { | |
| pins = "gpio79\0gpio80"; | |
| function = "wcss_wlan"; | |
| }; | |
| config { | |
| pins = "gpio76\0gpio77\0gpio78\0gpio79\0gpio80"; | |
| bias-pull-up; | |
| drive-strength = <0x06>; | |
| }; | |
| wcss_wlan0 { | |
| pins = "gpio78"; | |
| function = "wcss_wlan0"; | |
| }; | |
| wcss_wlan1 { | |
| pins = "gpio77"; | |
| function = "wcss_wlan1"; | |
| }; | |
| wcss_wlan2 { | |
| pins = "gpio76"; | |
| function = "wcss_wlan2"; | |
| }; | |
| }; | |
| }; | |
| cdc-pdm-2-lines { | |
| pdm_lines_2_off { | |
| phandle = <0x12f>; | |
| linux,phandle = <0x12f>; | |
| mux { | |
| pins = "gpio70\0gpio71\0gpio72"; | |
| function = "cdc_pdm0"; | |
| }; | |
| config { | |
| pins = "gpio70\0gpio71\0gpio72"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| pdm_lines_2_on { | |
| phandle = <0x134>; | |
| linux,phandle = <0x134>; | |
| mux { | |
| pins = "gpio70\0gpio71\0gpio72"; | |
| function = "cdc_pdm0"; | |
| }; | |
| config { | |
| pins = "gpio70\0gpio71\0gpio72"; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_rear_sleep { | |
| phandle = <0x180>; | |
| linux,phandle = <0x180>; | |
| mux { | |
| pins = "gpio40\0gpio39"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio40\0gpio39"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| cam_sensor_front_default { | |
| phandle = <0x185>; | |
| linux,phandle = <0x185>; | |
| mux { | |
| pins = "gpio131\0gpio132"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio131\0gpio132"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| wsa_clk { | |
| wsa_clk_off { | |
| phandle = <0xd6>; | |
| linux,phandle = <0xd6>; | |
| mux { | |
| pins = "gpio25"; | |
| function = "pri_mi2s_mclk_a"; | |
| }; | |
| config { | |
| pins = "gpio25"; | |
| output-low; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| wsa_clk_on { | |
| phandle = <0xd9>; | |
| linux,phandle = <0xd9>; | |
| mux { | |
| pins = "gpio25"; | |
| function = "pri_mi2s_mclk_a"; | |
| }; | |
| config { | |
| pins = "gpio25"; | |
| output-high; | |
| drive-strength = <0x08>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| clock-controller@b088000 { | |
| reg = <0xb088000 0x1000>; | |
| compatible = "qcom,arm-cortex-acc"; | |
| phandle = <0x18>; | |
| linux,phandle = <0x18>; | |
| }; | |
| clock-controller@b098000 { | |
| reg = <0xb098000 0x1000>; | |
| compatible = "qcom,arm-cortex-acc"; | |
| phandle = <0x1d>; | |
| linux,phandle = <0x1d>; | |
| }; | |
| jtagfuse@a601c { | |
| reg = <0xa601c 0x08>; | |
| reg-names = "fuse-base"; | |
| compatible = "qcom,jtag-fuse-v2"; | |
| }; | |
| clock-controller@b111000 { | |
| reg = <0xb111000 0x1000>; | |
| compatible = "qcom,8953-l2ccc"; | |
| phandle = <0x0e>; | |
| linux,phandle = <0x0e>; | |
| }; | |
| qcom,msm-dai-mi2s { | |
| compatible = "qcom,msm-dai-mi2s"; | |
| qcom,msm-dai-q6-mi2s-prim { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x00>; | |
| qcom,msm-mi2s-rx-lines = <0x03>; | |
| phandle = <0x145>; | |
| linux,phandle = <0x145>; | |
| qcom,msm-mi2s-tx-lines = <0x00>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-quat { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x03>; | |
| qcom,msm-mi2s-rx-lines = <0x01>; | |
| phandle = <0x148>; | |
| linux,phandle = <0x148>; | |
| qcom,msm-mi2s-tx-lines = <0x02>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-quin { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x05>; | |
| qcom,msm-mi2s-rx-lines = <0x01>; | |
| phandle = <0x149>; | |
| linux,phandle = <0x149>; | |
| qcom,msm-mi2s-tx-lines = <0x02>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-tert { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x02>; | |
| qcom,msm-mi2s-rx-lines = <0x00>; | |
| phandle = <0x147>; | |
| linux,phandle = <0x147>; | |
| qcom,msm-mi2s-tx-lines = <0x03>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-senary { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x06>; | |
| qcom,msm-mi2s-rx-lines = <0x00>; | |
| phandle = <0x14a>; | |
| linux,phandle = <0x14a>; | |
| qcom,msm-mi2s-tx-lines = <0x03>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-sec { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x01>; | |
| qcom,msm-mi2s-rx-lines = <0x01>; | |
| phandle = <0x146>; | |
| linux,phandle = <0x146>; | |
| qcom,msm-mi2s-tx-lines = <0x00>; | |
| }; | |
| }; | |
| qcom,rpm-smd { | |
| compatible = "qcom,rpm-smd"; | |
| rpm-channel-name = "rpm_requests"; | |
| rpm-channel-type = <0x0f>; | |
| rpm-regulator-clk0 { | |
| qcom,resource-id = <0x03>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "clk0"; | |
| status = "disabled"; | |
| qcom,regulator-type = <0x01>; | |
| regulator-clk0 { | |
| regulator-name = "rpm_apc"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| rpm-regulator-ldoa10 { | |
| qcom,resource-id = <0x0a>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l10 { | |
| regulator-name = "pm8953_l10"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| qcom,init-voltage = <0x2b7cd0>; | |
| regulator-min-microvolt = <0x2b7cd0>; | |
| regulator-max-microvolt = <0x2b7cd0>; | |
| status = "okay"; | |
| phandle = <0xe7>; | |
| linux,phandle = <0xe7>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa11 { | |
| qcom,resource-id = <0x0b>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l11 { | |
| regulator-name = "pm8953_l11"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| qcom,init-voltage = <0x2d0370>; | |
| regulator-min-microvolt = <0x2d0370>; | |
| regulator-max-microvolt = <0x2d0370>; | |
| status = "okay"; | |
| phandle = <0x6a>; | |
| linux,phandle = <0x6a>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa12 { | |
| qcom,resource-id = <0x0c>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l12 { | |
| regulator-name = "pm8953_l12"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x2d0370>; | |
| status = "okay"; | |
| phandle = <0x6b>; | |
| linux,phandle = <0x6b>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa13 { | |
| qcom,resource-id = <0x0d>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,hpm-min-load = <0x1388>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l13 { | |
| regulator-name = "pm8953_l13"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| qcom,init-voltage = <0x2faf08>; | |
| regulator-min-microvolt = <0x2faf08>; | |
| regulator-max-microvolt = <0x2faf08>; | |
| status = "okay"; | |
| phandle = <0xed>; | |
| linux,phandle = <0xed>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa16 { | |
| qcom,resource-id = <0x10>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,hpm-min-load = <0x1388>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l16 { | |
| regulator-name = "pm8953_l16"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| status = "okay"; | |
| }; | |
| }; | |
| rpm-regulator-ldoa17 { | |
| qcom,resource-id = <0x11>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l17 { | |
| regulator-name = "pm8953_l17"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| qcom,init-voltage = <0x2b7cd0>; | |
| regulator-min-microvolt = <0x2b7cd0>; | |
| regulator-max-microvolt = <0x2b7cd0>; | |
| status = "okay"; | |
| phandle = <0x179>; | |
| linux,phandle = <0x179>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa19 { | |
| qcom,resource-id = <0x13>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l19 { | |
| regulator-name = "pm8953_l19"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x149970>; | |
| status = "okay"; | |
| phandle = <0xf6>; | |
| linux,phandle = <0xf6>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa22 { | |
| qcom,resource-id = <0x16>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l22 { | |
| regulator-name = "pm8953_l22"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| qcom,init-voltage = <0x325aa0>; | |
| regulator-min-microvolt = <0x325aa0>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| status = "okay"; | |
| phandle = <0x183>; | |
| linux,phandle = <0x183>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa23 { | |
| qcom,resource-id = <0x17>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l23 { | |
| regulator-name = "pm8953_l23"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| qcom,init-voltage = <0xee098>; | |
| regulator-min-microvolt = <0xee098>; | |
| regulator-max-microvolt = <0x12b128>; | |
| status = "okay"; | |
| phandle = <0x182>; | |
| linux,phandle = <0x182>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa1 { | |
| qcom,resource-id = <0x01>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l1 { | |
| regulator-name = "pm8953_l1"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| qcom,init-voltage = <0xf4240>; | |
| regulator-min-microvolt = <0xf4240>; | |
| regulator-max-microvolt = <0xf4240>; | |
| status = "okay"; | |
| }; | |
| }; | |
| rpm-regulator-ldoa2 { | |
| qcom,resource-id = <0x02>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l2 { | |
| regulator-name = "pm8953_l2"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| qcom,init-voltage = <0xee098>; | |
| regulator-min-microvolt = <0xee098>; | |
| regulator-max-microvolt = <0x12b128>; | |
| status = "okay"; | |
| phandle = <0x17b>; | |
| linux,phandle = <0x17b>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa3 { | |
| qcom,resource-id = <0x03>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l3 { | |
| regulator-name = "pm8953_l3"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| qcom,init-voltage = <0xe1d48>; | |
| regulator-min-microvolt = <0xe1d48>; | |
| regulator-max-microvolt = <0xe1d48>; | |
| status = "okay"; | |
| phandle = <0x125>; | |
| linux,phandle = <0x125>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa5 { | |
| qcom,resource-id = <0x05>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l5 { | |
| regulator-name = "pm8953_l5"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| status = "okay"; | |
| phandle = <0xe8>; | |
| linux,phandle = <0xe8>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa6 { | |
| qcom,resource-id = <0x06>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l6 { | |
| regulator-name = "pm8953_l6"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| status = "okay"; | |
| phandle = <0x17a>; | |
| linux,phandle = <0x17a>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa7 { | |
| qcom,resource-id = <0x07>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l7-ao { | |
| regulator-name = "pm8953_l7_ao"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x01>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1cfde0>; | |
| }; | |
| regulator-l7 { | |
| regulator-name = "pm8953_l7"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1cfde0>; | |
| status = "okay"; | |
| phandle = <0xf5>; | |
| linux,phandle = <0xf5>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa8 { | |
| qcom,resource-id = <0x08>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l8 { | |
| regulator-name = "pm8953_l8"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| qcom,init-voltage = <0x2c4020>; | |
| regulator-min-microvolt = <0x2c4020>; | |
| regulator-max-microvolt = <0x2c4020>; | |
| status = "okay"; | |
| phandle = <0x100>; | |
| linux,phandle = <0x100>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa9 { | |
| qcom,resource-id = <0x09>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,hpm-min-load = <0x2710>; | |
| qcom,resource-name = "ldoa"; | |
| status = "okay"; | |
| qcom,regulator-type = <0x00>; | |
| regulator-l9 { | |
| regulator-name = "pm8953_l9"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| qcom,init-voltage = <0x2dc6c0>; | |
| regulator-min-microvolt = <0x2dc6c0>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| status = "okay"; | |
| phandle = <0xf7>; | |
| linux,phandle = <0xf7>; | |
| }; | |
| }; | |
| rpm-regulator-smpa1 { | |
| qcom,resource-id = <0x01>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,hpm-min-load = <0x186a0>; | |
| qcom,resource-name = "smpa"; | |
| status = "okay"; | |
| qcom,regulator-type = <0x01>; | |
| regulator-s1 { | |
| regulator-name = "pm8953_s1"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| qcom,init-voltage = <0xf4240>; | |
| regulator-min-microvolt = <0xd4670>; | |
| regulator-max-microvolt = <0x11a3a0>; | |
| status = "okay"; | |
| phandle = <0x115>; | |
| linux,phandle = <0x115>; | |
| }; | |
| }; | |
| rpm-regulator-smpa2 { | |
| qcom,resource-id = <0x02>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,hpm-min-load = <0x186a0>; | |
| qcom,resource-name = "smpa"; | |
| status = "okay"; | |
| qcom,regulator-type = <0x01>; | |
| regulator-s2-floor-level { | |
| regulator-name = "pm8953_s2_floor_level"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| regulator-min-microvolt = <0x10>; | |
| qcom,use-voltage-floor-level; | |
| regulator-max-microvolt = <0x180>; | |
| qcom,always-send-voltage; | |
| phandle = <0xc7>; | |
| linux,phandle = <0xc7>; | |
| }; | |
| regulator-s2-level-ao { | |
| regulator-name = "pm8953_s2_level_ao"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x01>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-max-microvolt = <0x180>; | |
| qcom,use-voltage-level; | |
| }; | |
| regulator-s2-level { | |
| regulator-name = "pm8953_s2_level"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-max-microvolt = <0x180>; | |
| phandle = <0xee>; | |
| qcom,use-voltage-level; | |
| linux,phandle = <0xee>; | |
| }; | |
| regulator-s2 { | |
| regulator-name = "pm8953_s2"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| rpm-regulator-smpa3 { | |
| qcom,resource-id = <0x03>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,hpm-min-load = <0x186a0>; | |
| qcom,resource-name = "smpa"; | |
| status = "okay"; | |
| qcom,regulator-type = <0x01>; | |
| regulator-s3 { | |
| regulator-name = "pm8953_s3"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| qcom,init-voltage = <0x12b128>; | |
| regulator-min-microvolt = <0x12b128>; | |
| regulator-max-microvolt = <0x12b128>; | |
| status = "okay"; | |
| phandle = <0x173>; | |
| linux,phandle = <0x173>; | |
| }; | |
| }; | |
| rpm-regulator-smpa4 { | |
| qcom,resource-id = <0x04>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,hpm-min-load = <0x186a0>; | |
| qcom,resource-name = "smpa"; | |
| status = "okay"; | |
| qcom,regulator-type = <0x01>; | |
| regulator-s4 { | |
| regulator-name = "pm8953_s4"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| qcom,init-voltage = <0x1cfde0>; | |
| regulator-min-microvolt = <0x1cfde0>; | |
| regulator-max-microvolt = <0x1f47d0>; | |
| status = "okay"; | |
| phandle = <0x114>; | |
| linux,phandle = <0x114>; | |
| }; | |
| }; | |
| rpm-regulator-smpa7 { | |
| qcom,resource-id = <0x07>; | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,hpm-min-load = <0x186a0>; | |
| qcom,resource-name = "smpa"; | |
| status = "okay"; | |
| qcom,regulator-type = <0x01>; | |
| regulator-s7-level { | |
| regulator-name = "pm8953_s7_level"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-max-microvolt = <0x180>; | |
| qcom,always-send-voltage; | |
| qcom,init-voltage-level = <0x10>; | |
| qcom,use-voltage-level; | |
| }; | |
| regulator-s7 { | |
| regulator-name = "pm8953_s7"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x03>; | |
| status = "disabled"; | |
| }; | |
| regulator-s7-level-ao { | |
| regulator-name = "pm8953_s7_level_ao"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x01>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-max-microvolt = <0x180>; | |
| qcom,always-send-voltage; | |
| phandle = <0xf1>; | |
| qcom,use-voltage-level; | |
| linux,phandle = <0xf1>; | |
| }; | |
| regulator-s7-level-so { | |
| regulator-name = "pm8953_s7_level_so"; | |
| compatible = "qcom,rpm-smd-regulator"; | |
| qcom,set = <0x02>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-max-microvolt = <0x180>; | |
| qcom,init-voltage-level = <0x10>; | |
| qcom,use-voltage-level; | |
| }; | |
| }; | |
| }; | |
| clock-controller@b188000 { | |
| reg = <0xb188000 0x1000>; | |
| compatible = "qcom,arm-cortex-acc"; | |
| phandle = <0x0a>; | |
| linux,phandle = <0x0a>; | |
| }; | |
| clock-controller@b198000 { | |
| reg = <0xb198000 0x1000>; | |
| compatible = "qcom,arm-cortex-acc"; | |
| phandle = <0x0f>; | |
| linux,phandle = <0x0f>; | |
| }; | |
| dsi_panel_pwr_supply { | |
| #address-cells = <0x01>; | |
| phandle = <0x192>; | |
| #size-cells = <0x00>; | |
| linux,phandle = <0x192>; | |
| qcom,panel-supply-entry@0 { | |
| reg = <0x00>; | |
| qcom,supply-disable-load = <0x64>; | |
| qcom,supply-max-voltage = <0x2b7cd0>; | |
| qcom,supply-min-voltage = <0x2b7cd0>; | |
| qcom,supply-name = "vdd"; | |
| qcom,supply-enable-load = <0x186a0>; | |
| }; | |
| qcom,panel-supply-entry@1 { | |
| reg = <0x01>; | |
| qcom,supply-disable-load = <0x64>; | |
| qcom,supply-max-voltage = <0x1b7740>; | |
| qcom,supply-min-voltage = <0x1b7740>; | |
| qcom,supply-name = "vddio"; | |
| qcom,supply-enable-load = <0x186a0>; | |
| }; | |
| }; | |
| qcom,smem@86300000 { | |
| reg = <0x86300000 0x100000 0xb011008 0x04 0x60000 0x8000 0x193d000 0x08>; | |
| reg-names = "smem\0irq-reg-base\0aux-mem1\0smem_targ_info_reg"; | |
| compatible = "qcom,smem"; | |
| qcom,mpu-enabled; | |
| qcom,smsm-adsp { | |
| interrupts = <0x00 0x122 0x01>; | |
| compatible = "qcom,smsm"; | |
| qcom,smsm-edge = <0x01>; | |
| qcom,smsm-irq-offset = <0x00>; | |
| qcom,smsm-irq-bitmask = <0x200>; | |
| }; | |
| qcom,smd-modem { | |
| interrupts = <0x00 0x19 0x01>; | |
| label = "modem"; | |
| compatible = "qcom,smd"; | |
| qcom,not-loadable; | |
| qcom,smd-irq-offset = <0x00>; | |
| qcom,smd-irq-bitmask = <0x1000>; | |
| qcom,smd-edge = <0x00>; | |
| }; | |
| qcom,smd-wcnss { | |
| interrupts = <0x00 0x8e 0x01>; | |
| label = "wcnss"; | |
| compatible = "qcom,smd"; | |
| qcom,smd-irq-offset = <0x00>; | |
| qcom,smd-irq-bitmask = <0x20000>; | |
| qcom,smd-edge = <0x06>; | |
| }; | |
| qcom,smsm-modem { | |
| interrupts = <0x00 0x1a 0x01>; | |
| compatible = "qcom,smsm"; | |
| qcom,smsm-edge = <0x00>; | |
| qcom,smsm-irq-offset = <0x00>; | |
| qcom,smsm-irq-bitmask = <0x2000>; | |
| }; | |
| qcom,smsm-wcnss { | |
| interrupts = <0x00 0x90 0x01>; | |
| compatible = "qcom,smsm"; | |
| qcom,smsm-edge = <0x06>; | |
| qcom,smsm-irq-offset = <0x00>; | |
| qcom,smsm-irq-bitmask = <0x80000>; | |
| }; | |
| qcom,smd-rpm { | |
| interrupts = <0x00 0xa8 0x01>; | |
| label = "rpm"; | |
| compatible = "qcom,smd"; | |
| qcom,not-loadable; | |
| qcom,smd-irq-offset = <0x00>; | |
| qcom,smd-irq-bitmask = <0x01>; | |
| qcom,smd-edge = <0x0f>; | |
| qcom,irq-no-suspend; | |
| }; | |
| qcom,smd-adsp { | |
| interrupts = <0x00 0x121 0x01>; | |
| label = "adsp"; | |
| compatible = "qcom,smd"; | |
| qcom,smd-irq-offset = <0x00>; | |
| qcom,smd-irq-bitmask = <0x100>; | |
| qcom,smd-edge = <0x01>; | |
| }; | |
| }; | |
| qcom,msm-hdmi-dba-codec-rx { | |
| compatible = "qcom,msm-hdmi-dba-codec-rx"; | |
| qcom,dba-bridge-chip = "adv7533"; | |
| phandle = <0x162>; | |
| linux,phandle = <0x162>; | |
| }; | |
| qcom,jpeg@1b1c000 { | |
| reg = <0x1b1c000 0x400 0x1b60000 0xc30>; | |
| qcom,msm-bus,vectors-KBps = <0x3e 0x200 0x00 0x00 0x3e 0x200 0xc3500 0xc3500>; | |
| interrupts = <0x00 0x3b 0x00>; | |
| qcom,vbif-reg-settings = <0xc0 0x10101000 0xb0 0x10100010>; | |
| reg-names = "jpeg_hw\0jpeg_vbif"; | |
| compatible = "qcom,jpeg"; | |
| clock-names = "core_clk\0iface_clk\0bus_clk0\0camss_top_ahb_clk\0camss_ahb_clk"; | |
| qcom,msm-bus,name = "msm_camera_jpeg0"; | |
| interrupt-names = "jpeg"; | |
| clocks = <0x37 0x1ed3f032 0x37 0x3bfa7603 0x37 0x3e278896 0x37 0x4e814a78 0x37 0x9894b414>; | |
| cell-index = <0x00>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| status = "ok"; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,vdd-names = "vdd"; | |
| qcom,qos-reg-settings = <0x28 0x555e 0xc8 0x5555>; | |
| vdd-supply = <0x177>; | |
| qcom,clock-rates = <0xfe50fb0 0x00 0x00 0x00 0x00>; | |
| }; | |
| qcom,msm-pcm-loopback { | |
| compatible = "qcom,msm-pcm-loopback"; | |
| phandle = <0x13d>; | |
| linux,phandle = <0x13d>; | |
| }; | |
| qcom,wcnss-wlan@0a000000 { | |
| reg = <0xa000000 0x280000 0xb011008 0x04 0xa21b000 0x3000 0x3204000 0x100 0x3200800 0x200 0xa100400 0x200 0xa205050 0x200 0xa219000 0x20 0xa080488 0x08 0xa080fb0 0x08 0xa08040c 0x08 0xa0120a8 0x08 0xa012448 0x08 0xa080c00 0x01>; | |
| interrupts = <0x00 0x91 0x00 0x00 0x92 0x00>; | |
| qcom,pronto-vddpx-supply = <0xe8>; | |
| pinctrl-0 = <0xf8>; | |
| pinctrl-1 = <0xf9>; | |
| pinctrl-2 = <0xfa>; | |
| reg-names = "wcnss_mmio\0wcnss_fiq\0pronto_phy_base\0riva_phy_base\0riva_ccu_base\0pronto_a2xb_base\0pronto_ccpu_base\0pronto_saw2_base\0wlan_tx_phy_aborts\0wlan_brdg_err_source\0wlan_tx_status\0alarms_txctl\0alarms_tactl\0pronto_mcu_base"; | |
| qcom,vddcx-voltage-level = <0x100 0x00 0x180>; | |
| gpios = <0xbe 0x4c 0x00 0xbe 0x4d 0x00 0xbe 0x4e 0x00 0xbe 0x4f 0x00 0xbe 0x50 0x00>; | |
| qcom,has-pronto-hw; | |
| qcom,iris-vddrfa-supply = <0xf6>; | |
| qcom,pronto-vddmx-current = <0x00>; | |
| compatible = "qcom,wcnss_wlan"; | |
| clock-names = "xo\0rf_clk\0measure\0wcnss_debug"; | |
| qcom,pronto-vddmx-supply = <0xf1>; | |
| qcom,iris-vddxo-current = <0x2710>; | |
| qcom,iris-vddpa-voltage-level = <0x325aa0 0x00 0x325aa0>; | |
| qcom,wcnss-adc_tm = <0xfc>; | |
| qcom,iris-vddpa-current = <0x7dbb8>; | |
| qcom,vddpx-voltage-level = <0x1b7740 0x00 0x1b7740>; | |
| qcom,iris-vddxo-supply = <0xf5>; | |
| interrupt-names = "wcnss_wlantx_irq\0wcnss_wlanrx_irq"; | |
| qcom,iris-vdddig-voltage-level = <0x1b7740 0x00 0x1b7740>; | |
| qcom,iris-vddpa-supply = <0xf7>; | |
| clocks = <0x37 0x116b76f 0x37 0x24a30992 0xfb 0x8121ac15 0x37 0x709f430b>; | |
| qcom,iris-vddrfa-voltage-level = <0x13d620 0x00 0x13d620>; | |
| qcom,iris-vddxo-voltage-level = <0x1b7740 0x00 0x1b7740>; | |
| qcom,pronto-vddcx-supply = <0xee>; | |
| qcom,iris-vdddig-current = <0x2710>; | |
| qcom,iris-vddrfa-current = <0x186a0>; | |
| qcom,vddmx-voltage-level = <0x180 0x00 0x180>; | |
| qcom,pronto-vddcx-current = <0x00>; | |
| qcom,has-autodetect-xo; | |
| qcom,has-vsys-adc-channel; | |
| qcom,iris-vdddig-supply = <0xe8>; | |
| qcom,is-pronto-v3; | |
| pinctrl-names = "wcnss_default\0wcnss_sleep\0wcnss_gpio_default"; | |
| qcom,has-a2xb-split-reg; | |
| qcom,pronto-vddpx-current = <0x00>; | |
| }; | |
| qcom,msm-thermal { | |
| qcom,disable-vdd-mx; | |
| qcom,core-temp-hysteresis = <0x0a>; | |
| qcom,disable-gfx-phase-ctrl; | |
| qcom,hotplug-temp = <0x69>; | |
| qcom,freq-mitigation-value = <0xfd200>; | |
| qcom,poll-ms = <0xfa>; | |
| qcom,temp-hysteresis = <0x0a>; | |
| qcom,core-limit-temp = <0x50>; | |
| compatible = "qcom,msm-thermal"; | |
| vdd-dig-supply = <0xc7>; | |
| qcom,vdd-restriction-temp = <0x05>; | |
| qcom,disable-cx-phase-ctrl; | |
| vdd-gfx-supply = <0xc8>; | |
| qcom,therm-reset-temp = <0x73>; | |
| qcom,disable-ocr; | |
| qcom,disable-psm; | |
| qcom,synchronous-cluster-map = <0x00 0x04 0x02 0x03 0x04 0x05 0x01 0x04 0x06 0x07 0x08 0x09>; | |
| qcom,freq-mitigation-temp = <0x69>; | |
| qcom,online-hotplug-core; | |
| qcom,freq-step = <0x02>; | |
| qcom,freq-mitigation-temp-hysteresis = <0x0f>; | |
| qcom,hotplug-temp-hysteresis = <0x0f>; | |
| qcom,sensor-id = <0x09>; | |
| qcom,limit-temp = <0x3c>; | |
| qcom,synchronous-cluster-id = <0x00 0x01>; | |
| qcom,vdd-restriction-temp-hysteresis = <0x0a>; | |
| qcom,vdd-apps-rstr { | |
| qcom,vdd-rstr-reg = "vdd-apps"; | |
| qcom,freq-req; | |
| qcom,levels = <0x19c800>; | |
| phandle = <0xc9>; | |
| linux,phandle = <0xc9>; | |
| }; | |
| qcom,vdd-gfx-rstr { | |
| qcom,vdd-rstr-reg = "vdd-gfx"; | |
| qcom,levels = <0x05 0x07 0x07>; | |
| qcom,min-level = <0x01>; | |
| }; | |
| qcom,vdd-dig-rstr { | |
| qcom,vdd-rstr-reg = "vdd-dig"; | |
| qcom,levels = <0x100 0x200 0x200>; | |
| qcom,min-level = <0x00>; | |
| }; | |
| }; | |
| clock-controller@b0a8000 { | |
| reg = <0xb0a8000 0x1000>; | |
| compatible = "qcom,arm-cortex-acc"; | |
| phandle = <0x20>; | |
| linux,phandle = <0x20>; | |
| }; | |
| clock-controller@b0b8000 { | |
| reg = <0xb0b8000 0x1000>; | |
| compatible = "qcom,arm-cortex-acc"; | |
| phandle = <0x23>; | |
| linux,phandle = <0x23>; | |
| }; | |
| qcom,vfe0@1b10000 { | |
| reg = <0x1b10000 0x1000 0x1b40000 0x200>; | |
| interrupts = <0x00 0x39 0x00>; | |
| reg-names = "vfe\0vfe_vbif"; | |
| ds-regs = <0x988 0x98c 0x990 0x994 0x998 0x99c 0x9a0 0x9a4 0x9a8 0x9ac 0x9b0 0x9b4 0x9b8 0x9bc 0x9c0 0x9c4 0x9c8>; | |
| compatible = "qcom,vfe40"; | |
| clock-names = "camss_top_ahb_clk\0camss_ahb_clk\0vfe_clk_src\0camss_vfe_vfe_clk\0camss_csi_vfe_clk\0iface_clk\0bus_clk\0iface_ahb_clk"; | |
| max-clk-turbo = <0x1bb75640>; | |
| interrupt-names = "vfe"; | |
| vbif-settings = <0x03>; | |
| max-clk-nominal = <0x1bb75640>; | |
| clocks = <0x37 0x4e814a78 0x37 0x9894b414 0x37 0xa0c2bd8f 0x37 0xaaa3cd97 0x37 0xcc73453c 0x37 0x4050f47a 0x37 0x77fe2384 0x37 0x3c0a858f>; | |
| vbif-entries = <0x01>; | |
| vbif-regs = <0x124>; | |
| ds-settings = <0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0x110>; | |
| cell-index = <0x00>; | |
| qos-settings = <0xaa55aa55 0xaa55aa55 0xaa55aa55 0xaa55aa55 0xaa55aa55 0xaa55aa55 0xaa55aa55 0xaa55aa55>; | |
| ds-entries = <0x11>; | |
| vdd-supply = <0x174>; | |
| qos-entries = <0x08>; | |
| qos-regs = <0x2c4 0x2c8 0x2cc 0x2d0 0x2d4 0x2d8 0x2dc 0x2e0>; | |
| qcom,clock-rates = <0x00 0x00 0xfe50fb0 0x00 0x00 0x00 0x00 0x00>; | |
| }; | |
| qcom,gcc-gfx@1800000 { | |
| reg = <0x1800000 0x80000>; | |
| #clock-cells = <0x01>; | |
| reg-names = "cc_base"; | |
| compatible = "qcom,gcc-gfx-sdm450"; | |
| phandle = <0x38>; | |
| qcom,gfxfreq-corner = <0x00 0x00 0x7f27450 0x01 0xcdfe600 0x02 0x1312d000 0x03 0x17d78400 0x04 0x1e65fb80 0x05 0x2160ec00 0x06 0x23c34600 0x07>; | |
| linux,phandle = <0x38>; | |
| vdd_gfx-supply = <0xc8>; | |
| }; | |
| clock-controller@b1a8000 { | |
| reg = <0xb1a8000 0x1000>; | |
| compatible = "qcom,arm-cortex-acc"; | |
| phandle = <0x12>; | |
| linux,phandle = <0x12>; | |
| }; | |
| clock-controller@b1b8000 { | |
| reg = <0xb1b8000 0x1000>; | |
| compatible = "qcom,arm-cortex-acc"; | |
| phandle = <0x15>; | |
| linux,phandle = <0x15>; | |
| }; | |
| qcom,iommu-domains { | |
| compatible = "qcom,iommu-domains"; | |
| qcom,iommu-domain2 { | |
| label = "venus_ns"; | |
| qcom,virtual-addr-pool = <0x5dc00000 0x7f000000 0xdcc00000 0x1000000>; | |
| phandle = <0xba>; | |
| qcom,iommu-contexts = <0xb4>; | |
| linux,phandle = <0xba>; | |
| }; | |
| qcom,iommu-domain3 { | |
| label = "venus_sec_bitstream"; | |
| qcom,secure-domain; | |
| qcom,virtual-addr-pool = <0x4b000000 0x12c00000>; | |
| phandle = <0xbb>; | |
| qcom,iommu-contexts = <0xb5>; | |
| linux,phandle = <0xbb>; | |
| }; | |
| qcom,iommu-domain4 { | |
| label = "venus_sec_pixel"; | |
| qcom,secure-domain; | |
| qcom,virtual-addr-pool = <0x25800000 0x25800000>; | |
| phandle = <0xbc>; | |
| qcom,iommu-contexts = <0xb6>; | |
| linux,phandle = <0xbc>; | |
| }; | |
| qcom,iommu-domain5 { | |
| label = "venus_sec_non_pixel"; | |
| qcom,secure-domain; | |
| qcom,virtual-addr-pool = <0x1000000 0x24800000>; | |
| phandle = <0xbd>; | |
| qcom,iommu-contexts = <0xb7>; | |
| linux,phandle = <0xbd>; | |
| }; | |
| }; | |
| telpo_gpio_custom { | |
| telpo,relay-on = <0xbe 0x2d 0x00>; | |
| telpo,wiegand-d0 = <0xbe 0x2a 0x00>; | |
| telpo,wiegand-d1 = <0xbe 0x2b 0x00>; | |
| pinctrl-0 = <0x1a2>; | |
| pinctrl-1 = <0x1a3>; | |
| compatible = "telpo-gpio"; | |
| telpo,relay2-on = <0xbe 0x87 0x00>; | |
| telpo,ucam-pwr = <0xbe 0x0b 0x00>; | |
| telpo,otg-en = <0xbe 0x30 0x00>; | |
| telpo,ir-ctrl = <0xbe 0x88 0x00>; | |
| telpo,rs485-ctrl = <0xbe 0x00 0x00>; | |
| telpo,unlock = <0xbe 0x5a 0x00>; | |
| telpo,flash-d0 = <0xbe 0x01 0x00>; | |
| telpo,flash-d1 = <0xbe 0x03 0x00>; | |
| telpo,flash-d2 = <0xbe 0x18 0x00>; | |
| telpo,flash-d3 = <0xbe 0x1f 0x00>; | |
| telpo,flash-d4 = <0xbe 0x20 0x00>; | |
| telpo,flash-en = <0xbe 0x02 0x00>; | |
| lan3v3-supply = <0x183>; | |
| pinctrl-names = "telpo_gpio_custom_active\0telpo_gpio_custom_suspend"; | |
| }; | |
| dcc@b3000 { | |
| reg = <0xb3000 0x1000 0xb4000 0x800>; | |
| reg-names = "dcc-base\0dcc-ram-base"; | |
| compatible = "qcom,dcc"; | |
| clock-names = "dcc_clk"; | |
| qcom,save-reg; | |
| clocks = <0x37 0xd1000c50>; | |
| }; | |
| qcom,spmi@200f000 { | |
| reg = <0x200f000 0x1000 0x2400000 0x800000 0x2c00000 0x800000 0x3800000 0x200000 0x200a000 0x2100>; | |
| interrupts = <0x00 0xbe 0x00>; | |
| qcom,pmic-arb-channel = <0x00>; | |
| reg-names = "core\0chnls\0obsrvr\0intr\0cnfg"; | |
| compatible = "qcom,spmi-pmic-arb"; | |
| qcom,pmic-arb-max-peripherals = <0x100>; | |
| #interrupt-cells = <0x03>; | |
| qcom,pmic-arb-max-periph-interrupts = <0x100>; | |
| cell-index = <0x00>; | |
| #address-cells = <0x01>; | |
| phandle = <0x113>; | |
| qcom,pmic-arb-ee = <0x00>; | |
| interrupt-controller; | |
| #size-cells = <0x00>; | |
| linux,phandle = <0x113>; | |
| qcom,pm8953@0 { | |
| reg = <0x00>; | |
| spmi-slave-container; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| mpps { | |
| #gpio-cells = <0x02>; | |
| label = "pm8953-mpp"; | |
| compatible = "qcom,qpnp-pin"; | |
| #address-cells = <0x01>; | |
| spmi-dev-container; | |
| phandle = <0x191>; | |
| #size-cells = <0x01>; | |
| gpio-controller; | |
| linux,phandle = <0x191>; | |
| mpp@a000 { | |
| reg = <0xa000 0x100>; | |
| qcom,pin-num = <0x01>; | |
| status = "disabled"; | |
| }; | |
| mpp@a100 { | |
| reg = <0xa100 0x100>; | |
| qcom,pin-num = <0x02>; | |
| qcom,ain-route = <0x03>; | |
| qcom,mode = <0x04>; | |
| qcom,src-sel = <0x00>; | |
| qcom,invert = <0x00>; | |
| qcom,master-en = <0x01>; | |
| }; | |
| mpp@a200 { | |
| reg = <0xa200 0x100>; | |
| qcom,pin-num = <0x03>; | |
| status = "disabled"; | |
| }; | |
| mpp@a300 { | |
| reg = <0xa300 0x100>; | |
| qcom,pin-num = <0x04>; | |
| qcom,mode = <0x01>; | |
| qcom,src-sel = <0x05>; | |
| status = "okay"; | |
| qcom,invert = <0x00>; | |
| qcom,master-en = <0x01>; | |
| qcom,vin-sel = <0x03>; | |
| }; | |
| }; | |
| gpios { | |
| #gpio-cells = <0x02>; | |
| label = "pm8953-gpio"; | |
| compatible = "qcom,qpnp-pin"; | |
| #address-cells = <0x01>; | |
| spmi-dev-container; | |
| phandle = <0x12b>; | |
| #size-cells = <0x01>; | |
| gpio-controller; | |
| linux,phandle = <0x12b>; | |
| gpio@c000 { | |
| reg = <0xc000 0x100>; | |
| qcom,pin-num = <0x01>; | |
| qcom,mode = <0x01>; | |
| qcom,pull = <0x05>; | |
| qcom,src-sel = <0x02>; | |
| status = "ok"; | |
| qcom,master-en = <0x01>; | |
| qcom,vin-sel = <0x00>; | |
| qcom,out-strength = <0x02>; | |
| }; | |
| gpio@c100 { | |
| reg = <0xc100 0x100>; | |
| qcom,pin-num = <0x02>; | |
| qcom,output-type = <0x00>; | |
| qcom,mode = <0x00>; | |
| qcom,pull = <0x00>; | |
| qcom,src-sel = <0x00>; | |
| status = "okay"; | |
| qcom,master-en = <0x01>; | |
| qcom,vin-sel = <0x02>; | |
| qcom,out-strength = <0x03>; | |
| }; | |
| gpio@c200 { | |
| reg = <0xc200 0x100>; | |
| qcom,pin-num = <0x03>; | |
| status = "disabled"; | |
| }; | |
| gpio@c300 { | |
| reg = <0xc300 0x100>; | |
| qcom,pin-num = <0x04>; | |
| status = "disabled"; | |
| }; | |
| gpio@c400 { | |
| reg = <0xc400 0x100>; | |
| qcom,pin-num = <0x05>; | |
| status = "disabled"; | |
| }; | |
| gpio@c500 { | |
| reg = <0xc500 0x100>; | |
| qcom,pin-num = <0x06>; | |
| status = "disabled"; | |
| }; | |
| gpio@c600 { | |
| reg = <0xc600 0x100>; | |
| qcom,pin-num = <0x07>; | |
| qcom,mode = <0x00>; | |
| qcom,pull = <0x05>; | |
| qcom,src-sel = <0x00>; | |
| qcom,invert = <0x00>; | |
| qcom,master-en = <0x01>; | |
| qcom,vin-sel = <0x03>; | |
| qcom,out-strength = <0x01>; | |
| }; | |
| gpio@c700 { | |
| reg = <0xc700 0x100>; | |
| qcom,pin-num = <0x08>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| qcom,pm8953_typec@bf00 { | |
| reg = <0xbf00 0x100>; | |
| interrupts = <0x00 0xbf 0x00 0x00 0xbf 0x01 0x00 0xbf 0x02 0x00 0xbf 0x03 0x00 0xbf 0x04 0x00 0xbf 0x06 0x00 0xbf 0x07>; | |
| pinctrl-0 = <0x112>; | |
| compatible = "qcom,qpnp-typec"; | |
| ss-mux-supply = <0xed>; | |
| interrupt-names = "vrd-change\0ufp-detect\0ufp-detach\0dfp-detect\0dfp-detach\0vbus-err\0vconn-oc"; | |
| qcom,ssmux-gpio = <0xbe 0x8b 0x01>; | |
| pinctrl-names = "default"; | |
| }; | |
| qcom,power-on@800 { | |
| qcom,system-reset; | |
| reg = <0x800 0x100>; | |
| interrupts = <0x00 0x08 0x00 0x00 0x08 0x01 0x00 0x08 0x04 0x00 0x08 0x05>; | |
| compatible = "qcom,qpnp-power-on"; | |
| interrupt-names = "kpdpwr\0resin\0resin-bark\0kpdpwr-resin-bark"; | |
| qcom,clear-warm-reset; | |
| qcom,pon-dbc-delay = <0x3d09>; | |
| qcom,pon_1 { | |
| qcom,pull-up = <0x01>; | |
| qcom,s1-timer = <0x1a40>; | |
| qcom,pon-type = <0x00>; | |
| qcom,s2-timer = <0x3e8>; | |
| qcom,support-reset = <0x01>; | |
| linux,code = <0x74>; | |
| qcom,s2-type = <0x04>; | |
| }; | |
| qcom,pon_2 { | |
| qcom,pull-up = <0x01>; | |
| qcom,pon-type = <0x01>; | |
| linux,code = <0x72>; | |
| }; | |
| }; | |
| vadc@3100 { | |
| reg = <0x3100 0x100>; | |
| interrupts = <0x00 0x31 0x00>; | |
| compatible = "qcom,qpnp-vadc"; | |
| interrupt-names = "eoc-int-en-set"; | |
| qcom,adc-bit-resolution = <0x0f>; | |
| qcom,vadc-poll-eoc; | |
| #address-cells = <0x01>; | |
| phandle = <0x111>; | |
| #size-cells = <0x00>; | |
| qcom,adc-vdd-reference = <0x708>; | |
| linux,phandle = <0x111>; | |
| chan@5 { | |
| reg = <0x05>; | |
| label = "vcoin"; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x01>; | |
| qcom,scale-function = <0x00>; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,decimation = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| }; | |
| chan@7 { | |
| reg = <0x07>; | |
| label = "vph_pwr"; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x01>; | |
| qcom,scale-function = <0x00>; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,decimation = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| }; | |
| chan@8 { | |
| reg = <0x08>; | |
| label = "die_temp"; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| qcom,scale-function = <0x03>; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,decimation = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| }; | |
| chan@9 { | |
| reg = <0x09>; | |
| label = "ref_625mv"; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| qcom,scale-function = <0x00>; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,decimation = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| }; | |
| chan@a { | |
| reg = <0x0a>; | |
| label = "ref_1250v"; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| qcom,scale-function = <0x00>; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,decimation = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| }; | |
| chan@c { | |
| reg = <0x0c>; | |
| label = "ref_buf_625mv"; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| qcom,scale-function = <0x00>; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,decimation = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| }; | |
| chan@11 { | |
| reg = <0x11>; | |
| label = "pa_therm1"; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,vadc-thermal-node; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| qcom,scale-function = <0x02>; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,decimation = <0x00>; | |
| qcom,calibration-type = "ratiometric"; | |
| }; | |
| chan@13 { | |
| reg = <0x13>; | |
| label = "case_therm"; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,vadc-thermal-node; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| qcom,scale-function = <0x02>; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,decimation = <0x00>; | |
| qcom,calibration-type = "ratiometric"; | |
| }; | |
| chan@21 { | |
| reg = <0x21>; | |
| label = "mpp2"; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x01>; | |
| qcom,scale-function = <0x00>; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,decimation = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| }; | |
| chan@32 { | |
| reg = <0x32>; | |
| label = "xo_therm"; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,vadc-thermal-node; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| qcom,scale-function = <0x04>; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,decimation = <0x00>; | |
| qcom,calibration-type = "ratiometric"; | |
| }; | |
| chan@36 { | |
| reg = <0x36>; | |
| label = "pa_therm0"; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| qcom,scale-function = <0x02>; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,decimation = <0x00>; | |
| qcom,calibration-type = "ratiometric"; | |
| }; | |
| chan@3c { | |
| reg = <0x3c>; | |
| label = "xo_therm_buf"; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,vadc-thermal-node; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| qcom,scale-function = <0x04>; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,decimation = <0x00>; | |
| qcom,calibration-type = "ratiometric"; | |
| }; | |
| }; | |
| vadc@3400 { | |
| reg = <0x3400 0x100>; | |
| interrupts = <0x00 0x34 0x00 0x00 0x34 0x03 0x00 0x34 0x04>; | |
| compatible = "qcom,qpnp-adc-tm"; | |
| qcom,adc_tm-vadc = <0x111>; | |
| interrupt-names = "eoc-int-en-set\0high-thr-en-set\0low-thr-en-set"; | |
| qcom,adc-bit-resolution = <0x0f>; | |
| #address-cells = <0x01>; | |
| phandle = <0xfc>; | |
| #size-cells = <0x00>; | |
| qcom,adc-vdd-reference = <0x708>; | |
| linux,phandle = <0xfc>; | |
| chan@7 { | |
| reg = <0x07>; | |
| label = "vph_pwr"; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x01>; | |
| qcom,scale-function = <0x00>; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,decimation = <0x00>; | |
| qcom,btm-channel-number = <0x68>; | |
| qcom,calibration-type = "absolute"; | |
| }; | |
| chan@36 { | |
| reg = <0x36>; | |
| label = "pa_therm0"; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| qcom,scale-function = <0x02>; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,decimation = <0x00>; | |
| qcom,btm-channel-number = <0x48>; | |
| qcom,thermal-node; | |
| qcom,calibration-type = "ratiometric"; | |
| }; | |
| }; | |
| qcom,revid@100 { | |
| reg = <0x100 0x100>; | |
| compatible = "qcom,qpnp-revid"; | |
| }; | |
| qcom,pm8953_rtc { | |
| compatible = "qcom,qpnp-rtc"; | |
| #address-cells = <0x01>; | |
| spmi-dev-container; | |
| qcom,qpnp-rtc-alarm-pwrup = <0x00>; | |
| #size-cells = <0x01>; | |
| qcom,qpnp-rtc-write = <0x00>; | |
| qcom,pm8953_rtc_alarm@6100 { | |
| reg = <0x6100 0x100>; | |
| interrupts = <0x00 0x61 0x01>; | |
| }; | |
| qcom,pm8953_rtc_rw@6000 { | |
| reg = <0x6000 0x100>; | |
| }; | |
| }; | |
| qcom,temp-alarm@2400 { | |
| reg = <0x2400 0x100>; | |
| interrupts = <0x00 0x24 0x00>; | |
| label = "pm8953_tz"; | |
| compatible = "qcom,qpnp-temp-alarm"; | |
| qcom,temp_alarm-vadc = <0x111>; | |
| qcom,channel-num = <0x08>; | |
| qcom,threshold-set = <0x00>; | |
| }; | |
| qcom,coincell@2800 { | |
| reg = <0x2800 0x100>; | |
| compatible = "qcom,qpnp-coincell"; | |
| }; | |
| }; | |
| qcom,pm8953@1 { | |
| reg = <0x01>; | |
| spmi-slave-container; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| spm-regulator@2000 { | |
| reg = <0x2000 0x100>; | |
| regulator-name = "pm8953_s5"; | |
| compatible = "qcom,spm-regulator"; | |
| regulator-min-microvolt = <0x61a80>; | |
| regulator-max-microvolt = <0x116520>; | |
| phandle = <0x127>; | |
| linux,phandle = <0x127>; | |
| avs-limit-regulator { | |
| regulator-name = "pm8953_s5_avs_limit"; | |
| regulator-min-microvolt = <0x61a80>; | |
| regulator-max-microvolt = <0x116520>; | |
| phandle = <0x128>; | |
| linux,phandle = <0x128>; | |
| }; | |
| }; | |
| pwm@bc00 { | |
| reg = <0xbc00 0x100>; | |
| qcom,dtest-line = <0x02>; | |
| reg-names = "qpnp-lpg-channel-base"; | |
| compatible = "qcom,qpnp-pwm"; | |
| #pwm-cells = <0x02>; | |
| qcom,supported-sizes = <0x06 0x09>; | |
| qcom,dtest-output = <0x02>; | |
| qcom,channel-owner = "lcd_bl"; | |
| status = "okay"; | |
| qcom,channel-id = <0x00>; | |
| }; | |
| 8953_wcd_codec@f000 { | |
| reg = <0xf000 0x100>; | |
| interrupts = <0x01 0xf0 0x00 0x01 0xf0 0x01 0x01 0xf0 0x02 0x01 0xf0 0x03 0x01 0xf0 0x04 0x01 0xf0 0x05 0x01 0xf0 0x06 0x01 0xf0 0x07>; | |
| qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias"; | |
| qcom,dig-cdc-base-addr = <0xc0f0000>; | |
| compatible = "qcom,msm8x16_wcd_codec"; | |
| qcom,cdc-vdd-mic-bias-current = <0x1388>; | |
| interrupt-names = "spk_cnp_int\0spk_clip_int\0spk_ocp_int\0ins_rem_det1\0but_rel_det\0but_press_det\0ins_rem_det\0mbhc_int"; | |
| qcom,cdc-vdda-cp-voltage = <0x1cfde0 0x1f47d0>; | |
| cdc-vdd-pa-supply = <0x114>; | |
| qcom,cdc-vdd-pa-voltage = <0x1cfde0 0x1f47d0>; | |
| cdc-vdd-mic-bias-supply = <0xed>; | |
| qcom,cdc-vdd-io-voltage = <0x1b7740 0x1b7740>; | |
| status = "okay"; | |
| qcom,cdc-vdda-cp-current = <0x7a120>; | |
| cdc-vdd-io-supply = <0xe8>; | |
| qcom,cdc-static-supplies = "cdc-vdd-io\0cdc-vdd-pa\0cdc-vdda-cp"; | |
| cdc-vdda-cp-supply = <0x114>; | |
| qcom,cdc-vdd-pa-current = <0x3f7a0>; | |
| phandle = <0x161>; | |
| qcom,cdc-vdd-mic-bias-voltage = <0x2faf08 0x2faf08>; | |
| qcom,cdc-vdd-io-current = <0x1388>; | |
| qcom,cdc-mclk-clk-rate = <0x927c00>; | |
| linux,phandle = <0x161>; | |
| interrupt-parent = <0x113>; | |
| }; | |
| 8953_wcd_codec@f100 { | |
| reg = <0xf100 0x100>; | |
| interrupts = <0x01 0xf1 0x00 0x01 0xf1 0x01 0x01 0xf1 0x02 0x01 0xf1 0x03 0x01 0xf1 0x04 0x01 0xf1 0x05>; | |
| qcom,dig-cdc-base-addr = <0xc0f0000>; | |
| compatible = "qcom,msm8x16_wcd_codec"; | |
| interrupt-names = "ear_ocp_int\0hphr_ocp_int\0hphl_ocp_det\0ear_cnp_int\0hphr_cnp_int\0hphl_cnp_int"; | |
| status = "okay"; | |
| interrupt-parent = <0x113>; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-stub-codec { | |
| compatible = "qcom,msm-stub-codec"; | |
| phandle = <0x160>; | |
| linux,phandle = <0x160>; | |
| }; | |
| qcom,cpu-bwmon { | |
| reg = <0x408000 0x300 0x401000 0x200>; | |
| interrupts = <0x00 0xb7 0x04>; | |
| reg-names = "base\0global_base"; | |
| qcom,target-dev = <0xf3>; | |
| compatible = "qcom,bimc-bwmon2"; | |
| qcom,mport = <0x00>; | |
| }; | |
| qcom,mdss_mdp@1a00000 { | |
| reg = <0x1a00000 0x90000 0x1ab0000 0x1040>; | |
| qcom,msm-bus,vectors-KBps = <0x16 0x200 0x00 0x00 0x16 0x200 0x00 0x61a800 0x16 0x200 0x00 0x61a800>; | |
| interrupts = <0x00 0x48 0x00>; | |
| qcom,mdss-pipe-rgb-clk-ctrl-offsets = <0x2ac 0x04 0x08 0x2b4 0x04 0x08>; | |
| qcom,mdss-vbif-qos-rt-setting = <0x01 0x02 0x02 0x02>; | |
| qcom,mdss-pipe-cursor-off = <0x35000>; | |
| qcom,mdss-pipe-rgb-xin-id = <0x01 0x05>; | |
| reg-names = "mdp_phys\0vbif_phys"; | |
| qcom,mdss-pref-prim-intf = "dsi"; | |
| qcom,max-clk-rate = <0x17d78400>; | |
| qcom,mdss-dspp-off = <0x55000>; | |
| compatible = "qcom,mdss_mdp"; | |
| qcom,mdp-settings = <0x506c 0x00 0x1506c 0x00 0x1706c 0x00 0x2506c 0x00>; | |
| qcom,mdss-has-rotator-downscale; | |
| clock-names = "iface_clk\0bus_clk\0core_clk_src\0core_clk\0vsync_clk"; | |
| qcom,mdss-has-non-scalar-rgb; | |
| qcom,mdss-pipe-vig-xin-id = <0x00>; | |
| qcom,mdss-prefill-scaler-buffer-lines-bilinear = <0x02>; | |
| qcom,max-pipe-width = <0x800>; | |
| qcom,mdss-pipe-rgb-off = <0x15000 0x17000>; | |
| qcom,regs-dump-names-mdp = "MDP\0CTL_0\0CTL_1\0CTL_2\0VIG0_SSPP\0VIG0\0RGB0_SSPP\0RGB1_SSPP\0DMA0_SSPP\0CURSOR0_SSPP\0LAYER_0\0LAYER_1\0DSPP_0\0WB_0\0WB_2\0INTF_1\0INTF_2\0PP_0\0PP_1"; | |
| qcom,mdss-mixer-intf-off = <0x45000 0x46000>; | |
| qcom,mdss-pipe-dma-off = <0x25000>; | |
| qcom,msm-bus,name = "mdss_mdp"; | |
| qcom,mdss-wb-off = <0x65000 0x66000>; | |
| qcom,mdss-clk-factor = <0x69 0x64>; | |
| qcom,mdss-pipe-dma-xin-id = <0x02>; | |
| qcom,mdss-prefill-y-buffer-bytes = <0x00>; | |
| qcom,mdss-ib-factor = <0x01 0x01>; | |
| qcom,mdss-highest-bank-bit = <0x01>; | |
| qcom,mdss-slave-pingpong-off = "\0\a0"; | |
| qcom,mdss-cdm-off = <0x7a200>; | |
| qcom,mdss-pipe-cursor-xin-id = <0x07>; | |
| qcom,mdss-ppb-off = <0x330>; | |
| qcom,mdss-intf-off = <0x6b000 0x6b800 0x6c000>; | |
| clocks = <0x37 0xbfb92ed3 0x37 0x668f51de 0x37 0x6dc1f8f1 0x18e 0x588460a4 0x37 0x32a09f1f>; | |
| qcom,mdss-wfd-mode = "intf"; | |
| qcom,mdss-has-decimation; | |
| qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3a8 0x10 0x0f>; | |
| qcom,mdss-prefill-outstanding-buffer-bytes = <0x00>; | |
| qcom,mdss-vbif-qos-nrt-setting = <0x01 0x01 0x01 0x01>; | |
| qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x2ac 0x00 0x00>; | |
| qcom,max-bandwidth-low-kbps = <0x33e140>; | |
| qcom,mdss-prefill-post-scaler-buffer-pixels = <0x800>; | |
| qcom,vbif-settings = <0xd0 0x10>; | |
| qcom,mdss-ctl-off = <0x2000 0x2200 0x2400>; | |
| qcom,max-bandwidth-per-pipe-kbps = <0x231860>; | |
| qcom,mdss-prefill-pingpong-buffer-pixels = <0x1000>; | |
| qcom,mdss-has-pingpong-split; | |
| qcom,mdss-has-panic-ctrl; | |
| qcom,msm-bus,num-cases = <0x03>; | |
| qcom,mdss-default-ot-rd-limit = <0x20>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,mdss-prefill-scaler-buffer-lines-caf = <0x04>; | |
| qcom,mdss-default-ot-wr-limit = <0x10>; | |
| qcom,mdss-ab-factor = <0x01 0x01>; | |
| qcom,max-bw-settings = <0x01 0x33e140 0x02 0x2f4d60>; | |
| qcom,mdss-per-pipe-panic-luts = <0x0f 0xffff 0xfffc 0xff00>; | |
| phandle = <0x196>; | |
| qcom,mdss-mdp-reg-offset = <0x1000>; | |
| qcom,mdss-pipe-vig-off = <0x5000>; | |
| vdd-supply = <0x172>; | |
| qcom,mdss-idle-power-collapse-enabled; | |
| qcom,max-bandwidth-high-kbps = <0x33e140>; | |
| qcom,regs-dump-mdp = <0x1000 0x1454 0x2000 0x2064 0x2200 0x2264 0x2400 0x2464 0x5000 0x5150 0x5200 0x5230 0x15000 0x15150 0x17000 0x17150 0x25000 0x25150 0x35000 0x35150 0x45000 0x452bc 0x46000 0x462bc 0x55000 0x5522c 0x65000 0x652c0 0x66000 0x662c0 0x6b800 0x6ba68 0x6c000 0x6c268 0x71000 0x710d4 0x71800 0x718d4>; | |
| qcom,mdss-pingpong-off = <0x71000 0x71800>; | |
| qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2ac 0x08 0x0c>; | |
| qcom,max-mixer-width = <0x800>; | |
| linux,phandle = <0x196>; | |
| qcom,mdss-rot-block-size = <0x40>; | |
| qcom,mdss_fb_secondary { | |
| compatible = "qcom,mdss-fb"; | |
| cell-index = <0x02>; | |
| phandle = <0x195>; | |
| linux,phandle = <0x195>; | |
| }; | |
| qcom,mdss-pp-offsets { | |
| qcom,mdss-sspp-rgb-pcc-off = <0x380>; | |
| qcom,mdss-sspp-mdss-igc-lut-off = <0x2000>; | |
| qcom,mdss-sspp-vig-pcc-off = <0x1780>; | |
| qcom,mdss-lm-pgc-off = <0x3c0>; | |
| qcom,mdss-dspp-pcc-off = <0x1700>; | |
| qcom,mdss-dspp-pgc-off = <0x17c0>; | |
| qcom,mdss-sspp-dma-pcc-off = <0x380>; | |
| }; | |
| qcom,mdss_dsi_ili9881d_720p_video { | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-name = "ili9881d 720p video mode dsi panel"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-controller = <0x190>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 96 00 02 10 00]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xff>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-h-front-porch = <0x28>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x01>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-panel-timings = <0x761a1000 0x3c40141c 0x12030400>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsi-panel-destination = "display_1"; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x14 0x01 0x78>; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-h-pulse-width = <0x14>; | |
| qcom,mdss-dsi-t-clk-post = <0x1e>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x1e1b0405 0x20304a0 0x1e1b0405 0x20304a0 0x1e1b0405 0x20304a0 0x1e1b0405 0x20304a0 0x1e1b0405 0x20304a0>; | |
| qcom,mdss-dsi-bl-pmic-bank-select = <0x00>; | |
| qcom,mdss-dsi-t-clk-pre = <0x38>; | |
| qcom,mdss-dsi-on-command = <0x39010000 0x4ff 0x98810339 0x1000000 0x20100 0x39010000 0x202 0x390100 0x100002 0x3723901 0x00 0x2040039 0x1000000 0x20500 0x39010000 0x206 0x9390100 0x02 0x7003901 0x00 0x2080039 0x1000000 0x20901 0x39010000 0x20a 0x390100 0x02 0xb003901 0x00 0x20c0139 0x1000000 0x20d00 0x39010000 0x20e 0x390100 0x02 0xf003901 0x00 0x2100039 0x1000000 0x21100 0x39010000 0x212 0x390100 0x02 0x13003901 0x00 0x2140039 0x1000000 0x21508 0x39010000 0x216 0x8390100 0x02 0x17003901 0x00 0x2180839 0x1000000 0x21900 0x39010000 0x21a 0x390100 0x02 0x1b003901 0x00 0x21c0039 0x1000000 0x21d00 0x39010000 0x21e 0x40390100 0x02 0x1f803901 0x00 0x2200539 0x1000000 0x22102 0x39010000 0x222 0x390100 0x02 0x23003901 0x00 0x2240039 0x1000000 0x22500 0x39010000 0x226 0x390100 0x02 0x27003901 0x00 0x2283339 0x1000000 0x22902 0x39010000 0x22a 0x390100 0x02 0x2b003901 0x00 0x22c0039 0x1000000 0x22d00 0x39010000 0x22e 0x390100 0x02 0x2f003901 0x00 0x2300039 0x1000000 0x23100 0x39010000 0x232 0x390100 0x02 0x33003901 0x00 0x2341439 0x1000000 0x23500 0x39010000 0x236 0x390100 0x02 0x37003901 0x00 0x2383c39 0x1000000 0x23935 0x39010000 0x23a 0x1390100 0x02 0x3b403901 0x00 0x23c0039 0x1000000 0x23d01 0x39010000 0x23e 0x390100 0x02 0x3f003901 0x00 0x2400039 0x1000000 0x24188 0x39010000 0x242 0x390100 0x02 0x43003901 0x00 0x2441f39 0x1000000 0x25001 0x39010000 0x251 0x23390100 0x02 0x52453901 0x00 0x2536739 0x1000000 0x25489 0x39010000 0x255 0xab390100 0x02 0x56013901 0x00 0x2572339 0x1000000 0x25845 0x39010000 0x259 0x67390100 0x02 0x5a893901 0x00 0x25bab39 0x1000000 0x25ccd 0x39010000 0x25d 0xef390100 0x02 0x5e113901 0x00 0x25f0139 0x1000000 0x26000 0x39010000 0x261 0x15390100 0x02 0x62143901 0x00 0x2630e39 0x1000000 0x2640f 0x39010000 0x265 0xc390100 0x02 0x660d3901 0x00 0x2670639 0x1000000 0x26802 0x39010000 0x269 0x2390100 0x02 0x6a023901 0x00 0x26b0239 0x1000000 0x26c02 0x39010000 0x26d 0x2390100 0x02 0x6e073901 0x00 0x26f0239 0x1000000 0x27002 0x39010000 0x271 0x2390100 0x02 0x72023901 0x00 0x2730239 0x1000000 0x27402 0x39010000 0x275 0x1390100 0x02 0x76003901 0x00 0x2771439 0x1000000 0x27815 0x39010000 0x279 0xe390100 0x02 0x7a0f3901 0x00 0x27b0c39 0x1000000 0x27c0d 0x39010000 0x27d 0x6390100 0x02 0x7e023901 0x00 0x27f0239 0x1000000 0x28002 0x39010000 0x281 0x2390100 0x02 0x82023901 0x00 0x2830239 0x1000000 0x28407 0x39010000 0x285 0x2390100 0x02 0x86023901 0x00 0x2870239 0x1000000 0x28802 0x39010000 0x289 0x2390100 0x02 0x8a023901 0x00 0x4ff9881 0x4390100 0x02 0x70003901 0x00 0x2710039 0x1000000 0x266fe 0x39010000 0x282 0xf390100 0x02 0x840f3901 0x00 0x2850d39 0x1000000 0x23a24 0x39010000 0x232 0xac390100 0x02 0x8c803901 0x00 0x23cf539 0x1000000 0x2b502 0x39010000 0x231 0x25390100 0x02 0x88333901 0x00 0x4ff9881 0x1390100 0x02 0x220a3901 0x00 0x2310039 0x1000000 0x25393 0x39010000 0x255 0x95390100 0x02 0x506b3901 0x00 0x2516b39 0x1000000 0x26020 0x39010000 0x261 0x390100 0x02 0x620d3901 0x00 0x2630039 0x1000000 0x4ff98 0x81013901 0x00 0x2a00039 0x1000000 0x2a116 0x39010000 0x2a2 0x23390100 0x02 0xa3143901 0x00 0x2a41b39 0x1000000 0x2a52d 0x39010000 0x2a6 0x1f390100 0x02 0xa7213901 0x00 0x2a87b39 0x1000000 0x2a91b 0x39010000 0x2aa 0x27390100 0x02 0xab693901 0x00 0x2ac1a39 0x1000000 0x2ad19 0x39010000 0x2ae 0x4c390100 0x02 0xaf223901 0x00 0x2b02839 0x1000000 0x2b14d 0x39010000 0x2b2 0x5f390100 0x02 0xb3393901 0x00 0x2c00039 0x1000000 0x2c116 0x39010000 0x2c2 0x23390100 0x02 0xc3143901 0x00 0x2c41b39 0x1000000 0x2c52d 0x39010000 0x2c6 0x1f390100 0x02 0xc7213901 0x00 0x2c87b39 0x1000000 0x2c91b 0x39010000 0x2ca 0x27390100 0x02 0xcb693901 0x00 0x2cc1a39 0x1000000 0x2cd19 0x39010000 0x2ce 0x4c390100 0x02 0xcf223901 0x00 0x2d02839 0x1000000 0x2d14d 0x39010000 0x2d2 0x5f390100 0x02 0xd3393901 0x00 0x4ff9881 0x390100 0x02 0x36030501 0x7800 0x2110005 0x100000a 0x22900>; | |
| qcom,mdss-dsi-v-front-porch = <0x18>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-bl-pmic-pwm-frequency = <0x1a>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-pwm-gpio = <0x191 0x04 0x00>; | |
| qcom,mdss-dsi-v-pulse-width = <0x04>; | |
| qcom,mdss-dsi-h-back-porch = <0x3c>; | |
| qcom,mdss-dsi-v-back-porch = <0x18>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,panel-supply-entries = <0x192>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| }; | |
| qcom,mdss_fb_wfd { | |
| compatible = "qcom,mdss-fb"; | |
| cell-index = <0x01>; | |
| phandle = <0x19c>; | |
| linux,phandle = <0x19c>; | |
| }; | |
| qcom,mdss_dsi_nt35532_1080p_video2 { | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-name = "nt35532 1080p video2 mode dsi panel"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-controller = <0x193>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xff>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x01>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-panel-timings = <0xee382600 0x6a6c2c3c 0x2c030400>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-panel-destination = "display_2"; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x02 0x01 0x14>; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-h-pulse-width = <0x14>; | |
| qcom,mdss-dsi-t-clk-post = <0x02>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241b0809 0x50304a0>; | |
| qcom,mdss-dsi-bl-pmic-bank-select = <0x00>; | |
| qcom,mdss-dsi-t-clk-pre = <0x2c>; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 01 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 59 15 01 00 00 00 00 02 04 0c 15 01 00 00 00 00 02 05 2b 15 01 00 00 00 00 02 06 64 15 01 00 00 00 00 02 07 c6 15 01 00 00 00 00 02 0d 89 15 01 00 00 00 00 02 0e 89 15 01 00 00 00 00 02 0f e0 15 01 00 00 00 00 02 10 03 15 01 00 00 00 00 02 11 5a 15 01 00 00 00 00 02 12 5a 15 01 00 00 00 00 02 13 85 15 01 00 00 00 00 02 14 85 15 01 00 00 00 00 02 15 60 15 01 00 00 00 00 02 16 13 15 01 00 00 00 00 02 17 13 15 01 00 00 00 00 02 1c a3 15 01 00 00 00 00 02 60 77 15 01 00 00 00 00 02 ff 01 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 75 00 15 01 00 00 00 00 02 76 77 15 01 00 00 00 00 02 77 00 15 01 00 00 00 00 02 78 78 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 7a a4 15 01 00 00 00 00 02 7b 00 15 01 00 00 00 00 02 7c c2 15 01 00 00 00 00 02 7d 00 15 01 00 00 00 00 02 7e d9 15 01 00 00 00 00 02 7f 00 15 01 00 00 00 00 02 80 ec 15 01 00 00 00 00 02 81 00 15 01 00 00 00 00 02 82 fd 15 01 00 00 00 00 02 83 01 15 01 00 00 00 00 02 84 0c 15 01 00 00 00 00 02 85 01 15 01 00 00 00 00 02 86 1a 15 01 00 00 00 00 02 87 01 15 01 00 00 00 00 02 88 47 15 01 00 00 00 00 02 89 01 15 01 00 00 00 00 02 8a 69 15 01 00 00 00 00 02 8b 01 15 01 00 00 00 00 02 8c a1 15 01 00 00 00 00 02 8d 01 15 01 00 00 00 00 02 8e cc 15 01 00 00 00 00 02 8f 02 15 01 00 00 00 00 02 90 0f 15 01 00 00 00 00 02 91 02 15 01 00 00 00 00 02 92 46 15 01 00 00 00 00 02 93 02 15 01 00 00 00 00 02 94 47 15 01 00 00 00 00 02 95 02 15 01 00 00 00 00 02 96 7a 15 01 00 00 00 00 02 97 02 15 01 00 00 00 00 02 98 b3 15 01 00 00 00 00 02 99 02 15 01 00 00 00 00 02 9a d7 15 01 00 00 00 00 02 9b 03 15 01 00 00 00 00 02 9c 07 15 01 00 00 00 00 02 9d 03 15 01 00 00 00 00 02 9e 26 15 01 00 00 00 00 02 9f 03 15 01 00 00 00 00 02 a0 4d 15 01 00 00 00 00 02 a2 03 15 01 00 00 00 00 02 a3 58 15 01 00 00 00 00 02 a4 03 15 01 00 00 00 00 02 a5 64 15 01 00 00 00 00 02 a6 03 15 01 00 00 00 00 02 a7 72 15 01 00 00 00 00 02 a9 03 15 01 00 00 00 00 02 aa 82 15 01 00 00 00 00 02 ab 03 15 01 00 00 00 00 02 ac 93 15 01 00 00 00 00 02 ad 03 15 01 00 00 00 00 02 ae a9 15 01 00 00 00 00 02 af 03 15 01 00 00 00 00 02 b0 c4 15 01 00 00 00 00 02 b1 03 15 01 00 00 00 00 02 b2 dc 15 01 00 00 00 00 02 b3 00 15 01 00 00 00 00 02 b4 18 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 74 15 01 00 00 00 00 02 b7 00 15 01 00 00 00 00 02 b8 a4 15 01 00 00 00 00 02 b9 00 15 01 00 00 00 00 02 ba c2 15 01 00 00 00 00 02 bb 00 15 01 00 00 00 00 02 bc d9 15 01 00 00 00 00 02 bd 00 15 01 00 00 00 00 02 be ec 15 01 00 00 00 00 02 bf 00 15 01 00 00 00 00 02 c0 fd 15 01 00 00 00 00 02 c1 01 15 01 00 00 00 00 02 c2 0c 15 01 00 00 00 00 02 c3 01 15 01 00 00 00 00 02 c4 1a 15 01 00 00 00 00 02 c5 01 15 01 00 00 00 00 02 c6 47 15 01 00 00 00 00 02 c7 01 15 01 00 00 00 00 02 c8 69 15 01 00 00 00 00 02 c9 01 15 01 00 00 00 00 02 ca a1 15 01 00 00 00 00 02 cb 01 15 01 00 00 00 00 02 cc cc 15 01 00 00 00 00 02 cd 02 15 01 00 00 00 00 02 ce 0f 15 01 00 00 00 00 02 cf 02 15 01 00 00 00 00 02 d0 46 15 01 00 00 00 00 02 d1 02 15 01 00 00 00 00 02 d2 47 15 01 00 00 00 00 02 d3 02 15 01 00 00 00 00 02 d4 7a 15 01 00 00 00 00 02 d5 02 15 01 00 00 00 00 02 d6 b3 15 01 00 00 00 00 02 d7 02 15 01 00 00 00 00 02 d8 d7 15 01 00 00 00 00 02 d9 03 15 01 00 00 00 00 02 da 07 15 01 00 00 00 00 02 db 03 15 01 00 00 00 00 02 dc 26 15 01 00 00 00 00 02 dd 03 15 01 00 00 00 00 02 de 4d 15 01 00 00 00 00 02 df 03 15 01 00 00 00 00 02 e0 58 15 01 00 00 00 00 02 e1 03 15 01 00 00 00 00 02 e2 64 15 01 00 00 00 00 02 e3 03 15 01 00 00 00 00 02 e4 72 15 01 00 00 00 00 02 e5 03 15 01 00 00 00 00 02 e6 82 15 01 00 00 00 00 02 e7 03 15 01 00 00 00 00 02 e8 93 15 01 00 00 00 00 02 e9 03 15 01 00 00 00 00 02 ea a9 15 01 00 00 00 00 02 eb 03 15 01 00 00 00 00 02 ec c4 15 01 00 00 00 00 02 ed 03 15 01 00 00 00 00 02 ee dc 15 01 00 00 00 00 02 ef 00 15 01 00 00 00 00 02 f0 77 15 01 00 00 00 00 02 f1 00 15 01 00 00 00 00 02 f2 78 15 01 00 00 00 00 02 f3 00 15 01 00 00 00 00 02 f4 a4 15 01 00 00 00 00 02 f5 00 15 01 00 00 00 00 02 f6 c2 15 01 00 00 00 00 02 f7 00 15 01 00 00 00 00 02 f8 d9 15 01 00 00 00 00 02 f9 00 15 01 00 00 00 00 02 fa ec 15 01 00 00 00 00 02 ff 02 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 00 15 01 00 00 00 00 02 01 fd 15 01 00 00 00 00 02 02 01 15 01 00 00 00 00 02 03 0c 15 01 00 00 00 00 02 04 01 15 01 00 00 00 00 02 05 1a 15 01 00 00 00 00 02 06 01 15 01 00 00 00 00 02 07 47 15 01 00 00 00 00 02 08 01 15 01 00 00 00 00 02 09 69 15 01 00 00 00 00 02 0a 01 15 01 00 00 00 00 02 0b a1 15 01 00 00 00 00 02 0c 01 15 01 00 00 00 00 02 0d cc 15 01 00 00 00 00 02 0e 02 15 01 00 00 00 00 02 0f 0f 15 01 00 00 00 00 02 10 02 15 01 00 00 00 00 02 11 46 15 01 00 00 00 00 02 12 02 15 01 00 00 00 00 02 13 47 15 01 00 00 00 00 02 14 02 15 01 00 00 00 00 02 15 7a 15 01 00 00 00 00 02 16 02 15 01 00 00 00 00 02 17 b3 15 01 00 00 00 00 02 18 02 15 01 00 00 00 00 02 19 d7 15 01 00 00 00 00 02 1a 03 15 01 00 00 00 00 02 1b 07 15 01 00 00 00 00 02 1c 03 15 01 00 00 00 00 02 1d 26 15 01 00 00 00 00 02 1e 03 15 01 00 00 00 00 02 1f 4d 15 01 00 00 00 00 02 20 03 15 01 00 00 00 00 02 21 58 15 01 00 00 00 00 02 22 03 15 01 00 00 00 00 02 23 64 15 01 00 00 00 00 02 24 03 15 01 00 00 00 00 02 25 72 15 01 00 00 00 00 02 26 03 15 01 00 00 00 00 02 27 82 15 01 00 00 00 00 02 28 03 15 01 00 00 00 00 02 29 93 15 01 00 00 00 00 02 2a 03 15 01 00 00 00 00 02 2b a9 15 01 00 00 00 00 02 2d 03 15 01 00 00 00 00 02 2f c4 15 01 00 00 00 00 02 30 03 15 01 00 00 00 00 02 31 dc 15 01 00 00 00 00 02 32 00 15 01 00 00 00 00 02 33 18 15 01 00 00 00 00 02 34 00 15 01 00 00 00 00 02 35 74 15 01 00 00 00 00 02 36 00 15 01 00 00 00 00 02 37 a4 15 01 00 00 00 00 02 38 00 15 01 00 00 00 00 02 39 c2 15 01 00 00 00 00 02 3a 00 15 01 00 00 00 00 02 3b d9 15 01 00 00 00 00 02 3d 00 15 01 00 00 00 00 02 3f ec 15 01 00 00 00 00 02 40 00 15 01 00 00 00 00 02 41 fd 15 01 00 00 00 00 02 42 01 15 01 00 00 00 00 02 43 0c 15 01 00 00 00 00 02 44 01 15 01 00 00 00 00 02 45 1a 15 01 00 00 00 00 02 46 01 15 01 00 00 00 00 02 47 47 15 01 00 00 00 00 02 48 01 15 01 00 00 00 00 02 49 69 15 01 00 00 00 00 02 4a 01 15 01 00 00 00 00 02 4b a1 15 01 00 00 00 00 02 4c 01 15 01 00 00 00 00 02 4d cc 15 01 00 00 00 00 02 4e 02 15 01 00 00 00 00 02 4f 0f 15 01 00 00 00 00 02 50 02 15 01 00 00 00 00 02 51 46 15 01 00 00 00 00 02 52 02 15 01 00 00 00 00 02 53 47 15 01 00 00 00 00 02 54 02 15 01 00 00 00 00 02 55 7a 15 01 00 00 00 00 02 56 02 15 01 00 00 00 00 02 58 b3 15 01 00 00 00 00 02 59 02 15 01 00 00 00 00 02 5a d7 15 01 00 00 00 00 02 5b 03 15 01 00 00 00 00 02 5c 07 15 01 00 00 00 00 02 5d 03 15 01 00 00 00 00 02 5e 26 15 01 00 00 00 00 02 5f 03 15 01 00 00 00 00 02 60 4d 15 01 00 00 00 00 02 61 03 15 01 00 00 00 00 02 62 58 15 01 00 00 00 00 02 63 03 15 01 00 00 00 00 02 64 64 15 01 00 00 00 00 02 65 03 15 01 00 00 00 00 02 66 72 15 01 00 00 00 00 02 67 03 15 01 00 00 00 00 02 68 82 15 01 00 00 00 00 02 69 03 15 01 00 00 00 00 02 6a 93 15 01 00 00 00 00 02 6b 03 15 01 00 00 00 00 02 6c a9 15 01 00 00 00 00 02 6d 03 15 01 00 00 00 00 02 6e c4 15 01 00 00 00 00 02 6f 03 15 01 00 00 00 00 02 70 dc 15 01 00 00 00 00 02 71 00 15 01 00 00 00 00 02 72 77 15 01 00 00 00 00 02 73 00 15 01 00 00 00 00 02 74 78 15 01 00 00 00 00 02 75 00 15 01 00 00 00 00 02 76 a4 15 01 00 00 00 00 02 77 00 15 01 00 00 00 00 02 78 c2 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 7a d9 15 01 00 00 00 00 02 7b 00 15 01 00 00 00 00 02 7c ec 15 01 00 00 00 00 02 7d 00 15 01 00 00 00 00 02 7e fd 15 01 00 00 00 00 02 7f 01 15 01 00 00 00 00 02 80 0c 15 01 00 00 00 00 02 81 01 15 01 00 00 00 00 02 82 1a 15 01 00 00 00 00 02 83 01 15 01 00 00 00 00 02 84 47 15 01 00 00 00 00 02 85 01 15 01 00 00 00 00 02 86 69 15 01 00 00 00 00 02 87 01 15 01 00 00 00 00 02 88 a1 15 01 00 00 00 00 02 89 01 15 01 00 00 00 00 02 8a cc 15 01 00 00 00 00 02 8b 02 15 01 00 00 00 00 02 8c 0f 15 01 00 00 00 00 02 8d 02 15 01 00 00 00 00 02 8e 46 15 01 00 00 00 00 02 8f 02 15 01 00 00 00 00 02 90 47 15 01 00 00 00 00 02 91 02 15 01 00 00 00 00 02 92 7a 15 01 00 00 00 00 02 93 02 15 01 00 00 00 00 02 94 b3 15 01 00 00 00 00 02 95 02 15 01 00 00 00 00 02 96 d7 15 01 00 00 00 00 02 97 03 15 01 00 00 00 00 02 98 07 15 01 00 00 00 00 02 99 03 15 01 00 00 00 00 02 9a 26 15 01 00 00 00 00 02 9b 03 15 01 00 00 00 00 02 9c 4d 15 01 00 00 00 00 02 9d 03 15 01 00 00 00 00 02 9e 58 15 01 00 00 00 00 02 9f 03 15 01 00 00 00 00 02 a0 64 15 01 00 00 00 00 02 a2 03 15 01 00 00 00 00 02 a3 72 15 01 00 00 00 00 02 a4 03 15 01 00 00 00 00 02 a5 82 15 01 00 00 00 00 02 a6 03 15 01 00 00 00 00 02 a7 93 15 01 00 00 00 00 02 a9 03 15 01 00 00 00 00 02 aa a9 15 01 00 00 00 00 02 ab 03 15 01 00 00 00 00 02 ac c4 15 01 00 00 00 00 02 ad 03 15 01 00 00 00 00 02 ae dc 15 01 00 00 00 00 02 af 00 15 01 00 00 00 00 02 b0 18 15 01 00 00 00 00 02 b1 00 15 01 00 00 00 00 02 b2 74 15 01 00 00 00 00 02 b3 00 15 01 00 00 00 00 02 b4 a4 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 c2 15 01 00 00 00 00 02 b7 00 15 01 00 00 00 00 02 b8 d9 15 01 00 00 00 00 02 b9 00 15 01 00 00 00 00 02 ba ec 15 01 00 00 00 00 02 bb 00 15 01 00 00 00 00 02 bc fd 15 01 00 00 00 00 02 bd 01 15 01 00 00 00 00 02 be 0c 15 01 00 00 00 00 02 bf 01 15 01 00 00 00 00 02 c0 1a 15 01 00 00 00 00 02 c1 01 15 01 00 00 00 00 02 c2 47 15 01 00 00 00 00 02 c3 01 15 01 00 00 00 00 02 c4 69 15 01 00 00 00 00 02 c5 01 15 01 00 00 00 00 02 c6 a1 15 01 00 00 00 00 02 c7 01 15 01 00 00 00 00 02 c8 cc 15 01 00 00 00 00 02 c9 02 15 01 00 00 00 00 02 ca 0f 15 01 00 00 00 00 02 cb 02 15 01 00 00 00 00 02 cc 46 15 01 00 00 00 00 02 cd 02 15 01 00 00 00 00 02 ce 47 15 01 00 00 00 00 02 cf 02 15 01 00 00 00 00 02 d0 7a 15 01 00 00 00 00 02 d1 02 15 01 00 00 00 00 02 d2 b3 15 01 00 00 00 00 02 d3 02 15 01 00 00 00 00 02 d4 d7 15 01 00 00 00 00 02 d5 03 15 01 00 00 00 00 02 d6 07 15 01 00 00 00 00 02 d7 03 15 01 00 00 00 00 02 d8 26 15 01 00 00 00 00 02 d9 03 15 01 00 00 00 00 02 da 4d 15 01 00 00 00 00 02 db 03 15 01 00 00 00 00 02 dc 58 15 01 00 00 00 00 02 dd 03 15 01 00 00 00 00 02 de 64 15 01 00 00 00 00 02 df 03 15 01 00 00 00 00 02 e0 72 15 01 00 00 00 00 02 e1 03 15 01 00 00 00 00 02 e2 82 15 01 00 00 00 00 02 e3 03 15 01 00 00 00 00 02 e4 93 15 01 00 00 00 00 02 e5 03 15 01 00 00 00 00 02 e6 a9 15 01 00 00 00 00 02 e7 03 15 01 00 00 00 00 02 e8 c4 15 01 00 00 00 00 02 e9 03 15 01 00 00 00 00 02 ea dc 15 01 00 00 00 00 02 ff 05 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 38 15 01 00 00 00 00 02 01 38 15 01 00 00 00 00 02 02 07 15 01 00 00 00 00 02 03 40 15 01 00 00 00 00 02 04 40 15 01 00 00 00 00 02 05 25 15 01 00 00 00 00 02 06 1d 15 01 00 00 00 00 02 07 23 15 01 00 00 00 00 02 08 1b 15 01 00 00 00 00 02 09 21 15 01 00 00 00 00 02 0a 19 15 01 00 00 00 00 02 0b 1f 15 01 00 00 00 00 02 0c 17 15 01 00 00 00 00 02 0d 05 15 01 00 00 00 00 02 0e 04 15 01 00 00 00 00 02 0f 0f 15 01 00 00 00 00 02 10 38 15 01 00 00 00 00 02 11 38 15 01 00 00 00 00 02 12 38 15 01 00 00 00 00 02 13 38 15 01 00 00 00 00 02 14 38 15 01 00 00 00 00 02 15 38 15 01 00 00 00 00 02 16 06 15 01 00 00 00 00 02 17 40 15 01 00 00 00 00 02 18 40 15 01 00 00 00 00 02 19 24 15 01 00 00 00 00 02 1a 1c 15 01 00 00 00 00 02 1b 22 15 01 00 00 00 00 02 1c 1a 15 01 00 00 00 00 02 1d 20 15 01 00 00 00 00 02 1e 18 15 01 00 00 00 00 02 1f 1e 15 01 00 00 00 00 02 20 16 15 01 00 00 00 00 02 21 05 15 01 00 00 00 00 02 22 04 15 01 00 00 00 00 02 23 0e 15 01 00 00 00 00 02 24 38 15 01 00 00 00 00 02 25 38 15 01 00 00 00 00 02 26 38 15 01 00 00 00 00 02 27 38 15 01 00 00 00 00 02 28 38 15 01 00 00 00 00 02 29 38 15 01 00 00 00 00 02 2a 0e 15 01 00 00 00 00 02 2b 40 15 01 00 00 00 00 02 2d 40 15 01 00 00 00 00 02 2f 16 15 01 00 00 00 00 02 30 1e 15 01 00 00 00 00 02 31 18 15 01 00 00 00 00 02 32 20 15 01 00 00 00 00 02 33 1a 15 01 00 00 00 00 02 34 22 15 01 00 00 00 00 02 35 1c 15 01 00 00 00 00 02 36 24 15 01 00 00 00 00 02 37 05 15 01 00 00 00 00 02 38 04 15 01 00 00 00 00 02 39 06 15 01 00 00 00 00 02 3a 38 15 01 00 00 00 00 02 3b 38 15 01 00 00 00 00 02 3d 38 15 01 00 00 00 00 02 3f 38 15 01 00 00 00 00 02 40 38 15 01 00 00 00 00 02 41 38 15 01 00 00 00 00 02 42 0f 15 01 00 00 00 00 02 43 40 15 01 00 00 00 00 02 44 40 15 01 00 00 00 00 02 45 17 15 01 00 00 00 00 02 46 1f 15 01 00 00 00 00 02 47 19 15 01 00 00 00 00 02 48 21 15 01 00 00 00 00 02 49 1b 15 01 00 00 00 00 02 4a 23 15 01 00 00 00 00 02 4b 1d 15 01 00 00 00 00 02 4c 25 15 01 00 00 00 00 02 4d 05 15 01 00 00 00 00 02 4e 04 15 01 00 00 00 00 02 4f 07 15 01 00 00 00 00 02 50 38 15 01 00 00 00 00 02 51 38 15 01 00 00 00 00 02 52 38 15 01 00 00 00 00 02 53 38 15 01 00 00 00 00 02 5b 0a 15 01 00 00 00 00 02 5c 0a 15 01 00 00 00 00 02 63 0a 15 01 00 00 00 00 02 64 15 15 01 00 00 00 00 02 68 24 15 01 00 00 00 00 02 69 24 15 01 00 00 00 00 02 90 7b 15 01 00 00 00 00 02 91 11 15 01 00 00 00 00 02 92 14 15 01 00 00 00 00 02 7e 10 15 01 00 00 00 00 02 7f 10 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 98 00 15 01 00 00 00 00 02 99 00 15 01 00 00 00 00 02 54 2e 15 01 00 00 00 00 02 59 38 15 01 00 00 00 00 02 5d 01 15 01 00 00 00 00 02 5e 27 15 01 00 00 00 00 02 62 39 15 01 00 00 00 00 02 66 88 15 01 00 00 00 00 02 67 11 15 01 00 00 00 00 02 6a 0e 15 01 00 00 00 00 02 6b 20 15 01 00 00 00 00 02 6c 08 15 01 00 00 00 00 02 6d 00 15 01 00 00 00 00 02 7d 01 15 01 00 00 00 00 02 b7 01 15 01 00 00 00 00 02 b8 0a 15 01 00 00 00 00 02 ba 13 15 01 00 00 00 00 02 bc 01 15 01 00 00 00 00 02 bd 55 15 01 00 00 00 00 02 be 38 15 01 00 00 00 00 02 bf 44 15 01 00 00 00 00 02 cf 88 15 01 00 00 00 00 02 c8 00 15 01 00 00 00 00 02 c9 55 15 01 00 00 00 00 02 ca 00 15 01 00 00 00 00 02 cb 55 15 01 00 00 00 00 02 cc a2 15 01 00 00 00 00 02 ce 88 15 01 00 00 00 00 02 cf 88 15 01 00 00 00 00 02 d0 00 15 01 00 00 00 00 02 d1 00 15 01 00 00 00 00 02 d3 00 15 01 00 00 00 00 02 d5 00 15 01 00 00 00 00 02 d6 22 15 01 00 00 00 00 02 d7 31 15 01 00 00 00 00 02 d8 7e 15 01 00 00 00 00 02 ff 01 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 6e 80 15 01 00 00 00 00 02 ff 00 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 d3 15 15 01 00 00 00 00 02 d4 10 15 01 00 00 00 00 02 d5 18 15 01 00 00 00 00 02 d6 b8 15 01 00 00 00 00 02 d7 00 15 01 00 00 00 00 02 55 80 05 01 00 00 78 00 02 11 00 05 01 00 00 32 00 02 29 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x10>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-bl-pmic-pwm-frequency = <0x64>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| phandle = <0x19b>; | |
| qcom,mdss-dsi-pwm-gpio = <0x191 0x04 0x00>; | |
| qcom,mdss-dsi-v-pulse-width = <0x05>; | |
| qcom,mdss-dsi-h-back-porch = <0x50>; | |
| qcom,mdss-dsi-v-back-porch = <0x10>; | |
| linux,phandle = <0x19b>; | |
| qcom,cont-splash-enabled; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,panel-supply-entries = <0x192>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| }; | |
| qcom,smmu_mdp_sec_cb { | |
| compatible = "qcom,smmu_mdp_sec"; | |
| }; | |
| qcom,mdss_fb_primary { | |
| compatible = "qcom,mdss-fb"; | |
| cell-index = <0x00>; | |
| phandle = <0x194>; | |
| linux,phandle = <0x194>; | |
| qcom,cont-splash-memory { | |
| linux,contiguous-region = <0x18f>; | |
| }; | |
| }; | |
| qcom,mdss-reg-bus { | |
| qcom,msm-bus,vectors-KBps = <0x01 0x24e 0x00 0x00 0x01 0x24e 0x00 0x12c00 0x01 0x24e 0x00 0x27100 0x01 0x24e 0x00 0x4e200>; | |
| qcom,msm-bus,active-only; | |
| qcom,msm-bus,name = "mdss_reg"; | |
| qcom,msm-bus,num-cases = <0x04>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| }; | |
| qcom,mdss_dsi_hx8394f_720p_video { | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-name = "hx8394f 720p video mode dsi panel"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-controller = <0x190>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xff>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-h-front-porch = <0x50>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x01>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-panel-timings = <0x7a1a1200 0x3e42161e 0x14030400>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsi-panel-destination = "display_1"; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x02 0x01 0x14>; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-h-pulse-width = <0x18>; | |
| qcom,mdss-dsi-t-clk-post = <0x04>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x1e1b0406 0x20304a0 0x1e1b0406 0x20304a0 0x1e1b0406 0x20304a0 0x1e1b0406 0x20304a0 0x1e0d0405 0x20304a0>; | |
| qcom,mdss-dsi-bl-pmic-bank-select = <0x00>; | |
| qcom,mdss-dsi-t-clk-pre = <0x1a>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 04 b9 ff 83 94 39 01 00 00 00 00 0b b1 48 0f 6f 09 33 54 51 51 30 43 39 01 00 00 00 00 07 ba 63 03 68 6b b2 c0 39 01 00 00 00 00 07 b2 00 80 64 0c 06 2f 39 01 00 00 00 00 15 b4 19 74 19 74 19 74 01 0c 86 75 00 3f 19 74 19 74 09 74 01 0c 39 01 00 00 00 00 22 d3 00 00 07 07 00 00 12 10 32 10 01 00 01 32 13 c0 00 00 32 10 08 00 00 37 04 03 03 37 04 00 47 0c 40 39 01 00 00 00 00 2d d5 18 18 18 18 00 01 02 03 04 05 06 07 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 19 19 19 19 20 21 22 23 39 01 00 00 00 00 2d d6 18 18 19 19 07 06 05 04 03 02 01 00 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 19 19 18 18 23 22 21 20 39 01 00 00 00 00 03 b6 2f 2f 39 01 00 00 00 00 3b e0 00 02 08 0c 0e 11 14 11 24 32 41 40 4a 5a 5f 62 72 77 77 8b a2 52 53 5a 60 66 6e 7f 7f 00 02 08 0c 0e 11 14 11 24 32 41 40 49 5a 5f 62 71 76 77 8b a1 52 54 5b 61 67 73 7f 7f 39 01 00 00 00 00 02 cc 0b 39 01 00 00 00 00 03 c0 1f 31 39 01 00 00 00 00 02 d4 02 39 01 00 00 00 00 02 bd 01 39 01 00 00 00 00 02 b1 60 39 01 00 00 00 00 02 bd 00 39 01 00 00 00 00 08 bf 40 81 50 00 1a fc 01 05 01 00 00 78 00 02 11 00 05 01 00 00 14 00 02 29 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-bl-pmic-pwm-frequency = <0x64>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-pwm-gpio = <0x191 0x04 0x00>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsi-h-back-porch = <0x50>; | |
| qcom,mdss-dsi-v-back-porch = <0x0c>; | |
| qcom,cont-splash-enabled; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,panel-supply-entries = <0x192>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| }; | |
| qcom,mdss-hw-rt-bus { | |
| qcom,msm-bus,vectors-KBps = <0x16 0x200 0x00 0x00 0x16 0x200 0x00 0x3e8>; | |
| qcom,msm-bus,name = "mdss_hw_rt"; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| }; | |
| qcom,smmu_mdp_unsec_cb { | |
| compatible = "qcom,smmu_mdp_unsec"; | |
| }; | |
| qcom,mdss_dsi_nt35532_1080p_video { | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-name = "nt35532 1080p video mode dsi panel"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-controller = <0x190>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xff>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x01>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-panel-timings = <0xee382600 0x6a6c2c3c 0x2c030400>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-panel-destination = "display_1"; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x02 0x01 0x14>; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-h-pulse-width = <0x14>; | |
| qcom,mdss-dsi-t-clk-post = <0x02>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241b0809 0x50304a0>; | |
| qcom,mdss-dsi-bl-pmic-bank-select = <0x00>; | |
| qcom,mdss-dsi-t-clk-pre = <0x2c>; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 01 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 59 15 01 00 00 00 00 02 04 0c 15 01 00 00 00 00 02 05 2b 15 01 00 00 00 00 02 06 64 15 01 00 00 00 00 02 07 c6 15 01 00 00 00 00 02 0d 89 15 01 00 00 00 00 02 0e 89 15 01 00 00 00 00 02 0f e0 15 01 00 00 00 00 02 10 03 15 01 00 00 00 00 02 11 5a 15 01 00 00 00 00 02 12 5a 15 01 00 00 00 00 02 13 85 15 01 00 00 00 00 02 14 85 15 01 00 00 00 00 02 15 60 15 01 00 00 00 00 02 16 13 15 01 00 00 00 00 02 17 13 15 01 00 00 00 00 02 1c a3 15 01 00 00 00 00 02 60 77 15 01 00 00 00 00 02 ff 01 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 75 00 15 01 00 00 00 00 02 76 77 15 01 00 00 00 00 02 77 00 15 01 00 00 00 00 02 78 78 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 7a a4 15 01 00 00 00 00 02 7b 00 15 01 00 00 00 00 02 7c c2 15 01 00 00 00 00 02 7d 00 15 01 00 00 00 00 02 7e d9 15 01 00 00 00 00 02 7f 00 15 01 00 00 00 00 02 80 ec 15 01 00 00 00 00 02 81 00 15 01 00 00 00 00 02 82 fd 15 01 00 00 00 00 02 83 01 15 01 00 00 00 00 02 84 0c 15 01 00 00 00 00 02 85 01 15 01 00 00 00 00 02 86 1a 15 01 00 00 00 00 02 87 01 15 01 00 00 00 00 02 88 47 15 01 00 00 00 00 02 89 01 15 01 00 00 00 00 02 8a 69 15 01 00 00 00 00 02 8b 01 15 01 00 00 00 00 02 8c a1 15 01 00 00 00 00 02 8d 01 15 01 00 00 00 00 02 8e cc 15 01 00 00 00 00 02 8f 02 15 01 00 00 00 00 02 90 0f 15 01 00 00 00 00 02 91 02 15 01 00 00 00 00 02 92 46 15 01 00 00 00 00 02 93 02 15 01 00 00 00 00 02 94 47 15 01 00 00 00 00 02 95 02 15 01 00 00 00 00 02 96 7a 15 01 00 00 00 00 02 97 02 15 01 00 00 00 00 02 98 b3 15 01 00 00 00 00 02 99 02 15 01 00 00 00 00 02 9a d7 15 01 00 00 00 00 02 9b 03 15 01 00 00 00 00 02 9c 07 15 01 00 00 00 00 02 9d 03 15 01 00 00 00 00 02 9e 26 15 01 00 00 00 00 02 9f 03 15 01 00 00 00 00 02 a0 4d 15 01 00 00 00 00 02 a2 03 15 01 00 00 00 00 02 a3 58 15 01 00 00 00 00 02 a4 03 15 01 00 00 00 00 02 a5 64 15 01 00 00 00 00 02 a6 03 15 01 00 00 00 00 02 a7 72 15 01 00 00 00 00 02 a9 03 15 01 00 00 00 00 02 aa 82 15 01 00 00 00 00 02 ab 03 15 01 00 00 00 00 02 ac 93 15 01 00 00 00 00 02 ad 03 15 01 00 00 00 00 02 ae a9 15 01 00 00 00 00 02 af 03 15 01 00 00 00 00 02 b0 c4 15 01 00 00 00 00 02 b1 03 15 01 00 00 00 00 02 b2 dc 15 01 00 00 00 00 02 b3 00 15 01 00 00 00 00 02 b4 18 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 74 15 01 00 00 00 00 02 b7 00 15 01 00 00 00 00 02 b8 a4 15 01 00 00 00 00 02 b9 00 15 01 00 00 00 00 02 ba c2 15 01 00 00 00 00 02 bb 00 15 01 00 00 00 00 02 bc d9 15 01 00 00 00 00 02 bd 00 15 01 00 00 00 00 02 be ec 15 01 00 00 00 00 02 bf 00 15 01 00 00 00 00 02 c0 fd 15 01 00 00 00 00 02 c1 01 15 01 00 00 00 00 02 c2 0c 15 01 00 00 00 00 02 c3 01 15 01 00 00 00 00 02 c4 1a 15 01 00 00 00 00 02 c5 01 15 01 00 00 00 00 02 c6 47 15 01 00 00 00 00 02 c7 01 15 01 00 00 00 00 02 c8 69 15 01 00 00 00 00 02 c9 01 15 01 00 00 00 00 02 ca a1 15 01 00 00 00 00 02 cb 01 15 01 00 00 00 00 02 cc cc 15 01 00 00 00 00 02 cd 02 15 01 00 00 00 00 02 ce 0f 15 01 00 00 00 00 02 cf 02 15 01 00 00 00 00 02 d0 46 15 01 00 00 00 00 02 d1 02 15 01 00 00 00 00 02 d2 47 15 01 00 00 00 00 02 d3 02 15 01 00 00 00 00 02 d4 7a 15 01 00 00 00 00 02 d5 02 15 01 00 00 00 00 02 d6 b3 15 01 00 00 00 00 02 d7 02 15 01 00 00 00 00 02 d8 d7 15 01 00 00 00 00 02 d9 03 15 01 00 00 00 00 02 da 07 15 01 00 00 00 00 02 db 03 15 01 00 00 00 00 02 dc 26 15 01 00 00 00 00 02 dd 03 15 01 00 00 00 00 02 de 4d 15 01 00 00 00 00 02 df 03 15 01 00 00 00 00 02 e0 58 15 01 00 00 00 00 02 e1 03 15 01 00 00 00 00 02 e2 64 15 01 00 00 00 00 02 e3 03 15 01 00 00 00 00 02 e4 72 15 01 00 00 00 00 02 e5 03 15 01 00 00 00 00 02 e6 82 15 01 00 00 00 00 02 e7 03 15 01 00 00 00 00 02 e8 93 15 01 00 00 00 00 02 e9 03 15 01 00 00 00 00 02 ea a9 15 01 00 00 00 00 02 eb 03 15 01 00 00 00 00 02 ec c4 15 01 00 00 00 00 02 ed 03 15 01 00 00 00 00 02 ee dc 15 01 00 00 00 00 02 ef 00 15 01 00 00 00 00 02 f0 77 15 01 00 00 00 00 02 f1 00 15 01 00 00 00 00 02 f2 78 15 01 00 00 00 00 02 f3 00 15 01 00 00 00 00 02 f4 a4 15 01 00 00 00 00 02 f5 00 15 01 00 00 00 00 02 f6 c2 15 01 00 00 00 00 02 f7 00 15 01 00 00 00 00 02 f8 d9 15 01 00 00 00 00 02 f9 00 15 01 00 00 00 00 02 fa ec 15 01 00 00 00 00 02 ff 02 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 00 15 01 00 00 00 00 02 01 fd 15 01 00 00 00 00 02 02 01 15 01 00 00 00 00 02 03 0c 15 01 00 00 00 00 02 04 01 15 01 00 00 00 00 02 05 1a 15 01 00 00 00 00 02 06 01 15 01 00 00 00 00 02 07 47 15 01 00 00 00 00 02 08 01 15 01 00 00 00 00 02 09 69 15 01 00 00 00 00 02 0a 01 15 01 00 00 00 00 02 0b a1 15 01 00 00 00 00 02 0c 01 15 01 00 00 00 00 02 0d cc 15 01 00 00 00 00 02 0e 02 15 01 00 00 00 00 02 0f 0f 15 01 00 00 00 00 02 10 02 15 01 00 00 00 00 02 11 46 15 01 00 00 00 00 02 12 02 15 01 00 00 00 00 02 13 47 15 01 00 00 00 00 02 14 02 15 01 00 00 00 00 02 15 7a 15 01 00 00 00 00 02 16 02 15 01 00 00 00 00 02 17 b3 15 01 00 00 00 00 02 18 02 15 01 00 00 00 00 02 19 d7 15 01 00 00 00 00 02 1a 03 15 01 00 00 00 00 02 1b 07 15 01 00 00 00 00 02 1c 03 15 01 00 00 00 00 02 1d 26 15 01 00 00 00 00 02 1e 03 15 01 00 00 00 00 02 1f 4d 15 01 00 00 00 00 02 20 03 15 01 00 00 00 00 02 21 58 15 01 00 00 00 00 02 22 03 15 01 00 00 00 00 02 23 64 15 01 00 00 00 00 02 24 03 15 01 00 00 00 00 02 25 72 15 01 00 00 00 00 02 26 03 15 01 00 00 00 00 02 27 82 15 01 00 00 00 00 02 28 03 15 01 00 00 00 00 02 29 93 15 01 00 00 00 00 02 2a 03 15 01 00 00 00 00 02 2b a9 15 01 00 00 00 00 02 2d 03 15 01 00 00 00 00 02 2f c4 15 01 00 00 00 00 02 30 03 15 01 00 00 00 00 02 31 dc 15 01 00 00 00 00 02 32 00 15 01 00 00 00 00 02 33 18 15 01 00 00 00 00 02 34 00 15 01 00 00 00 00 02 35 74 15 01 00 00 00 00 02 36 00 15 01 00 00 00 00 02 37 a4 15 01 00 00 00 00 02 38 00 15 01 00 00 00 00 02 39 c2 15 01 00 00 00 00 02 3a 00 15 01 00 00 00 00 02 3b d9 15 01 00 00 00 00 02 3d 00 15 01 00 00 00 00 02 3f ec 15 01 00 00 00 00 02 40 00 15 01 00 00 00 00 02 41 fd 15 01 00 00 00 00 02 42 01 15 01 00 00 00 00 02 43 0c 15 01 00 00 00 00 02 44 01 15 01 00 00 00 00 02 45 1a 15 01 00 00 00 00 02 46 01 15 01 00 00 00 00 02 47 47 15 01 00 00 00 00 02 48 01 15 01 00 00 00 00 02 49 69 15 01 00 00 00 00 02 4a 01 15 01 00 00 00 00 02 4b a1 15 01 00 00 00 00 02 4c 01 15 01 00 00 00 00 02 4d cc 15 01 00 00 00 00 02 4e 02 15 01 00 00 00 00 02 4f 0f 15 01 00 00 00 00 02 50 02 15 01 00 00 00 00 02 51 46 15 01 00 00 00 00 02 52 02 15 01 00 00 00 00 02 53 47 15 01 00 00 00 00 02 54 02 15 01 00 00 00 00 02 55 7a 15 01 00 00 00 00 02 56 02 15 01 00 00 00 00 02 58 b3 15 01 00 00 00 00 02 59 02 15 01 00 00 00 00 02 5a d7 15 01 00 00 00 00 02 5b 03 15 01 00 00 00 00 02 5c 07 15 01 00 00 00 00 02 5d 03 15 01 00 00 00 00 02 5e 26 15 01 00 00 00 00 02 5f 03 15 01 00 00 00 00 02 60 4d 15 01 00 00 00 00 02 61 03 15 01 00 00 00 00 02 62 58 15 01 00 00 00 00 02 63 03 15 01 00 00 00 00 02 64 64 15 01 00 00 00 00 02 65 03 15 01 00 00 00 00 02 66 72 15 01 00 00 00 00 02 67 03 15 01 00 00 00 00 02 68 82 15 01 00 00 00 00 02 69 03 15 01 00 00 00 00 02 6a 93 15 01 00 00 00 00 02 6b 03 15 01 00 00 00 00 02 6c a9 15 01 00 00 00 00 02 6d 03 15 01 00 00 00 00 02 6e c4 15 01 00 00 00 00 02 6f 03 15 01 00 00 00 00 02 70 dc 15 01 00 00 00 00 02 71 00 15 01 00 00 00 00 02 72 77 15 01 00 00 00 00 02 73 00 15 01 00 00 00 00 02 74 78 15 01 00 00 00 00 02 75 00 15 01 00 00 00 00 02 76 a4 15 01 00 00 00 00 02 77 00 15 01 00 00 00 00 02 78 c2 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 7a d9 15 01 00 00 00 00 02 7b 00 15 01 00 00 00 00 02 7c ec 15 01 00 00 00 00 02 7d 00 15 01 00 00 00 00 02 7e fd 15 01 00 00 00 00 02 7f 01 15 01 00 00 00 00 02 80 0c 15 01 00 00 00 00 02 81 01 15 01 00 00 00 00 02 82 1a 15 01 00 00 00 00 02 83 01 15 01 00 00 00 00 02 84 47 15 01 00 00 00 00 02 85 01 15 01 00 00 00 00 02 86 69 15 01 00 00 00 00 02 87 01 15 01 00 00 00 00 02 88 a1 15 01 00 00 00 00 02 89 01 15 01 00 00 00 00 02 8a cc 15 01 00 00 00 00 02 8b 02 15 01 00 00 00 00 02 8c 0f 15 01 00 00 00 00 02 8d 02 15 01 00 00 00 00 02 8e 46 15 01 00 00 00 00 02 8f 02 15 01 00 00 00 00 02 90 47 15 01 00 00 00 00 02 91 02 15 01 00 00 00 00 02 92 7a 15 01 00 00 00 00 02 93 02 15 01 00 00 00 00 02 94 b3 15 01 00 00 00 00 02 95 02 15 01 00 00 00 00 02 96 d7 15 01 00 00 00 00 02 97 03 15 01 00 00 00 00 02 98 07 15 01 00 00 00 00 02 99 03 15 01 00 00 00 00 02 9a 26 15 01 00 00 00 00 02 9b 03 15 01 00 00 00 00 02 9c 4d 15 01 00 00 00 00 02 9d 03 15 01 00 00 00 00 02 9e 58 15 01 00 00 00 00 02 9f 03 15 01 00 00 00 00 02 a0 64 15 01 00 00 00 00 02 a2 03 15 01 00 00 00 00 02 a3 72 15 01 00 00 00 00 02 a4 03 15 01 00 00 00 00 02 a5 82 15 01 00 00 00 00 02 a6 03 15 01 00 00 00 00 02 a7 93 15 01 00 00 00 00 02 a9 03 15 01 00 00 00 00 02 aa a9 15 01 00 00 00 00 02 ab 03 15 01 00 00 00 00 02 ac c4 15 01 00 00 00 00 02 ad 03 15 01 00 00 00 00 02 ae dc 15 01 00 00 00 00 02 af 00 15 01 00 00 00 00 02 b0 18 15 01 00 00 00 00 02 b1 00 15 01 00 00 00 00 02 b2 74 15 01 00 00 00 00 02 b3 00 15 01 00 00 00 00 02 b4 a4 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 c2 15 01 00 00 00 00 02 b7 00 15 01 00 00 00 00 02 b8 d9 15 01 00 00 00 00 02 b9 00 15 01 00 00 00 00 02 ba ec 15 01 00 00 00 00 02 bb 00 15 01 00 00 00 00 02 bc fd 15 01 00 00 00 00 02 bd 01 15 01 00 00 00 00 02 be 0c 15 01 00 00 00 00 02 bf 01 15 01 00 00 00 00 02 c0 1a 15 01 00 00 00 00 02 c1 01 15 01 00 00 00 00 02 c2 47 15 01 00 00 00 00 02 c3 01 15 01 00 00 00 00 02 c4 69 15 01 00 00 00 00 02 c5 01 15 01 00 00 00 00 02 c6 a1 15 01 00 00 00 00 02 c7 01 15 01 00 00 00 00 02 c8 cc 15 01 00 00 00 00 02 c9 02 15 01 00 00 00 00 02 ca 0f 15 01 00 00 00 00 02 cb 02 15 01 00 00 00 00 02 cc 46 15 01 00 00 00 00 02 cd 02 15 01 00 00 00 00 02 ce 47 15 01 00 00 00 00 02 cf 02 15 01 00 00 00 00 02 d0 7a 15 01 00 00 00 00 02 d1 02 15 01 00 00 00 00 02 d2 b3 15 01 00 00 00 00 02 d3 02 15 01 00 00 00 00 02 d4 d7 15 01 00 00 00 00 02 d5 03 15 01 00 00 00 00 02 d6 07 15 01 00 00 00 00 02 d7 03 15 01 00 00 00 00 02 d8 26 15 01 00 00 00 00 02 d9 03 15 01 00 00 00 00 02 da 4d 15 01 00 00 00 00 02 db 03 15 01 00 00 00 00 02 dc 58 15 01 00 00 00 00 02 dd 03 15 01 00 00 00 00 02 de 64 15 01 00 00 00 00 02 df 03 15 01 00 00 00 00 02 e0 72 15 01 00 00 00 00 02 e1 03 15 01 00 00 00 00 02 e2 82 15 01 00 00 00 00 02 e3 03 15 01 00 00 00 00 02 e4 93 15 01 00 00 00 00 02 e5 03 15 01 00 00 00 00 02 e6 a9 15 01 00 00 00 00 02 e7 03 15 01 00 00 00 00 02 e8 c4 15 01 00 00 00 00 02 e9 03 15 01 00 00 00 00 02 ea dc 15 01 00 00 00 00 02 ff 05 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 38 15 01 00 00 00 00 02 01 38 15 01 00 00 00 00 02 02 07 15 01 00 00 00 00 02 03 40 15 01 00 00 00 00 02 04 40 15 01 00 00 00 00 02 05 25 15 01 00 00 00 00 02 06 1d 15 01 00 00 00 00 02 07 23 15 01 00 00 00 00 02 08 1b 15 01 00 00 00 00 02 09 21 15 01 00 00 00 00 02 0a 19 15 01 00 00 00 00 02 0b 1f 15 01 00 00 00 00 02 0c 17 15 01 00 00 00 00 02 0d 05 15 01 00 00 00 00 02 0e 04 15 01 00 00 00 00 02 0f 0f 15 01 00 00 00 00 02 10 38 15 01 00 00 00 00 02 11 38 15 01 00 00 00 00 02 12 38 15 01 00 00 00 00 02 13 38 15 01 00 00 00 00 02 14 38 15 01 00 00 00 00 02 15 38 15 01 00 00 00 00 02 16 06 15 01 00 00 00 00 02 17 40 15 01 00 00 00 00 02 18 40 15 01 00 00 00 00 02 19 24 15 01 00 00 00 00 02 1a 1c 15 01 00 00 00 00 02 1b 22 15 01 00 00 00 00 02 1c 1a 15 01 00 00 00 00 02 1d 20 15 01 00 00 00 00 02 1e 18 15 01 00 00 00 00 02 1f 1e 15 01 00 00 00 00 02 20 16 15 01 00 00 00 00 02 21 05 15 01 00 00 00 00 02 22 04 15 01 00 00 00 00 02 23 0e 15 01 00 00 00 00 02 24 38 15 01 00 00 00 00 02 25 38 15 01 00 00 00 00 02 26 38 15 01 00 00 00 00 02 27 38 15 01 00 00 00 00 02 28 38 15 01 00 00 00 00 02 29 38 15 01 00 00 00 00 02 2a 0e 15 01 00 00 00 00 02 2b 40 15 01 00 00 00 00 02 2d 40 15 01 00 00 00 00 02 2f 16 15 01 00 00 00 00 02 30 1e 15 01 00 00 00 00 02 31 18 15 01 00 00 00 00 02 32 20 15 01 00 00 00 00 02 33 1a 15 01 00 00 00 00 02 34 22 15 01 00 00 00 00 02 35 1c 15 01 00 00 00 00 02 36 24 15 01 00 00 00 00 02 37 05 15 01 00 00 00 00 02 38 04 15 01 00 00 00 00 02 39 06 15 01 00 00 00 00 02 3a 38 15 01 00 00 00 00 02 3b 38 15 01 00 00 00 00 02 3d 38 15 01 00 00 00 00 02 3f 38 15 01 00 00 00 00 02 40 38 15 01 00 00 00 00 02 41 38 15 01 00 00 00 00 02 42 0f 15 01 00 00 00 00 02 43 40 15 01 00 00 00 00 02 44 40 15 01 00 00 00 00 02 45 17 15 01 00 00 00 00 02 46 1f 15 01 00 00 00 00 02 47 19 15 01 00 00 00 00 02 48 21 15 01 00 00 00 00 02 49 1b 15 01 00 00 00 00 02 4a 23 15 01 00 00 00 00 02 4b 1d 15 01 00 00 00 00 02 4c 25 15 01 00 00 00 00 02 4d 05 15 01 00 00 00 00 02 4e 04 15 01 00 00 00 00 02 4f 07 15 01 00 00 00 00 02 50 38 15 01 00 00 00 00 02 51 38 15 01 00 00 00 00 02 52 38 15 01 00 00 00 00 02 53 38 15 01 00 00 00 00 02 5b 0a 15 01 00 00 00 00 02 5c 0a 15 01 00 00 00 00 02 63 0a 15 01 00 00 00 00 02 64 15 15 01 00 00 00 00 02 68 24 15 01 00 00 00 00 02 69 24 15 01 00 00 00 00 02 90 7b 15 01 00 00 00 00 02 91 11 15 01 00 00 00 00 02 92 14 15 01 00 00 00 00 02 7e 10 15 01 00 00 00 00 02 7f 10 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 98 00 15 01 00 00 00 00 02 99 00 15 01 00 00 00 00 02 54 2e 15 01 00 00 00 00 02 59 38 15 01 00 00 00 00 02 5d 01 15 01 00 00 00 00 02 5e 27 15 01 00 00 00 00 02 62 39 15 01 00 00 00 00 02 66 88 15 01 00 00 00 00 02 67 11 15 01 00 00 00 00 02 6a 0e 15 01 00 00 00 00 02 6b 20 15 01 00 00 00 00 02 6c 08 15 01 00 00 00 00 02 6d 00 15 01 00 00 00 00 02 7d 01 15 01 00 00 00 00 02 b7 01 15 01 00 00 00 00 02 b8 0a 15 01 00 00 00 00 02 ba 13 15 01 00 00 00 00 02 bc 01 15 01 00 00 00 00 02 bd 55 15 01 00 00 00 00 02 be 38 15 01 00 00 00 00 02 bf 44 15 01 00 00 00 00 02 cf 88 15 01 00 00 00 00 02 c8 00 15 01 00 00 00 00 02 c9 55 15 01 00 00 00 00 02 ca 00 15 01 00 00 00 00 02 cb 55 15 01 00 00 00 00 02 cc a2 15 01 00 00 00 00 02 ce 88 15 01 00 00 00 00 02 cf 88 15 01 00 00 00 00 02 d0 00 15 01 00 00 00 00 02 d1 00 15 01 00 00 00 00 02 d3 00 15 01 00 00 00 00 02 d5 00 15 01 00 00 00 00 02 d6 22 15 01 00 00 00 00 02 d7 31 15 01 00 00 00 00 02 d8 7e 15 01 00 00 00 00 02 ff 01 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 6e 80 15 01 00 00 00 00 02 ff 00 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 d3 15 15 01 00 00 00 00 02 d4 10 15 01 00 00 00 00 02 d5 18 15 01 00 00 00 00 02 d6 b8 15 01 00 00 00 00 02 d7 00 15 01 00 00 00 00 02 55 80 05 01 00 00 78 00 02 11 00 05 01 00 00 32 00 02 29 00]; | |
| qcom,mdss-dsi-v-front-porch = <0x10>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-bl-pmic-pwm-frequency = <0x64>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-pwm-gpio = <0x191 0x04 0x00>; | |
| qcom,mdss-dsi-v-pulse-width = <0x05>; | |
| qcom,mdss-dsi-h-back-porch = <0x50>; | |
| qcom,mdss-dsi-v-back-porch = <0x10>; | |
| qcom,cont-splash-enabled; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,panel-supply-entries = <0x192>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| }; | |
| qcom,mdss_dsi_st7703_720p_video { | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-name = "st7703 720p video mode dsi panel"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-controller = <0x190>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 96 00 02 10 00]; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-bl-max-level = <0xff>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-h-front-porch = <0x32>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x01>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-panel-timings = <0x7d241900 0x34311d26 0x2a030400>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsi-panel-destination = "display_1"; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x02 0x01 0x14>; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-h-pulse-width = <0x32>; | |
| qcom,mdss-dsi-t-clk-post = <0x1f>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x1e1a0405 0x20304a0 0x1e1a0405 0x20304a0 0x1e1a0405 0x20304a0 0x1e1a0405 0x20304a0 0x1e0d0305 0x20304a0>; | |
| qcom,mdss-dsi-bl-pmic-bank-select = <0x00>; | |
| qcom,mdss-dsi-t-clk-pre = <0x2c>; | |
| qcom,mdss-dsi-on-command = <0x39010000 0x4b9 0xf1128339 0x1000000 0x1cba33 0x8105f90e 0xe000000 0x00 0x442500 0x910a0000 0x24fd100 0x373901 0x00 0x3b82522 0x39010000 0x4bf 0x2110039 0x1000000 0xbb30c 0x100a5003 0xff000000 0x390100 0x0a 0xc0737350 0x50000008 0x70003901 0x00 0x2bc4639 0x1000000 0x2cc07 0x39010000 0x2b4 0x80390100 0x04 0xb2c81230 0x39010000 0xfe3 0x7070b0b 0x30b0000 0xff00 0x40103901 0x00 0xdc15300 0x1e1e77c1 0xffffafaf 0x7f7f3901 0x00 0x3b50707 0x39010000 0x3b6 0x70703901 0x00 0x7c60000 0xffff01ff 0x39010000 0x40e9 0xc2100504 0xfe02a112 0x31453f83 0x12b13b2a 0x8050000 0x805 0x00 0xff024602 0x48688888 0x888088ff 0x13571358 0x78888888 0x81880000 0x12 0xb13b0000 0x39 0x1000000 0x3eea00 0x1a000000 0x00 0xff 0x31753118 0x78888888 0x8588ff20 0x64200868 0x88888884 0x88201000 0x540000 0x00 0xc00000 0xc000000 0x3002a1 0x00 0x39010000 0x23e0 0x5071a 0x393f332c 0x60b0d11 0x13121410 0x1a000507 0x1a393f33 0x2c060b0d 0x11131214 0x101a0501 0x7800 0x2110005 0x1000096 0x22900>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-bl-pmic-pwm-frequency = <0x1a>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-pwm-gpio = <0x191 0x04 0x00>; | |
| qcom,mdss-dsi-v-pulse-width = <0x04>; | |
| qcom,mdss-dsi-h-back-porch = <0x32>; | |
| qcom,mdss-dsi-v-back-porch = <0x08>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,panel-supply-entries = <0x192>; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| }; | |
| }; | |
| qcom,cam_smmu { | |
| compatible = "qcom,msm-cam-smmu"; | |
| status = "ok"; | |
| msm_cam_smmu_cb1 { | |
| label = "vfe"; | |
| compatible = "qcom,qsmmu-cam-cb"; | |
| iommus = <0x176 0x400 0x176 0x2800>; | |
| qcom,scratch-buf-support; | |
| }; | |
| msm_cam_smmu_cb3 { | |
| label = "cpp"; | |
| compatible = "qcom,qsmmu-cam-cb"; | |
| iommus = <0x176 0x1c00>; | |
| }; | |
| msm_cam_smmu_cb4 { | |
| label = "jpeg_enc0"; | |
| compatible = "qcom,qsmmu-cam-cb"; | |
| iommus = <0x176 0x1800>; | |
| }; | |
| }; | |
| qcedev@720000 { | |
| reg = <0x720000 0x20000 0x704000 0x20000>; | |
| qcom,msm-bus,vectors-KBps = <0x37 0x200 0x00 0x00 0x37 0x200 0x60180 0x60180>; | |
| interrupts = <0x00 0xcf 0x00>; | |
| qcom,ce-opp-freq = <0x5f5e100>; | |
| qcom,ce-device = <0x00>; | |
| reg-names = "crypto-base\0crypto-bam-base"; | |
| compatible = "qcom,qcedev"; | |
| clock-names = "core_clk_src\0core_clk\0iface_clk\0bus_clk"; | |
| qcom,ce-hw-instance = <0x00>; | |
| qcom,msm-bus,name = "qcedev-noc"; | |
| clocks = <0x37 0x37a21414 0x37 0xd390d2 0x37 0x94de4919 0x37 0xd4415c9b>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,ce-hw-shared; | |
| qcom,bam-pipe-pair = <0x01>; | |
| }; | |
| ssphy@78000 { | |
| reg = <0x78000 0x9f8 0x193f244 0x04 0x193f044 0x04>; | |
| reg-names = "qmp_phy_base\0vls_clamp_reg\0tcsr_phy_clk_scheme_sel"; | |
| qcom,qmp-phy-reg-offset = <0x988 0x98c 0x990 0x994 0x974 0x8d8 0x8dc 0x804 0x800 0x808>; | |
| compatible = "qcom,usb-ssphy-qmp"; | |
| clock-names = "aux_clk\0pipe_clk\0cfg_ahb_clk\0phy_reset\0phy_phy_reset\0ref_clk_src\0ref_clk"; | |
| qcom,vdd-voltage-level = <0x00 0xe1d48 0xe1d48>; | |
| clocks = <0x37 0x555d16b2 0x37 0x26f8a97a 0x37 0xccb7e26f 0x37 0x3d559f1 0x37 0xb1a4f885 0x37 0xf5304268 0x37 0xb85dadfa>; | |
| qcom,vbus-valid-override; | |
| phandle = <0x124>; | |
| vdd-supply = <0x125>; | |
| core-supply = <0xf5>; | |
| qcom,qmp-phy-init-seq = <0xac 0x14 0x1a 0x00 0x34 0x08 0x08 0x00 0x174 0x30 0x30 0x00 0x3c 0x06 0x06 0x00 0xb4 0x00 0x00 0x00 0xb8 0x08 0x08 0x00 0x194 0x06 0x06 0x3e8 0x19c 0x01 0x01 0x00 0x178 0x00 0x00 0x00 0xd0 0x82 0x82 0x00 0xdc 0x55 0x55 0x00 0xe0 0x55 0x55 0x00 0xe4 0x03 0x03 0x00 0x78 0x0b 0x0b 0x00 0x84 0x16 0x16 0x00 0x90 0x28 0x28 0x00 0x108 0x80 0x80 0x00 0x10c 0x00 0x00 0x00 0x184 0x0a 0x0a 0x00 0x4c 0x15 0x15 0x00 0x50 0x34 0x34 0x00 0x54 0x00 0x00 0x00 0xc8 0x00 0x00 0x00 0x18c 0x00 0x00 0x00 0xcc 0x00 0x00 0x00 0x128 0x00 0x00 0x00 0x0c 0x0a 0x0a 0x00 0x10 0x01 0x01 0x00 0x1c 0x31 0x31 0x00 0x20 0x01 0x01 0x00 0x14 0x00 0x00 0x00 0x18 0x00 0x00 0x00 0x24 0xde 0xde 0x00 0x28 0x07 0x07 0x00 0x48 0x0f 0x0f 0x00 0x70 0x0f 0x0f 0x00 0x100 0x80 0x80 0x00 0x440 0x0b 0x0b 0x00 0x4d8 0x02 0x02 0x00 0x4dc 0x6c 0x6c 0x00 0x4e0 0xbb 0xbb 0x00 0x508 0x77 0x77 0x00 0x50c 0x80 0x80 0x00 0x514 0x03 0x03 0x00 0x51c 0x16 0x16 0x00 0x448 0x75 0x75 0x00 0x454 0x00 0x00 0x00 0x40c 0x0a 0x0a 0x00 0x41c 0x06 0x06 0x00 0x510 0x00 0x00 0x00 0x268 0x45 0x45 0x00 0x2ac 0x12 0x12 0x00 0x294 0x06 0x06 0x00 0x254 0x00 0x00 0x00 0x8c8 0x83 0x83 0x00 0x8c4 0x02 0x02 0x00 0x8cc 0x09 0x09 0x00 0x8d0 0xa2 0xa2 0x00 0x8d4 0x85 0x85 0x00 0x880 0xd1 0xd1 0x00 0x884 0x1f 0x1f 0x00 0x888 0x47 0x47 0x00 0x80c 0x9f 0x9f 0x00 0x824 0x17 0x17 0x00 0x828 0x0f 0x0f 0x00 0x8b8 0x75 0x75 0x00 0x8bc 0x13 0x13 0x00 0x8b0 0x86 0x86 0x00 0x8a0 0x04 0x04 0x00 0x88c 0x44 0x44 0x00 0x870 0xe7 0xe7 0x00 0x874 0x03 0x03 0x00 0x878 0x40 0x40 0x00 0x87c 0x00 0x00 0x00 0x9d8 0x88 0x88 0x00 0xffffffff 0xffffffff 0x00 0x00>; | |
| linux,phandle = <0x124>; | |
| }; | |
| sdhci@7824900 { | |
| reg = <0x7824900 0x500 0x7824000 0x800 0x7824e00 0x200 0x119d000 0x04>; | |
| qcom,msm-bus,vectors-KBps = <0x4e 0x200 0x00 0x00 0x4e 0x200 0x416 0xc80 0x4e 0x200 0xcc3e 0x27100 0x4e 0x200 0xff50 0x30d40 0x4e 0x200 0x1fe9e 0x61a80 0x4e 0x200 0x1fe9e 0x61a80 0x4e 0x200 0x3fd3e 0xc3500 0x4e 0x200 0x3fd3e 0xc3500 0x4e 0x200 0x146cc2 0x3e8000>; | |
| interrupts = <0x00 0x7b 0x00 0x00 0x8a 0x00>; | |
| sdhc-msm-crypto = <0xff>; | |
| qcom,pm-qos-irq-type = "affine_irq"; | |
| qcom,vdd-io-always-on; | |
| qcom,bus-bw-vectors-bps = <0x00 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0x17d78400 0xffffffff>; | |
| pinctrl-0 = <0x101 0x102 0x103 0x104>; | |
| pinctrl-1 = <0x105 0x106 0x107 0x108>; | |
| reg-names = "hc_mem\0core_mem\0cmdq_mem\0tlmm_mem"; | |
| qcom,bus-speed-mode = "HS400_1p8v\0HS200_1p8v\0DDR_1p8v"; | |
| qcom,nonremovable; | |
| compatible = "qcom,sdhci-msm"; | |
| clock-names = "iface_clk\0core_clk\0ice_core_clk"; | |
| qcom,vdd-current-level = <0xc8 0x8b290>; | |
| qcom,msm-bus,name = "sdhc1"; | |
| vdd-io-supply = <0xe8>; | |
| qcom,vdd-voltage-level = <0x2c4020 0x2c4020>; | |
| interrupt-names = "hc_irq\0pwr_irq"; | |
| clocks = <0x37 0x691e0caa 0x37 0x9ad6fb96 0x37 0xfd5680a>; | |
| qcom,pm-qos-cmdq-latency-us = <0x02 0xd5 0x02 0xd5>; | |
| qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xb71b000 0x16e36000>; | |
| qcom,pm-qos-cpu-groups = <0x0f 0xf0>; | |
| qcom,msm-bus,num-cases = <0x09>; | |
| qcom,vdd-io-current-level = <0xc8 0x4f588>; | |
| status = "ok"; | |
| qcom,bus-width = <0x08>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,vdd-io-lpm-sup; | |
| qcom,pm-qos-legacy-latency-us = <0x02 0xd5 0x02 0xd5>; | |
| qcom,vdd-io-voltage-level = <0x1b7740 0x1b7740>; | |
| qcom,ice-clk-rates = <0x1017df80 0x9896800>; | |
| vdd-supply = <0x100>; | |
| qcom,pm-qos-irq-latency = <0x02 0xd5>; | |
| qcom,large-address-bus; | |
| qcom,devfreq,freq-table = <0x2faf080 0xbebc200>; | |
| pinctrl-names = "active\0sleep"; | |
| }; | |
| restart@4ab000 { | |
| reg = <0x4ab000 0x04 0x193d100 0x04>; | |
| reg-names = "pshold-base\0tcsr-boot-misc-detect"; | |
| compatible = "qcom,pshold"; | |
| }; | |
| sdhci@7864900 { | |
| reg = <0x7864900 0x500 0x7864000 0x800>; | |
| qcom,msm-bus,vectors-KBps = <0x51 0x200 0x00 0x00 0x51 0x200 0x416 0xc80 0x51 0x200 0xcc3e 0x27100 0x51 0x200 0xff50 0x30d40 0x51 0x200 0x1fe9e 0x61a80 0x51 0x200 0x3fd3e 0xc3500 0x51 0x200 0x3fd3e 0xc3500 0x51 0x200 0x146cc2 0x3e8000>; | |
| cd-gpios = <0xbe 0x85 0x01>; | |
| interrupts = <0x00 0x01 0x02>; | |
| qcom,pm-qos-irq-type = "affine_irq"; | |
| qcom,bus-bw-vectors-bps = <0x00 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>; | |
| pinctrl-0 = <0x109 0x10a 0x10b 0x10c>; | |
| pinctrl-1 = <0x10d 0x10e 0x10f>; | |
| reg-names = "hc_mem\0core_mem"; | |
| qcom,bus-speed-mode = "SDR12\0SDR25\0SDR50\0DDR50\0SDR104"; | |
| compatible = "qcom,sdhci-msm"; | |
| clock-names = "iface_clk\0core_clk"; | |
| qcom,vdd-current-level = <0x3a98 0xc3500>; | |
| qcom,msm-bus,name = "sdhc2"; | |
| vdd-io-supply = <0x6b>; | |
| qcom,vdd-voltage-level = <0x2d0370 0x2d0370>; | |
| interrupt-names = "hc_irq\0pwr_irq\0status_irq"; | |
| clocks = <0x37 0x23d5727f 0x37 0x861b20ac>; | |
| #interrupt-cells = <0x01>; | |
| qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200>; | |
| qcom,pm-qos-cpu-groups = <0x0f 0xf0>; | |
| qcom,msm-bus,num-cases = <0x08>; | |
| qcom,vdd-io-current-level = <0xc8 0x55f0>; | |
| status = "ok"; | |
| qcom,bus-width = <0x04>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,pm-qos-legacy-latency-us = <0x02 0xd5 0x02 0xd5>; | |
| qcom,vdd-io-voltage-level = <0x1b7740 0x2d0370>; | |
| #address-cells = <0x00>; | |
| interrupt-map = <0x00 0x01 0x00 0x7d 0x00 0x01 0x01 0x00 0xdd 0x00 0x02 0xbe 0x85 0x00>; | |
| interrupt-map-mask = <0xffffffff>; | |
| phandle = <0x110>; | |
| vdd-supply = <0x6a>; | |
| qcom,pm-qos-irq-latency = <0x02 0xd5>; | |
| qcom,large-address-bus; | |
| qcom,devfreq,freq-table = <0x2faf080 0xbebc200>; | |
| pinctrl-names = "active\0sleep"; | |
| linux,phandle = <0x110>; | |
| interrupt-parent = <0x110>; | |
| }; | |
| replicator@6026000 { | |
| reg = <0x6026000 0x1000>; | |
| reg-names = "replicator-base"; | |
| coresight-outports = <0x00 0x01>; | |
| coresight-name = "coresight-replicator"; | |
| compatible = "qcom,coresight-replicator"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-child-ports = <0x00 0x00>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| phandle = <0x6e>; | |
| coresight-child-list = <0x6c 0x6d>; | |
| coresight-nr-inports = <0x01>; | |
| linux,phandle = <0x6e>; | |
| coresight-id = <0x02>; | |
| }; | |
| gpio_keys { | |
| pinctrl-0 = <0x1a0>; | |
| pinctrl-1 = <0x1a1>; | |
| compatible = "gpio-keys"; | |
| input-name = "gpio-keys"; | |
| pinctrl-names = "tlmm_gpio_key_active\0tlmm_gpio_key_suspend"; | |
| camera_focus { | |
| gpios = <0xbe 0x57 0x01>; | |
| label = "camera_focus"; | |
| debounce-interval = <0x0f>; | |
| linux,code = <0x210>; | |
| linux,input-type = <0x01>; | |
| }; | |
| vol_up { | |
| gpios = <0xbe 0x55 0x01>; | |
| label = "volume_up"; | |
| debounce-interval = <0x0f>; | |
| linux,code = <0x73>; | |
| linux,input-type = <0x01>; | |
| }; | |
| camera_snapshot { | |
| gpios = <0xbe 0x56 0x01>; | |
| label = "camera_snapshot"; | |
| debounce-interval = <0x0f>; | |
| linux,code = <0x2fe>; | |
| linux,input-type = <0x01>; | |
| }; | |
| }; | |
| qcom,mdss_wb_panel { | |
| qcom,mdss-fb-map = <0x19c>; | |
| compatible = "qcom,mdss_wb"; | |
| qcom,mdss_pan_bpp = <0x18>; | |
| qcom,mdss_pan_res = <0x280 0x280>; | |
| }; | |
| flashlight { | |
| pinctrl-0 = <0x19e>; | |
| compatible = "qcom,leds-gpio-flash"; | |
| linux,name = "flashlight"; | |
| linux,default-trigger = "flashlight-trigger"; | |
| status = "okay"; | |
| qcom,flash-seq-val = <0x01 0x00>; | |
| qcom,flash-now = <0xbe 0x5b 0x00>; | |
| qcom,torch-seq-val = <0x00 0x01>; | |
| qcom,flash-en = <0xbe 0x5a 0x00>; | |
| qcom,op-seq = "flash_en\0flash_now"; | |
| phandle = <0x19f>; | |
| pinctrl-names = "flash_default"; | |
| linux,phandle = <0x19f>; | |
| }; | |
| i2c@78b6000 { | |
| reg = <0x78b6000 0x600>; | |
| dmas = <0xd2 0x06 0x40 0x20000020 0x20 0xd2 0x07 0x20 0x20000020 0x20>; | |
| interrupts = <0x00 0x60 0x00>; | |
| pinctrl-0 = <0xd0>; | |
| pinctrl-1 = <0xd1>; | |
| reg-names = "qup_phys_addr"; | |
| compatible = "qcom,i2c-msm-v2"; | |
| clock-names = "iface_clk\0core_clk"; | |
| qcom,clk-freq-in = <0x124f800>; | |
| interrupt-names = "qup_irq"; | |
| clocks = <0x37 0x8caa5b4f 0x37 0x1076f220>; | |
| qcom,clk-freq-out = <0x61a80>; | |
| qcom,noise-rjct-scl = <0x00>; | |
| qcom,noise-rjct-sda = <0x00>; | |
| #address-cells = <0x01>; | |
| qcom,master-id = <0x56>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| pinctrl-names = "i2c_active\0i2c_sleep"; | |
| wsa881x-i2c-codec@44 { | |
| reg = <0x44>; | |
| compatible = "qcom,wsa881x-i2c-codec"; | |
| status = "disabled"; | |
| }; | |
| wsa881x-i2c-codec@45 { | |
| reg = <0x45>; | |
| compatible = "qcom,wsa881x-i2c-codec"; | |
| status = "disabled"; | |
| }; | |
| wsa881x-i2c-codec@e { | |
| reg = <0x0e>; | |
| pinctrl-0 = <0xd6 0xd7 0xd8>; | |
| pinctrl-1 = <0xd9 0xd7 0xd8>; | |
| pinctrl-2 = <0xd6 0xda 0xd8>; | |
| pinctrl-3 = <0xd9 0xda 0xd8>; | |
| pinctrl-4 = <0xd6 0xd7 0xdb>; | |
| pinctrl-5 = <0xd9 0xd7 0xdb>; | |
| pinctrl-6 = <0xd6 0xda 0xdb>; | |
| pinctrl-7 = <0xd9 0xda 0xdb>; | |
| qcom,pinctrl-names = "all_off\0wsa_clk\0wsa_active\0wsa_clk_active\0wsa_vi\0wsa_clk_vi\0wsa_active_vi\0wsa_all"; | |
| compatible = "qcom,wsa881x-i2c-codec"; | |
| status = "disabled"; | |
| qcom,msm-gpios = "wsa_clk\0wsa_reset\0wsa_vi"; | |
| pinctrl-names = "all_off\0wsa_clk\0wsa_active\0wsa_clk_active\0wsa_vi\0wsa_clk_vi\0wsa_active_vi\0wsa_all"; | |
| }; | |
| wsa881x-i2c-codec@f { | |
| reg = <0x0f>; | |
| pinctrl-0 = <0xd6 0xd7 0xd8>; | |
| pinctrl-1 = <0xd9 0xd7 0xd8>; | |
| pinctrl-2 = <0xd6 0xda 0xd8>; | |
| pinctrl-3 = <0xd9 0xda 0xd8>; | |
| pinctrl-4 = <0xd6 0xd7 0xdb>; | |
| pinctrl-5 = <0xd9 0xd7 0xdb>; | |
| pinctrl-6 = <0xd6 0xda 0xdb>; | |
| pinctrl-7 = <0xd9 0xda 0xdb>; | |
| qcom,pinctrl-names = "all_off\0wsa_clk\0wsa_active\0wsa_clk_active\0wsa_vi\0wsa_clk_vi\0wsa_active_vi\0wsa_all"; | |
| compatible = "qcom,wsa881x-i2c-codec"; | |
| status = "disabled"; | |
| qcom,msm-gpios = "wsa_clk\0wsa_reset\0wsa_vi"; | |
| pinctrl-names = "all_off\0wsa_clk\0wsa_active\0wsa_clk_active\0wsa_vi\0wsa_clk_vi\0wsa_active_vi\0wsa_all"; | |
| }; | |
| adv7533@39 { | |
| reg = <0x39>; | |
| qcom,disable-load = <0x00>; | |
| pinctrl-0 = <0xd3>; | |
| pinctrl-1 = <0xd4>; | |
| hpd-5v-en-supply = <0xd5>; | |
| adi,main-addr = <0x39>; | |
| instance_id = <0x00>; | |
| adi,enable-audio; | |
| qcom,enable-load = <0x00>; | |
| compatible = "adv7533"; | |
| qcom,max-voltage-level = <0x00>; | |
| adi,cec-dsi-addr = <0x3c>; | |
| adi,video-mode = <0x03>; | |
| adi,irq-gpio = <0xbe 0x5a 0x2002>; | |
| qcom,min-voltage-level = <0x00>; | |
| qcom,supply-names = "hpd-5v-en"; | |
| pinctrl-names = "pmx_adv7533_active\0pmx_adv7533_suspend"; | |
| }; | |
| }; | |
| i2c@78b8000 { | |
| reg = <0x78b8000 0x600>; | |
| dmas = <0xd2 0x0a 0x40 0x20000020 0x20 0xd2 0x0b 0x20 0x20000020 0x20>; | |
| interrupts = <0x00 0x62 0x00>; | |
| pinctrl-0 = <0xdc>; | |
| pinctrl-1 = <0xdd>; | |
| reg-names = "qup_phys_addr"; | |
| compatible = "qcom,i2c-msm-v2"; | |
| clock-names = "iface_clk\0core_clk"; | |
| qcom,clk-freq-in = <0x124f800>; | |
| interrupt-names = "qup_irq"; | |
| clocks = <0x37 0x8caa5b4f 0x37 0xd7f40f6f>; | |
| qcom,clk-freq-out = <0x61a80>; | |
| qcom,noise-rjct-scl = <0x00>; | |
| qcom,noise-rjct-sda = <0x00>; | |
| #address-cells = <0x01>; | |
| qcom,master-id = <0x56>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| pinctrl-names = "i2c_active\0i2c_sleep"; | |
| nq@28 { | |
| reg = <0x28>; | |
| interrupts = <0x2c 0x00>; | |
| pinctrl-0 = <0xde 0xdf>; | |
| pinctrl-1 = <0xe0 0xe1>; | |
| compatible = "qcom,nq-nci"; | |
| interrupt-names = "nfc_irq"; | |
| qcom,nq-firm = <0xbe 0x3f 0x00>; | |
| qcom,nq-irq = <0xbe 0x2c 0x00>; | |
| qcom,nq-ven = <0xbe 0x3b 0x00>; | |
| pinctrl-names = "nfc_active\0nfc_suspend"; | |
| interrupt-parent = <0xbe>; | |
| }; | |
| nxp@2f { | |
| reg = <0x2f>; | |
| compatible = "nxp,pn512"; | |
| irq-gpio = <0xbe 0x2c 0x00>; | |
| npd-gpio = <0xbe 0x3b 0x00>; | |
| }; | |
| }; | |
| usb_nop_phy { | |
| compatible = "usb-nop-xceiv"; | |
| status = "disabled"; | |
| }; | |
| qcom,msm-ultra-low-latency { | |
| qcom,msm-pcm-dsp-id = <0x02>; | |
| compatible = "qcom,msm-pcm-dsp"; | |
| qcom,latency-level = "ultra"; | |
| phandle = <0x13a>; | |
| qcom,msm-pcm-low-latency; | |
| linux,phandle = <0x13a>; | |
| }; | |
| ldo@0185f000 { | |
| reg = <0x185f000 0x30 0xa4000 0x1000>; | |
| qcom,ldo-voltage-floor = <0x7c830 0x7c830 0x927c0>; | |
| regulator-name = "msm_gfx_ldo"; | |
| reg-names = "ldo_addr\0efuse_addr"; | |
| compatible = "qcom,msm8953-gfx-ldo"; | |
| qcom,num-corners = <0x07>; | |
| regulator-min-microvolt = <0x01>; | |
| vdd-cx-supply = <0xee>; | |
| qcom,init-corner = <0x04>; | |
| mem-acc-supply = <0x12a>; | |
| qcom,ldo-voltage-ceiling = <0x975e0 0xa6040 0xb71b0>; | |
| qcom,vdd-cx-corner-map = <0x40 0x40 0x80 0xc0 0x100 0x140 0x180>; | |
| regulator-max-microvolt = <0x07>; | |
| qcom,mem-acc-corner-map = <0x01 0x01 0x01 0x02 0x02 0x02 0x02>; | |
| qcom,num-ldo-corners = <0x03>; | |
| phandle = <0xc8>; | |
| qcom,ldo-init-voltage-adjustment = <0x88b8 0x61a8 0x00>; | |
| linux,phandle = <0xc8>; | |
| qcom,ldo-enable-corner-map = <0x01 0x01 0x01 0x00 0x00 0x00 0x00>; | |
| }; | |
| tz-log@08600720 { | |
| reg = "\b`\a \0\0 "; | |
| compatible = "qcom,tz-log"; | |
| }; | |
| qcom,msm-cam@1b00000 { | |
| reg = <0x1b00000 0x40000>; | |
| reg-names = "msm-cam"; | |
| compatible = "qcom,msm-cam"; | |
| status = "ok"; | |
| qcom,bus-votes = <0x00 0x1312d000 0x2625a000 0x2625a000>; | |
| bus-vectors = "suspend\0svs\0nominal\0turbo"; | |
| }; | |
| qcom,sensor-information { | |
| compatible = "qcom,sensor-information"; | |
| qcom,sensor-information-0 { | |
| qcom,sensor-name = "tsens_tz_sensor0"; | |
| qcom,sensor-type = "tsens"; | |
| qcom,scaling-factor = <0x0a>; | |
| }; | |
| qcom,sensor-information-1 { | |
| qcom,sensor-name = "tsens_tz_sensor1"; | |
| qcom,sensor-type = "tsens"; | |
| qcom,scaling-factor = <0x0a>; | |
| }; | |
| qcom,sensor-information-2 { | |
| qcom,alias-name = "pop_mem"; | |
| qcom,sensor-name = "tsens_tz_sensor2"; | |
| qcom,sensor-type = "tsens"; | |
| qcom,scaling-factor = <0x0a>; | |
| }; | |
| qcom,sensor-information-3 { | |
| qcom,sensor-name = "tsens_tz_sensor3"; | |
| qcom,sensor-type = "tsens"; | |
| qcom,scaling-factor = <0x0a>; | |
| }; | |
| qcom,sensor-information-4 { | |
| qcom,sensor-name = "tsens_tz_sensor4"; | |
| qcom,sensor-type = "tsens"; | |
| phandle = <0xc3>; | |
| qcom,scaling-factor = <0x0a>; | |
| linux,phandle = <0xc3>; | |
| }; | |
| qcom,sensor-information-5 { | |
| qcom,sensor-name = "tsens_tz_sensor5"; | |
| qcom,sensor-type = "tsens"; | |
| phandle = <0xc4>; | |
| qcom,scaling-factor = <0x0a>; | |
| linux,phandle = <0xc4>; | |
| }; | |
| qcom,sensor-information-6 { | |
| qcom,sensor-name = "tsens_tz_sensor6"; | |
| qcom,sensor-type = "tsens"; | |
| phandle = <0xc5>; | |
| qcom,scaling-factor = <0x0a>; | |
| linux,phandle = <0xc5>; | |
| }; | |
| qcom,sensor-information-7 { | |
| qcom,sensor-name = "tsens_tz_sensor7"; | |
| qcom,sensor-type = "tsens"; | |
| phandle = <0xc6>; | |
| qcom,scaling-factor = <0x0a>; | |
| linux,phandle = <0xc6>; | |
| }; | |
| qcom,sensor-information-8 { | |
| qcom,alias-name = "L2_cache_1"; | |
| qcom,sensor-name = "tsens_tz_sensor8"; | |
| qcom,sensor-type = "tsens"; | |
| qcom,scaling-factor = <0x0a>; | |
| }; | |
| qcom,sensor-information-9 { | |
| qcom,sensor-name = "tsens_tz_sensor9"; | |
| qcom,sensor-type = "tsens"; | |
| phandle = <0xbf>; | |
| qcom,scaling-factor = <0x0a>; | |
| linux,phandle = <0xbf>; | |
| }; | |
| qcom,sensor-information-10 { | |
| qcom,sensor-name = "tsens_tz_sensor10"; | |
| qcom,sensor-type = "tsens"; | |
| phandle = <0xc0>; | |
| qcom,scaling-factor = <0x0a>; | |
| linux,phandle = <0xc0>; | |
| }; | |
| qcom,sensor-information-11 { | |
| qcom,sensor-name = "tsens_tz_sensor11"; | |
| qcom,sensor-type = "tsens"; | |
| phandle = <0xc1>; | |
| qcom,scaling-factor = <0x0a>; | |
| linux,phandle = <0xc1>; | |
| }; | |
| qcom,sensor-information-12 { | |
| qcom,sensor-name = "tsens_tz_sensor12"; | |
| qcom,sensor-type = "tsens"; | |
| phandle = <0xc2>; | |
| qcom,scaling-factor = <0x0a>; | |
| linux,phandle = <0xc2>; | |
| }; | |
| qcom,sensor-information-13 { | |
| qcom,alias-name = "L2_cache_0"; | |
| qcom,sensor-name = "tsens_tz_sensor13"; | |
| qcom,sensor-type = "tsens"; | |
| qcom,scaling-factor = <0x0a>; | |
| }; | |
| qcom,sensor-information-14 { | |
| qcom,sensor-name = "tsens_tz_sensor14"; | |
| qcom,sensor-type = "tsens"; | |
| qcom,scaling-factor = <0x0a>; | |
| }; | |
| qcom,sensor-information-15 { | |
| qcom,alias-name = "gpu"; | |
| qcom,sensor-name = "tsens_tz_sensor15"; | |
| qcom,sensor-type = "tsens"; | |
| qcom,scaling-factor = <0x0a>; | |
| }; | |
| qcom,sensor-information-16 { | |
| qcom,sensor-name = "pm8953_tz"; | |
| qcom,sensor-type = "alarm"; | |
| qcom,scaling-factor = <0x3e8>; | |
| }; | |
| qcom,sensor-information-17 { | |
| qcom,sensor-name = "pa_therm0"; | |
| qcom,sensor-type = "adc"; | |
| }; | |
| qcom,sensor-information-18 { | |
| qcom,sensor-name = "pa_therm1"; | |
| qcom,sensor-type = "adc"; | |
| }; | |
| qcom,sensor-information-19 { | |
| qcom,sensor-name = "xo_therm"; | |
| qcom,sensor-type = "adc"; | |
| }; | |
| qcom,sensor-information-20 { | |
| qcom,sensor-name = "xo_therm_buf"; | |
| qcom,sensor-type = "adc"; | |
| }; | |
| qcom,sensor-information-21 { | |
| qcom,sensor-name = "case_therm"; | |
| qcom,sensor-type = "adc"; | |
| }; | |
| }; | |
| qcom,adsprpc-mem { | |
| compatible = "qcom,msm-adsprpc-mem-region"; | |
| memory-region = <0xfd>; | |
| }; | |
| android_usb@86000c8 { | |
| reg = <0x86000c8 0xc8>; | |
| compatible = "qcom,android-usb"; | |
| qcom,pm-qos-latency = <0x02 0xd5 0x2b14>; | |
| }; | |
| serial@7af0000 { | |
| reg = <0x7af0000 0x200>; | |
| interrupts = <0x00 0x133 0x00>; | |
| pinctrl-0 = <0xcc>; | |
| compatible = "qcom,msm-lsuart-v14"; | |
| clock-names = "core_clk\0iface_clk"; | |
| clocks = <0x37 0x1e1965a3 0x37 0x8f283c1d>; | |
| status = "ok"; | |
| pinctrl-names = "default"; | |
| }; | |
| qcom,gcc-mdss@1800000 { | |
| reg = <0x1800000 0x80000>; | |
| #clock-cells = <0x01>; | |
| reg-names = "cc_base"; | |
| compatible = "qcom,gcc-mdss-8953"; | |
| clock-names = "pclk0_src\0pclk1_src\0byte0_src\0byte1_src"; | |
| clocks = <0xef 0x792379e1 0xf0 0x36458019 0xef 0x60e83f06 0xf0 0xb5a42b7b>; | |
| phandle = <0x18e>; | |
| linux,phandle = <0x18e>; | |
| }; | |
| qcom,ipa@07900000 { | |
| reg = <0x7900000 0x4effc 0x7904000 0x26934>; | |
| qcom,msm-bus,vectors-KBps = <0x5a 0x200 0x00 0x00 0x5a 0x200 0x186a0 0xc3500 0x5a 0x200 0x186a0 0x124f80>; | |
| interrupts = <0x00 0xe4 0x00 0x00 0xe6 0x00>; | |
| reg-names = "ipa-base\0bam-base"; | |
| compatible = "qcom,ipa"; | |
| clock-names = "core_clk"; | |
| qcom,msm-bus,name = "ipa"; | |
| qcom,ipa-hw-ver = <0x06>; | |
| qcom,ipa-hw-mode = <0x00>; | |
| interrupt-names = "ipa-irq\0bam-irq"; | |
| qcom,wan-rx-ring-size = <0xc0>; | |
| qcom,use-ipa-tethering-bridge; | |
| clocks = <0x37 0xfa685cda>; | |
| qcom,bus-vector-names = "MIN\0SVS\0PERF"; | |
| qcom,msm-bus,num-cases = <0x03>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,lan-rx-ring-size = <0xc0>; | |
| qcom,ee = <0x00>; | |
| qcom,modem-cfg-emb-pipe-flt; | |
| }; | |
| serial@7aef000 { | |
| reg = <0x7aef000 0x200>; | |
| interrupts = <0x00 0x132 0x00>; | |
| pinctrl-0 = <0xcb>; | |
| compatible = "qcom,msm-lsuart-v14"; | |
| clock-names = "core_clk\0iface_clk"; | |
| clocks = <0x37 0x8c3512ff 0x37 0x8f283c1d>; | |
| status = "ok"; | |
| pinctrl-names = "default"; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_15_in { | |
| gpios = <0x40 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_15_in"; | |
| }; | |
| rpm_etm0 { | |
| qcom,inst-id = <0x04>; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-rpm-etm0"; | |
| compatible = "qcom,coresight-remote-etm"; | |
| coresight-child-ports = <0x00>; | |
| coresight-child-list = <0x74>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x33>; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_1_out { | |
| gpios = <0x43 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_1_out"; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_2_out { | |
| gpios = <0x47 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_2_out"; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_4_out { | |
| gpios = <0x45 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_4_out"; | |
| }; | |
| qcom,smp2pgpio-smp2p-1-out { | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x01>; | |
| compatible = "qcom,smp2pgpio"; | |
| #interrupt-cells = <0x02>; | |
| qcom,entry-name = "smp2p"; | |
| phandle = <0x43>; | |
| interrupt-controller; | |
| gpio-controller; | |
| linux,phandle = <0x43>; | |
| }; | |
| qcom,smp2pgpio-smp2p-15-in { | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x0f>; | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,is-inbound; | |
| #interrupt-cells = <0x02>; | |
| qcom,entry-name = "smp2p"; | |
| phandle = <0x40>; | |
| interrupt-controller; | |
| gpio-controller; | |
| linux,phandle = <0x40>; | |
| }; | |
| qcom,smp2pgpio-smp2p-2-out { | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x02>; | |
| compatible = "qcom,smp2pgpio"; | |
| #interrupt-cells = <0x02>; | |
| qcom,entry-name = "smp2p"; | |
| phandle = <0x47>; | |
| interrupt-controller; | |
| gpio-controller; | |
| linux,phandle = <0x47>; | |
| }; | |
| dbm@70f8000 { | |
| reg = <0x70f8000 0x300>; | |
| compatible = "qcom,usb-dbm-1p5"; | |
| qcom,reset-ep-after-lpm-resume; | |
| phandle = <0x122>; | |
| linux,phandle = <0x122>; | |
| }; | |
| qcom,smp2pgpio-smp2p-4-out { | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x04>; | |
| compatible = "qcom,smp2pgpio"; | |
| #interrupt-cells = <0x02>; | |
| qcom,entry-name = "smp2p"; | |
| phandle = <0x45>; | |
| interrupt-controller; | |
| gpio-controller; | |
| linux,phandle = <0x45>; | |
| }; | |
| jtagmm@619c000 { | |
| reg = <0x619c000 0x1000 0x6190000 0x1000>; | |
| reg-names = "etm-base\0debug-base"; | |
| compatible = "qcom,jtagv8-mm"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| qcom,coresight-jtagmm-cpu = <0x02>; | |
| }; | |
| jtagmm@619d000 { | |
| reg = <0x619d000 0x1000 0x6192000 0x1000>; | |
| reg-names = "etm-base\0debug-base"; | |
| compatible = "qcom,jtagv8-mm"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| qcom,coresight-jtagmm-cpu = <0x03>; | |
| }; | |
| jtagmm@619e000 { | |
| reg = <0x619e000 0x1000 0x6194000 0x1000>; | |
| reg-names = "etm-base\0debug-base"; | |
| compatible = "qcom,jtagv8-mm"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| qcom,coresight-jtagmm-cpu = <0x04>; | |
| }; | |
| jtagmm@619f000 { | |
| reg = <0x619f000 0x1000 0x6196000 0x1000>; | |
| reg-names = "etm-base\0debug-base"; | |
| compatible = "qcom,jtagv8-mm"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| qcom,coresight-jtagmm-cpu = <0x05>; | |
| }; | |
| qcom,mincpubw { | |
| qcom,active-only; | |
| qcom,src-dst-ports = <0x01 0x200>; | |
| compatible = "qcom,devbw"; | |
| qcom,bw-tbl = <0x301 0x64b 0x84c 0xb71 0xc95 0x1098 0x1406 0x16e3 0x1808 0x192d 0x1bc0>; | |
| phandle = <0xf4>; | |
| linux,phandle = <0xf4>; | |
| governor = "cpufreq"; | |
| }; | |
| qcom,ispif@1b31000 { | |
| reg = <0x1b31000 0x500 0x1b00020 0x10>; | |
| interrupts = <0x00 0x37 0x00>; | |
| reg-names = "ispif\0csi_clk_mux"; | |
| compatible = "qcom,ispif-v3.0\0qcom,ispif"; | |
| clock-names = "ispif_ahb_clk\0camss_ahb_clk\0camss_top_ahb_clk\0camss_ahb_src\0csi0_src_clk\0csi0_clk\0csi0_rdi_clk\0csi0_pix_clk\0csi1_src_clk\0csi1_clk\0csi1_rdi_clk\0csi1_pix_clk\0csi2_src_clk\0csi2_clk\0csi2_rdi_clk\0csi2_pix_clk\0vfe0_clk_src\0camss_vfe_vfe0_clk\0camss_csi_vfe0_clk\0vfe1_clk_src\0camss_vfe_vfe1_clk\0camss_csi_vfe1_clk"; | |
| interrupt-names = "ispif"; | |
| clocks = <0x37 0x3c0a858f 0x37 0x9894b414 0x37 0x4e814a78 0x37 0xf92304fb 0x37 0x227e65bc 0x37 0x6b01b3e1 0x37 0x7053c7ae 0x37 0x61a8a930 0x37 0x6a2a6c36 0x37 0x1aba4a8c 0x37 0x6ac996fe 0x37 0x87fc98d8 0x37 0x4113589f 0x37 0xb6857fa2 0x37 0x19fd3f1 0x37 0xa619561a 0x37 0xa0c2bd8f 0x37 0xaaa3cd97 0x37 0xcc73453c 0x37 0x4e357366 0x37 0xcaf20d99 0x37 0xb1ef6e8b>; | |
| qcom,clock-cntl-support; | |
| cell-index = <0x00>; | |
| vfe0-vdd-supply = <0x174>; | |
| qcom,vdd-names = "vfe0-vdd\0vfe1-vdd"; | |
| qcom,clock-control = "SET_RATE\0NO_SET_RATE\0NO_SET_RATE\0NO_SET_RATE\0SET_RATE\0NO_SET_RATE\0NO_SET_RATE\0NO_SET_RATE\0SET_RATE\0NO_SET_RATE\0NO_SET_RATE\0NO_SET_RATE\0SET_RATE\0NO_SET_RATE\0NO_SET_RATE\0NO_SET_RATE\0INIT_RATE\0NO_SET_RATE\0NO_SET_RATE\0INIT_RATE\0NO_SET_RATE\0NO_SET_RATE"; | |
| vfe1-vdd-supply = <0x175>; | |
| qcom,num-isps = <0x02>; | |
| qcom,clock-rates = <0x3ab06a0 0x00 0x00 0x00 0xbebc200 0x00 0x00 0x00 0xbebc200 0x00 0x00 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| }; | |
| qcom,sps-dma@7884000 { | |
| reg = <0x7884000 0x1f000>; | |
| interrupts = <0x00 0xee 0x00>; | |
| compatible = "qcom,sps-dma"; | |
| #dma-cells = <0x04>; | |
| phandle = <0xd2>; | |
| qcom,summing-threshold = <0x0a>; | |
| linux,phandle = <0xd2>; | |
| }; | |
| jtagmm@61bc000 { | |
| reg = <0x61bc000 0x1000 0x61b0000 0x1000>; | |
| reg-names = "etm-base\0debug-base"; | |
| compatible = "qcom,jtagv8-mm"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| qcom,coresight-jtagmm-cpu = <0x06>; | |
| }; | |
| jtagmm@61bd000 { | |
| reg = <0x61bd000 0x1000 0x61b2000 0x1000>; | |
| reg-names = "etm-base\0debug-base"; | |
| compatible = "qcom,jtagv8-mm"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| qcom,coresight-jtagmm-cpu = <0x07>; | |
| }; | |
| jtagmm@61be000 { | |
| reg = <0x61be000 0x1000 0x61b4000 0x1000>; | |
| reg-names = "etm-base\0debug-base"; | |
| compatible = "qcom,jtagv8-mm"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| qcom,coresight-jtagmm-cpu = <0x08>; | |
| }; | |
| jtagmm@61bf000 { | |
| reg = <0x61bf000 0x1000 0x61b6000 0x1000>; | |
| reg-names = "etm-base\0debug-base"; | |
| compatible = "qcom,jtagv8-mm"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| qcom,coresight-jtagmm-cpu = <0x09>; | |
| }; | |
| qcom,vidc@1d00000 { | |
| reg = <0x1d00000 0xff000 0xa4124 0x04 0xa0164 0x04>; | |
| interrupts = <0x00 0x2c 0x00>; | |
| qcom,firmware-name = "venus"; | |
| reg-names = "vidc\0efuse\0efuse2"; | |
| compatible = "qcom,msm-vidc"; | |
| qcom,hfi = "venus"; | |
| clock-names = "core_clk\0core0_clk\0iface_clk\0bus_clk"; | |
| qcom,qdss-presets = <0x825000 0x1000 0x826000 0x1000 0x821000 0x1000 0x802000 0x1000 0x9180000 0x1000 0x9181000 0x1000>; | |
| clocks = <0x37 0xf76a02bb 0x37 0x83a7f549 0x37 0x8d778c6 0x37 0xcdf4c8f6>; | |
| qcom,hfi-version = "3xx"; | |
| qcom,dcvs-tbl = <0xc7380 0xc7380 0xef100 0x3f00000c 0xd0bd8 0xc876c 0xef100 0x4000004 0xc7380 0xafc80 0xcc000 0x4000004>; | |
| qcom,reg-presets = <0xe0020 0x5555556 0xe0024 0x5555556 0x80124 0x03>; | |
| qcom,dcvs-limit = <0x7080 0x18 0x7e90 0x18>; | |
| qcom,max-hw-load = <0xff000>; | |
| qcom,platform-version = <0x180000 0x13>; | |
| qcom,clock-configs = <0x01 0x00 0x00 0x00 0x00>; | |
| venus-core0-supply = <0xb9>; | |
| venus-supply = <0xb8>; | |
| qcom,pm-qos-latency-us = <0xd5>; | |
| qcom,capability-version = <0x2000 0x0d>; | |
| qcom,slave-side-cp; | |
| qcom,allowed-clock-rates = <0x1bb75640 0x17d78400 0x15752a00 0x127a3980 0xd9fb390 0x6cfed50>; | |
| qcom,sw-power-collapse; | |
| qcom,clock-freq-tbl { | |
| qcom,profile-hevcdec { | |
| qcom,cycles-per-mb = <0x190>; | |
| qcom,codec-mask = <0xc000000>; | |
| }; | |
| qcom,profile-dec { | |
| qcom,cycles-per-mb = <0x163>; | |
| qcom,codec-mask = <0xf3ffffff>; | |
| }; | |
| qcom,profile-enc { | |
| qcom,cycles-per-mb = <0x35f>; | |
| qcom,low-power-mode-factor = <0x8b20>; | |
| qcom,codec-mask = <0x55555555>; | |
| }; | |
| }; | |
| arm9_bus_ddr { | |
| label = "venus-arm9-ddr"; | |
| compatible = "qcom,msm-vidc,bus"; | |
| qcom,bus-governor = "performance"; | |
| qcom,bus-master = <0x3f>; | |
| qcom,bus-slave = <0x200>; | |
| qcom,bus-range-kbps = <0x01 0x01>; | |
| }; | |
| qcom,vidc-iommu-domains { | |
| qcom,domain-sec-bs { | |
| qcom,vidc-domain-phandle = <0xbb>; | |
| qcom,vidc-buffer-types = <0x241>; | |
| }; | |
| qcom,domain-sec-np { | |
| qcom,vidc-domain-phandle = <0xbd>; | |
| qcom,vidc-buffer-types = <0x480>; | |
| }; | |
| qcom,domain-sec-px { | |
| qcom,vidc-domain-phandle = <0xbc>; | |
| qcom,vidc-buffer-types = <0x106>; | |
| }; | |
| qcom,domain-ns { | |
| qcom,vidc-domain-phandle = <0xba>; | |
| qcom,vidc-buffer-types = <0xfff>; | |
| }; | |
| }; | |
| venus_bus_ddr { | |
| label = "venus-ddr"; | |
| compatible = "qcom,msm-vidc,bus"; | |
| qcom,bus-governor = "venus-ddr-gov"; | |
| qcom,bus-master = <0x3f>; | |
| qcom,bus-slave = <0x200>; | |
| qcom,bus-range-kbps = <0x3e8 0x241648>; | |
| }; | |
| }; | |
| qcom,mdss_dsi_pll@994400 { | |
| reg = <0x1a94400 0x588 0x184d074 0x08 0x1a94200 0x98>; | |
| #clock-cells = <0x01>; | |
| reg-names = "pll_base\0gdsc_base\0dynamic_pll_base"; | |
| label = "MDSS DSI 0 PLL"; | |
| compatible = "qcom,mdss_dsi_pll_8953"; | |
| clock-names = "iface_clk"; | |
| gdsc-supply = <0x172>; | |
| clocks = <0x37 0xbfb92ed3>; | |
| cell-index = <0x00>; | |
| qcom,dsi-pll-ssc-mode = "down-spread"; | |
| qcom,dsi-pll-ssc-en; | |
| phandle = <0xef>; | |
| clock-rate = <0x00>; | |
| memory-region = <0x19d>; | |
| linux,phandle = <0xef>; | |
| qcom,platform-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,platform-supply-entry@0 { | |
| reg = <0x00>; | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-max-voltage = <0x00>; | |
| qcom,supply-min-voltage = <0x00>; | |
| qcom,supply-name = "gdsc"; | |
| qcom,supply-enable-load = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_pll@996400 { | |
| reg = <0x1a96400 0x588 0x184d074 0x08 0x1a96200 0x98>; | |
| #clock-cells = <0x01>; | |
| reg-names = "pll_base\0gdsc_base\0dynamic_pll_base"; | |
| label = "MDSS DSI 1 PLL"; | |
| compatible = "qcom,mdss_dsi_pll_8953"; | |
| clock-names = "iface_clk"; | |
| gdsc-supply = <0x172>; | |
| clocks = <0x37 0xbfb92ed3>; | |
| cell-index = <0x01>; | |
| qcom,dsi-pll-ssc-mode = "down-spread"; | |
| qcom,dsi-pll-ssc-en; | |
| phandle = <0xf0>; | |
| clock-rate = <0x00>; | |
| linux,phandle = <0xf0>; | |
| qcom,platform-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,platform-supply-entry@0 { | |
| reg = <0x00>; | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-max-voltage = <0x00>; | |
| qcom,supply-min-voltage = <0x00>; | |
| qcom,supply-name = "gdsc"; | |
| qcom,supply-enable-load = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-pcm { | |
| qcom,msm-pcm-dsp-id = <0x00>; | |
| compatible = "qcom,msm-pcm-dsp"; | |
| phandle = <0x138>; | |
| linux,phandle = <0x138>; | |
| }; | |
| qcom,msm-rtb { | |
| qcom,rtb-size = <0x100000>; | |
| compatible = "qcom,msm-rtb"; | |
| }; | |
| qcrypto@720000 { | |
| reg = <0x720000 0x20000 0x704000 0x20000>; | |
| qcom,msm-bus,vectors-KBps = <0x37 0x200 0x00 0x00 0x37 0x200 0x60180 0x60180>; | |
| interrupts = <0x00 0xcf 0x00>; | |
| qcom,ce-opp-freq = <0x5f5e100>; | |
| qcom,ce-device = <0x00>; | |
| reg-names = "crypto-base\0crypto-bam-base"; | |
| qcom,use-sw-aead-algo; | |
| qcom,use-sw-aes-xts-algo; | |
| qcom,clk-mgmt-sus-res; | |
| compatible = "qcom,qcrypto"; | |
| clock-names = "core_clk_src\0core_clk\0iface_clk\0bus_clk"; | |
| qcom,ce-hw-instance = <0x00>; | |
| qcom,msm-bus,name = "qcrypto-noc"; | |
| qcom,use-sw-aes-cbc-ecb-ctr-algo; | |
| clocks = <0x37 0x37a21414 0x37 0xd390d2 0x37 0x94de4919 0x37 0xd4415c9b>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,ce-hw-shared; | |
| qcom,bam-pipe-pair = <0x02>; | |
| qcom,use-sw-hmac-algo; | |
| qcom,use-sw-ahash-algo; | |
| qcom,use-sw-aes-ccm-algo; | |
| }; | |
| qpdi@1941000 { | |
| reg = <0x1941000 0x04>; | |
| reg-names = "qpdi-base"; | |
| coresight-name = "coresight-qpdi"; | |
| compatible = "qcom,coresight-qpdi"; | |
| qcom,vdd-current-level = <0x3a98 0x61a80>; | |
| vdd-io-supply = <0x6b>; | |
| qcom,vdd-voltage-level = <0x2d0370 0x2d0370>; | |
| qcom,vdd-io-current-level = <0xc8 0xc350>; | |
| qcom,vdd-io-voltage-level = <0x2d0370 0x2d0370>; | |
| vdd-supply = <0x6a>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x3d>; | |
| }; | |
| qcom,msm-pcm-routing { | |
| compatible = "qcom,msm-pcm-routing"; | |
| phandle = <0x142>; | |
| linux,phandle = <0x142>; | |
| }; | |
| audio_ext_clk { | |
| #clock-cells = <0x01>; | |
| pinctrl-0 = <0x170>; | |
| pinctrl-1 = <0x171>; | |
| compatible = "qcom,audio-ref-clk"; | |
| clock-names = "osr_clk"; | |
| qcom,audio-ref-clk-gpio = <0x12b 0x01 0x00>; | |
| qcom,node_has_rpm_clock; | |
| clocks = <0x37 0xd454019f>; | |
| qcom,lpass-mclk-id = "pri_mclk"; | |
| status = "disabled"; | |
| phandle = <0xeb>; | |
| pinctrl-names = "sleep\0active"; | |
| linux,phandle = <0xeb>; | |
| }; | |
| wcn_etm0 { | |
| qcom,inst-id = <0x03>; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-wcn-etm0"; | |
| compatible = "qcom,coresight-remote-etm"; | |
| coresight-child-ports = <0x00>; | |
| coresight-child-list = <0x3c>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x32>; | |
| }; | |
| arm64-cpu-erp { | |
| interrupts = <0x00 0x113 0x00 0x00 0x114 0x00 0x00 0x111 0x00 0x00 0x112 0x00>; | |
| compatible = "arm,arm64-cpu-erp"; | |
| interrupt-names = "pri-dbe-irq\0sec-dbe-irq\0pri-ext-irq\0sec-ext-irq"; | |
| poll-delay-ms = <0x1388>; | |
| }; | |
| qcom,cpp@1b04000 { | |
| reg = <0x1b04000 0x100 0x1b80000 0x200 0x1b18000 0x18 0x1858078 0x04>; | |
| qcom,msm-bus,vectors-KBps = <0x6a 0x200 0x00 0x00 0x6a 0x200 0x00 0x00>; | |
| interrupts = <0x00 0x31 0x00>; | |
| reg-names = "cpp\0cpp_vbif\0cpp_hw\0camss_cpp"; | |
| compatible = "qcom,cpp"; | |
| clock-names = "camss_ahb_src\0camss_top_ahb_clk\0cpp_core_clk\0camss_vfe_cpp_ahb_clk\0camss_vfe_cpp_axi_clk\0camss_vfe_cpp_clk\0micro_iface_clk\0camss_ahb_clk"; | |
| qcom,msm-bus,name = "msm_camera_cpp"; | |
| qcom,bus-master = <0x01>; | |
| qcom,msm-bus-vector-dyn-vote; | |
| interrupt-names = "cpp"; | |
| clocks = <0x37 0xf92304fb 0x37 0x4e814a78 0x37 0x8382f56d 0x37 0x4ac95e14 0x37 0xbbf73861 0x37 0x7118a0de 0x37 0xfbbee8cf 0x37 0x9894b414>; | |
| cell-index = <0x00>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| status = "ok"; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,vdd-names = "vdd"; | |
| qcom,min-clock-rate = <0x5f5e100>; | |
| vdd-supply = <0x178>; | |
| qcom,clock-rates = <0x4c4b400 0x00 0xaba9500 0x00 0x00 0xaba9500 0x00 0x00>; | |
| qcom,cpp-fw-payload-info { | |
| qcom,plane-base = <0x8d>; | |
| qcom,plane-size = <0x05>; | |
| qcom,stripe-base = <0x9c>; | |
| qcom,stripe-size = <0x1b>; | |
| qcom,fe-ptr-off = <0x05>; | |
| qcom,we-ptr-off = <0x0b>; | |
| }; | |
| }; | |
| qcom,kgsl-3d0@1c00000 { | |
| reg = <0x1c00000 0x40000>; | |
| qcom,msm-bus,vectors-KBps = <0x1a 0x200 0x00 0x00 0x1a 0x200 0x00 0x19c800 0x1a 0x200 0x00 0x21fc00 0x1a 0x200 0x00 0x2ee000 0x1a 0x200 0x00 0x339000 0x1a 0x200 0x00 0x43f800 0x1a 0x200 0x00 0x520800 0x1a 0x200 0x00 0x5dc000 0x1a 0x200 0x00 0x627000 0x1a 0x200 0x00 0x672000 0x1a 0x200 0x00 0x71ac00>; | |
| interrupts = <0x00 0x21 0x00>; | |
| reg-names = "kgsl_3d0_reg_memory"; | |
| label = "kgsl-3d0"; | |
| vddcx-supply = <0x3a>; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-gfx"; | |
| compatible = "qcom,kgsl-3d0\0qcom,kgsl-3d"; | |
| clock-names = "core_clk\0iface_clk\0mem_iface_clk\0alt_mem_iface_clk\0rbbmtimer_clk\0alwayson_clk"; | |
| qcom,msm-bus,name = "grp3d"; | |
| qcom,ca-target-pwrlevel = <0x03>; | |
| coresight-child-ports = <0x06>; | |
| qcom,deep-nap-timeout = <0x64>; | |
| interrupt-names = "kgsl_3d0_irq"; | |
| qcom,enable-ca-jump; | |
| clocks = <0x38 0x49a51fd9 0x38 0xd15c8a00 0x38 0x3edd69ad 0x38 0x19922503 0x38 0x1180db06 0x38 0xae18e54d>; | |
| qcom,ca-busy-penalty = <0x2ee0>; | |
| qcom,gpubw-dev = <0x39>; | |
| qcom,strtstp-sleepwake; | |
| qcom,pm-qos-active-latency = <0xd5>; | |
| qcom,idle-timeout = <0x50>; | |
| qcom,chipid = <0x5000600>; | |
| qcom,msm-bus,num-cases = <0x0b>; | |
| status = "ok"; | |
| qcom,bus-width = <0x10>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,gpu-quirk-dp2clockgating-disable; | |
| qcom,initial-pwrlevel = <0x04>; | |
| qcom,snapshot-size = <0x100000>; | |
| coresight-child-list = <0x3c>; | |
| vdd-supply = <0x3b>; | |
| regulator-names = "vddcx\0vdd"; | |
| qcom,pm-qos-wakeup-latency = <0xd5>; | |
| qcom,highest-bank-bit = <0x0e>; | |
| qcom,gpu-quirk-two-pass-use-wfi; | |
| coresight-nr-inports = <0x00>; | |
| qcom,gpu-quirk-lmloadkill-disable; | |
| qcom,id = <0x00>; | |
| qcom,bus-control; | |
| coresight-id = <0x43>; | |
| qcom,gpu-mempools { | |
| compatible = "qcom,gpu-mempools"; | |
| #address-cells = <0x01>; | |
| qcom,mempool-max-pages = <0x8000>; | |
| #size-cells = <0x00>; | |
| qcom,gpu-mempool@0 { | |
| reg = <0x00>; | |
| qcom,mempool-page-size = <0x1000>; | |
| }; | |
| qcom,gpu-mempool@1 { | |
| reg = <0x01>; | |
| qcom,mempool-page-size = <0x10000>; | |
| }; | |
| }; | |
| qcom,gpu-pwrlevels { | |
| compatible = "qcom,gpu-pwrlevels"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,gpu-pwrlevel@0 { | |
| reg = <0x00>; | |
| qcom,gpu-freq = <0x23c34600>; | |
| qcom,bus-max = <0x0a>; | |
| qcom,bus-min = <0x0a>; | |
| qcom,bus-freq = <0x0a>; | |
| }; | |
| qcom,gpu-pwrlevel@1 { | |
| reg = <0x01>; | |
| qcom,gpu-freq = <0x2160ec00>; | |
| qcom,bus-max = <0x0a>; | |
| qcom,bus-min = <0x08>; | |
| qcom,bus-freq = <0x0a>; | |
| }; | |
| qcom,gpu-pwrlevel@2 { | |
| reg = <0x02>; | |
| qcom,gpu-freq = <0x1e65fb80>; | |
| qcom,bus-max = <0x0a>; | |
| qcom,bus-min = <0x06>; | |
| qcom,bus-freq = <0x09>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| reg = <0x03>; | |
| qcom,gpu-freq = <0x17d78400>; | |
| qcom,bus-max = <0x08>; | |
| qcom,bus-min = <0x05>; | |
| qcom,bus-freq = <0x07>; | |
| }; | |
| qcom,gpu-pwrlevel@4 { | |
| reg = <0x04>; | |
| qcom,gpu-freq = <0x1312d000>; | |
| qcom,bus-max = <0x06>; | |
| qcom,bus-min = <0x02>; | |
| qcom,bus-freq = <0x04>; | |
| }; | |
| qcom,gpu-pwrlevel@5 { | |
| reg = <0x05>; | |
| qcom,gpu-freq = <0xcdfe600>; | |
| qcom,bus-max = <0x04>; | |
| qcom,bus-min = <0x01>; | |
| qcom,bus-freq = <0x01>; | |
| }; | |
| qcom,gpu-pwrlevel@6 { | |
| reg = <0x06>; | |
| qcom,gpu-freq = <0x7f1ff20>; | |
| qcom,bus-max = <0x04>; | |
| qcom,bus-min = <0x01>; | |
| qcom,bus-freq = <0x01>; | |
| }; | |
| qcom,gpu-pwrlevel@7 { | |
| reg = <0x07>; | |
| qcom,gpu-freq = <0x124f800>; | |
| qcom,bus-min = <0x00>; | |
| qcom,bus-freq = <0x00>; | |
| }; | |
| }; | |
| }; | |
| sound-9335 { | |
| reg = <0xc051000 0x04 0xc051004 0x04 0xc055000 0x04 0xc052000 0x04>; | |
| pinctrl-0 = <0x131 0x132 0x130>; | |
| pinctrl-1 = <0x136 0x137 0x130>; | |
| pinctrl-2 = <0x131 0x132 0x135>; | |
| pinctrl-3 = <0x136 0x137 0x135>; | |
| reg-names = "csr_gp_io_mux_mic_ctl\0csr_gp_io_mux_spkr_ctl\0csr_gp_io_lpaif_pri_pcm_pri_mode_muxsel\0csr_gp_io_mux_quin_ctl"; | |
| qcom,pinctrl-names = "all_off\0quin_act\0us_eu_gpio_act\0quin_us_eu_gpio_act"; | |
| asoc-platform-names = "msm-pcm-dsp.0\0msm-pcm-dsp.1\0msm-pcm-dsp.2\0msm-voip-dsp\0msm-pcm-voice\0msm-pcm-loopback\0msm-compress-dsp\0msm-pcm-hostless\0msm-pcm-afe\0msm-lsm-client\0msm-pcm-routing\0msm-cpe-lsm\0msm-pcm-lpa"; | |
| compatible = "qcom,msm8952-audio-slim-codec"; | |
| asoc-platform = <0x138 0x139 0x13a 0x13b 0x13c 0x13d 0x13e 0x13f 0x140 0x141 0x142 0x163 0x143>; | |
| qcom,wsa-aux-dev-prefix = "SpkrLeft\0SpkrRight\0SpkrLeft\0SpkrRight"; | |
| qcom,msm-mbhc-gnd-swh = <0x00>; | |
| qcom,audio-routing = "AIF4 VI\0MCLK\0AIF4 VI\0MICBIAS_REGULATOR\0RX_BIAS\0MCLK\0MADINPUT\0MCLK\0AIF4 MAD\0MICBIAS_REGULATOR\0AMIC2\0MIC BIAS2\0MIC BIAS2\0Headset Mic\0AMIC3\0MIC BIAS2\0MIC BIAS2\0ANCRight Headset Mic\0AMIC4\0MIC BIAS2\0MIC BIAS2\0ANCLeft Headset Mic\0AMIC5\0MIC BIAS3\0MIC BIAS3\0Handset Mic\0AMIC6\0MIC BIAS4\0MIC BIAS4\0Analog Mic6\0DMIC0\0MIC BIAS1\0MIC BIAS1\0Digital Mic0\0DMIC1\0MIC BIAS1\0MIC BIAS1\0Digital Mic1\0DMIC2\0MIC BIAS3\0MIC BIAS3\0Digital Mic2\0DMIC3\0MIC BIAS3\0MIC BIAS3\0Digital Mic3\0DMIC4\0MIC BIAS4\0MIC BIAS4\0Digital Mic4\0DMIC5\0MIC BIAS4\0MIC BIAS4\0Digital Mic5\0MIC BIAS1\0MICBIAS_REGULATOR\0MIC BIAS2\0MICBIAS_REGULATOR\0MIC BIAS3\0MICBIAS_REGULATOR\0MIC BIAS4\0MICBIAS_REGULATOR\0SpkrLeft IN\0SPK1 OUT\0SpkrRight IN\0SPK2 OUT"; | |
| qcom,tasha-mclk-clk-freq = <0x927c00>; | |
| qcom,wsa-max-devs = <0x02>; | |
| asoc-cpu-names = "msm-dai-q6-auxpcm.1\0msm-dai-q6-mi2s.2\0msm-dai-q6-mi2s.3\0msm-dai-q6-mi2s.5\0msm-dai-q6-dev.16384\0msm-dai-q6-dev.16385\0msm-dai-q6-dev.16386\0msm-dai-q6-dev.16387\0msm-dai-q6-dev.16388\0msm-dai-q6-dev.16389\0msm-dai-q6-dev.16390\0msm-dai-q6-dev.16391\0msm-dai-q6-dev.16392\0msm-dai-q6-dev.16393\0msm-dai-q6-dev.16395\0msm-dai-q6-dev.224\0msm-dai-q6-dev.225\0msm-dai-q6-dev.241\0msm-dai-q6-dev.240\0msm-dai-q6-dev.32771\0msm-dai-q6-dev.32772\0msm-dai-q6-dev.32773\0msm-dai-q6-dev.32770\0msm-dai-q6-dev.16394\0msm-dai-q6-dev.12288\0msm-dai-q6-dev.12289\0msm-dai-q6-dev.12292\0msm-dai-q6-dev.12293\0msm-dai-q6-dev.16396"; | |
| asoc-codec = <0x160 0x162>; | |
| status = "disabled"; | |
| qcom,cdc-us-euro-gpios = <0xbe 0x12 0x00>; | |
| qcom,msm-gpios = "quin_i2s\0us_eu_gpio"; | |
| asoc-cpu = <0x144 0x147 0x148 0x149 0x14b 0x14c 0x14d 0x14e 0x164 0x165 0x14f 0x150 0x151 0x152 0x166 0x157 0x158 0x159 0x15a 0x15b 0x15c 0x15d 0x15e 0x167 0x153 0x154 0x155 0x156 0x168>; | |
| qcom,msm-mbhc-hphl-swh = <0x00>; | |
| qcom,hdmi-dba-codec-rx; | |
| pinctrl-names = "all_off\0quin_act\0us_eu_gpio_act\0quin_us_eu_gpio_act"; | |
| asoc-codec-names = "msm-stub-codec.1\0msm-hdmi-dba-codec-rx"; | |
| qcom,model = "msm8953-tasha-snd-card"; | |
| qcom,wsa-devs = <0x169 0x16a 0x16b 0x16c>; | |
| }; | |
| adv_vreg { | |
| gpio = <0x12b 0x05 0x00>; | |
| regulator-name = "adv_vreg"; | |
| compatible = "regulator-fixed"; | |
| enable-active-high; | |
| phandle = <0xd5>; | |
| startup-delay-us = <0x190>; | |
| linux,phandle = <0xd5>; | |
| }; | |
| etm@619c000 { | |
| reg = <0x619c000 0x1000>; | |
| reg-names = "etm-base"; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-etm0"; | |
| compatible = "arm,coresight-etmv4"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-child-ports = <0x00>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-etm-cpu = <0x02>; | |
| coresight-child-list = <0x73>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x0b>; | |
| }; | |
| etm@619d000 { | |
| reg = <0x619d000 0x1000>; | |
| reg-names = "etm-base"; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-etm1"; | |
| compatible = "arm,coresight-etmv4"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-child-ports = <0x01>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-etm-cpu = <0x03>; | |
| coresight-child-list = <0x73>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x0c>; | |
| }; | |
| etm@619e000 { | |
| reg = <0x619e000 0x1000>; | |
| reg-names = "etm-base"; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-etm2"; | |
| compatible = "arm,coresight-etmv4"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-child-ports = <0x02>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-etm-cpu = <0x04>; | |
| coresight-child-list = <0x73>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x0d>; | |
| }; | |
| etm@619f000 { | |
| reg = <0x619f000 0x1000>; | |
| reg-names = "etm-base"; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-etm3"; | |
| compatible = "arm,coresight-etmv4"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-child-ports = <0x03>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-etm-cpu = <0x05>; | |
| coresight-child-list = <0x73>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x0e>; | |
| }; | |
| qcom,msm-pcm-afe { | |
| compatible = "qcom,msm-pcm-afe"; | |
| phandle = <0x140>; | |
| linux,phandle = <0x140>; | |
| }; | |
| qcom,msm-pcm-lpa { | |
| compatible = "qcom,msm-pcm-lpa"; | |
| phandle = <0x143>; | |
| linux,phandle = <0x143>; | |
| }; | |
| devfreq-cpufreq { | |
| cpubw-cpufreq { | |
| target-dev = <0xf3>; | |
| cpu-to-dev-map = <0x9f600 0x64b 0xfd200 0xc95 0x156300 0x16e3 0x19c800 0x192d 0x1b8a00 0x1bc0 0x1de200 0x1bc0 0x21b100 0x1bc0>; | |
| }; | |
| mincpubw-cpufreq { | |
| target-dev = <0xf4>; | |
| cpu-to-dev-map = <0x9f600 0x64b 0x156300 0xc95 0x21b100 0x16e3>; | |
| }; | |
| }; | |
| etm@61bc000 { | |
| reg = <0x61bc000 0x1000>; | |
| reg-names = "etm-base"; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-etm4"; | |
| compatible = "arm,coresight-etmv4"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-child-ports = <0x04>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-etm-cpu = <0x06>; | |
| coresight-child-list = <0x73>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x0f>; | |
| }; | |
| qcom,msm-pcm-low-latency { | |
| qcom,msm-pcm-dsp-id = <0x01>; | |
| compatible = "qcom,msm-pcm-dsp"; | |
| qcom,latency-level = "regular"; | |
| phandle = <0x139>; | |
| qcom,msm-pcm-low-latency; | |
| linux,phandle = <0x139>; | |
| }; | |
| etm@61bd000 { | |
| reg = <0x61bd000 0x1000>; | |
| reg-names = "etm-base"; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-etm5"; | |
| compatible = "arm,coresight-etmv4"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-child-ports = <0x05>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-etm-cpu = <0x07>; | |
| coresight-child-list = <0x73>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x10>; | |
| }; | |
| etm@61be000 { | |
| reg = <0x61be000 0x1000>; | |
| reg-names = "etm-base"; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-etm6"; | |
| compatible = "arm,coresight-etmv4"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-child-ports = <0x06>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-etm-cpu = <0x08>; | |
| coresight-child-list = <0x73>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x11>; | |
| }; | |
| etm@61bf000 { | |
| reg = <0x61bf000 0x1000>; | |
| reg-names = "etm-base"; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-etm7"; | |
| compatible = "arm,coresight-etmv4"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-child-ports = <0x07>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-etm-cpu = <0x09>; | |
| coresight-child-list = <0x73>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x12>; | |
| }; | |
| modem_etm0 { | |
| qcom,inst-id = <0x0b>; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-modem-etm0"; | |
| compatible = "qcom,coresight-remote-etm"; | |
| coresight-child-ports = <0x02>; | |
| coresight-child-list = <0x71>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x35>; | |
| }; | |
| modem_etm1 { | |
| qcom,inst-id = <0x02>; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-modem-etm1"; | |
| compatible = "qcom,coresight-remote-etm"; | |
| coresight-child-ports = <0x01>; | |
| coresight-child-list = <0x71>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x36>; | |
| }; | |
| tpiu@6020000 { | |
| reg = <0x6020000 0x1000 0x1100000 0xb0000>; | |
| nidnt-gpio = <0x85>; | |
| interrupts = <0x00 0x52 0x00>; | |
| pinctrl-0 = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; | |
| pinctrl-1 = <0x50 0x51 0x52 0x53 0x54 0x55>; | |
| pinctrl-2 = <0x56 0x57 0x58 0x59 0x5a>; | |
| pinctrl-3 = <0x5b 0x5c 0x5d 0x5e 0x5f 0x60>; | |
| pinctrl-4 = <0x61 0x62 0x63 0x64 0x65>; | |
| pinctrl-5 = <0x66 0x67 0x68 0x69>; | |
| reg-names = "tpiu-base\0nidnt-base"; | |
| nidnt-gpio-polarity = <0x01>; | |
| coresight-name = "coresight-tpiu"; | |
| compatible = "arm,coresight-tpiu"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| qcom,vdd-current-level = <0x3a98 0x61a80>; | |
| vdd-io-supply = <0x6b>; | |
| qcom,vdd-voltage-level = <0x2d0370 0x2d0370>; | |
| interrupt-names = "nidnt-irq"; | |
| qcom,nidnt-swduart; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| qcom,vdd-io-current-level = <0xc8 0xc350>; | |
| qcom,nidnt-swdtrc; | |
| qcom,nidnthw; | |
| qcom,vdd-io-voltage-level = <0x2d0370 0x2d0370>; | |
| qcom,nidnt-jtag; | |
| qcom,nidnt-spmi; | |
| phandle = <0x6d>; | |
| vdd-supply = <0x6a>; | |
| coresight-nr-inports = <0x01>; | |
| pinctrl-names = "sdcard\0trace\0swduart\0swdtrc\0jtag\0spmi"; | |
| linux,phandle = <0x6d>; | |
| coresight-id = <0x01>; | |
| }; | |
| wcd9xxx-irq { | |
| interrupts = <0x49 0x00>; | |
| pinctrl-0 = <0x16d>; | |
| compatible = "qcom,wcd9xxx-irq"; | |
| interrupt-names = "cdc-int"; | |
| #interrupt-cells = <0x01>; | |
| qcom,gpio-connect = <0xbe 0x49 0x00>; | |
| status = "disabled"; | |
| phandle = <0xe9>; | |
| interrupt-controller; | |
| pinctrl-names = "default"; | |
| linux,phandle = <0xe9>; | |
| interrupt-parent = <0xbe>; | |
| }; | |
| slim@c140000 { | |
| reg = <0xc140000 0x2c000 0xc104000 0x2a000>; | |
| interrupts = <0x00 0xa3 0x00 0x00 0xb4 0x00>; | |
| reg-names = "slimbus_physical\0slimbus_bam_physical"; | |
| compatible = "qcom,slim-ngd"; | |
| interrupt-names = "slimbus_irq\0slimbus_bam_irq"; | |
| cell-index = <0x01>; | |
| qcom,apps-ch-pipes = <0x600000>; | |
| status = "disabled"; | |
| qcom,ea-pc = <0x200>; | |
| tasha_codec { | |
| qcom,cdc-buck-sido-voltage = <0x1b7740 0x1b7740>; | |
| qcom,cdc-micbias1-mv = <0x708>; | |
| qcom,cdc-vdd-rx-h-current = <0x61a8>; | |
| qcom,cdc-micbias2-mv = <0x708>; | |
| qcom,cdc-micbias3-mv = <0x708>; | |
| qcom,cdc-micbias4-mv = <0x708>; | |
| interrupts = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e>; | |
| qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias"; | |
| qcom,cdc-dmic-sample-rate = <0x249f00>; | |
| compatible = "qcom,tasha-slim-pgd"; | |
| qcom,cdc-vdd-mic-bias-current = <0x3a98>; | |
| clock-names = "wcd_clk\0wcd_native_clk"; | |
| qcom,cdc-vdd-tx-h-current = <0x61a8>; | |
| cdc-vdd-px-supply = <0xec>; | |
| qcom,cdc-buck-sido-current = <0x249f0>; | |
| cdc-vdd-rx-h-supply = <0xec>; | |
| clocks = <0xeb 0xb7ba2274 0xeb 0xf0fbaf5b>; | |
| cdc-vdd-mic-bias-supply = <0xed>; | |
| qcom,cdc-reset-gpio = <0xbe 0x43 0x00>; | |
| qcom,cdc-slim-ifd = "tasha-slim-ifd"; | |
| qcom,cdc-vdd-px-voltage = <0x1b7740 0x1b7740>; | |
| qcom,cdc-vdd-buck-voltage = <0x1b7740 0x1b7740>; | |
| status = "disabled"; | |
| qcom,cdc-vdd-rx-h-voltage = <0x1b7740 0x1b7740>; | |
| qcom,cdc-static-supplies = "cdc-vdd-buck\0cdc-buck-sido\0cdc-vdd-tx-h\0cdc-vdd-rx-h\0cdc-vdd-px"; | |
| cdc-buck-sido-supply = <0xec>; | |
| qcom,wcd-rst-gpio-node = <0xea>; | |
| qcom,cdc-slim-ifd-elemental-addr = [00 00 a0 01 17 02]; | |
| cdc-vdd-buck-supply = <0xec>; | |
| cdc-vdd-tx-h-supply = <0xec>; | |
| qcom,cdc-vdd-mic-bias-voltage = <0x2faf08 0x2faf08>; | |
| qcom,cdc-vdd-tx-h-voltage = <0x1b7740 0x1b7740>; | |
| elemental-addr = [00 01 a0 01 17 02]; | |
| qcom,cdc-mclk-clk-rate = <0x927c00>; | |
| qcom,cdc-vdd-px-current = <0x2710>; | |
| interrupt-parent = <0xe9>; | |
| qcom,cdc-vdd-buck-current = <0x9eb10>; | |
| swr_master { | |
| compatible = "qcom,swr-wcd"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| wsa881x@21170213 { | |
| reg = <0x00 0x21170213>; | |
| compatible = "qcom,wsa881x"; | |
| qcom,spkr-sd-n-gpio = <0xbe 0x60 0x00>; | |
| phandle = <0x16b>; | |
| linux,phandle = <0x16b>; | |
| }; | |
| wsa881x@21170214 { | |
| reg = <0x00 0x21170214>; | |
| compatible = "qcom,wsa881x"; | |
| qcom,spkr-sd-n-gpio = <0xbe 0x60 0x00>; | |
| phandle = <0x16c>; | |
| linux,phandle = <0x16c>; | |
| }; | |
| wsa881x@20170211 { | |
| reg = <0x00 0x20170211>; | |
| compatible = "qcom,wsa881x"; | |
| qcom,spkr-sd-n-gpio = <0xbe 0x60 0x00>; | |
| phandle = <0x169>; | |
| linux,phandle = <0x169>; | |
| }; | |
| wsa881x@20170212 { | |
| reg = <0x00 0x20170212>; | |
| compatible = "qcom,wsa881x"; | |
| qcom,spkr-sd-n-gpio = <0xbe 0x60 0x00>; | |
| phandle = <0x16a>; | |
| linux,phandle = <0x16a>; | |
| }; | |
| }; | |
| }; | |
| msm_dai_slim { | |
| compatible = "qcom,msm-dai-slim"; | |
| status = "disabled"; | |
| elemental-addr = [ff ff ff fe 17 02]; | |
| }; | |
| }; | |
| venus-ddr-gov { | |
| compatible = "qcom,msm-vidc,governor,table"; | |
| status = "ok"; | |
| qcom,bus-freq-table { | |
| qcom,profile-dec-ubwc { | |
| qcom,load-busfreq-tbl = <0xef100 0x1cdea0 0xd2f00 0x17b650 0x77880 0xda818 0x69780 0xbeac8 0x3bc40 0x704e0 0x34bc0 0x497c8 0x1a5e0 0x31510 0x00 0x00>; | |
| qcom,ubwc-mode; | |
| qcom,codec-mask = <0xffffffff>; | |
| }; | |
| qcom,profile-dec { | |
| qcom,load-busfreq-tbl = <0xef100 0x241648 0xd2f00 0x1e2e90 0x77880 0x1149c8 0x69780 0xf2ad0 0x3bc40 0x8d9a0 0x34bc0 0x7a508 0x1a5e0 0x3e418 0x00 0x00>; | |
| qcom,codec-mask = <0xffffffff>; | |
| }; | |
| qcom,profile-enc { | |
| qcom,load-busfreq-tbl = <0xef100 0xfee20 0xd2f00 0xd88d8 0x77880 0xa2990 0x69780 0x8d1d0 0x3bc40 0x54790 0x34bc0 0x47888 0x1a5e0 0x24dd8 0x00 0x00>; | |
| qcom,codec-mask = <0x55555555>; | |
| }; | |
| }; | |
| }; | |
| qcom,cc-debug@1874000 { | |
| reg = <0x1874000 0x04>; | |
| #clock-cells = <0x01>; | |
| reg-names = "cc_base"; | |
| compatible = "qcom,cc-debug-8953"; | |
| clock-names = "debug_cpu_clk"; | |
| clocks = <0xb3 0x61a2945f>; | |
| phandle = <0xfb>; | |
| linux,phandle = <0xfb>; | |
| }; | |
| qcom,smdpkt { | |
| compatible = "qcom,smdpkt"; | |
| qcom,smdpkt-apr-apps2 { | |
| qcom,smdpkt-port-name = "apr_apps2"; | |
| qcom,smdpkt-dev-name = "apr_apps2"; | |
| qcom,smdpkt-remote = "adsp"; | |
| }; | |
| qcom,smdpkt-loopback { | |
| qcom,smdpkt-port-name = "LOOPBACK"; | |
| qcom,smdpkt-dev-name = "smd_pkt_loopback"; | |
| qcom,smdpkt-remote = "modem"; | |
| }; | |
| qcom,smdpkt-data40-cntl { | |
| qcom,smdpkt-port-name = "DATA40_CNTL"; | |
| qcom,smdpkt-dev-name = "smdcntl8"; | |
| qcom,smdpkt-remote = "modem"; | |
| }; | |
| qcom,smdpkt-data5-cntl { | |
| qcom,smdpkt-port-name = "DATA5_CNTL"; | |
| qcom,smdpkt-dev-name = "smdcntl0"; | |
| qcom,smdpkt-remote = "modem"; | |
| }; | |
| qcom,smdpkt-data22 { | |
| qcom,smdpkt-port-name = "DATA22"; | |
| qcom,smdpkt-dev-name = "smd22"; | |
| qcom,smdpkt-remote = "modem"; | |
| }; | |
| }; | |
| qcom,smdtty { | |
| compatible = "qcom,smdtty"; | |
| qcom,smdtty-data1 { | |
| qcom,smdtty-remote = "modem"; | |
| qcom,smdtty-port-name = "DATA1"; | |
| }; | |
| qcom,smdtty-data4 { | |
| qcom,smdtty-remote = "modem"; | |
| qcom,smdtty-port-name = "DATA4"; | |
| }; | |
| qcom,smdtty-apps-fm { | |
| qcom,smdtty-remote = "wcnss"; | |
| qcom,smdtty-port-name = "APPS_FM"; | |
| }; | |
| smdtty-apps-riva-ant-cmd { | |
| qcom,smdtty-remote = "wcnss"; | |
| qcom,smdtty-port-name = "APPS_RIVA_ANT_CMD"; | |
| }; | |
| smdtty-loopback { | |
| qcom,smdtty-remote = "modem"; | |
| qcom,smdtty-port-name = "LOOPBACK"; | |
| qcom,smdtty-dev-name = "LOOPBACK_TTY"; | |
| }; | |
| smdtty-apps-riva-bt-acl { | |
| qcom,smdtty-remote = "wcnss"; | |
| qcom,smdtty-port-name = "APPS_RIVA_BT_ACL"; | |
| }; | |
| qcom,smdtty-mbalbridge { | |
| qcom,smdtty-remote = "modem"; | |
| qcom,smdtty-port-name = "MBALBRIDGE"; | |
| }; | |
| smdtty-apps-riva-ant-data { | |
| qcom,smdtty-remote = "wcnss"; | |
| qcom,smdtty-port-name = "APPS_RIVA_ANT_DATA"; | |
| }; | |
| qcom,smdtty-apps-riva-bt-cmd { | |
| qcom,smdtty-remote = "wcnss"; | |
| qcom,smdtty-port-name = "APPS_RIVA_BT_CMD"; | |
| }; | |
| qcom,smdtty-data11 { | |
| qcom,smdtty-remote = "modem"; | |
| qcom,smdtty-port-name = "DATA11"; | |
| }; | |
| qcom,smdtty-data21 { | |
| qcom,smdtty-remote = "modem"; | |
| qcom,smdtty-port-name = "DATA21"; | |
| }; | |
| }; | |
| qseecom@85b00000 { | |
| reg = <0x85b00000 0x800000>; | |
| qcom,msm-bus,vectors-KBps = <0x37 0x200 0x00 0x00 0x37 0x200 0x00 0x00 0x37 0x200 0x1d4c0 0x124f80 0x37 0x200 0x60180 0x3c0f00>; | |
| qcom,ce-opp-freq = <0x5f5e100>; | |
| reg-names = "secapp-region"; | |
| qcom,support-bus-scaling; | |
| compatible = "qcom,qseecom"; | |
| clock-names = "core_clk_src\0core_clk\0iface_clk\0bus_clk"; | |
| qcom,msm-bus,name = "qseecom-noc"; | |
| qcom,hlos-ce-hw-instance = <0x00>; | |
| clocks = <0x37 0x37a21414 0x37 0xd390d2 0x37 0x94de4919 0x37 0xd4415c9b>; | |
| qcom,qsee-ce-hw-instance = <0x00>; | |
| qcom,hlos-num-ce-hw-instances = <0x01>; | |
| qcom,disk-encrypt-pipe-pair = <0x02>; | |
| qcom,msm-bus,num-cases = <0x04>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,support-fde; | |
| }; | |
| qcom,smp2pgpio-smp2p-1-in { | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x01>; | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,is-inbound; | |
| #interrupt-cells = <0x02>; | |
| qcom,entry-name = "smp2p"; | |
| phandle = <0x42>; | |
| interrupt-controller; | |
| gpio-controller; | |
| linux,phandle = <0x42>; | |
| }; | |
| qcom,smp2pgpio-smp2p-2-in { | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x02>; | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,is-inbound; | |
| #interrupt-cells = <0x02>; | |
| qcom,entry-name = "smp2p"; | |
| phandle = <0x46>; | |
| interrupt-controller; | |
| gpio-controller; | |
| linux,phandle = <0x46>; | |
| }; | |
| qcom,smp2pgpio-smp2p-4-in { | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x04>; | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,is-inbound; | |
| #interrupt-cells = <0x02>; | |
| qcom,entry-name = "smp2p"; | |
| phandle = <0x44>; | |
| interrupt-controller; | |
| gpio-controller; | |
| linux,phandle = <0x44>; | |
| }; | |
| qcom,mdss_rotator { | |
| qcom,mdss-has-downscale; | |
| qcom,msm-bus,vectors-KBps = <0x16 0x200 0x00 0x00 0x16 0x200 0x00 0x61a800 0x16 0x200 0x00 0x61a800>; | |
| rot-vdd-supply = <0x172>; | |
| compatible = "qcom,mdss_rotator"; | |
| clock-names = "iface_clk\0rot_core_clk"; | |
| qcom,mdss-wb-count = <0x01>; | |
| qcom,msm-bus,name = "mdss_rotator"; | |
| clocks = <0x37 0xbfb92ed3 0x18e 0x5b1f675e>; | |
| qcom,msm-bus,num-cases = <0x03>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,mdss-has-reg-bus; | |
| qcom,mdss-has-ubwc; | |
| qcom,supply-names = "rot-vdd"; | |
| qcom,mdss-rot-reg-bus { | |
| qcom,msm-bus,vectors-KBps = <0x01 0x24e 0x00 0x00 0x01 0x24e 0x00 0x12c00>; | |
| qcom,msm-bus,active-only; | |
| qcom,msm-bus,name = "mdss_rot_reg"; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| }; | |
| }; | |
| qcom,lpass@c200000 { | |
| reg = <0xc200000 0x100>; | |
| interrupts = <0x00 0x125 0x01>; | |
| vdd_cx-supply = <0xee>; | |
| qcom,firmware-name = "adsp"; | |
| qcom,gpio-err-fatal = <0x119 0x00 0x00>; | |
| qcom,gpio-err-ready = <0x119 0x01 0x00>; | |
| compatible = "qcom,pil-tz-generic"; | |
| clock-names = "xo\0scm_core_clk\0scm_iface_clk\0scm_bus_clk\0scm_core_clk_src"; | |
| qcom,gpio-force-stop = <0x11a 0x00 0x00>; | |
| qcom,gpio-stop-ack = <0x119 0x03 0x00>; | |
| clocks = <0x37 0xb72aa4c9 0x37 0xd390d2 0x37 0x94de4919 0x37 0xd4415c9b 0x37 0x37a21414>; | |
| qcom,vdd_cx-uV-uA = <0x180 0x186a0>; | |
| qcom,complete-ramdump; | |
| qcom,smem-id = <0x1a7>; | |
| qcom,ssctl-instance-id = <0x14>; | |
| qcom,proxy-reg-names = "vdd_cx"; | |
| qcom,sysmon-id = <0x01>; | |
| qcom,proxy-timeout-ms = <0x2710>; | |
| qcom,scm_core_clk_src-freq = <0x4c4b400>; | |
| qcom,gpio-proxy-unvote = <0x119 0x02 0x00>; | |
| qcom,pas-id = <0x01>; | |
| memory-region = <0x11b>; | |
| qcom,proxy-clock-names = "xo\0scm_core_clk\0scm_iface_clk\0scm_bus_clk\0scm_core_clk_src"; | |
| }; | |
| qcom,ipc_router { | |
| compatible = "qcom,ipc_router"; | |
| qcom,node-id = <0x01>; | |
| }; | |
| cpr4-ctrl@b018000 { | |
| reg = <0xb018000 0x4000 0xa4000 0x1000>; | |
| qcom,cpr-hw-closed-loop; | |
| qcom,cpr-enable; | |
| interrupts = <0x00 0x0f 0x01>; | |
| qcom,cpr-up-error-step-limit = <0x01>; | |
| reg-names = "cpr_ctrl\0fuse_base"; | |
| qcom,cpr-sensor-time = <0x3e8>; | |
| qcom,cpr-panic-reg-name-list = "CCI_SAW4_PMIC_STS\0CCI_SAW4_VCTL\0APCS_ALIAS0_APM_CTLER_STATUS\0APCS0_CPR_CORE_ADJ_MODE_REG"; | |
| compatible = "qcom,cpr4-msm8953-apss-regulator"; | |
| qcom,apm-threshold-voltage = <0xcf850>; | |
| qcom,cpr-down-error-step-limit = <0x01>; | |
| qcom,cpr-idle-cycles = <0x0f>; | |
| interrupt-names = "cpr"; | |
| qcom,cpr-ctrl-name = "apc"; | |
| qcom,cpr-aging-ref-voltage = <0xf1b30>; | |
| qcom,cpr-panic-reg-addr-list = <0xb1d2c18 0xb1d2900 0xb1112b0 0xb018798>; | |
| qcom,apm-ctrl = <0x126>; | |
| mem-acc-supply = <0x129>; | |
| qcom,cpr-count-repeat = <0x0e>; | |
| qcom,cpr-initial-temp-band = <0x00>; | |
| qcom,cpr-step-quot-init-max = <0x0e>; | |
| qcom,cpr-step-quot-init-min = <0x0c>; | |
| vdd-limit-supply = <0x128>; | |
| qcom,voltage-step = <0x1388>; | |
| qcom,apm-hysteresis-voltage = <0x1388>; | |
| qcom,cpr-temp-point-map = <0xfa 0x28a 0x352>; | |
| vdd-supply = <0x127>; | |
| qcom,cpr-count-mode = <0x00>; | |
| qcom,cpr-loop-time = <0x4c4b40>; | |
| thread@0 { | |
| qcom,cpr-consecutive-down = <0x02>; | |
| qcom,cpr-down-threshold = <0x01>; | |
| qcom,cpr-consecutive-up = <0x00>; | |
| qcom,cpr-up-threshold = <0x02>; | |
| qcom,cpr-thread-id = <0x00>; | |
| regulator { | |
| qcom,cpr-corner2-temp-core-voltage-adjustment = <0x00 0xffffec78 0xffffc568 0xffffc568>; | |
| qcom,corner-frequencies = <0x26e8f000 0x3dcc5000 0x538ab800 0x64b54000 0x6b931000 0x74bad000 0x7829b800 0x802c8000 0x839b6800 0x26e8f000 0x3dcc5000 0x538ab800 0x64b54000 0x6b931000 0x74bad000 0x7829b800 0x26e8f000 0x3dcc5000 0x538ab800 0x64b54000 0x6b931000 0x74bad000 0x7829b800 0x26e8f000 0x3dcc5000 0x538ab800 0x64b54000 0x6b931000 0x74bad000 0x7829b800 0x802c8000 0x839b6800>; | |
| regulator-name = "apc_corner"; | |
| qcom,cpr-speed-bin-corners = <0x09 0x00 0x07 0x00 0x00 0x00 0x07 0x09>; | |
| qcom,cpr-scaled-open-loop-voltage-as-ceiling; | |
| qcom,cpr-open-loop-voltage-fuse-adjustment = <0x00 0x00 0x00 0x00 0x61a8 0x00 0x1388 0x9c40 0x61a8 0x00 0x1388 0x9c40 0x61a8 0x00 0x1388 0x9c40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x61a8 0x00 0x1388 0x9c40 0x61a8 0x00 0x1388 0x9c40 0x61a8 0x00 0x1388 0x9c40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x61a8 0x00 0x1388 0x9c40 0x61a8 0x00 0x1388 0x9c40 0x61a8 0x00 0x1388 0x9c40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x61a8 0x00 0x1388 0x9c40 0x61a8 0x00 0x1388 0x9c40 0x61a8 0x00 0x1388 0x9c40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| qcom,cpr-floor-to-ceiling-max-range = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350>; | |
| qcom,cpr-corner1-temp-core-voltage-adjustment = <0x00 0xffffec78 0xffffc568 0xffffb1e0>; | |
| qcom,allow-quotient-interpolation; | |
| regulator-min-microvolt = <0x01>; | |
| qcom,allow-voltage-interpolation; | |
| qcom,cpr-corner4-temp-core-voltage-adjustment = <0x00 0xffffec78 0xffffc568 0x00>; | |
| qcom,allow-aging-voltage-adjustment = <0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x01>; | |
| qcom,cpr-fuse-corners = <0x04>; | |
| qcom,cpr-fuse-combos = <0x40>; | |
| qcom,cpr-corner-fmax-map = <0x01 0x02 0x04 0x09 0x00 0x00 0x00 0x00 0x01 0x02 0x04 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x02 0x04 0x07 0x01 0x02 0x04 0x09>; | |
| qcom,mem-acc-voltage = <0x01 0x01 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x01 0x01 0x02 0x02 0x02 0x02 0x02 0x01 0x01 0x02 0x02 0x02 0x02 0x02 0x01 0x01 0x02 0x02 0x02 0x02 0x02 0x02 0x02>; | |
| qcom,cpr-aging-max-voltage-adjustment = <0x3a98>; | |
| qcom,cpr-speed-bins = <0x08>; | |
| qcom,cpr-aging-ref-corner = <0x06>; | |
| qcom,cpr-voltage-ceiling = <0xae8f8 0xc0df0 0xd1f60 0xd32e8 0xe09c0 0xf1b30 0x104028 0x104028 0x104028 0xae8f8 0xc0df0 0xd1f60 0xd32e8 0xe09c0 0xf1b30 0x104028 0xae8f8 0xc0df0 0xd1f60 0xd32e8 0xe09c0 0xf1b30 0x104028 0xae8f8 0xc0df0 0xd1f60 0xd32e8 0xe09c0 0xf1b30 0x104028 0x104028 0x104028>; | |
| regulator-max-microvolt = <0x09>; | |
| qcom,cpr-corner3-temp-core-voltage-adjustment = <0x00 0xffffec78 0xffffc568 0x00>; | |
| qcom,cpr-aging-ro-scaling-factor = <0xaf0>; | |
| qcom,cpr-ro-scaling-factor = <0xe1a 0xece 0x00 0x898 0x992 0x906 0x87a 0x8a2 0x91a 0x8a2 0x9a6 0x924 0x30c 0xa8c 0x992 0x82a 0xe1a 0xece 0x00 0x898 0x992 0x906 0x87a 0x8a2 0x91a 0x8a2 0x9a6 0x924 0x30c 0xa8c 0x992 0x82a 0xe1a 0xece 0x00 0x898 0x992 0x906 0x87a 0x8a2 0x91a 0x8a2 0x9a6 0x924 0x30c 0xa8c 0x992 0x82a 0xe1a 0xece 0x00 0x898 0x992 0x906 0x87a 0x8a2 0x91a 0x8a2 0x9a6 0x924 0x30c 0xa8c 0x992 0x82a>; | |
| qcom,cpr-closed-loop-voltage-fuse-adjustment = <0x00 0x00 0x00 0x00 0x2710 0xffffc568 0x00 0x61a8 0x2710 0xffffc568 0x00 0x61a8 0xffffec78 0xffff8ad0 0xffffc568 0x2710 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x2710 0xffffc568 0x00 0x61a8 0x2710 0xffffc568 0x00 0x61a8 0xffffec78 0xffff8ad0 0xffffc568 0x2710 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x2710 0xffffc568 0x00 0x61a8 0x2710 0xffffc568 0x00 0x61a8 0xffffec78 0xffff8ad0 0xffffc568 0x2710 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x2710 0xffffc568 0x00 0x61a8 0x2710 0xffffc568 0x00 0x61a8 0xffffec78 0xffff8ad0 0xffffc568 0x2710 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| qcom,corner-allow-temp-adjustment = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00>; | |
| phandle = <0xf2>; | |
| qcom,cpr-voltage-floor = <0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120>; | |
| qcom,cpr-corners = <0x09 0x09 0x09 0x09 0x09 0x09 0x09 0x09 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x07 0x07 0x07 0x07 0x07 0x07 0x07 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x07 0x07 0x07 0x07 0x07 0x07 0x07 0x07 0x09 0x09 0x09 0x09 0x09 0x09 0x09 0x09>; | |
| linux,phandle = <0xf2>; | |
| qcom,cpr-misc-fuse-voltage-adjustment = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x7530 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x7530 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x7530 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x7530 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,csiphy@1b34000 { | |
| reg = <0x1b34000 0x1000 0x1b00030 0x04>; | |
| interrupts = <0x00 0x4e 0x00>; | |
| reg-names = "csiphy\0csiphy_clk_mux"; | |
| compatible = "qcom,csiphy-v3.5\0qcom,csiphy"; | |
| clock-names = "camss_top_ahb_clk\0ispif_ahb_clk\0csiphy_timer_src_clk\0csiphy_timer_clk\0camss_ahb_src\0camss_ahb_clk"; | |
| interrupt-names = "csiphy"; | |
| clocks = <0x37 0x4e814a78 0x37 0x3c0a858f 0x37 0xc8a309be 0x37 0xf8897589 0x37 0xf92304fb 0x37 0x9894b414>; | |
| cell-index = <0x00>; | |
| status = "ok"; | |
| qcom,clock-rates = <0x00 0x3ab06a0 0xbebc200 0x00 0x00 0x00>; | |
| }; | |
| qcom,csiphy@1b35000 { | |
| reg = <0x1b35000 0x1000 0x1b00038 0x04>; | |
| interrupts = <0x00 0x4f 0x00>; | |
| reg-names = "csiphy\0csiphy_clk_mux"; | |
| compatible = "qcom,csiphy-v3.5\0qcom,csiphy"; | |
| clock-names = "camss_top_ahb_clk\0ispif_ahb_clk\0csiphy_timer_src_clk\0csiphy_timer_clk\0camss_ahb_src\0camss_ahb_clk"; | |
| interrupt-names = "csiphy"; | |
| clocks = <0x37 0x4e814a78 0x37 0x3c0a858f 0x37 0x7c0fe23a 0x37 0x4d26438f 0x37 0xf92304fb 0x37 0x9894b414>; | |
| cell-index = <0x01>; | |
| status = "ok"; | |
| qcom,clock-rates = <0x00 0x3ab06a0 0xbebc200 0x00 0x00 0x00>; | |
| }; | |
| qcom,csiphy@1b36000 { | |
| reg = <0x1b36000 0x1000 0x1b00040 0x04>; | |
| interrupts = <0x00 0x13b 0x00>; | |
| reg-names = "csiphy\0csiphy_clk_mux"; | |
| compatible = "qcom,csiphy-v3.5\0qcom,csiphy"; | |
| clock-names = "camss_top_ahb_clk\0ispif_ahb_clk\0csiphy_timer_src_clk\0csiphy_timer_clk\0camss_ahb_src\0camss_ahb_clk"; | |
| interrupt-names = "csiphy"; | |
| clocks = <0x37 0x4e814a78 0x37 0x3c0a858f 0x37 0x62ffea9c 0x37 0xe768898c 0x37 0xf92304fb 0x37 0x9894b414>; | |
| cell-index = <0x02>; | |
| status = "ok"; | |
| qcom,clock-rates = <0x00 0x3ab06a0 0xbebc200 0x00 0x00 0x00>; | |
| }; | |
| stm@6002000 { | |
| reg = <0x6002000 0x1000 0x9280000 0x180000>; | |
| reg-names = "stm-base\0stm-data-base"; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-stm"; | |
| compatible = "arm,coresight-stm"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-child-ports = <0x07>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-child-list = <0x70>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x13>; | |
| }; | |
| qcom,rpm-master-stats@60150 { | |
| reg = <0x60150 0x5000>; | |
| compatible = "qcom,rpm-master-stats"; | |
| qcom,master-offset = <0x1000>; | |
| qcom,masters = "APSS\0MPSS\0PRONTO\0TZ\0LPASS"; | |
| qcom,master-stats-version = <0x02>; | |
| }; | |
| timer@b120000 { | |
| reg = <0xb120000 0x1000>; | |
| compatible = "arm,armv7-timer-mem"; | |
| clock-frequency = <0x124f800>; | |
| ranges; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| frame@b121000 { | |
| reg = <0xb121000 0x1000 0xb122000 0x1000>; | |
| interrupts = <0x00 0x08 0x04 0x00 0x07 0x04>; | |
| frame-number = <0x00>; | |
| }; | |
| frame@b123000 { | |
| reg = <0xb123000 0x1000>; | |
| interrupts = <0x00 0x09 0x04>; | |
| frame-number = <0x01>; | |
| status = "disabled"; | |
| }; | |
| frame@b124000 { | |
| reg = <0xb124000 0x1000>; | |
| interrupts = <0x00 0x0a 0x04>; | |
| frame-number = <0x02>; | |
| status = "disabled"; | |
| }; | |
| frame@b125000 { | |
| reg = <0xb125000 0x1000>; | |
| interrupts = <0x00 0x0b 0x04>; | |
| frame-number = <0x03>; | |
| status = "disabled"; | |
| }; | |
| frame@b126000 { | |
| reg = <0xb126000 0x1000>; | |
| interrupts = <0x00 0x0c 0x04>; | |
| frame-number = <0x04>; | |
| status = "disabled"; | |
| }; | |
| frame@b127000 { | |
| reg = <0xb127000 0x1000>; | |
| interrupts = <0x00 0x0d 0x04>; | |
| frame-number = <0x05>; | |
| status = "disabled"; | |
| }; | |
| frame@b128000 { | |
| reg = <0xb128000 0x1000>; | |
| interrupts = <0x00 0x0e 0x04>; | |
| frame-number = <0x06>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| audio_etm0 { | |
| qcom,inst-id = <0x05>; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-audio-etm0"; | |
| compatible = "qcom,coresight-remote-etm"; | |
| coresight-child-ports = <0x05>; | |
| coresight-child-list = <0x3c>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x34>; | |
| }; | |
| tpdm@6110000 { | |
| reg = <0x6110000 0x1000>; | |
| reg-names = "tpdm-base"; | |
| coresight-outports = <0x00>; | |
| coresight-name = "coresight-tpdm-dcc"; | |
| compatible = "qcom,coresight-tpdm"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| coresight-child-ports = <0x00>; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| coresight-child-list = <0x75>; | |
| coresight-nr-inports = <0x01>; | |
| coresight-id = <0x3a>; | |
| }; | |
| csr@6001000 { | |
| reg = <0x6001000 0x1000>; | |
| reg-names = "csr-base"; | |
| coresight-name = "coresight-csr"; | |
| compatible = "qcom,coresight-csr"; | |
| clock-names = "core_clk\0core_a_clk"; | |
| clocks = <0x37 0x1492202a 0x37 0xdd121669>; | |
| qcom,blk-size = <0x01>; | |
| coresight-nr-inports = <0x00>; | |
| coresight-id = <0x37>; | |
| }; | |
| qcom,cpubw { | |
| qcom,active-only; | |
| qcom,src-dst-ports = <0x01 0x200>; | |
| compatible = "qcom,devbw"; | |
| qcom,bw-tbl = <0x301 0x64b 0x84c 0xb71 0xc95 0x1098 0x1406 0x16e3 0x1808 0x192d 0x1bc0>; | |
| phandle = <0xf3>; | |
| linux,phandle = <0xf3>; | |
| governor = "cpufreq"; | |
| }; | |
| qcom,msm-adsp-loader { | |
| compatible = "qcom,adsp-loader"; | |
| qcom,adsp-state = <0x00>; | |
| }; | |
| qcom,gpubw { | |
| qcom,active-only; | |
| qcom,src-dst-ports = <0x1a 0x200>; | |
| compatible = "qcom,devbw"; | |
| qcom,bw-tbl = <0x00 0x64b 0x84c 0xb71 0xc96 0x1098 0x1406 0x16e3 0x1808 0x192d 0x1bc0>; | |
| phandle = <0x39>; | |
| linux,phandle = <0x39>; | |
| governor = "bw_vbif"; | |
| }; | |
| usb-otg-switch { | |
| gpio = <0xbe 0x5d 0x00>; | |
| regulator-name = "usb_otg_vreg"; | |
| compatible = "regulator-fixed"; | |
| enable-active-high; | |
| status = "ok"; | |
| phandle = <0x121>; | |
| linux,phandle = <0x121>; | |
| }; | |
| qcom,rmnet-ipa { | |
| qcom,ipa-advertise-sg-support; | |
| compatible = "qcom,rmnet-ipa"; | |
| qcom,rmnet-ipa-ssr; | |
| qcom,ipa-loaduC; | |
| }; | |
| qcom,limit_info-0 { | |
| qcom,emergency-frequency-mitigate; | |
| qcom,hotplug-mitigation-enable; | |
| qcom,boot-frequency-mitigate; | |
| qcom,temperature-sensor = <0xbf>; | |
| phandle = <0x0b>; | |
| linux,phandle = <0x0b>; | |
| }; | |
| qcom,limit_info-1 { | |
| qcom,emergency-frequency-mitigate; | |
| qcom,hotplug-mitigation-enable; | |
| qcom,boot-frequency-mitigate; | |
| qcom,temperature-sensor = <0xc0>; | |
| phandle = <0x10>; | |
| linux,phandle = <0x10>; | |
| }; | |
| qcom,limit_info-2 { | |
| qcom,emergency-frequency-mitigate; | |
| qcom,hotplug-mitigation-enable; | |
| qcom,boot-frequency-mitigate; | |
| qcom,temperature-sensor = <0xc1>; | |
| phandle = <0x13>; | |
| linux,phandle = <0x13>; | |
| }; | |
| qcom,limit_info-3 { | |
| qcom,emergency-frequency-mitigate; | |
| qcom,hotplug-mitigation-enable; | |
| qcom,boot-frequency-mitigate; | |
| qcom,temperature-sensor = <0xc2>; | |
| phandle = <0x16>; | |
| linux,phandle = <0x16>; | |
| }; | |
| qcom,limit_info-4 { | |
| qcom,emergency-frequency-mitigate; | |
| qcom,hotplug-mitigation-enable; | |
| qcom,boot-frequency-mitigate; | |
| qcom,temperature-sensor = <0xc3>; | |
| phandle = <0x19>; | |
| linux,phandle = <0x19>; | |
| }; | |
| qcom,limit_info-5 { | |
| qcom,emergency-frequency-mitigate; | |
| qcom,hotplug-mitigation-enable; | |
| qcom,boot-frequency-mitigate; | |
| qcom,temperature-sensor = <0xc4>; | |
| phandle = <0x1e>; | |
| linux,phandle = <0x1e>; | |
| }; | |
| qcom,limit_info-6 { | |
| qcom,emergency-frequency-mitigate; | |
| qcom,hotplug-mitigation-enable; | |
| qcom,boot-frequency-mitigate; | |
| qcom,temperature-sensor = <0xc5>; | |
| phandle = <0x21>; | |
| linux,phandle = <0x21>; | |
| }; | |
| qcom,limit_info-7 { | |
| qcom,emergency-frequency-mitigate; | |
| qcom,hotplug-mitigation-enable; | |
| qcom,boot-frequency-mitigate; | |
| qcom,temperature-sensor = <0xc6>; | |
| phandle = <0x24>; | |
| linux,phandle = <0x24>; | |
| }; | |
| }; | |
| cpus { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| cpu-map { | |
| cluster0 { | |
| core0 { | |
| cpu = <0x02>; | |
| }; | |
| core1 { | |
| cpu = <0x03>; | |
| }; | |
| core2 { | |
| cpu = <0x04>; | |
| }; | |
| core3 { | |
| cpu = <0x05>; | |
| }; | |
| }; | |
| cluster1 { | |
| core0 { | |
| cpu = <0x06>; | |
| }; | |
| core1 { | |
| cpu = <0x07>; | |
| }; | |
| core2 { | |
| cpu = <0x08>; | |
| }; | |
| core3 { | |
| cpu = <0x09>; | |
| }; | |
| }; | |
| }; | |
| cpu@100 { | |
| reg = <0x100>; | |
| next-level-cache = <0x1b>; | |
| compatible = "arm,cortex-a53"; | |
| qcom,acc = <0x18>; | |
| enable-method = "psci"; | |
| efficiency = <0x466>; | |
| device_type = "cpu"; | |
| qcom,limits-info = <0x19>; | |
| phandle = <0x06>; | |
| qcom,ea = <0x1a>; | |
| linux,phandle = <0x06>; | |
| l2-cache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x00>; | |
| cache-level = <0x02>; | |
| power-domain = <0x1c>; | |
| phandle = <0x1b>; | |
| linux,phandle = <0x1b>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x9000>; | |
| phandle = <0x32>; | |
| linux,phandle = <0x32>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x8800>; | |
| phandle = <0x2a>; | |
| linux,phandle = <0x2a>; | |
| }; | |
| }; | |
| cpu@101 { | |
| reg = <0x101>; | |
| next-level-cache = <0x1b>; | |
| compatible = "arm,cortex-a53"; | |
| qcom,acc = <0x1d>; | |
| enable-method = "psci"; | |
| efficiency = <0x466>; | |
| device_type = "cpu"; | |
| qcom,limits-info = <0x1e>; | |
| phandle = <0x07>; | |
| qcom,ea = <0x1f>; | |
| linux,phandle = <0x07>; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x9000>; | |
| phandle = <0x33>; | |
| linux,phandle = <0x33>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x8800>; | |
| phandle = <0x2b>; | |
| linux,phandle = <0x2b>; | |
| }; | |
| }; | |
| cpu@102 { | |
| reg = <0x102>; | |
| next-level-cache = <0x1b>; | |
| compatible = "arm,cortex-a53"; | |
| qcom,acc = <0x20>; | |
| enable-method = "psci"; | |
| efficiency = <0x466>; | |
| device_type = "cpu"; | |
| qcom,limits-info = <0x21>; | |
| phandle = <0x08>; | |
| qcom,ea = <0x22>; | |
| linux,phandle = <0x08>; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x9000>; | |
| phandle = <0x34>; | |
| linux,phandle = <0x34>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x8800>; | |
| phandle = <0x2c>; | |
| linux,phandle = <0x2c>; | |
| }; | |
| }; | |
| cpu@103 { | |
| reg = <0x103>; | |
| next-level-cache = <0x1b>; | |
| compatible = "arm,cortex-a53"; | |
| qcom,acc = <0x23>; | |
| enable-method = "psci"; | |
| efficiency = <0x466>; | |
| device_type = "cpu"; | |
| qcom,limits-info = <0x24>; | |
| phandle = <0x09>; | |
| qcom,ea = <0x25>; | |
| linux,phandle = <0x09>; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x9000>; | |
| phandle = <0x35>; | |
| linux,phandle = <0x35>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x8800>; | |
| phandle = <0x2d>; | |
| linux,phandle = <0x2d>; | |
| }; | |
| }; | |
| cpu@0 { | |
| reg = <0x00>; | |
| next-level-cache = <0x0d>; | |
| compatible = "arm,cortex-a53"; | |
| qcom,acc = <0x0a>; | |
| enable-method = "psci"; | |
| efficiency = <0x400>; | |
| device_type = "cpu"; | |
| qcom,limits-info = <0x0b>; | |
| phandle = <0x02>; | |
| qcom,ea = <0x0c>; | |
| linux,phandle = <0x02>; | |
| l2-cache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x00>; | |
| cache-level = <0x02>; | |
| power-domain = <0x0e>; | |
| phandle = <0x0d>; | |
| linux,phandle = <0x0d>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x9000>; | |
| phandle = <0x2e>; | |
| linux,phandle = <0x2e>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x8800>; | |
| phandle = <0x26>; | |
| linux,phandle = <0x26>; | |
| }; | |
| }; | |
| cpu@1 { | |
| reg = <0x01>; | |
| next-level-cache = <0x0d>; | |
| compatible = "arm,cortex-a53"; | |
| qcom,acc = <0x0f>; | |
| enable-method = "psci"; | |
| efficiency = <0x400>; | |
| device_type = "cpu"; | |
| qcom,limits-info = <0x10>; | |
| phandle = <0x03>; | |
| qcom,ea = <0x11>; | |
| linux,phandle = <0x03>; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x9000>; | |
| phandle = <0x2f>; | |
| linux,phandle = <0x2f>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x8800>; | |
| phandle = <0x27>; | |
| linux,phandle = <0x27>; | |
| }; | |
| }; | |
| cpu@2 { | |
| reg = <0x02>; | |
| next-level-cache = <0x0d>; | |
| compatible = "arm,cortex-a53"; | |
| qcom,acc = <0x12>; | |
| enable-method = "psci"; | |
| efficiency = <0x400>; | |
| device_type = "cpu"; | |
| qcom,limits-info = <0x13>; | |
| phandle = <0x04>; | |
| qcom,ea = <0x14>; | |
| linux,phandle = <0x04>; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x9000>; | |
| phandle = <0x30>; | |
| linux,phandle = <0x30>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x8800>; | |
| phandle = <0x28>; | |
| linux,phandle = <0x28>; | |
| }; | |
| }; | |
| cpu@3 { | |
| reg = <0x03>; | |
| next-level-cache = <0x0d>; | |
| compatible = "arm,cortex-a53"; | |
| qcom,acc = <0x15>; | |
| enable-method = "psci"; | |
| efficiency = <0x400>; | |
| device_type = "cpu"; | |
| qcom,limits-info = <0x16>; | |
| phandle = <0x05>; | |
| qcom,ea = <0x17>; | |
| linux,phandle = <0x05>; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x9000>; | |
| phandle = <0x31>; | |
| linux,phandle = <0x31>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x8800>; | |
| phandle = <0x29>; | |
| linux,phandle = <0x29>; | |
| }; | |
| }; | |
| }; | |
| psci { | |
| compatible = "arm,psci-1.0"; | |
| method = "smc"; | |
| }; | |
| chosen { | |
| linux,initrd-end = <0x83783ba8>; | |
| bootargs = "sched_enable_hmp=1 sched_enable_power_aware=1 console=ttyHSL0,115200,n8 androidboot.console=ttyHSL0 androidboot.hardware=qcom androidboot.selinux=permissive msm_rtb.filter=0x237 ehci-hcd.park=3 lpm_levels.sleep_disabled=1 androidboot.bootdevice=7824900.sdhci earlycon=msm_hsl_uart,0x78af000 buildvariant=user androidboot.emmc=true androidboot.verifiedbootstate=orange androidboot.veritymode=enforcing androidboot.keymaster=1 androidboot.serialno=b05c072b androidboot.baseband=msm mdss_mdp.panel=1:dsi:0:qcom,mdss_dsi_ili9881d_720p_video:1:none:cfg:single_dsi"; | |
| linux,initrd-start = <0x83600000>; | |
| }; | |
| firmware { | |
| android { | |
| compatible = "android,firmware"; | |
| fstab { | |
| compatible = "android,fstab"; | |
| system { | |
| dev = "/dev/block/platform/soc/7824900.sdhci/by-name/system"; | |
| type = "ext4"; | |
| mnt_flags = "ro,barrier=1,discard"; | |
| fsmgr_flags = "wait"; | |
| compatible = "android,system"; | |
| status = "ok"; | |
| }; | |
| vendor { | |
| dev = "/dev/block/platform/soc/7824900.sdhci/by-name/vendor"; | |
| type = "ext4"; | |
| mnt_flags = "ro,barrier=1,discard"; | |
| fsmgr_flags = "wait"; | |
| compatible = "android,vendor"; | |
| status = "ok"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| memory { | |
| reg = <0x00 0x80000000 0x00 0x40000000 0x00 0xc0000000 0x00 0x40000000>; | |
| device_type = "memory"; | |
| }; | |
| reserved-memory { | |
| ranges; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| other_ext_region@0 { | |
| reg = <0x00 0x85b00000 0x00 0xd00000>; | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| }; | |
| gpu_region@0 { | |
| size = <0x00 0x800000>; | |
| reusable; | |
| compatible = "shared-dma-pool"; | |
| alloc-ranges = <0x00 0x80000000 0x00 0x10000000>; | |
| alignment = <0x00 0x400000>; | |
| phandle = <0x36>; | |
| linux,phandle = <0x36>; | |
| }; | |
| splash_region@0x90001000 { | |
| reg = <0x00 0x90001000 0x00 0x13ff000>; | |
| label = "cont_splash_mem"; | |
| phandle = <0x18f>; | |
| linux,phandle = <0x18f>; | |
| }; | |
| adsp_region@0 { | |
| size = <0x00 0x400000>; | |
| reusable; | |
| compatible = "shared-dma-pool"; | |
| phandle = <0xfd>; | |
| linux,phandle = <0xfd>; | |
| }; | |
| modem_region@0 { | |
| reg = <0x00 0x86c00000 0x00 0x6a00000>; | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| phandle = <0x118>; | |
| linux,phandle = <0x118>; | |
| }; | |
| wcnss_fw_region@0 { | |
| reg = <0x00 0x8e700000 0x00 0x700000>; | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| phandle = <0x11f>; | |
| linux,phandle = <0x11f>; | |
| }; | |
| dfps_data_mem@90000000 { | |
| reg = <0x00 0x90000000 0x00 0x1000>; | |
| label = "dfps_data_mem"; | |
| phandle = <0x19d>; | |
| linux,phandle = <0x19d>; | |
| }; | |
| venus_region@0 { | |
| size = <0x00 0x800000>; | |
| reusable; | |
| compatible = "shared-dma-pool"; | |
| alloc-ranges = <0x00 0x80000000 0x00 0x10000000>; | |
| alignment = <0x00 0x400000>; | |
| phandle = <0x11c>; | |
| linux,phandle = <0x11c>; | |
| }; | |
| qseecom_region@0 { | |
| size = <0x00 0x1000000>; | |
| reusable; | |
| compatible = "shared-dma-pool"; | |
| alignment = <0x00 0x400000>; | |
| phandle = <0x3f>; | |
| linux,phandle = <0x3f>; | |
| }; | |
| secure_region@0 { | |
| size = <0x00 0x9800000>; | |
| reusable; | |
| compatible = "shared-dma-pool"; | |
| alignment = <0x00 0x400000>; | |
| phandle = <0x3e>; | |
| linux,phandle = <0x3e>; | |
| }; | |
| adsp_fw_region@0 { | |
| reg = <0x00 0x8d600000 0x00 0x1100000>; | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| phandle = <0x11b>; | |
| linux,phandle = <0x11b>; | |
| }; | |
| }; | |
| aliases { | |
| i2c2 = "/soc/i2c@78b6000"; | |
| i2c4 = "/soc/i2c@78b8000"; | |
| i2c5 = "/soc/i2c@7af5000"; | |
| i2c8 = "/soc/i2c@7af8000"; | |
| smd1 = "/soc/qcom,smdtty/qcom,smdtty-apps-fm"; | |
| smd2 = "/soc/qcom,smdtty/smdtty-apps-riva-bt-acl"; | |
| smd3 = "/soc/qcom,smdtty/qcom,smdtty-apps-riva-bt-cmd"; | |
| smd4 = "/soc/qcom,smdtty/qcom,smdtty-mbalbridge"; | |
| smd5 = "/soc/qcom,smdtty/smdtty-apps-riva-ant-cmd"; | |
| smd6 = "/soc/qcom,smdtty/smdtty-apps-riva-ant-data"; | |
| smd7 = "/soc/qcom,smdtty/qcom,smdtty-data1"; | |
| smd8 = "/soc/qcom,smdtty/qcom,smdtty-data4"; | |
| sdhc1 = "/soc/sdhci@7824900"; | |
| sdhc2 = "/soc/sdhci@7864900"; | |
| smd11 = "/soc/qcom,smdtty/qcom,smdtty-data11"; | |
| smd21 = "/soc/qcom,smdtty/qcom,smdtty-data21"; | |
| smd36 = "/soc/qcom,smdtty/smdtty-loopback"; | |
| }; | |
| }; |
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| /dts-v1/; | |
| /include/ "msm8953.dtsi" | |
| / { | |
| #address-cells = <2>; | |
| #size-cells = <2>; | |
| qcom,msm-id = <0x152 0x00>; | |
| qcom,board-id = <0x08 0x00>; | |
| model = "Qualcomm Technologies, Inc. SDM450"; | |
| compatible = "qcom,sdm450", "qcom,msm8953", "lk2nd,device"; | |
| lk2nd,pstore = <0xef000000 0x80000>; | |
| lk2nd,motorola-unitinfo = <1>; | |
| panel { | |
| compatible = "motorola,potter-panel"; | |
| qcom,mdss_dsi_mot_tianma_520_1080p_vid_v0 { | |
| compatible = "tianma,tl052vdpx02"; | |
| }; | |
| qcom,mdss_dsi_mot_boe_520_1080p_vid_v0 { | |
| compatible = "boe,bs052fhm-a00-6c01"; | |
| }; | |
| }; | |
| }; |
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