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SuperMicro X11SSH-F
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Readme.md

What is the procedure to turn the following hardware into an OpenCore Hackintosh setup

from a SuperMicro X11SSH-F w/Asus dual STRIX RX580?

CPU: Intel E3-1220 v6 KabyLake
CPUID: 0906E9h
Raw
cpuid-i.txt
CPU 0:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
model = 0xe (14)
stepping id = 0x9 (9)
extended family = 0x0 (0)
extended model = 0x9 (9)
(simple synth) = Intel Core i5-7000 / i5-7000K / i5-7000T / i7-7000 / E3-15x5MV6 / i3-7100H / i5-7000HQ / i7-7000HQ (Kaby Lake), 14nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x0 (0)
cpu count = 0x10 (16)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
virtual-8086 mode enhancement = true
debugging extensions = true
page size extensions = true
time stamp counter = true
RDMSR and WRMSR support = true
physical address extensions = true
machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
memory type range registers = true
PTE global bit = true
machine check architecture = true
conditional move/compare instruction = true
page attribute table = true
page size extension = true
processor serial number = false
CLFLUSH instruction = true
debug store = true
thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
self snoop = true
hyper-threading / multi-core supported = true
therm. monitor = true
IA64 = false
pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
FMA instruction = true
CMPXCHG16B instruction = true
xTPR disable = true
perfmon and debug = true
process context identifiers = true
direct cache access = false
SSE4.1 extensions = true
SSE4.2 extensions = true
extended xAPIC support = true
MOVBE instruction = true
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID 4
0xb6: instruction TLB: 4K, 8-way, 128 entries
0xf0: 64 byte prefetching
0xc3: L2 TLB: 4K/2M pages, 6-way, 1536 entries
processor serial number: dead-beef-dead-beef-dead-beef
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
extra threads sharing this cache = 0x1 (1)
extra processor cores on this die = 0x7 (7)
system coherency line size = 0x3f (63)
physical line partitions = 0x0 (0)
ways of associativity = 0x7 (7)
ways of associativity = 0x0 (0)
WBINVD/INVD behavior on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets - 1 (s) = 63
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
extra threads sharing this cache = 0x1 (1)
extra processor cores on this die = 0x7 (7)
system coherency line size = 0x3f (63)
physical line partitions = 0x0 (0)
ways of associativity = 0x7 (7)
ways of associativity = 0x0 (0)
WBINVD/INVD behavior on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets - 1 (s) = 63
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
extra threads sharing this cache = 0x1 (1)
extra processor cores on this die = 0x7 (7)
system coherency line size = 0x3f (63)
physical line partitions = 0x0 (0)
ways of associativity = 0x3 (3)
ways of associativity = 0x0 (0)
WBINVD/INVD behavior on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets - 1 (s) = 1023
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
extra threads sharing this cache = 0xf (15)
extra processor cores on this die = 0x7 (7)
system coherency line size = 0x3f (63)
physical line partitions = 0x0 (0)
ways of associativity = 0xf (15)
ways of associativity = 0x6 (6)
WBINVD/INVD behavior on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets - 1 (s) = 8191
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x2 (2)
number of C4 sub C-states using MWAIT = 0x4 (4)
number of C5 sub C-states using MWAIT = 0x1 (1)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = true
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = true
HWP notification = true
HWP activity window = true
HWP energy performance preference = true
HWP package level request = false
HDC base registers = true
digital thermometer thresholds = 0x2 (2)
ACNT/MCNT supported performance measure = true
ACNT2 available = false
performance-energy bias capability = true
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = true
SGX: Software Guard Extensions supported = true
BMI instruction = true
HLE hardware lock elision = true
AVX2: advanced vector extensions 2 = true
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = true
enhanced REP MOVSB/STOSB = true
INVPCID instruction = true
RTM: restricted transactional memory = true
QM: quality of service monitoring = false
deprecated FPU CS/DS = true
intel memory protection extensions = true
PQE: platform quality of service enforce = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = true
ADX instructions = true
SMAP: supervisor mode access prevention = true
AVX512IFMA: fused multiply add = false
CLFLUSHOPT instruction = true
CLWB instruction = false
Intel processor trace = true
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
SGX_LC: SGX launch config supported = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 0
Architecture Performance Monitoring Features (0xa/eax):
version ID = 0x4 (4)
number of counters per logical processor = 0x8 (8)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
Architecture Performance Monitoring Features (0xa/ebx):
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
Architecture Performance Monitoring Features (0xa/edx):
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
x2APIC features / processor topology (0xb):
--- level 0 (thread) ---
bits to shift APIC ID to get next = 0x1 (1)
logical processors at this level = 0x1 (1)
level number = 0x0 (0)
level type = thread (1)
extended APIC ID = 0
--- level 1 (core) ---
bits to shift APIC ID to get next = 0x4 (4)
logical processors at this level = 0x4 (4)
level number = 0x1 (1)
level type = core (2)
extended APIC ID = 0
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x0000001f
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = true
XCR0 supported: MPX BNDCSR = true
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
bytes required by fields in XCR0 = 0x00000440 (1088)
bytes required by XSAVE/XRSTOR area = 0x00000440 (1088)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = true
XGETBV instruction = true
XSAVES/XRSTORS instructions = true
SAVE area size in bytes = 0x000003c0 (960)
IA32_XSS lower 32 bits valid bit field mask = 0x00000100
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
MPX BNDREGS features (0xd/3):
MPX BNDREGS save state byte size = 0x00000040 (64)
MPX BNDREGS save state byte offset = 0x000003c0 (960)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
MPX BNDCSR features (0xd/4):
MPX BNDCSR save state byte size = 0x00000040 (64)
MPX BNDCSR save state byte offset = 0x00000400 (1024)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
PT features (0xd/8):
PT save state byte size = 0x00000080 (128)
PT save state byte offset = 0x00000000 (0)
supported in IA32_XSS or XCR0 = IA32_XSS (supervisor state)
64-byte alignment in compacted XSAVE = false
Quality of Service Monitoring Resource Type (0xf/0):
Maximum range of RMID = 0
supports L3 cache QoS monitoring = false
Resource Director Technology allocation (0x10/0):
L3 cache allocation technology supported = false
L2 cache allocation technology supported = false
0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
SGX capability (0x12/0):
SGX1 supported = false
SGX2 supported = false
MISCSELECT.EXINFO supported: #PF & #GP = false
MaxEnclaveSize_Not64 (log2) = 0x0 (0)
MaxEnclaveSize_64 (log2) = 0x0 (0)
0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
Intel Processor Trace (0x14):
IA32_RTIT_CR3_MATCH is accessible = true
configurable PSB & cycle-accurate = true
IP & TraceStop filtering; PT preserve = true
MTC timing packet; suppress COFI-based = true
PTWRITE support = false
power event trace support = false
IA32_RTIT_CTL can enable tracing = true
ToPA can hold many output entries = true
single-range output scheme = true
output to trace transport = false
IP payloads have LIP values & CS = false
configurable address ranges = 0x2 (2)
supported MTC periods bitmask = 0x249 (585)
supported cycle threshold bitmask = 0x3fff (16383)
supported config PSB freq bitmask = 0x3f (63)
Time Stamp Counter/Core Crystal Clock Information (0x15):
TSC/clock ratio = 250/2
nominal core crystal clock = 0 Hz
Processor Frequency Information (0x16):
Core Base Frequency (MHz) = 0xbb8 (3000)
Core Maximum Frequency (MHz) = 0xdac (3500)
Bus (Reference) Frequency (MHz) = 0x64 (100)
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = true
3DNow! PREFETCH/PREFETCHW instructions = true
brand = "Intel(R) Xeon(R) CPU E3-1220 v6 @ 3.00GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
temperature sensing diode = false
frequency ID (FID) control = false
voltage ID (VID) control = false
thermal trip (TTP) = false
thermal monitor (TM) = false
software thermal control (STC) = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x27 (39)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Logical CPU cores (0x80000008/ecx):
number of CPU cores - 1 = 0x0 (0)
ApicIdCoreIdSize = 0x0 (0)
(multi-processing synth): multi-core (c=4)
(multi-processing method): Intel leaf 0xb
(APIC widths synth): CORE_width=4 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
(synth) = Intel Core i5-7000 / i5-7000K / i5-7000T / i7-7000 / E3-15x5MV6 / i3-7100H / i5-7000HQ / i7-7000HQ (Kaby Lake), 14nm
CPU 1:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
model = 0xe (14)
stepping id = 0x9 (9)
extended family = 0x0 (0)
extended model = 0x9 (9)
(simple synth) = Intel Core i5-7000 / i5-7000K / i5-7000T / i7-7000 / E3-15x5MV6 / i3-7100H / i5-7000HQ / i7-7000HQ (Kaby Lake), 14nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x2 (2)
cpu count = 0x10 (16)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
virtual-8086 mode enhancement = true
debugging extensions = true
page size extensions = true
time stamp counter = true
RDMSR and WRMSR support = true
physical address extensions = true
machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
memory type range registers = true
PTE global bit = true
machine check architecture = true
conditional move/compare instruction = true
page attribute table = true
page size extension = true
processor serial number = false
CLFLUSH instruction = true
debug store = true
thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
self snoop = true
hyper-threading / multi-core supported = true
therm. monitor = true
IA64 = false
pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
FMA instruction = true
CMPXCHG16B instruction = true
xTPR disable = true
perfmon and debug = true
process context identifiers = true
direct cache access = false
SSE4.1 extensions = true
SSE4.2 extensions = true
extended xAPIC support = true
MOVBE instruction = true
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID 4
0xb6: instruction TLB: 4K, 8-way, 128 entries
0xf0: 64 byte prefetching
0xc3: L2 TLB: 4K/2M pages, 6-way, 1536 entries
processor serial number: dead-beef-dead-beef-dead-beef
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
extra threads sharing this cache = 0x1 (1)
extra processor cores on this die = 0x7 (7)
system coherency line size = 0x3f (63)
physical line partitions = 0x0 (0)
ways of associativity = 0x7 (7)
ways of associativity = 0x0 (0)
WBINVD/INVD behavior on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets - 1 (s) = 63
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
extra threads sharing this cache = 0x1 (1)
extra processor cores on this die = 0x7 (7)
system coherency line size = 0x3f (63)
physical line partitions = 0x0 (0)
ways of associativity = 0x7 (7)
ways of associativity = 0x0 (0)
WBINVD/INVD behavior on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets - 1 (s) = 63
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
extra threads sharing this cache = 0x1 (1)
extra processor cores on this die = 0x7 (7)
system coherency line size = 0x3f (63)
physical line partitions = 0x0 (0)
ways of associativity = 0x3 (3)
ways of associativity = 0x0 (0)
WBINVD/INVD behavior on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets - 1 (s) = 1023
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
extra threads sharing this cache = 0xf (15)
extra processor cores on this die = 0x7 (7)
system coherency line size = 0x3f (63)
physical line partitions = 0x0 (0)
ways of associativity = 0xf (15)
ways of associativity = 0x6 (6)
WBINVD/INVD behavior on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets - 1 (s) = 8191
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x2 (2)
number of C4 sub C-states using MWAIT = 0x4 (4)
number of C5 sub C-states using MWAIT = 0x1 (1)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = true
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = true
HWP notification = true
HWP activity window = true
HWP energy performance preference = true
HWP package level request = false
HDC base registers = true
digital thermometer thresholds = 0x2 (2)
ACNT/MCNT supported performance measure = true
ACNT2 available = false
performance-energy bias capability = true
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = true
SGX: Software Guard Extensions supported = true
BMI instruction = true
HLE hardware lock elision = true
AVX2: advanced vector extensions 2 = true
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = true
enhanced REP MOVSB/STOSB = true
INVPCID instruction = true
RTM: restricted transactional memory = true
QM: quality of service monitoring = false
deprecated FPU CS/DS = true
intel memory protection extensions = true
PQE: platform quality of service enforce = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = true
ADX instructions = true
SMAP: supervisor mode access prevention = true
AVX512IFMA: fused multiply add = false
CLFLUSHOPT instruction = true
CLWB instruction = false
Intel processor trace = true
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
SGX_LC: SGX launch config supported = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 0
Architecture Performance Monitoring Features (0xa/eax):
version ID = 0x4 (4)
number of counters per logical processor = 0x8 (8)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
Architecture Performance Monitoring Features (0xa/ebx):
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
Architecture Performance Monitoring Features (0xa/edx):
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
x2APIC features / processor topology (0xb):
--- level 0 (thread) ---
bits to shift APIC ID to get next = 0x1 (1)
logical processors at this level = 0x1 (1)
level number = 0x0 (0)
level type = thread (1)
extended APIC ID = 2
--- level 1 (core) ---
bits to shift APIC ID to get next = 0x4 (4)
logical processors at this level = 0x4 (4)
level number = 0x1 (1)
level type = core (2)
extended APIC ID = 2
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x0000001f
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = true
XCR0 supported: MPX BNDCSR = true
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
bytes required by fields in XCR0 = 0x00000440 (1088)
bytes required by XSAVE/XRSTOR area = 0x00000440 (1088)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = true
XGETBV instruction = true
XSAVES/XRSTORS instructions = true
SAVE area size in bytes = 0x000003c0 (960)
IA32_XSS lower 32 bits valid bit field mask = 0x00000100
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
MPX BNDREGS features (0xd/3):
MPX BNDREGS save state byte size = 0x00000040 (64)
MPX BNDREGS save state byte offset = 0x000003c0 (960)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
MPX BNDCSR features (0xd/4):
MPX BNDCSR save state byte size = 0x00000040 (64)
MPX BNDCSR save state byte offset = 0x00000400 (1024)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
PT features (0xd/8):
PT save state byte size = 0x00000080 (128)
PT save state byte offset = 0x00000000 (0)
supported in IA32_XSS or XCR0 = IA32_XSS (supervisor state)
64-byte alignment in compacted XSAVE = false
Quality of Service Monitoring Resource Type (0xf/0):
Maximum range of RMID = 0
supports L3 cache QoS monitoring = false
Resource Director Technology allocation (0x10/0):
L3 cache allocation technology supported = false
L2 cache allocation technology supported = false
0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
SGX capability (0x12/0):
SGX1 supported = false
SGX2 supported = false
MISCSELECT.EXINFO supported: #PF & #GP = false
MaxEnclaveSize_Not64 (log2) = 0x0 (0)
MaxEnclaveSize_64 (log2) = 0x0 (0)
0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
Intel Processor Trace (0x14):
IA32_RTIT_CR3_MATCH is accessible = true
configurable PSB & cycle-accurate = true
IP & TraceStop filtering; PT preserve = true
MTC timing packet; suppress COFI-based = true
PTWRITE support = false
power event trace support = false
IA32_RTIT_CTL can enable tracing = true
ToPA can hold many output entries = true
single-range output scheme = true
output to trace transport = false
IP payloads have LIP values & CS = false
configurable address ranges = 0x2 (2)
supported MTC periods bitmask = 0x249 (585)
supported cycle threshold bitmask = 0x3fff (16383)
supported config PSB freq bitmask = 0x3f (63)
Time Stamp Counter/Core Crystal Clock Information (0x15):
TSC/clock ratio = 250/2
nominal core crystal clock = 0 Hz
Processor Frequency Information (0x16):
Core Base Frequency (MHz) = 0xbb8 (3000)
Core Maximum Frequency (MHz) = 0xdac (3500)
Bus (Reference) Frequency (MHz) = 0x64 (100)
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = true
3DNow! PREFETCH/PREFETCHW instructions = true
brand = "Intel(R) Xeon(R) CPU E3-1220 v6 @ 3.00GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
temperature sensing diode = false
frequency ID (FID) control = false
voltage ID (VID) control = false
thermal trip (TTP) = false
thermal monitor (TM) = false
software thermal control (STC) = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x27 (39)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Logical CPU cores (0x80000008/ecx):
number of CPU cores - 1 = 0x0 (0)
ApicIdCoreIdSize = 0x0 (0)
(multi-processing synth): multi-core (c=4)
(multi-processing method): Intel leaf 0xb
(APIC widths synth): CORE_width=4 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=0
(synth) = Intel Core i5-7000 / i5-7000K / i5-7000T / i7-7000 / E3-15x5MV6 / i3-7100H / i5-7000HQ / i7-7000HQ (Kaby Lake), 14nm
CPU 2:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
model = 0xe (14)
stepping id = 0x9 (9)
extended family = 0x0 (0)
extended model = 0x9 (9)
(simple synth) = Intel Core i5-7000 / i5-7000K / i5-7000T / i7-7000 / E3-15x5MV6 / i3-7100H / i5-7000HQ / i7-7000HQ (Kaby Lake), 14nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x4 (4)
cpu count = 0x10 (16)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
virtual-8086 mode enhancement = true
debugging extensions = true
page size extensions = true
time stamp counter = true
RDMSR and WRMSR support = true
physical address extensions = true
machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
memory type range registers = true
PTE global bit = true
machine check architecture = true
conditional move/compare instruction = true
page attribute table = true
page size extension = true
processor serial number = false
CLFLUSH instruction = true
debug store = true
thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
self snoop = true
hyper-threading / multi-core supported = true
therm. monitor = true
IA64 = false
pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
FMA instruction = true
CMPXCHG16B instruction = true
xTPR disable = true
perfmon and debug = true
process context identifiers = true
direct cache access = false
SSE4.1 extensions = true
SSE4.2 extensions = true
extended xAPIC support = true
MOVBE instruction = true
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID 4
0xb6: instruction TLB: 4K, 8-way, 128 entries
0xf0: 64 byte prefetching
0xc3: L2 TLB: 4K/2M pages, 6-way, 1536 entries
processor serial number: dead-beef-dead-beef-dead-beef
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
extra threads sharing this cache = 0x1 (1)
extra processor cores on this die = 0x7 (7)
system coherency line size = 0x3f (63)
physical line partitions = 0x0 (0)
ways of associativity = 0x7 (7)
ways of associativity = 0x0 (0)
WBINVD/INVD behavior on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets - 1 (s) = 63
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
extra threads sharing this cache = 0x1 (1)
extra processor cores on this die = 0x7 (7)
system coherency line size = 0x3f (63)
physical line partitions = 0x0 (0)
ways of associativity = 0x7 (7)
ways of associativity = 0x0 (0)
WBINVD/INVD behavior on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets - 1 (s) = 63
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
extra threads sharing this cache = 0x1 (1)
extra processor cores on this die = 0x7 (7)
system coherency line size = 0x3f (63)
physical line partitions = 0x0 (0)
ways of associativity = 0x3 (3)
ways of associativity = 0x0 (0)
WBINVD/INVD behavior on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets - 1 (s) = 1023
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
extra threads sharing this cache = 0xf (15)
extra processor cores on this die = 0x7 (7)
system coherency line size = 0x3f (63)
physical line partitions = 0x0 (0)
ways of associativity = 0xf (15)
ways of associativity = 0x6 (6)
WBINVD/INVD behavior on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets - 1 (s) = 8191
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x2 (2)
number of C4 sub C-states using MWAIT = 0x4 (4)
number of C5 sub C-states using MWAIT = 0x1 (1)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = true
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = true
HWP notification = true
HWP activity window = true
HWP energy performance preference = true
HWP package level request = false
HDC base registers = true
digital thermometer thresholds = 0x2 (2)
ACNT/MCNT supported performance measure = true
ACNT2 available = false
performance-energy bias capability = true
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = true
SGX: Software Guard Extensions supported = true
BMI instruction = true
HLE hardware lock elision = true
AVX2: advanced vector extensions 2 = true
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = true
enhanced REP MOVSB/STOSB = true
INVPCID instruction = true
RTM: restricted transactional memory = true
QM: quality of service monitoring = false
deprecated FPU CS/DS = true
intel memory protection extensions = true
PQE: platform quality of service enforce = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = true
ADX instructions = true
SMAP: supervisor mode access prevention = true
AVX512IFMA: fused multiply add = false
CLFLUSHOPT instruction = true
CLWB instruction = false
Intel processor trace = true
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
SGX_LC: SGX launch config supported = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 0
Architecture Performance Monitoring Features (0xa/eax):
version ID = 0x4 (4)
number of counters per logical processor = 0x8 (8)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
Architecture Performance Monitoring Features (0xa/ebx):
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
Architecture Performance Monitoring Features (0xa/edx):
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
x2APIC features / processor topology (0xb):
--- level 0 (thread) ---
bits to shift APIC ID to get next = 0x1 (1)
logical processors at this level = 0x1 (1)
level number = 0x0 (0)
level type = thread (1)
extended APIC ID = 4
--- level 1 (core) ---
bits to shift APIC ID to get next = 0x4 (4)
logical processors at this level = 0x4 (4)
level number = 0x1 (1)
level type = core (2)
extended APIC ID = 4
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x0000001f
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = true
XCR0 supported: MPX BNDCSR = true
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
bytes required by fields in XCR0 = 0x00000440 (1088)
bytes required by XSAVE/XRSTOR area = 0x00000440 (1088)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = true
XGETBV instruction = true
XSAVES/XRSTORS instructions = true
SAVE area size in bytes = 0x000003c0 (960)
IA32_XSS lower 32 bits valid bit field mask = 0x00000100
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
MPX BNDREGS features (0xd/3):
MPX BNDREGS save state byte size = 0x00000040 (64)
MPX BNDREGS save state byte offset = 0x000003c0 (960)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
MPX BNDCSR features (0xd/4):
MPX BNDCSR save state byte size = 0x00000040 (64)
MPX BNDCSR save state byte offset = 0x00000400 (1024)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
PT features (0xd/8):
PT save state byte size = 0x00000080 (128)
PT save state byte offset = 0x00000000 (0)
supported in IA32_XSS or XCR0 = IA32_XSS (supervisor state)
64-byte alignment in compacted XSAVE = false
Quality of Service Monitoring Resource Type (0xf/0):
Maximum range of RMID = 0
supports L3 cache QoS monitoring = false
Resource Director Technology allocation (0x10/0):
L3 cache allocation technology supported = false
L2 cache allocation technology supported = false
0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
SGX capability (0x12/0):
SGX1 supported = false
SGX2 supported = false
MISCSELECT.EXINFO supported: #PF & #GP = false
MaxEnclaveSize_Not64 (log2) = 0x0 (0)
MaxEnclaveSize_64 (log2) = 0x0 (0)
0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
Intel Processor Trace (0x14):
IA32_RTIT_CR3_MATCH is accessible = true
configurable PSB & cycle-accurate = true
IP & TraceStop filtering; PT preserve = true
MTC timing packet; suppress COFI-based = true
PTWRITE support = false
power event trace support = false
IA32_RTIT_CTL can enable tracing = true
ToPA can hold many output entries = true
single-range output scheme = true
output to trace transport = false
IP payloads have LIP values & CS = false
configurable address ranges = 0x2 (2)
supported MTC periods bitmask = 0x249 (585)
supported cycle threshold bitmask = 0x3fff (16383)
supported config PSB freq bitmask = 0x3f (63)
Time Stamp Counter/Core Crystal Clock Information (0x15):
TSC/clock ratio = 250/2
nominal core crystal clock = 0 Hz
Processor Frequency Information (0x16):
Core Base Frequency (MHz) = 0xbb8 (3000)
Core Maximum Frequency (MHz) = 0xdac (3500)
Bus (Reference) Frequency (MHz) = 0x64 (100)
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = true
3DNow! PREFETCH/PREFETCHW instructions = true
brand = "Intel(R) Xeon(R) CPU E3-1220 v6 @ 3.00GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
temperature sensing diode = false
frequency ID (FID) control = false
voltage ID (VID) control = false
thermal trip (TTP) = false
thermal monitor (TM) = false
software thermal control (STC) = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x27 (39)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Logical CPU cores (0x80000008/ecx):
number of CPU cores - 1 = 0x0 (0)
ApicIdCoreIdSize = 0x0 (0)
(multi-processing synth): multi-core (c=4)
(multi-processing method): Intel leaf 0xb
(APIC widths synth): CORE_width=4 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=0
(synth) = Intel Core i5-7000 / i5-7000K / i5-7000T / i7-7000 / E3-15x5MV6 / i3-7100H / i5-7000HQ / i7-7000HQ (Kaby Lake), 14nm
CPU 3:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
model = 0xe (14)
stepping id = 0x9 (9)
extended family = 0x0 (0)
extended model = 0x9 (9)
(simple synth) = Intel Core i5-7000 / i5-7000K / i5-7000T / i7-7000 / E3-15x5MV6 / i3-7100H / i5-7000HQ / i7-7000HQ (Kaby Lake), 14nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x6 (6)
cpu count = 0x10 (16)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
virtual-8086 mode enhancement = true
debugging extensions = true
page size extensions = true
time stamp counter = true
RDMSR and WRMSR support = true
physical address extensions = true
machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
memory type range registers = true
PTE global bit = true
machine check architecture = true
conditional move/compare instruction = true
page attribute table = true
page size extension = true
processor serial number = false
CLFLUSH instruction = true
debug store = true
thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
self snoop = true
hyper-threading / multi-core supported = true
therm. monitor = true
IA64 = false
pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
FMA instruction = true
CMPXCHG16B instruction = true
xTPR disable = true
perfmon and debug = true
process context identifiers = true
direct cache access = false
SSE4.1 extensions = true
SSE4.2 extensions = true
extended xAPIC support = true
MOVBE instruction = true
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID 4
0xb6: instruction TLB: 4K, 8-way, 128 entries
0xf0: 64 byte prefetching
0xc3: L2 TLB: 4K/2M pages, 6-way, 1536 entries
processor serial number: dead-beef-dead-beef-dead-beef
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
extra threads sharing this cache = 0x1 (1)
extra processor cores on this die = 0x7 (7)
system coherency line size = 0x3f (63)
physical line partitions = 0x0 (0)
ways of associativity = 0x7 (7)
ways of associativity = 0x0 (0)
WBINVD/INVD behavior on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets - 1 (s) = 63
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
extra threads sharing this cache = 0x1 (1)
extra processor cores on this die = 0x7 (7)
system coherency line size = 0x3f (63)
physical line partitions = 0x0 (0)
ways of associativity = 0x7 (7)
ways of associativity = 0x0 (0)
WBINVD/INVD behavior on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets - 1 (s) = 63
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
extra threads sharing this cache = 0x1 (1)
extra processor cores on this die = 0x7 (7)
system coherency line size = 0x3f (63)
physical line partitions = 0x0 (0)
ways of associativity = 0x3 (3)
ways of associativity = 0x0 (0)
WBINVD/INVD behavior on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets - 1 (s) = 1023
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
extra threads sharing this cache = 0xf (15)
extra processor cores on this die = 0x7 (7)
system coherency line size = 0x3f (63)
physical line partitions = 0x0 (0)
ways of associativity = 0xf (15)
ways of associativity = 0x6 (6)
WBINVD/INVD behavior on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets - 1 (s) = 8191
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x2 (2)
number of C4 sub C-states using MWAIT = 0x4 (4)
number of C5 sub C-states using MWAIT = 0x1 (1)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = true
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = true
HWP notification = true
HWP activity window = true
HWP energy performance preference = true
HWP package level request = false
HDC base registers = true
digital thermometer thresholds = 0x2 (2)
ACNT/MCNT supported performance measure = true
ACNT2 available = false
performance-energy bias capability = true
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = true
SGX: Software Guard Extensions supported = true
BMI instruction = true
HLE hardware lock elision = true
AVX2: advanced vector extensions 2 = true
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = true
enhanced REP MOVSB/STOSB = true
INVPCID instruction = true
RTM: restricted transactional memory = true
QM: quality of service monitoring = false
deprecated FPU CS/DS = true
intel memory protection extensions = true
PQE: platform quality of service enforce = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = true
ADX instructions = true
SMAP: supervisor mode access prevention = true
AVX512IFMA: fused multiply add = false
CLFLUSHOPT instruction = true
CLWB instruction = false
Intel processor trace = true
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
SGX_LC: SGX launch config supported = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 0
Architecture Performance Monitoring Features (0xa/eax):
version ID = 0x4 (4)
number of counters per logical processor = 0x8 (8)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
Architecture Performance Monitoring Features (0xa/ebx):
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
Architecture Performance Monitoring Features (0xa/edx):
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
x2APIC features / processor topology (0xb):
--- level 0 (thread) ---
bits to shift APIC ID to get next = 0x1 (1)
logical processors at this level = 0x1 (1)
level number = 0x0 (0)
level type = thread (1)
extended APIC ID = 6
--- level 1 (core) ---
bits to shift APIC ID to get next = 0x4 (4)
logical processors at this level = 0x4 (4)
level number = 0x1 (1)
level type = core (2)
extended APIC ID = 6
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x0000001f
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = true
XCR0 supported: MPX BNDCSR = true
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
bytes required by fields in XCR0 = 0x00000440 (1088)
bytes required by XSAVE/XRSTOR area = 0x00000440 (1088)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = true
XGETBV instruction = true
XSAVES/XRSTORS instructions = true
SAVE area size in bytes = 0x000003c0 (960)
IA32_XSS lower 32 bits valid bit field mask = 0x00000100
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
MPX BNDREGS features (0xd/3):
MPX BNDREGS save state byte size = 0x00000040 (64)
MPX BNDREGS save state byte offset = 0x000003c0 (960)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
MPX BNDCSR features (0xd/4):
MPX BNDCSR save state byte size = 0x00000040 (64)
MPX BNDCSR save state byte offset = 0x00000400 (1024)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
PT features (0xd/8):
PT save state byte size = 0x00000080 (128)
PT save state byte offset = 0x00000000 (0)
supported in IA32_XSS or XCR0 = IA32_XSS (supervisor state)
64-byte alignment in compacted XSAVE = false
Quality of Service Monitoring Resource Type (0xf/0):
Maximum range of RMID = 0
supports L3 cache QoS monitoring = false
Resource Director Technology allocation (0x10/0):
L3 cache allocation technology supported = false
L2 cache allocation technology supported = false
0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
SGX capability (0x12/0):
SGX1 supported = false
SGX2 supported = false
MISCSELECT.EXINFO supported: #PF & #GP = false
MaxEnclaveSize_Not64 (log2) = 0x0 (0)
MaxEnclaveSize_64 (log2) = 0x0 (0)
0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
Intel Processor Trace (0x14):
IA32_RTIT_CR3_MATCH is accessible = true
configurable PSB & cycle-accurate = true
IP & TraceStop filtering; PT preserve = true
MTC timing packet; suppress COFI-based = true
PTWRITE support = false
power event trace support = false
IA32_RTIT_CTL can enable tracing = true
ToPA can hold many output entries = true
single-range output scheme = true
output to trace transport = false
IP payloads have LIP values & CS = false
configurable address ranges = 0x2 (2)
supported MTC periods bitmask = 0x249 (585)
supported cycle threshold bitmask = 0x3fff (16383)
supported config PSB freq bitmask = 0x3f (63)
Time Stamp Counter/Core Crystal Clock Information (0x15):
TSC/clock ratio = 250/2
nominal core crystal clock = 0 Hz
Processor Frequency Information (0x16):
Core Base Frequency (MHz) = 0xbb8 (3000)
Core Maximum Frequency (MHz) = 0xdac (3500)
Bus (Reference) Frequency (MHz) = 0x64 (100)
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = true
3DNow! PREFETCH/PREFETCHW instructions = true
brand = "Intel(R) Xeon(R) CPU E3-1220 v6 @ 3.00GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
temperature sensing diode = false
frequency ID (FID) control = false
voltage ID (VID) control = false
thermal trip (TTP) = false
thermal monitor (TM) = false
software thermal control (STC) = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x27 (39)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Logical CPU cores (0x80000008/ecx):
number of CPU cores - 1 = 0x0 (0)
ApicIdCoreIdSize = 0x0 (0)
(multi-processing synth): multi-core (c=4)
(multi-processing method): Intel leaf 0xb
(APIC widths synth): CORE_width=4 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=0
(synth) = Intel Core i5-7000 / i5-7000K / i5-7000T / i7-7000 / E3-15x5MV6 / i3-7100H / i5-7000HQ / i7-7000HQ (Kaby Lake), 14nm
Raw
lshw.xml
<?xml version="1.0" standalone="yes" ?>
<!-- generated by lshw-B.02.18 -->
<!-- GCC 7.3.0 -->
<!-- Linux 4.15.0-99-generic #100-Ubuntu SMP Wed Apr 22 20:32:56 UTC 2020 x86_64 -->
<!-- GNU libc 2 (glibc 2.27) -->
<list>
<node id="smws01" claimed="true" class="system" handle="DMI:0001">
<description>System</description>
<product>Super Server (To be filled by O.E.M.)</product>
<vendor>Supermicro</vendor>
<version>0123456789</version>
<serial>0123456789</serial>
<width units="bits">64</width>
<configuration>
<setting id="boot" value="normal" />
<setting id="chassis" value="server" />
<setting id="family" value="To be filled by O.E.M." />
<setting id="sku" value="To be filled by O.E.M." />
<setting id="uuid" value="00000000-0000-0000-0000-AC1F6B1A04B8" />
</configuration>
<capabilities>
<capability id="smbios-3.0" >SMBIOS version 3.0</capability>
<capability id="dmi-3.0" >DMI version 3.0</capability>
<capability id="smp" >Symmetric Multi-Processing</capability>
<capability id="vsyscall32" >32-bit processes</capability>
</capabilities>
<node id="core" claimed="true" class="bus" handle="DMI:0002">
<description>Motherboard</description>
<product>X11SSH-F</product>
<vendor>Supermicro</vendor>
<physid>0</physid>
<version>1.01</version>
<serial>Blah blah blah</serial>
<slot>To be filled by O.E.M.</slot>
<node id="firmware" claimed="true" class="memory" handle="">
<description>BIOS</description>
<vendor>American Megatrends Inc.</vendor>
<physid>0</physid>
<version>2.0b</version>
<date>07/27/2017</date>
<size units="bytes">65536</size>
<capacity units="bytes">16711680</capacity>
<capabilities>
<capability id="pci" >PCI bus</capability>
<capability id="upgrade" >BIOS EEPROM can be upgraded</capability>
<capability id="shadowing" >BIOS shadowing</capability>
<capability id="cdboot" >Booting from CD-ROM/DVD</capability>
<capability id="bootselect" >Selectable boot path</capability>
<capability id="socketedrom" >BIOS ROM is socketed</capability>
<capability id="edd" >Enhanced Disk Drive extensions</capability>
<capability id="int13floppy1200" >5.25&quot; 1.2MB floppy</capability>
<capability id="int13floppy720" >3.5&quot; 720KB floppy</capability>
<capability id="int13floppy2880" >3.5&quot; 2.88MB floppy</capability>
<capability id="int5printscreen" >Print Screen key</capability>
<capability id="int14serial" >INT14 serial line control</capability>
<capability id="int17printer" >INT17 printer control</capability>
<capability id="acpi" >ACPI</capability>
<capability id="usb" >USB legacy emulation</capability>
<capability id="biosbootspecification" >BIOS boot specification</capability>
<capability id="uefi" >UEFI specification is supported</capability>
</capabilities>
</node>
<node id="cache:0" claimed="true" class="memory" handle="DMI:002A">
<description>L1 cache</description>
<physid>2a</physid>
<slot>L1 Cache</slot>
<size units="bytes">131072</size>
<capacity units="bytes">131072</capacity>
<configuration>
<setting id="level" value="1" />
</configuration>
<capabilities>
<capability id="synchronous" >Synchronous</capability>
<capability id="internal" >Internal</capability>
<capability id="write-back" >Write-back</capability>
<capability id="data" >Data cache</capability>
</capabilities>
</node>
<node id="cache:1" claimed="true" class="memory" handle="DMI:002B">
<description>L1 cache</description>
<physid>2b</physid>
<slot>L1 Cache</slot>
<size units="bytes">131072</size>
<capacity units="bytes">131072</capacity>
<configuration>
<setting id="level" value="1" />
</configuration>
<capabilities>
<capability id="synchronous" >Synchronous</capability>
<capability id="internal" >Internal</capability>
<capability id="write-back" >Write-back</capability>
<capability id="instruction" >Instruction cache</capability>
</capabilities>
</node>
<node id="cache:2" claimed="true" class="memory" handle="DMI:002C">
<description>L2 cache</description>
<physid>2c</physid>
<slot>L2 Cache</slot>
<size units="bytes">1048576</size>
<capacity units="bytes">1048576</capacity>
<configuration>
<setting id="level" value="2" />
</configuration>
<capabilities>
<capability id="synchronous" >Synchronous</capability>
<capability id="internal" >Internal</capability>
<capability id="write-back" >Write-back</capability>
<capability id="unified" >Unified cache</capability>
</capabilities>
</node>
<node id="cache:3" claimed="true" class="memory" handle="DMI:002D">
<description>L3 cache</description>
<physid>2d</physid>
<slot>L3 Cache</slot>
<size units="bytes">8388608</size>
<capacity units="bytes">8388608</capacity>
<configuration>
<setting id="level" value="3" />
</configuration>
<capabilities>
<capability id="synchronous" >Synchronous</capability>
<capability id="internal" >Internal</capability>
<capability id="write-back" >Write-back</capability>
<capability id="unified" >Unified cache</capability>
</capabilities>
</node>
<node id="cpu" claimed="true" class="processor" handle="DMI:002E">
<description>CPU</description>
<product>Intel(R) Xeon(R) CPU E3-1220 v6 @ 3.00GHz</product>
<vendor>Intel Corp.</vendor>
<physid>2e</physid>
<businfo>cpu@0</businfo>
<version>Intel(R) Xeon(R) CPU E3-1220 v6 @ 3.00GHz</version>
<serial>To Be Filled By O.E.M.</serial>
<slot>CPU</slot>
<size units="Hz">3377318000</size>
<capacity units="Hz">3500000000</capacity>
<width units="bits">64</width>
<clock units="Hz">100000000</clock>
<configuration>
<setting id="cores" value="4" />
<setting id="enabledcores" value="4" />
<setting id="threads" value="4" />
</configuration>
<capabilities>
<capability id="x86-64" >64bits extensions (x86-64)</capability>
<capability id="fpu" >mathematical co-processor</capability>
<capability id="fpu_exception" >FPU exceptions reporting</capability>
<capability id="wp" />
<capability id="vme" >virtual mode extensions</capability>
<capability id="de" >debugging extensions</capability>
<capability id="pse" >page size extensions</capability>
<capability id="tsc" >time stamp counter</capability>
<capability id="msr" >model-specific registers</capability>
<capability id="pae" >4GB+ memory addressing (Physical Address Extension)</capability>
<capability id="mce" >machine check exceptions</capability>
<capability id="cx8" >compare and exchange 8-byte</capability>
<capability id="apic" >on-chip advanced programmable interrupt controller (APIC)</capability>
<capability id="sep" >fast system calls</capability>
<capability id="mtrr" >memory type range registers</capability>
<capability id="pge" >page global enable</capability>
<capability id="mca" >machine check architecture</capability>
<capability id="cmov" >conditional move instruction</capability>
<capability id="pat" >page attribute table</capability>
<capability id="pse36" >36-bit page size extensions</capability>
<capability id="clflush" />
<capability id="dts" >debug trace and EMON store MSRs</capability>
<capability id="acpi" >thermal control (ACPI)</capability>
<capability id="mmx" >multimedia extensions (MMX)</capability>
<capability id="fxsr" >fast floating point save/restore</capability>
<capability id="sse" >streaming SIMD extensions (SSE)</capability>
<capability id="sse2" >streaming SIMD extensions (SSE2)</capability>
<capability id="ss" >self-snoop</capability>
<capability id="ht" >HyperThreading</capability>
<capability id="tm" >thermal interrupt and status</capability>
<capability id="pbe" >pending break event</capability>
<capability id="syscall" >fast system calls</capability>
<capability id="nx" >no-execute bit (NX)</capability>
<capability id="pdpe1gb" />
<capability id="rdtscp" />
<capability id="constant_tsc" />
<capability id="art" />
<capability id="arch_perfmon" />
<capability id="pebs" />
<capability id="bts" />
<capability id="rep_good" />
<capability id="nopl" />
<capability id="xtopology" />
<capability id="nonstop_tsc" />
<capability id="cpuid" />
<capability id="aperfmperf" />
<capability id="tsc_known_freq" />
<capability id="pni" />
<capability id="pclmulqdq" />
<capability id="dtes64" />
<capability id="monitor" />
<capability id="ds_cpl" />
<capability id="vmx" />
<capability id="smx" />
<capability id="est" />
<capability id="tm2" />
<capability id="ssse3" />
<capability id="sdbg" />
<capability id="fma" />
<capability id="cx16" />
<capability id="xtpr" />
<capability id="pdcm" />
<capability id="pcid" />
<capability id="sse4_1" />
<capability id="sse4_2" />
<capability id="x2apic" />
<capability id="movbe" />
<capability id="popcnt" />
<capability id="tsc_deadline_timer" />
<capability id="aes" />
<capability id="xsave" />
<capability id="avx" />
<capability id="f16c" />
<capability id="rdrand" />
<capability id="lahf_lm" />
<capability id="abm" />
<capability id="3dnowprefetch" />
<capability id="cpuid_fault" />
<capability id="epb" />
<capability id="invpcid_single" />
<capability id="pti" />
<capability id="ssbd" />
<capability id="ibrs" />
<capability id="ibpb" />
<capability id="stibp" />
<capability id="tpr_shadow" />
<capability id="vnmi" />
<capability id="flexpriority" />
<capability id="ept" />
<capability id="vpid" />
<capability id="fsgsbase" />
<capability id="tsc_adjust" />
<capability id="bmi1" />
<capability id="hle" />
<capability id="avx2" />
<capability id="smep" />
<capability id="bmi2" />
<capability id="erms" />
<capability id="invpcid" />
<capability id="rtm" />
<capability id="mpx" />
<capability id="rdseed" />
<capability id="adx" />
<capability id="smap" />
<capability id="clflushopt" />
<capability id="intel_pt" />
<capability id="xsaveopt" />
<capability id="xsavec" />
<capability id="xgetbv1" />
<capability id="xsaves" />
<capability id="dtherm" />
<capability id="ida" />
<capability id="arat" />
<capability id="pln" />
<capability id="pts" />
<capability id="hwp" />
<capability id="hwp_notify" />
<capability id="hwp_act_window" />
<capability id="hwp_epp" />
<capability id="md_clear" />
<capability id="flush_l1d" />
<capability id="cpufreq" >CPU Frequency scaling</capability>
</capabilities>
</node>
<node id="memory" claimed="true" class="memory" handle="DMI:002F">
<description>System Memory</description>
<physid>2f</physid>
<slot>System board or motherboard</slot>
<size units="bytes">17179869184</size>
<configuration>
<setting id="errordetection" value="ecc" />
</configuration>
<capabilities>
<capability id="ecc" >Single-bit error-correcting code (ECC)</capability>
</capabilities>
<node id="bank:0" claimed="true" class="memory" handle="DMI:0030">
<description>[empty]</description>
<physid>0</physid>
<slot>DIMMA1</slot>
</node>
<node id="bank:1" claimed="true" class="memory" handle="DMI:0031">
<description>DIMM DDR4 Synchronous 2667 MHz (0.4 ns)</description>
<vendor>Undefined</vendor>
<physid>1</physid>
<serial>000003B6</serial>
<slot>DIMMA2</slot>
<size units="bytes">17179869184</size>
<width units="bits">64</width>
<clock units="Hz">2667000000</clock>
</node>
<node id="bank:2" claimed="true" class="memory" handle="DMI:0032">
<description>[empty]</description>
<physid>2</physid>
<slot>DIMMB1</slot>
</node>
<node id="bank:3" claimed="true" class="memory" handle="DMI:0033">
<description>[empty]</description>
<physid>3</physid>
<slot>DIMMB2</slot>
</node>
</node>
<node id="pci" claimed="true" class="bridge" handle="PCIBUS:0000:00">
<description>Host bridge</description>
<product>Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers</product>
<vendor>Intel Corporation</vendor>
<physid>100</physid>
<businfo>pci@0000:00:00.0</businfo>
<version>05</version>
<width units="bits">32</width>
<clock units="Hz">33000000</clock>
<configuration>
<setting id="driver" value="ie31200_edac" />
</configuration>
<resources>
<resource type="irq" value="0" />
</resources>
<node id="generic:0" class="generic" handle="PCI:0000:00:13.0">
<description>Non-VGA unclassified device</description>
<product>100 Series/C230 Series Chipset Family Integrated Sensor Hub</product>
<vendor>Intel Corporation</vendor>
<physid>13</physid>
<businfo>pci@0000:00:13.0</businfo>
<version>31</version>
<width units="bits">64</width>
<clock units="Hz">33000000</clock>
<configuration>
<setting id="latency" value="0" />
</configuration>
<capabilities>
<capability id="pm" >Power Management</capability>
<capability id="cap_list" >PCI capabilities listing</capability>
</capabilities>
<resources>
<resource type="memory" value="df422000-df422fff" />
</resources>
</node>
<node id="usb" claimed="true" class="bus" handle="PCI:0000:00:14.0">
<description>USB controller</description>
<product>100 Series/C230 Series Chipset Family USB 3.0 xHCI Controller</product>
<vendor>Intel Corporation</vendor>
<physid>14</physid>
<businfo>pci@0000:00:14.0</businfo>
<version>31</version>
<width units="bits">64</width>
<clock units="Hz">33000000</clock>
<configuration>
<setting id="driver" value="xhci_hcd" />
<setting id="latency" value="0" />
</configuration>
<capabilities>
<capability id="pm" >Power Management</capability>
<capability id="msi" >Message Signalled Interrupts</capability>
<capability id="xhci" />
<capability id="bus_master" >bus mastering</capability>
<capability id="cap_list" >PCI capabilities listing</capability>
</capabilities>
<resources>
<resource type="irq" value="28" />
<resource type="memory" value="df400000-df40ffff" />
</resources>
<node id="usbhost:0" claimed="true" class="bus" handle="USB:1:1">
<product>xHCI Host Controller</product>
<vendor>Linux 4.15.0-99-generic xhci-hcd</vendor>
<physid>0</physid>
<businfo>usb@1</businfo>
<logicalname>usb1</logicalname>
<version>4.15</version>
<configuration>
<setting id="driver" value="hub" />
<setting id="slots" value="16" />
<setting id="speed" value="480Mbit/s" />
</configuration>
<capabilities>
<capability id="usb-2.00" >USB 2.0</capability>
</capabilities>
<node id="usb:0" claimed="true" class="input" handle="USB:1:4">
<description>Keyboard</description>
<product>USB Keyboard</product>
<vendor>Holtek Semiconductor, Inc.</vendor>
<physid>4</physid>
<businfo>usb@1:4</businfo>
<version>1.01</version>
<configuration>
<setting id="driver" value="usbhid" />
<setting id="maxpower" value="100mA" />
<setting id="speed" value="2Mbit/s" />
</configuration>
<capabilities>
<capability id="usb-1.10" >USB 1.1</capability>
</capabilities>
</node>
<node id="usb:1" claimed="true" class="bus" handle="USB:1:2">
<description>USB hub</description>
<product>Hub</product>
<vendor>ATEN International Co., Ltd</vendor>
<physid>e</physid>
<businfo>usb@1:e</businfo>
<version>0.00</version>
<configuration>
<setting id="driver" value="hub" />
<setting id="maxpower" value="100mA" />
<setting id="slots" value="4" />
<setting id="speed" value="480Mbit/s" />
</configuration>
<capabilities>
<capability id="usb-2.00" >USB 2.0</capability>
</capabilities>
<node id="usb" claimed="true" class="input" handle="USB:1:3">
<description>Keyboard</description>
<vendor>ATEN International Co., Ltd</vendor>
<physid>1</physid>
<businfo>usb@1:e.1</businfo>
<version>1.00</version>
<configuration>
<setting id="driver" value="usbhid" />
<setting id="maxpower" value="160mA" />
<setting id="speed" value="2Mbit/s" />
</configuration>
<capabilities>
<capability id="usb-1.10" >USB 1.1</capability>
</capabilities>
</node>
</node>
</node>
<node id="usbhost:1" claimed="true" class="bus" handle="USB:2:1">
<product>xHCI Host Controller</product>
<vendor>Linux 4.15.0-99-generic xhci-hcd</vendor>
<physid>1</physid>
<businfo>usb@2</businfo>
<logicalname>usb2</logicalname>
<version>4.15</version>
<configuration>
<setting id="driver" value="hub" />
<setting id="slots" value="10" />
<setting id="speed" value="5000Mbit/s" />
</configuration>
<capabilities>
<capability id="usb-3.00" />
</capabilities>
</node>
</node>
<node id="generic:1" claimed="true" class="generic" handle="PCI:0000:00:14.2">
<description>Signal processing controller</description>
<product>100 Series/C230 Series Chipset Family Thermal Subsystem</product>
<vendor>Intel Corporation</vendor>
<physid>14.2</physid>
<businfo>pci@0000:00:14.2</businfo>
<version>31</version>
<width units="bits">64</width>
<clock units="Hz">33000000</clock>
<configuration>
<setting id="driver" value="intel_pch_thermal" />
<setting id="latency" value="0" />
</configuration>
<capabilities>
<capability id="pm" >Power Management</capability>
<capability id="msi" >Message Signalled Interrupts</capability>
<capability id="cap_list" >PCI capabilities listing</capability>
</capabilities>
<resources>
<resource type="irq" value="18" />
<resource type="memory" value="df421000-df421fff" />
</resources>
</node>
<node id="communication:0" class="communication" handle="PCI:0000:00:16.0">
<description>Communication controller</description>
<product>100 Series/C230 Series Chipset Family MEI Controller #1</product>
<vendor>Intel Corporation</vendor>
<physid>16</physid>
<businfo>pci@0000:00:16.0</businfo>
<version>31</version>
<width units="bits">64</width>
<clock units="Hz">33000000</clock>
<configuration>
<setting id="latency" value="0" />
</configuration>
<capabilities>
<capability id="pm" >Power Management</capability>
<capability id="msi" >Message Signalled Interrupts</capability>
<capability id="bus_master" >bus mastering</capability>
<capability id="cap_list" >PCI capabilities listing</capability>
</capabilities>
<resources>
<resource type="memory" value="df420000-df420fff" />
</resources>
</node>
<node id="communication:1" class="communication" handle="PCI:0000:00:16.1">
<description>Communication controller</description>
<product>100 Series/C230 Series Chipset Family MEI Controller #2</product>
<vendor>Intel Corporation</vendor>
<physid>16.1</physid>
<businfo>pci@0000:00:16.1</businfo>
<version>31</version>
<width units="bits">64</width>
<clock units="Hz">33000000</clock>
<configuration>
<setting id="latency" value="0" />
</configuration>
<capabilities>
<capability id="pm" >Power Management</capability>
<capability id="msi" >Message Signalled Interrupts</capability>
<capability id="bus_master" >bus mastering</capability>
<capability id="cap_list" >PCI capabilities listing</capability>
</capabilities>
<resources>
<resource type="memory" value="df41f000-df41ffff" />
</resources>
</node>
<node id="storage" claimed="true" class="storage" handle="PCI:0000:00:17.0">
<description>SATA controller</description>
<product>Q170/Q150/B150/H170/H110/Z170/CM236 Chipset SATA Controller [AHCI Mode]</product>
<vendor>Intel Corporation</vendor>
<physid>17</physid>
<businfo>pci@0000:00:17.0</businfo>
<version>31</version>
<width units="bits">32</width>
<clock units="Hz">66000000</clock>
<configuration>
<setting id="driver" value="ahci" />
<setting id="latency" value="0" />
</configuration>
<capabilities>
<capability id="storage" />
<capability id="msi" >Message Signalled Interrupts</capability>
<capability id="pm" >Power Management</capability>
<capability id="ahci_1.0" />
<capability id="bus_master" >bus mastering</capability>
<capability id="cap_list" >PCI capabilities listing</capability>
</capabilities>
<resources>
<resource type="irq" value="43" />
<resource type="memory" value="df410000-df411fff" />
<resource type="memory" value="df41e000-df41e0ff" />
<resource type="ioport" value="f050(size=8)" />
<resource type="ioport" value="f040(size=4)" />
<resource type="ioport" value="f020(size=32)" />
<resource type="memory" value="df41d000-df41d7ff" />
</resources>
</node>
<node id="pci:0" claimed="true" class="bridge" handle="PCIBUS:0000:01">
<description>PCI bridge</description>
<product>100 Series/C230 Series Chipset Family PCI Express Root Port #1</product>
<vendor>Intel Corporation</vendor>
<physid>1c</physid>
<businfo>pci@0000:00:1c.0</businfo>
<version>f1</version>
<width units="bits">32</width>
<clock units="Hz">33000000</clock>
<configuration>
<setting id="driver" value="pcieport" />
</configuration>
<capabilities>
<capability id="pci" />
<capability id="pciexpress" >PCI Express</capability>
<capability id="msi" >Message Signalled Interrupts</capability>
<capability id="pm" >Power Management</capability>
<capability id="normal_decode" />
<capability id="bus_master" >bus mastering</capability>
<capability id="cap_list" >PCI capabilities listing</capability>
</capabilities>
<resources>
<resource type="irq" value="24" />
<resource type="ioport" value="e000(size=4096)" />
<resource type="memory" value="df300000-df3fffff" />
</resources>
<node id="network" disabled="true" claimed="true" class="network" handle="PCI:0000:01:00.0">
<description>Ethernet interface</description>
<product>I210 Gigabit Network Connection</product>
<vendor>Intel Corporation</vendor>
<physid>0</physid>
<businfo>pci@0000:01:00.0</businfo>
<logicalname>eno1</logicalname>
<version>03</version>
<serial>ac:1f:6b:1a:04:b8</serial>
<capacity>1000000000</capacity>
<width units="bits">32</width>
<clock units="Hz">33000000</clock>
<configuration>
<setting id="autonegotiation" value="on" />
<setting id="broadcast" value="yes" />
<setting id="driver" value="igb" />
<setting id="driverversion" value="5.4.0-k" />
<setting id="firmware" value="3.25, 0x800005cc" />
<setting id="latency" value="0" />
<setting id="link" value="no" />
<setting id="multicast" value="yes" />
<setting id="port" value="twisted pair" />
</configuration>
<capabilities>
<capability id="pm" >Power Management</capability>
<capability id="msi" >Message Signalled Interrupts</capability>
<capability id="msix" >MSI-X</capability>
<capability id="pciexpress" >PCI Express</capability>
<capability id="bus_master" >bus mastering</capability>
<capability id="cap_list" >PCI capabilities listing</capability>
<capability id="ethernet" />
<capability id="physical" >Physical interface</capability>
<capability id="tp" >twisted pair</capability>
<capability id="10bt" >10Mbit/s</capability>
<capability id="10bt-fd" >10Mbit/s (full duplex)</capability>
<capability id="100bt" >100Mbit/s</capability>
<capability id="100bt-fd" >100Mbit/s (full duplex)</capability>
<capability id="1000bt-fd" >1Gbit/s (full duplex)</capability>
<capability id="autonegotiation" >Auto-negotiation</capability>
</capabilities>
<resources>
<resource type="irq" value="16" />
<resource type="memory" value="df300000-df37ffff" />
<resource type="ioport" value="e000(size=32)" />
<resource type="memory" value="df380000-df383fff" />
</resources>
</node>
</node>
<node id="pci:1" claimed="true" class="bridge" handle="PCIBUS:0000:02">
<description>PCI bridge</description>
<product>100 Series/C230 Series Chipset Family PCI Express Root Port #2</product>
<vendor>Intel Corporation</vendor>
<physid>1c.1</physid>
<businfo>pci@0000:00:1c.1</businfo>
<version>f1</version>
<width units="bits">32</width>
<clock units="Hz">33000000</clock>
<configuration>
<setting id="driver" value="pcieport" />
</configuration>
<capabilities>
<capability id="pci" />
<capability id="pciexpress" >PCI Express</capability>
<capability id="msi" >Message Signalled Interrupts</capability>
<capability id="pm" >Power Management</capability>
<capability id="normal_decode" />
<capability id="bus_master" >bus mastering</capability>
<capability id="cap_list" >PCI capabilities listing</capability>
</capabilities>
<resources>
<resource type="irq" value="25" />
<resource type="ioport" value="d000(size=4096)" />
<resource type="memory" value="df200000-df2fffff" />
</resources>
<node id="network" claimed="true" class="network" handle="PCI:0000:02:00.0">
<description>Ethernet interface</description>
<product>I210 Gigabit Network Connection</product>
<vendor>Intel Corporation</vendor>
<physid>0</physid>
<businfo>pci@0000:02:00.0</businfo>
<logicalname>eno2</logicalname>
<version>03</version>
<serial>ac:1f:6b:1a:04:b9</serial>
<capacity>1000000000</capacity>
<width units="bits">32</width>
<clock units="Hz">33000000</clock>
<configuration>
<setting id="autonegotiation" value="on" />
<setting id="broadcast" value="yes" />
<setting id="driver" value="igb" />
<setting id="driverversion" value="5.4.0-k" />
<setting id="firmware" value="3.25, 0x800005d0" />
<setting id="latency" value="0" />
<setting id="link" value="no" />
<setting id="multicast" value="yes" />
<setting id="port" value="twisted pair" />
</configuration>
<capabilities>
<capability id="pm" >Power Management</capability>
<capability id="msi" >Message Signalled Interrupts</capability>
<capability id="msix" >MSI-X</capability>
<capability id="pciexpress" >PCI Express</capability>
<capability id="bus_master" >bus mastering</capability>
<capability id="cap_list" >PCI capabilities listing</capability>
<capability id="ethernet" />
<capability id="physical" >Physical interface</capability>
<capability id="tp" >twisted pair</capability>
<capability id="10bt" >10Mbit/s</capability>
<capability id="10bt-fd" >10Mbit/s (full duplex)</capability>
<capability id="100bt" >100Mbit/s</capability>
<capability id="100bt-fd" >100Mbit/s (full duplex)</capability>
<capability id="1000bt-fd" >1Gbit/s (full duplex)</capability>
<capability id="autonegotiation" >Auto-negotiation</capability>
</capabilities>
<resources>
<resource type="irq" value="17" />
<resource type="memory" value="df200000-df27ffff" />
<resource type="ioport" value="d000(size=32)" />
<resource type="memory" value="df280000-df283fff" />
</resources>
</node>
</node>
<node id="pci:2" claimed="true" class="bridge" handle="PCIBUS:0000:03">
<description>PCI bridge</description>
<product>100 Series/C230 Series Chipset Family PCI Express Root Port #5</product>
<vendor>Intel Corporation</vendor>
<physid>1c.4</physid>
<businfo>pci@0000:00:1c.4</businfo>
<version>f1</version>
<width units="bits">32</width>
<clock units="Hz">33000000</clock>
<configuration>
<setting id="driver" value="pcieport" />
</configuration>
<capabilities>
<capability id="pci" />
<capability id="pciexpress" >PCI Express</capability>
<capability id="msi" >Message Signalled Interrupts</capability>
<capability id="pm" >Power Management</capability>
<capability id="normal_decode" />
<capability id="bus_master" >bus mastering</capability>
<capability id="cap_list" >PCI capabilities listing</capability>
</capabilities>
<resources>
<resource type="irq" value="26" />
<resource type="memory" value="df100000-df1fffff" />
</resources>
<node id="storage" claimed="true" class="storage" handle="PCI:0000:03:00.0">
<description>Non-Volatile memory controller</description>
<physid>0</physid>
<businfo>pci@0000:03:00.0</businfo>
<version>03</version>
<width units="bits">64</width>
<clock units="Hz">33000000</clock>
<configuration>
<setting id="driver" value="nvme" />
<setting id="latency" value="0" />
</configuration>
<capabilities>
<capability id="storage" />
<capability id="pm" >Power Management</capability>
<capability id="msi" >Message Signalled Interrupts</capability>
<capability id="pciexpress" >PCI Express</capability>
<capability id="msix" >MSI-X</capability>
<capability id="nvm_express" />
<capability id="bus_master" >bus mastering</capability>
<capability id="cap_list" >PCI capabilities listing</capability>
</capabilities>
<resources>
<resource type="irq" value="16" />
<resource type="memory" value="df100000-df103fff" />
</resources>
</node>
</node>
<node id="pci:3" claimed="true" class="bridge" handle="PCIBUS:0000:04">
<description>PCI bridge</description>
<product>100 Series/C230 Series Chipset Family PCI Express Root Port #7</product>
<vendor>Intel Corporation</vendor>
<physid>1c.6</physid>
<businfo>pci@0000:00:1c.6</businfo>
<version>f1</version>
<width units="bits">32</width>
<clock units="Hz">33000000</clock>
<configuration>
<setting id="driver" value="pcieport" />
</configuration>
<capabilities>
<capability id="pci" />
<capability id="pciexpress" >PCI Express</capability>
<capability id="msi" >Message Signalled Interrupts</capability>
<capability id="pm" >Power Management</capability>
<capability id="normal_decode" />
<capability id="bus_master" >bus mastering</capability>
<capability id="cap_list" >PCI capabilities listing</capability>
</capabilities>
<resources>
<resource type="irq" value="27" />
<resource type="ioport" value="c000(size=4096)" />
<resource type="memory" value="de000000-df0fffff" />
</resources>
<node id="pci" claimed="true" class="bridge" handle="PCIBUS:0000:05">
<description>PCI bridge</description>
<product>AST1150 PCI-to-PCI Bridge</product>
<vendor>ASPEED Technology, Inc.</vendor>
<physid>0</physid>
<businfo>pci@0000:04:00.0</businfo>
<logicalname>/dev/fb0</logicalname>
<dev>29:0</dev>
<version>03</version>
<width units="bits">64</width>
<clock units="Hz">33000000</clock>
<configuration>
<setting id="depth" value="32" />
<setting id="mode" value="1680x1050" />
<setting id="visual" value="truecolor" />
<setting id="xres" value="1680" />
<setting id="yres" value="1050" />
</configuration>
<capabilities>
<capability id="pci" />
<capability id="msi" >Message Signalled Interrupts</capability>
<capability id="pm" >Power Management</capability>
<capability id="pciexpress" >PCI Express</capability>
<capability id="normal_decode" />
<capability id="bus_master" >bus mastering</capability>
<capability id="cap_list" >PCI capabilities listing</capability>
<capability id="fb" />
</capabilities>
<resources>
<resource type="iomemory" value="220c1c10-220c1c0f" />
<resource type="ioport" value="c000(size=4096)" />
<resource type="memory" value="de000000-df0fffff" />
</resources>
<node id="display" claimed="true" class="display" handle="PCI:0000:05:00.0">
<description>VGA compatible controller</description>
<product>ASPEED Graphics Family</product>
<vendor>ASPEED Technology, Inc.</vendor>
<physid>0</physid>
<businfo>pci@0000:05:00.0</businfo>
<version>30</version>
<width units="bits">32</width>
<clock units="Hz">33000000</clock>
<configuration>
<setting id="driver" value="ast" />
<setting id="latency" value="0" />
</configuration>
<capabilities>
<capability id="pm" >Power Management</capability>
<capability id="msi" >Message Signalled Interrupts</capability>
<capability id="vga_controller" />
<capability id="bus_master" >bus mastering</capability>
<capability id="cap_list" >PCI capabilities listing</capability>
<capability id="rom" >extension ROM</capability>
</capabilities>
<resources>
<resource type="irq" value="18" />
<resource type="memory" value="de000000-deffffff" />
<resource type="memory" value="df000000-df01ffff" />
<resource type="ioport" value="c000(size=128)" />
<resource type="memory" value="c0000-dffff" />
</resources>
</node>
</node>
</node>
<node id="isa" claimed="true" class="bridge" handle="PCI:0000:00:1f.0">
<description>ISA bridge</description>
<product>C236 Chipset LPC/eSPI Controller</product>
<vendor>Intel Corporation</vendor>
<physid>1f</physid>
<businfo>pci@0000:00:1f.0</businfo>
<version>31</version>
<width units="bits">32</width>
<clock units="Hz">33000000</clock>
<configuration>
<setting id="latency" value="0" />
</configuration>
<capabilities>
<capability id="isa" />
<capability id="bus_master" >bus mastering</capability>
</capabilities>
</node>
<node id="memory" class="memory" handle="PCI:0000:00:1f.2">
<description>Memory controller</description>
<product>100 Series/C230 Series Chipset Family Power Management Controller</product>
<vendor>Intel Corporation</vendor>
<physid>1f.2</physid>
<businfo>pci@0000:00:1f.2</businfo>
<version>31</version>
<width units="bits">32</width>
<clock units="Hz">33000000</clock>
<configuration>
<setting id="latency" value="0" />
</configuration>
<resources>
<resource type="memory" value="df418000-df41bfff" />
</resources>
</node>
<node id="serial" class="bus" handle="PCI:0000:00:1f.4">
<description>SMBus</description>
<product>100 Series/C230 Series Chipset Family SMBus</product>
<vendor>Intel Corporation</vendor>
<physid>1f.4</physid>
<businfo>pci@0000:00:1f.4</businfo>
<version>31</version>
<width units="bits">64</width>
<clock units="Hz">33000000</clock>
<configuration>
<setting id="latency" value="0" />
</configuration>
<resources>
<resource type="memory" value="df41c000-df41c0ff" />
<resource type="ioport" value="f000(size=32)" />
</resources>
</node>
</node>
</node>
<node id="power:0" class="power" handle="">
<description>To Be Filled By O.E.M.</description>
<product>To Be Filled By O.E.M.</product>
<vendor>To Be Filled By O.E.M.</vendor>
<physid>1</physid>
<version>To Be Filled By O.E.M.</version>
<serial>To Be Filled By O.E.M.</serial>
<capacity units="mWh">32768</capacity>
</node>
<node id="power:1" class="power" handle="">
<description>To Be Filled By O.E.M.</description>
<product>To Be Filled By O.E.M.</product>
<vendor>To Be Filled By O.E.M.</vendor>
<physid>2</physid>
<version>To Be Filled By O.E.M.</version>
<serial>To Be Filled By O.E.M.</serial>
<capacity units="mWh">32768</capacity>
</node>
<node id="network" claimed="true" class="network" handle="">
<description>Ethernet interface</description>
<physid>3</physid>
<logicalname>docker0</logicalname>
<serial>02:42:f8:89:b0:a8</serial>
<configuration>
<setting id="broadcast" value="yes" />
<setting id="driver" value="bridge" />
<setting id="driverversion" value="2.3" />
<setting id="firmware" value="N/A" />
<setting id="ip" value="172.17.0.1" />
<setting id="link" value="no" />
<setting id="multicast" value="yes" />
</configuration>
<capabilities>
<capability id="ethernet" />
<capability id="physical" >Physical interface</capability>
</capabilities>
</node>
</node>
</list>
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