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Unh0lyTigg/74ls00.json

Last active August 29, 2015 14:24
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Prototype basic logic gate chip description json.
Raw
74ls00.json
{
"chipname": "74LS00",
"quickdesc": "Quad 2-Input NAND Gate",
"pincount": 14,
"pins": [
{ "type": "logic-input", "name": "A1" },
{ "type": "logic-input", "name": "B1" },
{ "type": "logic-output", "name": "Y1" },
{ "type": "logic-input", "name": "A2" },
{ "type": "logic-input", "name": "B2" },
{ "type": "logic-output", "name": "Y2" },
{ "type": "power", "name": "GND" },
{ "type": "logic-output", "name": "Y3" },
{ "type": "logic-input", "name": "A3" },
{ "type": "logic-input", "name": "B3" },
{ "type": "logic-output", "name": "Y4" },
{ "type": "logic-input", "name": "A4" },
{ "type": "logic-input", "name": "B4" },
{ "type": "power", "name": "VCC" }
],
"logic": [
{
"uniqueIdPerGate": "*",
"outputs": ["Y*"],
"inputs": ["A*", "B*"],
"truthtable": [
"A:L B:L Y:H",
"A:L B:H Y:H",
"A:H B:L Y:H",
"A:H B:H Y:L"
]
}
]
}
Raw
74ls02.json
{
"chipname": "74LS02",
"quickdesc": "Quad 2-Input NOR Gate",
"pincount": 14,
"pins": [
{ "type": "logic-output", "name": "Y1" },
{ "type": "logic-input", "name": "A1" },
{ "type": "logic-input", "name": "B1" },
{ "type": "logic-output", "name": "Y2" },
{ "type": "logic-input", "name": "A2" },
{ "type": "logic-input", "name": "B2" },
{ "type": "power", "name": "GND" },
{ "type": "logic-input", "name": "A3" },
{ "type": "logic-input", "name": "B3" },
{ "type": "logic-output", "name": "Y3" },
{ "type": "logic-input", "name": "A4" },
{ "type": "logic-input", "name": "B4" },
{ "type": "logic-output", "name": "Y4" },
{ "type": "power", "name": "VCC" }
],
"logic": [
{
"uniqueIdPerGate": "*",
"outputs": ["Y*"],
"inputs": ["A*", "B*"],
"truthtable": [
"A:L B:L Y:H",
"A:L B:H Y:L",
"A:H B:L Y:L",
"A:H B:H Y:L"
]
}
]
}
Raw
74ls04.json
{
"chipname": "74LS04",
"quickdesc": "Hex Inverter",
"pincount": 14,
"pins": [
{ "type": "logic-input", "name": "A1" },
{ "type": "logic-output", "name": "Y1" },
{ "type": "logic-input", "name": "A2" },
{ "type": "logic-output", "name": "Y2" },
{ "type": "logic-input", "name": "A3" },
{ "type": "logic-output", "name": "Y3" },
{ "type": "power", "name": "GND" },
{ "type": "logic-output", "name": "Y4" },
{ "type": "logic-input", "name": "A4" },
{ "type": "logic-output", "name": "Y5" },
{ "type": "logic-input", "name": "A5" },
{ "type": "logic-output", "name": "Y6" },
{ "type": "logic-input", "name": "A6" },
{ "type": "power", "name": "VCC" }
],
"logic": [
{
"uniqueIdPerGate": "*",
"outputs": ["Y*"],
"inputs": ["A*"],
"truthtable": [
"A:L Y:H",
"A:H Y:L"
]
}
]
}
Raw
74ls08.json
{
"chipname": "74LS08",
"quickdesc": "Quad 2-Input AND Gate",
"pincount": 14,
"pins": [
{ "type": "logic-input", "name": "A1" },
{ "type": "logic-input", "name": "B1" },
{ "type": "logic-output", "name": "Y1" },
{ "type": "logic-input", "name": "A2" },
{ "type": "logic-input", "name": "B2" },
{ "type": "logic-output", "name": "Y2" },
{ "type": "power", "name": "GND" },
{ "type": "logic-output", "name": "Y3" },
{ "type": "logic-input", "name": "A3" },
{ "type": "logic-input", "name": "B3" },
{ "type": "logic-output", "name": "Y4" },
{ "type": "logic-input", "name": "A4" },
{ "type": "logic-input", "name": "B4" },
{ "type": "power", "name": "VCC" }
],
"logic": [
{
"uniqueIdPerGate": "*",
"outputs": ["Y*"],
"inputs": ["A*", "B*"],
"truthtable": [
"A:L B:L Y:L",
"A:L B:H Y:L",
"A:H B:L Y:L",
"A:H B:H Y:H"
]
}
]
}
Raw
74ls10.json
{
"chipname": "74LS10",
"quickdesc": "Triple 3-Input NAND Gate",
"pincount": 14,
"pins": [
{ "type": "logic-input", "name": "A1" },
{ "type": "logic-input", "name": "B1" },
{ "type": "logic-input", "name": "A2" },
{ "type": "logic-input", "name": "B2" },
{ "type": "logic-input", "name": "C2" },
{ "type": "logic-output", "name": "Y2" },
{ "type": "power", "name": "GND" },
{ "type": "logic-output", "name": "Y3" },
{ "type": "logic-input", "name": "A3" },
{ "type": "logic-input", "name": "B3" },
{ "type": "logic-input", "name": "C3" },
{ "type": "logic-output", "name": "Y1" },
{ "type": "logic-input", "name": "C1" },
{ "type": "power", "name": "VCC" }
],
"logic": [
{
"uniqueIdPerGate": "*",
"outputs": ["Y*"],
"inputs": ["A*", "B*", "C*"],
"truthtable": [
"A:X B:X C:L Y:H",
"A:X B:L C:X Y:H",
"A:L B:X C:X Y:H",
"A:H B:H C:H Y:L"
]
}
]
}
Raw
74ls11.json
{
"chipname": "74LS11",
"quickdesc": "Triple 3-Input AND Gate",
"pincount": 14,
"pins": [
{ "type": "logic-input", "name": "A1" },
{ "type": "logic-input", "name": "B1" },
{ "type": "logic-input", "name": "A2" },
{ "type": "logic-input", "name": "B2" },
{ "type": "logic-input", "name": "C2" },
{ "type": "logic-output", "name": "Y2" },
{ "type": "power", "name": "GND" },
{ "type": "logic-output", "name": "Y3" },
{ "type": "logic-input", "name": "A3" },
{ "type": "logic-input", "name": "B3" },
{ "type": "logic-input", "name": "C3" },
{ "type": "logic-output", "name": "Y1" },
{ "type": "logic-input", "name": "C1" },
{ "type": "power", "name": "VCC" }
],
"logic": [
{
"uniqueIdPerGate": "*",
"outputs": ["Y*"],
"inputs": ["A*", "B*", "C*"],
"truthtable": [
"A:X B:X C:L Y:L",
"A:X B:L C:X Y:L",
"A:L B:X C:X Y:L",
"A:H B:H C:H Y:H"
]
}
]
}
Raw
74ls20.json
{
"chipname": "74LS20",
"quickdesc": "Dual 4-Input NAND Gate",
"pincount": 14,
"pins": [
{ "type": "logic-input", "name": "A1" },
{ "type": "logic-input", "name": "B1" },
{ "type": "no-connect", "name": "NC" },
{ "type": "logic-input", "name": "C1" },
{ "type": "logic-input", "name": "D1" },
{ "type": "logic-output", "name": "Y1" },
{ "type": "power", "name": "GND" },
{ "type": "logic-output", "name": "Y2" },
{ "type": "logic-input", "name": "A2" },
{ "type": "logic-input", "name": "B2" },
{ "type": "no-connect", "name": "NC" },
{ "type": "logic-input", "name": "C2" },
{ "type": "logic-input", "name": "D2" },
{ "type": "power", "name": "VCC" }
],
"logic": [
{
"uniqueIdPerGate": "*",
"outputs": ["Y*"],
"inputs": ["A*", "B*", "C*", "D*"],
"truthtable": [
"A:X B:X C:X D:L Y:H",
"A:X B:X C:L D:X Y:H",
"A:X B:L C:X D:X Y:H",
"A:L B:X C:X D:X Y:H",
"A:H B:H C:H D:H Y:L"
]
}
]
}
Raw
74ls21.json
{
"chipname": "74LS21",
"quickdesc": "Dual 4-Input AND Gate",
"pincount": 14,
"pins": [
{ "type": "logic-input", "name": "A1" },
{ "type": "logic-input", "name": "B1" },
{ "type": "no-connect", "name": "NC" },
{ "type": "logic-input", "name": "C1" },
{ "type": "logic-input", "name": "D1" },
{ "type": "logic-output", "name": "Y1" },
{ "type": "power", "name": "GND" },
{ "type": "logic-output", "name": "Y2" },
{ "type": "logic-input", "name": "A2" },
{ "type": "logic-input", "name": "B2" },
{ "type": "no-connect", "name": "NC" },
{ "type": "logic-input", "name": "C2" },
{ "type": "logic-input", "name": "D2" },
{ "type": "power", "name": "VCC" }
],
"logic": [
{
"uniqueIdPerGate": "*",
"outputs": ["Y*"],
"inputs": ["A*", "B*", "C*", "D*"],
"truthtable": [
"A:X B:X C:X D:L Y:L",
"A:X B:X C:L D:X Y:L",
"A:X B:L C:X D:X Y:L",
"A:L B:X C:X D:X Y:L",
"A:H B:H C:H D:H Y:H"
]
}
]
}
Raw
74ls27.json
{
"chipname": "74LS27",
"quickdesc": "Triple 3-Input NOR Gate",
"pincount": 14,
"pins": [
{ "type": "logic-input", "name": "A1" },
{ "type": "logic-input", "name": "B1" },
{ "type": "logic-input", "name": "A2" },
{ "type": "logic-input", "name": "B2" },
{ "type": "logic-input", "name": "C2" },
{ "type": "logic-output", "name": "Y2" },
{ "type": "power", "name": "GND" },
{ "type": "logic-output", "name": "Y3" },
{ "type": "logic-input", "name": "A3" },
{ "type": "logic-input", "name": "B3" },
{ "type": "logic-input", "name": "C3" },
{ "type": "logic-output", "name": "Y1" },
{ "type": "logic-input", "name": "C1" },
{ "type": "power", "name": "VCC" }
],
"logic": [
{
"uniqueIdPerGate": "*",
"outputs": ["Y*"],
"inputs": ["A*", "B*", "C*"],
"truthtable": [
"A:H B:X C:X Y:L",
"A:X B:H C:X Y:L",
"A:X B:X C:H Y:L",
"A:L B:L C:L Y:H"
]
}
]
}
Raw
74ls30.json
{
"chipname": "74LS30",
"quickdesc": "8-Input NAND Gate",
"pincount": 14,
"pins": [
{ "type": "logic-input", "name": "A" },
{ "type": "logic-input", "name": "B" },
{ "type": "logic-input", "name": "C" },
{ "type": "logic-input", "name": "D" },
{ "type": "logic-input", "name": "E" },
{ "type": "logic-input", "name": "F" },
{ "type": "power", "name": "GND" },
{ "type": "logic-input", "name": "Y" },
{ "type": "no-connect", "name": "NC" },
{ "type": "no-connect", "name": "NC" },
{ "type": "logic-input", "name": "G" },
{ "type": "logic-input", "name": "H" },
{ "type": "no-connect", "name": "NC" },
{ "type": "power", "name": "VCC" }
],
"logic": [
{
"uniqueIdPerGate": "",
"outputs": ["Y"],
"inputs": ["A", "B", "C", "D", "E", "F", "G", "H"],
"truthtable": [
"A:H B:H C:H D:H E:H F:H G:H H:H Y:L",
"A:L B:X C:X D:X E:X F:X G:X H:X Y:H",
"A:X B:L C:X D:X E:X F:X G:X H:X Y:H",
"A:X B:X C:L D:X E:X F:X G:X H:X Y:H",
"A:X B:X C:X D:L E:X F:X G:X H:X Y:H",
"A:X B:X C:X D:X E:L F:X G:X H:X Y:H",
"A:X B:X C:X D:X E:X F:L G:X H:X Y:H",
"A:X B:X C:X D:X E:X F:X G:L H:X Y:H",
"A:X B:X C:X D:X E:X F:X G:X H:L Y:H"
]
}
]
}
Raw
74ls32.json
{
"chipname": "74LS32",
"quickdesc": "Quad 2-Input OR Gate",
"pincount": 14,
"pins": [
{ "type": "logic-input", "name": "A1" },
{ "type": "logic-input", "name": "B1" },
{ "type": "logic-output", "name": "Y1" },
{ "type": "logic-input", "name": "A2" },
{ "type": "logic-input", "name": "B2" },
{ "type": "logic-output", "name": "Y2" },
{ "type": "power", "name": "GND" },
{ "type": "logic-output", "name": "Y3" },
{ "type": "logic-input", "name": "A3" },
{ "type": "logic-input", "name": "B3" },
{ "type": "logic-output", "name": "Y4" },
{ "type": "logic-input", "name": "A4" },
{ "type": "logic-input", "name": "B4" },
{ "type": "power", "name": "VCC" }
],
"logic": [
{
"uniqueIdPerGate": "*",
"outputs": ["Y*"],
"inputs": ["A*", "B*"],
"truthtable": [
"A:L B:L Y:L",
"A:L B:H Y:H",
"A:H B:L Y:H",
"A:H B:H Y:H"
]
}
]
}
Raw
74ls42.json
{
"chipname": "74LS42",
"quickdesc": "BCD to Decimal Decoder",
"pincount": 16,
"pins": [
{ "type": "logic-output", "name": "O0" },
{ "type": "logic-output", "name": "O1" },
{ "type": "logic-output", "name": "O2" },
{ "type": "logic-output", "name": "O3" },
{ "type": "logic-output", "name": "O4" },
{ "type": "logic-output", "name": "O5" },
{ "type": "logic-output", "name": "O6" },
{ "type": "power", "name": "GND" },
{ "type": "logic-output", "name": "O7" },
{ "type": "logic-output", "name": "O8" },
{ "type": "logic-output", "name": "O9" },
{ "type": "logic-input", "name": "A3" },
{ "type": "logic-input", "name": "A2" },
{ "type": "logic-input", "name": "A1" },
{ "type": "logic-input", "name": "A0" },
{ "type": "power", "name": "VCC" },
],
"logic": [
{
"uniqueIdPerGate": "",
"outputs": ["O0", "O1", "O2", "O3", "O4", "O5", "O6", "O7", "O8", "O9"],
"inputs": ["A0", "A1", "A2", "A3"],
"truthtable": [
"A0:L A1:L A2:L A3:L O0:L O1:H O2:H O3:H O4:H O5:H O6:H O7:H O8:H O9:H",
"A0:H A1:L A2:L A3:L O0:H O1:L O2:H O3:H O4:H O5:H O6:H O7:H O8:H O9:H",
"A0:L A1:H A2:L A3:L O0:H O1:H O2:L O3:H O4:H O5:H O6:H O7:H O8:H O9:H",
"A0:H A1:H A2:L A3:L O0:H O1:H O2:H O3:L O4:H O5:H O6:H O7:H O8:H O9:H",
"A0:L A1:L A2:H A3:L O0:H O1:H O2:H O3:H O4:L O5:H O6:H O7:H O8:H O9:H",
"A0:H A1:L A2:H A3:L O0:H O1:H O2:H O3:H O4:H O5:L O6:H O7:H O8:H O9:H",
"A0:L A1:H A2:H A3:L O0:H O1:H O2:H O3:H O4:H O5:H O6:L O7:H O8:H O9:H",
"A0:H A1:H A2:H A3:L O0:H O1:H O2:H O3:H O4:H O5:H O6:H O7:L O8:H O9:H",
"A0:L A1:L A2:L A3:H O0:H O1:H O2:H O3:H O4:H O5:H O6:H O7:H O8:L O9:H",
"A0:H A1:L A2:L A3:H O0:H O1:H O2:H O3:H O4:H O5:H O6:H O7:H O8:H O9:L",
"A0:L A1:H A2:L A3:H O0:H O1:H O2:H O3:H O4:H O5:H O6:H O7:H O8:H O9:H",
"A0:H A1:H A2:L A3:H O0:H O1:H O2:H O3:H O4:H O5:H O6:H O7:H O8:H O9:H",
"A0:L A1:L A2:H A3:H O0:H O1:H O2:H O3:H O4:H O5:H O6:H O7:H O8:H O9:H",
"A0:H A1:L A2:H A3:H O0:H O1:H O2:H O3:H O4:H O5:H O6:H O7:H O8:H O9:H",
"A0:L A1:H A2:H A3:H O0:H O1:H O2:H O3:H O4:H O5:H O6:H O7:H O8:H O9:H",
"A0:H A1:H A2:H A3:H O0:H O1:H O2:H O3:H O4:H O5:H O6:H O7:H O8:H O9:H"
]
}
]
}
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