m1n1 on QEMU

disable_sprr.patch

diff --git a/src/gxf.c b/src/gxf.c
index f306369..267d7a0 100644
--- a/src/gxf.c
+++ b/src/gxf.c
@@ -19,6 +19,8 @@ void *gl2_stack_base = &gl2_stack[GL_STACK_SIZE];
 
 bool in_gl12(void)
 {
+    return false;
+
     if (!(mrs(SYS_IMP_APL_SPRR_CONFIG_EL1) & SPRR_CONFIG_EN))
         return false;
     if (!(mrs(SYS_IMP_APL_GXF_CONFIG_EL1) & GXF_CONFIG_EN))
@@ -30,6 +32,8 @@ bool in_gl12(void)
 
 static uint64_t gl_call(void *func, uint64_t a, uint64_t b, uint64_t c, uint64_t d)
 {
+    return -1;
+
     // disable the MMU first since enabling SPRR will change the meaning of all
     // pagetable permission bits and also prevent us from having rwx pages
     u64 sprr_state = mrs(SYS_IMP_APL_SPRR_CONFIG_EL1);
@@ -65,6 +69,8 @@ static uint64_t gl_call_wrapper(struct gl_call_argv *args)
 
 uint64_t gl1_call(void *func, uint64_t a, uint64_t b, uint64_t c, uint64_t d)
 {
+    return -1;
+
     if (mrs(CurrentEL) == 0x4)
         return gl_call(func, a, b, c, d);
 
diff --git a/src/memory.c b/src/memory.c
index b4b778f..11e06de 100644
--- a/src/memory.c
+++ b/src/memory.c
@@ -423,7 +423,7 @@ void mmu_init(void)
     mmu_init_pagetables();
     mmu_add_default_mappings();
     mmu_configure();
-    mmu_init_sprr();
+    // mmu_init_sprr();
 
     // Enable EL0 memory access by EL1
     msr(PAN, 0);
diff --git a/src/startup.c b/src/startup.c
index b20c63b..129db41 100644
--- a/src/startup.c
+++ b/src/startup.c
@@ -92,7 +92,7 @@ void _start_c(void *boot_args, void *base)
         (void *)(((u64)cur_boot_args.devtree) - cur_boot_args.virt_base + cur_boot_args.phys_base);
 
     exception_initialize();
-    gxf_init();
+    // gxf_init();
     m1n1_main();
 }