Weissnix4711 · July 23, 2024 22:44
diff --git a/esptable.txt b/esptable.txt
 | Series  	| Announcement Date 	| Main Processor              	| Clock Freq (up to) 	| Co-processor 	| Cache  	| BT                  	| WiFi                    	| GPIO                     	| SRAM   	| ROM    	| Flash encryption 	| RTC memory 	| SPI 	| UART 	| USB         	| Touch Sensor 	| Timers                	| RMT           	|
 |---------	|-------------------	|-----------------------------	|--------------------	|--------------	|--------	|---------------------	|-------------------------	|--------------------------	|--------	|--------	|------------------	|------------	|-----	|------	|-------------	|--------------	|-----------------------	|---------------	|
 | S2      	| 2019, September   	| Xtensa single-core LX7      	| 240 MHz            	| ULP (RISC-V) 	| 8/16KB 	| No                  	| 4                       	| 43                       	| 320KB  	| 128 KB 	| XTS-AES-128/256  	| 16KB       	| 4   	| 2    	| USB OTG 1.1 	| 14           	| 4x 64-bit             	| 4x TX/RX      	|
 | S3      	| 2020, December    	| Xtensa LX7 dual-core        	| 240 MHz            	| ULP (RISC-V) 	|        	| BLE 5.0 + LE        	| 4                       	| 45                       	| 512 KB 	| 384KB  	|                  	| 16KB       	|     	|      	|             	|              	|                       	|               	|
 | C2      	|                   	| RISC-V single-core          	| 120 MHz            	|              	|        	| BLE 5.0 + LE        	|                         	| 14                       	| 272 KB 	| 576 KB 	|                  	|            	|     	|      	|             	|              	|                       	|               	|
 | C3      	| 2020, November    	| RISC-V single-core          	| 160 MHz            	|              	| 16KB   	| BLE 5.0 + LE        	| 4                       	| 22                       	| 400KB  	| 384 KB 	| XTS-AES-128      	| 8KB        	| 3   	| 2    	| Serial/JTAG 	|              	| 2x 54-bit + 1x 52-bit 	| 2x TX + 2x RX 	|
 | C6      	| 2021, April       	| RISC-V single-core          	| 160 MHz            	|              	|        	| BLE 5.0 + LE        	| 6                       	| 30 (QFN40) or 22 (QFN32) 	| 512KB  	| 320KB  	| XTS-AES-128      	|            	|     	|      	|             	|              	|                       	|               	|
 | ESP32   	| 2016, September   	| Xtensa LX6 single/dual-core 	| 160/240 MHz        	| ULP          	| 64KB   	| BT 4.2 BR/EDR & BLE 	| 4                       	| 34                       	| 520KB  	|        	|                  	| 16KB       	| 4   	| 3    	| No          	| 10           	| 4x 64b                	| 8x TX/RX      	|
 | ESP8266 	| 2014, August      	| Tensilica L106              	| 160MHz             	| No           	|        	| No                  	| 4 (only up to 72.2Mbps) 	| 17                       	| 160KB  	| No     	| No               	| 768B       	| 2   	| 2    	| No          	|              	| 2x 32b (*)            	| 1x TX 1x RX   	|
	\| Series \| Announcement Date \| Main Processor \| Clock Freq (up to) \| Co-processor \| Cache \| BT \| WiFi \| GPIO \| SRAM \| ROM \| Flash encryption \| RTC memory \| SPI \| UART \| USB \| Touch Sensor \| Timers \| RMT \|
	\|--------- \|------------------- \|----------------------------- \|-------------------- \|-------------- \|-------- \|--------------------- \|------------------------- \|-------------------------- \|-------- \|-------- \|------------------ \|------------ \|----- \|------ \|------------- \|-------------- \|----------------------- \|--------------- \|
	\| S2 \| 2019, September \| Xtensa single-core LX7 \| 240 MHz \| ULP (RISC-V) \| 8/16KB \| No \| 4 \| 43 \| 320KB \| 128 KB \| XTS-AES-128/256 \| 16KB \| 4 \| 2 \| USB OTG 1.1 \| 14 \| 4x 64-bit \| 4x TX/RX \|
	\| S3 \| 2020, December \| Xtensa LX7 dual-core \| 240 MHz \| ULP (RISC-V) \| \| BLE 5.0 + LE \| 4 \| 45 \| 512 KB \| 384KB \| \| 16KB \| \| \| \| \| \| \|
	\| C2 \| \| RISC-V single-core \| 120 MHz \| \| \| BLE 5.0 + LE \| \| 14 \| 272 KB \| 576 KB \| \| \| \| \| \| \| \| \|
	\| C3 \| 2020, November \| RISC-V single-core \| 160 MHz \| \| 16KB \| BLE 5.0 + LE \| 4 \| 22 \| 400KB \| 384 KB \| XTS-AES-128 \| 8KB \| 3 \| 2 \| Serial/JTAG \| \| 2x 54-bit + 1x 52-bit \| 2x TX + 2x RX \|
	\| C6 \| 2021, April \| RISC-V single-core \| 160 MHz \| \| \| BLE 5.0 + LE \| 6 \| 30 (QFN40) or 22 (QFN32) \| 512KB \| 320KB \| XTS-AES-128 \| \| \| \| \| \| \| \|
	\| ESP32 \| 2016, September \| Xtensa LX6 single/dual-core \| 160/240 MHz \| ULP \| 64KB \| BT 4.2 BR/EDR & BLE \| 4 \| 34 \| 520KB \| \| \| 16KB \| 4 \| 3 \| No \| 10 \| 4x 64b \| 8x TX/RX \|
	\| ESP8266 \| 2014, August \| Tensilica L106 \| 160MHz \| No \| \| No \| 4 (only up to 72.2Mbps) \| 17 \| 160KB \| No \| No \| 768B \| 2 \| 2 \| No \| \| 2x 32b (*) \| 1x TX 1x RX \|