Gpt 4 vhdl code

gistfile1.txt

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Display_Controller is
    Port (
        clk: in STD_LOGIC;
        reset: in STD_LOGIC;
        hex_value: in STD_LOGIC_VECTOR (15 downto 0);
        seg: out STD_LOGIC_VECTOR (6 downto 0);
        an: out STD_LOGIC_VECTOR (3 downto 0)
    );
end Display_Controller;

architecture Behavioral of Display_Controller is
    signal digit_counter: integer range 0 to 3 := 0;
    signal count: integer := 0;
    constant refresh_rate: integer := 5000; -- Adjust this value for desired display refresh rate

    function to_7seg (hex_digit: STD_LOGIC_VECTOR(3 downto 0)) return STD_LOGIC_VECTOR is
        variable temp: STD_LOGIC_VECTOR (6 downto 0);
    begin
        case hex_digit is
            when "0000" => temp := "0111111";
            when "0001" => temp := "0000110";
            when "0010" => temp := "1011011";
            when "0011" => temp := "1001111";
            when "0100" => temp := "1100110";
            when "0101" => temp := "1101101";
            when "0110" => temp := "1111101";
            when "0111" => temp := "0100111";
            when "1000" => temp := "1111111";
            when "1001" => temp := "1101111";
            when "1010" => temp := "1110111";
            when "1011" => temp := "1111100";
            when "1100" => temp := "0111001";
            when "1101" => temp := "1011110";
            when "1110" => temp := "1111001";
            when others => temp := "1110011";
        end case;
        return temp;
    end function;

begin
    process (clk, reset)
    begin
        if reset = '1' then
            count <= 0;
            digit_counter <= 0;
            seg <= (others => '1');
            an <= (others => '0');
        elsif rising_edge(clk) then
            count <= count + 1;
            if count = refresh_rate then
                count <= 0;
                case digit_counter is
                    when 0 =>
                        seg <= to_7seg(hex_value(3 downto 0));
                        an <= "1110";
                        digit_counter <= 1;
                    when 1 =>
                        seg <= to_7seg(hex_value(7 downto 4));
                        an <= "1101";
                        digit_counter <= 2;
                    when 2 =>
                        seg <= to_7seg(hex_value(11 downto 8));
                        an <= "1011";
                        digit_counter <= 3;
                    when others =>
                        seg <= to_7seg(hex_value(15 downto 12));
                        an <= "0111";
                        digit_counter <= 0;
                end case;
            end if;
        end if;
    end process;
end Behavioral;