We could take a simple stage model like ARM Cortex-M3 , ie 3 stages model : Fetch, Decode and Execute.
On Fetch stage :
- Checks if there is a interrupt. If there are enabled and there is a interrupt handler for it, the CPU accepts it, initiating the interrupt sequence.
- Reads 4 bytes from RAM
- Increase PC by 4.
On Decode stage :
- Decode instruction fetched on previus stage.
- If the instruction have a long immediate value (M & L bits are 1)