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CupicZi.md

Diglog Cupic demo - 31.01.2020

2018/2019 Zavrsni grupa a

1.

2/1
2/1 2/1
2/1 2/1 2/1
2/1
 a0  a1  a2

7

2.

X == 0
Si => Si+1

X == 1
Si => Si+2

S0 x=0 => S1
S0 x=1 => S2

S1 x=0 => S2
S1 x=1 => S3

S2 x=0 => S3
S2 x=1 => S0

S3 x=0 => S0
S3 x=1 => S1

S3 = 1
Others = 0

T bistabili

TP x TS
X q1q0|q1q0|x|T1T0|
0 0 0 |0 1 |0|0 1
0 0 1 |1 0 |0|1 1
0 1 0 |1 1 |0|0 1
0 1 1 |0 0 |1|1 1
1 0 0 |1 0 |0|1 0
1 0 1 |1 1 |0|1 0
1 1 0 |0 0 |0|1 0
1 1 1 |0 1 |1|1 0

T0 = !X
T1 = X || q0

b)

3.

Q2Q1Q0 | SIN | Q2Q1Q0
0 [0 0]| {1} | [0 0] {1} 0 -> 1 -> 3 -> 7 -> 6 -> 4 -> 1 (vratimo se nazad)
0 [0 1]| {1} | [0 1] {1} 1 -> 3
0 [1 0]| {0} | [1 0] {0} 2 -> 4
0 [1 1]| {1} | [1 1] {1} 3 -> 7
1 [0 0]| {1} | [0 0] {1} 4 -> 1
1 [0 1]| {0} | [0 1] {0} 5 -> 2
1 [1 0]| {0} | [1 0] {0} 6 -> 4
1 [1 1]| {0} | [1 1] {0} 7 -> 6

0 -> 1 -> 3 -> 7 -> 6 -> 4 -> 1 (vratimo se nazad)
               5 -> 2 -> 4

MUX
a1 = q2
a0 = q1

0 => 1
1 => q0
2 => !q0
3 => 0

!a1!a0 * d0 + !a1a0 * d1 + a1!a0 * d2 + a1a0 * d3

f(mux) = !q2!q1 * 1 + !q2q1q0 + q2!q1!q0
       = !q2!q1!q0 + !q2!q1q0 + !q2q1q0 + q2!q1!q0
              0          1         3         4
sin(q2, q1, q0) = summ(0, 1, 3, 4)

d)

4.

J0 = !Q1 + X
K0 = Q0
J1 = !X
K1 = Q! + Q0

q1q0 x|J1K1 J0K0|Q1Q0|
0 0 0 |1 1  1 0 |1 1 | 0 [0] -> 3
0 0 1 |0 1  1 0 |0 1 | 0 [1] -> 1
0 1 0 |1 0  1 1 |1 0 | 1 [0] -> 2
0 1 1 |0 0  1 1 |0 0 | 1 [1] -> 0
1 0 0 |1 1  0 0 |0 0 | 2 [0] -> 0
1 0 1 |0 1  1 0 |0 1 | 2 [1] -> 1
1 1 0 |1 1  0 1 |0 0 | 3 [0] -> 0
1 1 1 |0 1  1 1 |0 0 | 3 [1] -> 0

Za X=1 -> mozemo ici u [S0, S1] a)

5.

tDb = 20ns
tDls = tSetup = tRead = 10ns

### Sync - parallel
fp = 1 / (tDb + tDls + tSetup)
   = 1 / 40

### Sync - serial
fs = 1 / (tDb + (n - 2) * tDls + tSetup)
   = 1 / 60

### Async
fa = 1 / (n * tDb + tRead)
   = 1 / 110

fa > fs > fp

b)

6.

b)

7.

A2A1A0|D3D2D1D0|P
0 0 0 |0 1 0 1 |0
0 0 1 |0 0 1 1 |0
0 1 0 |1 0 0 0 |1
0 1 1 |1 1 0 1 |1
1 0 0 |0 1 1 0 |0
1 0 1 |1 0 0 1 |0
1 1 0 |1 0 1 0 |0
1 1 1 |0 1 1 0 |0

00110000

b)

8.

QnA B C | Qn+1 | D |
0 0 0 0 |  0   | 0 |
0 0 0 1 |  1   | 1 |
0 0 1 0 |  1   | 1 |
0 0 1 1 |  0   | 0 |

0 1 0 0 |  0   | 0 |
0 1 0 1 |  1   | 1 |
0 1 1 0 |  0   | 0 |
0 1 1 1 |  1   | 1 |

1 0 0 0 |  1   | 1 |
1 0 0 1 |  1   | 1 |
1 0 1 0 |  1   | 1 |
1 0 1 1 |  0   | 0 |

1 1 0 0 |  1   | 1 |
1 1 0 1 |  0   | 0 |
1 1 1 0 |  0   | 0 |
1 1 1 1 |  0   | 0 |

Lut -> D
0110

b)

9.

Decoder s not izlazima + NAND

A B C D | A B C D | A = SIN
0 0 0 0 |+1 0 0 0 ( ako dovedem 0 onda se vrtimo nazad na 0)
0 0 0 1 | 1 0 0 0
0 0 1 0 | 1 0 0 1
0 0 1 1 | 0 0 0 1
0 1 0 0 | 1 0 1 0
0 1 0 1 | 0 0 1 0
0 1 1 0 | 0 0 1 1
0 1 1 1 | 1 0 1 1
1 0 0 0 | 0 1 0 0
1 0 0 1 | 1 1 0 0
1 0 1 0 | 0 1 0 1
1 0 1 1 | 1 1 0 1
1 1 0 0 | 1 1 1 0
1 1 0 1 | 0 1 1 0
1 1 1 0 | 0 1 1 1
1 1 1 1 |+0 1 1 1 ( ako dovedem 1 onda se vrtimo nazad na 15)

1 1 1 0 1 0 0 1 0 1 0 1 1 0 0 0

summ(0,1,2,4,7,9,11,12)

a)

10.

d = 7
det = d - 1
isp = Math.floor((d - 1) / 2) = 3

e)

11.

Link za kTablice online summ(0,1,2,3,6,7,10,11,14,15) u input

func = m(0,1,2,3,6,7,10,11,14,15)

1 0 0 0
1 0 0 0
1 1 1 1
1 1 1 1

X = !C
f = !B!A + C
  = !B!A + X

A --> |PU|
B --> |  | --> F
C -!> |PD|

PU = p-channel
PD = n-channel

cnt = 1 (!C) + PU
    = 4

b)

12.

A3A2A1A0|Q3Q2Q1Q0|
0 0 0 0 | 0 1 0 1 |
0 0 0 1 | 0 1 1 1 |
0 0 1 0 | 0 1 0 0 |
0 0 1 1 | 1 1 0 0 |
0 1 0 0 | 0 0 1 1 |
0 1 0 1 | 1 1 1 0 |
0 1 1 0 | 1 0 1 1 |
0 1 1 1 | 1 0 0 1 |

1 0 0 0 | 0 0 1 0 |
1 0 0 1 | 1 1 1 1 |
1 0 1 0 | 1 1 0 1 |
1 0 1 1 | 1 0 0 0 |
1 1 0 0 | 1 0 1 0 |
1 1 0 1 | 0 0 0 0 |
1 1 1 0 | 0 0 0 1 |
1 1 1 1 | 0 1 1 0 |

ROM1
[
  [0 1 0 1 => 5],
  [0 1 1 1 => 7],
  [0 1 0 0 => 4],
  [1 1 0 0 => C],
  [0 0 1 1 => 3],
  [1 1 1 0 => E],
  [1 0 1 1 => B],
  [1 0 0 1 => 9]
]

ROM2 
[
  [0 0 1 0 => 2],
  [1 1 1 1 => F],
  [1 1 0 1 => D],
  [1 0 0 0 => 8],
  [1 0 1 0 => A],
  [0 0 0 0 => 0],
  [0 0 0 1 => 1],
  [0 1 1 0 => 6]
]

d) 56

13.

i7..i0 = 0 0 0 1 | 0 1 0 1
           1           5

d)

14.

!(A + B) * C
!A * !B * C
summ(1)

a)

15.

A -/n- B
     - B
     - ...
     - B

Ioha >= n * Iihb
n1 <= Ioha / Iihb = 50

Iola >= n * Iilb
n2 <= Iola / Iilb = 100

n = min(n1, n2) = 50

c)

16.

8 bit => 40us
9 bit => 40 / 8 * 9 = 45us

e)

17.

4bitni
         -> out
S3 -> R3 -> min - comp => out
S2    R2    gnd -
S1    R1
S0    R0

R0 = R
R1 = R / 2
R2 = R / 4
R3 = R / 8

X = 9V

Ii = Uref / Ri
I = a3 * (Uref / R/8) + a2 * (Uref / R/4) + a1 * (Uref / R/2) + a0 * (Uref / R/1)
  = Uref / R * X

R = 4.5 Rf

Uiz = -I * Rf = -Uref / R * X * Rf = -Uref * X * (Rf / R) = -5 * 9 * 0.222222222 = -9.99999999 ≈ -10V

b)

18.

00           11
0|--|--|--|Umax
4 - 1

000              111
0|-|-|-|-|-|-|-|Umax
7-1

15-1...

Smanjiti gresku 8 puta -> qvant / 8 -> dodati jos 3 bita

b)

19.

16K x 8 => 2.5D
2^4 * 2^10 * 2^3 = 2 ^ 17
Broj log rijeci - 2^4 * 2^10 = 2 ^ 14
log rijec sirina - 8bit
duljina fizicke rijeci - 32bin

d = [] [] [] [] -> 4 log rijeci, 32 bita

Mux(a[1, 0], d) = D7

Za Addrisrati 16k lokacija treba 14 addr bitova

14 - 2 = 12 ide na decoder

b)

20.

0    | 0    | 0    | 0
..   | ..   | ..   | ..
511  | 511  | 511  | 511
     |      |      | 
512  | 512  | 512  | 512
...  | ...  | ...  | ...
1023 | 1023 | 1023 | 1023
     |      |      |
...  | ...  | ...  | ...
4095 | 4095 | 4095 | 4095

4096 / 512 = 2^3 = 8
8 modula

Svaki modul je 512x4, treba nam 512x16
Znaci jos 3 u svaki red

Decoder - 8 izlaza (3 addr bita)
Mux - 4 ulaza (2 addr bita)

d)

21.

3D org

64K x 1bit
2^6 * 2^10 = 2^16 lokacija

2^8 * 2^8
Dek   Dek

2^8 * 2 izlaza = 512

a)

22.

d)

VHDL + OTHER

23.

QnJ K |Qn
0 0 0 |0
0 0 1 |0
0 1 0 |1
0 1 1 |1
1 0 0 |1
1 0 1 |0
1 1 0 |1
1 1 1 |0

   K
0 0 1 1
1 0 0 1 Qn
     J

Qn <= J AND !Qn + !K AND !Qn

entity jkff IS PORT (
  j, k, cp, cd: in std_logic;
  q, qn: out std_logic
);
END jkff;

architecture arch1 of jkff is
begin
  process(cp, cd)
    varible state: std_logic;
  begin
    if cd = '0' then
      stanje := '0';
    elsif falling_edge(cp) then
      stanje := (j and not stanje) or (not k and stanje);
    end if;

    q <= stanje;
    qn <= not stanje;
  end process;
end arch1;

24.

    |      |      |      |
| Dq0 -> Dq1 -> Dq2 -> Dq3 -> beginD |

Cp on all

S0 = Reset
Cd0 = 0
S[1..3] = 0
Cd[1..3] = Reset

     |
-|d SD q|-
-|cp    |
-|cd    |

entity pb is port (
  cp, reset: in std_logic;
  q: out std_logic_vector(0 to 3)
);
end pb;

architecture str of pb is
  signal iq: std_logic_vector(0 to 3); -- interni q
begin
  -- Redosljed signala na ff0
  -- D,Sd,Cd,Cp,Q

  ff0: ENTITY work.dff PORT MAP (iq(3), reset, '0', cp, iq(0));
  ff1: ENTITY work.dff PORT MAP (iq(0), '0', reset, cp, iq(1));
  ff2: ENTITY work.dff PORT MAP (iq(1), '0', reset, cp, iq(2));
  ff3: ENTITY work.dff PORT MAP (iq(2), '0', reset, cp, iq(3));

  q <= iq;
end str;
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