pmod_out.v

`timescale 1ns / 1ps
`default_nettype	none
// Module which sends the total calculated output signal to the PmodI2S
// stereo audio output device
module pmod_out(sig, i_clk, o_i2s_mclk, o_i2s_lrclk, o_i2s_sclk, o_i2s_sdin);
    input [15:0] sig;
    input wire	i_clk;      // 500MHz clock
    output reg	o_i2s_mclk;    // Master clock to send to PmodI2S to maintain
                    // synchronization
    output reg	o_i2s_lrclk;   // Left-right clock stereo audio output
    output reg	o_i2s_sclk;    // Clock for transmitting induvidual signal bits
                    // to PmodI2S
    output reg	o_i2s_sdin;    // Current signal bit to transmit
    

    reg [15:0] sig_temp;
    integer o_i2s_mclk_count;
    integer o_i2s_lrclk_count;
    integer o_i2s_sclk_count;

    initial begin
        o_i2s_mclk  = 0;
        o_i2s_lrclk = 0;
        o_i2s_sclk  = 0;
    
        sig_temp    = 0;;
        o_i2s_mclk_count  = 0;
        o_i2s_lrclk_count = 0;
        o_i2s_sclk_count  = 0;
    end

    always @(posedge i_clk)
    begin
        // 2000kHz
        if (o_i2s_mclk_count == 24) begin
            o_i2s_mclk <= ~o_i2s_mclk;
            o_i2s_mclk_count <= 0;
        end
        // 1000kHz
        if (o_i2s_sclk_count == 49) begin
            o_i2s_sclk <= ~o_i2s_sclk;
            o_i2s_sclk_count <= 0;
            // Transmit the signal bit-by-bit at every negative edge of
            // the o_i2s_sclk
            if (o_i2s_sclk == 0) begin
                o_i2s_sdin <= sig_temp[15];
                sig_temp <= sig_temp << 1;
            end
        end
        // 31.25kHz
        if (o_i2s_lrclk_count == 1600) begin
            o_i2s_lrclk <= ~o_i2s_lrclk;
            o_i2s_lrclk_count <= 0;
            // Reset sig_temp to the current signal when switching sides
            // of stereo output to transmit
            sig_temp <= sig;
        end
        
        o_i2s_mclk_count  <= o_i2s_mclk_count  + 1;
        o_i2s_lrclk_count <= o_i2s_lrclk_count + 1;
        o_i2s_sclk_count  <= o_i2s_sclk_count  + 1;
    end

endmodule