ZipCPU · July 19, 2018 00:20
diff --git a/test.v b/test.v
 `default_nettype none
 //
 module test(i_clk, i_value, o_value);
 	input	wire		i_clk;
 	input	wire	[15:0]	i_value;
 	output	reg	[15:0]	o_value;

 	wire	[15:0]	pre_value;
 	assign	pre_value = i_value + 1;

 	always @(posedge i_clk)
 		o_value <= pre_value;

 endmodule
	`default_nettype none
	//
	module test(i_clk, i_value, o_value);
	input wire i_clk;
	input wire [15:0] i_value;
	output reg [15:0] o_value;

	wire [15:0] pre_value;
	assign pre_value = i_value + 1;

	always @(posedge i_clk)
	o_value <= pre_value;

	endmodule